[X86SchedSandyBridge] update cost of COPY to 1 cycle from 0

[nickdesaulniers]

Summary

To match the cost of other scheduling models. This is expected to
schedule mov instructions around INLINEASM less frequently for the
default machineschedule (pre-RA scheduling).

Suggested by Craig Topper.

Link: https://github.com/llvm/llvm-project/issues/41914

[lebedev.ri]

I think this is a correct fix, most good X86Schedule*.td already do that.

[pengfei]

Do we still need this one?

[nickdesaulniers]

In D122350#3476064, @pengfei wrote:

Do we still need this one?

Yes; I need to rebase and fix the newly failing test cases first though.

[nickdesaulniers]

• fix up tests

[RKSimon]

LGTM - we should have this on all our current x86 models tbh

llvm/lib/Target/X86/X86SchedSandyBridge.td

 // A folded store needs a cycle on port 4 for the store data, and an extra port
 // 2/3 cycle to recompute the address.
 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
 
 def : WriteRes<WriteStore,   [SBPort23, SBPort4]>;
 def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>;
 def : WriteRes<WriteLoad,    [SBPort23]> { let Latency = 5; }
 def : WriteRes<WriteMove,    [SBPort015]>;
+def : InstRW<[WriteMove], (instrs COPY)>;
 def : WriteRes<WriteZero,    []>;
 def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 5; let NumMicroOps = 0; }
 
 // Arithmetic.
 defm : SBWriteResPair<WriteALU,    [SBPort015], 1>;
 defm : SBWriteResPair<WriteADC,    [SBPort05,SBPort015], 2, [1,1], 2>;
 
 defm : SBWriteResPair<WriteIMul8,     [SBPort1],   3>;

llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll

 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    addq %rsi, %rbx
 ; CHECK-NEXT:    leaq (%r9,%r10), %rdx
 ; CHECK-NEXT:    addq %rdx, %rdx
 ; CHECK-NEXT:    addq %r8, %rdx
 ; CHECK-NEXT:    movq X(%rip), %rdi
 ; CHECK-NEXT:    addq %rbx, %r12
 ; CHECK-NEXT:    addq %r8, %rdx
-; CHECK-NEXT:    bswapq %rdi
 ; CHECK-NEXT:    addq %rbx, %rdx
+; CHECK-NEXT:    bswapq %rdi
 ; CHECK-NEXT:    leaq (%r15,%r14), %rsi
 ; CHECK-NEXT:    addq %r12, %rsi
 ; CHECK-NEXT:    addq %r11, %rdi
 ; CHECK-NEXT:    addq %rsi, %rdi
 ; CHECK-NEXT:    leaq (%r10,%r8), %rsi
 ; CHECK-NEXT:    addq %rsi, %rsi
 ; CHECK-NEXT:    addq %rdx, %rsi
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r12, %rdi
 ; CHECK-NEXT:    addq %rdi, %r9
 ; CHECK-NEXT:    addq %rdx, %rsi
 ; CHECK-NEXT:    addq %rdi, %rsi
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r12,%r15), %rdi
 ; CHECK-NEXT:    addq %r9, %rdi
 ; CHECK-NEXT:    addq %r14, %rbx
 ; CHECK-NEXT:    addq %rdi, %rbx
 ; CHECK-NEXT:    leaq (%rdx,%r8), %rdi
 ; CHECK-NEXT:    addq %rdi, %rdi
 ; CHECK-NEXT:    addq %rsi, %rdi
 ; CHECK-NEXT:    movq X(%rip), %rcx
 ; CHECK-NEXT:    addq %r9, %rbx
 ; CHECK-NEXT:    addq %rbx, %r10
 ; CHECK-NEXT:    addq %rsi, %rdi
-; CHECK-NEXT:    bswapq %rcx
 ; CHECK-NEXT:    addq %rbx, %rdi
+; CHECK-NEXT:    bswapq %rcx
 ; CHECK-NEXT:    leaq (%r9,%r12), %rax
 ; CHECK-NEXT:    addq %r10, %rax
 ; CHECK-NEXT:    addq %r15, %rcx
 ; CHECK-NEXT:    addq %rax, %rcx
 ; CHECK-NEXT:    leaq (%rsi,%rdx), %r11
 ; CHECK-NEXT:    addq %r11, %r11
 ; CHECK-NEXT:    addq %rdi, %r11
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r10, %rcx
 ; CHECK-NEXT:    addq %rcx, %r8
 ; CHECK-NEXT:    addq %rdi, %r11
 ; CHECK-NEXT:    addq %rcx, %r11
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r10,%r9), %rcx
 ; CHECK-NEXT:    addq %r8, %rcx
 ; CHECK-NEXT:    addq %r12, %rbx
 ; CHECK-NEXT:    addq %rcx, %rbx
 ; CHECK-NEXT:    leaq (%rdi,%rsi), %r14
 ; CHECK-NEXT:    addq %r14, %r14
 ; CHECK-NEXT:    addq %r11, %r14
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    addq %r8, %rbx
 ; CHECK-NEXT:    addq %rbx, %rdx
 ; CHECK-NEXT:    addq %r11, %r14
-; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    addq %rbx, %r14
+; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    leaq (%r8,%r10), %rbx
 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    addq %r9, %rax
 ; CHECK-NEXT:    addq %rbx, %rax
 ; CHECK-NEXT:    leaq (%r11,%rdi), %r9
 ; CHECK-NEXT:    addq %r9, %r9
 ; CHECK-NEXT:    addq %r14, %r9
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    addq %rax, %rsi
 ; CHECK-NEXT:    addq %r14, %r9
 ; CHECK-NEXT:    addq %rax, %r9
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%rdx,%r8), %rax
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    addq %r10, %rbx
 ; CHECK-NEXT:    addq %rax, %rbx
 ; CHECK-NEXT:    leaq (%r14,%r11), %r10
 ; CHECK-NEXT:    addq %r10, %r10
 ; CHECK-NEXT:    addq %r9, %r10
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    addq %rsi, %rbx
 ; CHECK-NEXT:    addq %rbx, %rdi
 ; CHECK-NEXT:    addq %r9, %r10
-; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    addq %rbx, %r10
+; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    leaq (%rsi,%rdx), %rbx
 ; CHECK-NEXT:    addq %rdi, %rbx
 ; CHECK-NEXT:    addq %r8, %rax
 ; CHECK-NEXT:    addq %rbx, %rax
 ; CHECK-NEXT:    leaq (%r9,%r14), %r8
 ; CHECK-NEXT:    addq %r8, %r8
 ; CHECK-NEXT:    addq %r10, %r8
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    addq %rax, %r11
 ; CHECK-NEXT:    addq %r10, %r8
 ; CHECK-NEXT:    addq %rax, %r8
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%rdi,%rsi), %rax
 ; CHECK-NEXT:    addq %r11, %rax
 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    addq %rax, %rbx
 ; CHECK-NEXT:    leaq (%r10,%r9), %r15
 ; CHECK-NEXT:    addq %r15, %r15
 ; CHECK-NEXT:    addq %r8, %r15
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    addq %r11, %rbx
 ; CHECK-NEXT:    addq %rbx, %r14
 ; CHECK-NEXT:    addq %r8, %r15
-; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    addq %rbx, %r15
+; CHECK-NEXT:    bswapq %rax
 ; CHECK-NEXT:    leaq (%r11,%rdi), %rbx
 ; CHECK-NEXT:    addq %r14, %rbx
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    addq %rbx, %rax
 ; CHECK-NEXT:    leaq (%r8,%r10), %rsi
 ; CHECK-NEXT:    addq %rsi, %rsi
 ; CHECK-NEXT:    addq %r15, %rsi
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r14, %rax
 ; CHECK-NEXT:    addq %rax, %r9
 ; CHECK-NEXT:    addq %r15, %rsi
 ; CHECK-NEXT:    addq %rax, %rsi
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r14,%r11), %rax
 ; CHECK-NEXT:    addq %r9, %rax
 ; CHECK-NEXT:    addq %rdi, %rbx
 ; CHECK-NEXT:    addq %rax, %rbx
 ; CHECK-NEXT:    leaq (%r15,%r8), %r12
 ; CHECK-NEXT:    addq %r12, %r12
 ; CHECK-NEXT:    addq %rsi, %r12
 ; CHECK-NEXT:    movq X(%rip), %rcx
 ; CHECK-NEXT:    addq %r9, %rbx
 ; CHECK-NEXT:    addq %rbx, %r10
 ; CHECK-NEXT:    addq %rsi, %r12
-; CHECK-NEXT:    bswapq %rcx
 ; CHECK-NEXT:    addq %rbx, %r12
+; CHECK-NEXT:    bswapq %rcx
 ; CHECK-NEXT:    leaq (%r9,%r14), %rax
 ; CHECK-NEXT:    addq %r10, %rax
 ; CHECK-NEXT:    addq %r11, %rcx
 ; CHECK-NEXT:    addq %rax, %rcx
 ; CHECK-NEXT:    leaq (%rsi,%r15), %rax
 ; CHECK-NEXT:    addq %rax, %rax
 ; CHECK-NEXT:    addq %r12, %rax
 ; CHECK-NEXT:    movq X(%rip), %rbx
 ; CHECK-NEXT:    addq %r10, %rcx
 ; CHECK-NEXT:    addq %rcx, %r8
 ; CHECK-NEXT:    addq %r12, %rax
 ; CHECK-NEXT:    addq %rcx, %rax
 ; CHECK-NEXT:    bswapq %rbx
 ; CHECK-NEXT:    leaq (%r10,%r9), %rcx
 ; CHECK-NEXT:    addq %r8, %rcx
 ; CHECK-NEXT:    addq %r14, %rbx
 ; CHECK-NEXT:    addq %rcx, %rbx
 ; CHECK-NEXT:    leaq (%r12,%rsi), %rcx
 ; CHECK-NEXT:    addq %rcx, %rcx
 ; CHECK-NEXT:    addq %rax, %rcx
 ; CHECK-NEXT:    movq X(%rip), %rdx
 ; CHECK-NEXT:    addq %r8, %rbx
 ; CHECK-NEXT:    addq %rbx, %r15
 ; CHECK-NEXT:    addq %rax, %rcx
-; CHECK-NEXT:    bswapq %rdx
 ; CHECK-NEXT:    addq %rbx, %rcx
+; CHECK-NEXT:    bswapq %rdx
 ; CHECK-NEXT:    leaq (%r8,%r10), %rbx
 ; CHECK-NEXT:    addq %r15, %rbx
 ; CHECK-NEXT:    addq %r9, %rdx
 ; CHECK-NEXT:    addq %rbx, %rdx
 ; CHECK-NEXT:    leaq (%rax,%r12), %rbx
 ; CHECK-NEXT:    addq %rbx, %rbx
 ; CHECK-NEXT:    addq %rcx, %rbx
 ; CHECK-NEXT:    addq %r15, %rdx
 ; CHECK-NEXT:    addq %rdx, %rsi
 ; CHECK-NEXT:    addq %rcx, %rbx
 ; CHECK-NEXT:    addq %rdx, %rbx
 ; CHECK-NEXT:    movq X(%rip), %rdx
 ; CHECK-NEXT:    bswapq %rdx
 ; CHECK-NEXT:    addq %r10, %rdx
 ; CHECK-NEXT:    leaq (%r15,%r8), %rdi
 ; CHECK-NEXT:    addq %rsi, %rdi
 ; CHECK-NEXT:    addq %rdi, %rdx
 ; CHECK-NEXT:    addq %rax, %rcx
 ; CHECK-NEXT:    addq %rcx, %rcx
 ; CHECK-NEXT:    addq %rbx, %rcx
 ; CHECK-NEXT:    addq %rbx, %rcx
 ; CHECK-NEXT:    addq %rsi, %rdx
 ; CHECK-NEXT:    addq %rdx, %r12
 ; CHECK-NEXT:    addq %rdx, %rcx
-; CHECK-NEXT:    addq %r15, %rsi
 ; CHECK-NEXT:    movq X(%rip), %rax
 ; CHECK-NEXT:    bswapq %rax
+; CHECK-NEXT:    addq %r15, %rsi
 ; CHECK-NEXT:    movq %rax, X(%rip)
 ; CHECK-NEXT:    addq %r8, %rax
 ; CHECK-NEXT:    addq %r12, %rsi
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    addq %r12, %rax
 ; CHECK-NEXT:    addq %rcx, %rax
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    popq %r12

llvm/test/CodeGen/X86/fp-load-trunc.ll

; AVX-NEXT:    retl
   %y = fptrunc <4 x double> %x to <4 x float>
   ret <4 x float> %y
 }
 
 define <8 x float> @test4(<8 x double>* %p) nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    cvtpd2ps 16(%eax), %xmm1
+; CHECK-NEXT:    cvtpd2ps 16(%eax), %xmm2
 ; CHECK-NEXT:    cvtpd2ps (%eax), %xmm0
-; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; CHECK-NEXT:    cvtpd2ps 48(%eax), %xmm2
+; CHECK-NEXT:    cvtpd2ps 48(%eax), %xmm3
 ; CHECK-NEXT:    cvtpd2ps 32(%eax), %xmm1
-; CHECK-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; CHECK-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
 ; CHECK-NEXT:    retl
 ;
 ; AVX-LABEL: test4:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; AVX-NEXT:    vcvtpd2psy (%eax), %xmm0
 ; AVX-NEXT:    vcvtpd2psy 32(%eax), %xmm1
 ; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX-NEXT:    retl
   %x = load <8 x double>, <8 x double>* %p
   %y = fptrunc <8 x double> %x to <8 x float>
   ret <8 x float> %y
 }
 
 

llvm/test/CodeGen/X86/fp-trunc.ll

; AVX-NEXT:    retl
   %y = fptrunc <4 x double> %x to <4 x float>
   ret <4 x float> %y
 }
 
 define <8 x float> @test4(<8 x double> %x) nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subl $12, %esp
-; CHECK-NEXT:    cvtpd2ps %xmm1, %xmm1
+; CHECK-NEXT:    cvtpd2ps %xmm1, %xmm3
 ; CHECK-NEXT:    cvtpd2ps %xmm0, %xmm0
-; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; CHECK-NEXT:    cvtpd2ps %xmm2, %xmm1
 ; CHECK-NEXT:    cvtpd2ps {{[0-9]+}}(%esp), %xmm2
+; CHECK-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm3[0]
 ; CHECK-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    retl
 ;
 ; AVX-LABEL: test4:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vcvtpd2ps %ymm0, %xmm0
 ; AVX-NEXT:    vcvtpd2ps %ymm1, %xmm1
 ; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX-NEXT:    retl
   %y = fptrunc <8 x double> %x to <8 x float>
   ret <8 x float> %y
 }
 
 

llvm/test/CodeGen/X86/gather-addresses.ll

 ; LIN-SSE4-NEXT:    pand (%rdx), %xmm0
 ; LIN-SSE4-NEXT:    movd %xmm0, %eax
 ; LIN-SSE4-NEXT:    pextrd $1, %xmm0, %ecx
 ; LIN-SSE4-NEXT:    pextrd $2, %xmm0, %edx
 ; LIN-SSE4-NEXT:    pextrd $3, %xmm0, %esi
 ; LIN-SSE4-NEXT:    cltq
 ; LIN-SSE4-NEXT:    movslq %ecx, %rcx
 ; LIN-SSE4-NEXT:    movslq %edx, %rdx
+; LIN-SSE4-NEXT:    movslq %esi, %rsi
 ; LIN-SSE4-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; LIN-SSE4-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
-; LIN-SSE4-NEXT:    movslq %esi, %rax
 ; LIN-SSE4-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; LIN-SSE4-NEXT:    movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
 ; LIN-SSE4-NEXT:    retq
 ;
 ; WIN-SSE2-LABEL: foo:
 ; WIN-SSE2:       # %bb.0:
 ; WIN-SSE2-NEXT:    movdqa (%rdx), %xmm0
 ; WIN-SSE2-NEXT:    pand (%r8), %xmm0

 ; WIN-SSE4-NEXT:    pand (%r8), %xmm0
 ; WIN-SSE4-NEXT:    movd %xmm0, %eax
 ; WIN-SSE4-NEXT:    pextrd $1, %xmm0, %edx
 ; WIN-SSE4-NEXT:    pextrd $2, %xmm0, %r8d
 ; WIN-SSE4-NEXT:    pextrd $3, %xmm0, %r9d
 ; WIN-SSE4-NEXT:    cltq
 ; WIN-SSE4-NEXT:    movslq %edx, %rdx
 ; WIN-SSE4-NEXT:    movslq %r8d, %r8
+; WIN-SSE4-NEXT:    movslq %r9d, %r9
 ; WIN-SSE4-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; WIN-SSE4-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
-; WIN-SSE4-NEXT:    movslq %r9d, %rax
 ; WIN-SSE4-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; WIN-SSE4-NEXT:    movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
 ; WIN-SSE4-NEXT:    retq
 ;
 ; LIN32-LABEL: foo:
 ; LIN32:       # %bb.0:
 ; LIN32-NEXT:    pushl %edi
 ; LIN32-NEXT:    pushl %esi
 ; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; LIN32-NEXT:    movdqa (%edx), %xmm0
-; LIN32-NEXT:    pand (%ecx), %xmm0
-; LIN32-NEXT:    pextrd $1, %xmm0, %ecx
-; LIN32-NEXT:    pextrd $2, %xmm0, %edx
-; LIN32-NEXT:    pextrd $3, %xmm0, %esi
-; LIN32-NEXT:    movd %xmm0, %edi
+; LIN32-NEXT:    movdqa (%ecx), %xmm0
+; LIN32-NEXT:    pand (%eax), %xmm0
+; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; LIN32-NEXT:    movd %xmm0, %ecx
+; LIN32-NEXT:    pextrd $1, %xmm0, %edx
+; LIN32-NEXT:    pextrd $2, %xmm0, %esi
+; LIN32-NEXT:    pextrd $3, %xmm0, %edi
 ; LIN32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; LIN32-NEXT:    movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
 ; LIN32-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; LIN32-NEXT:    movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
 ; LIN32-NEXT:    popl %esi
 ; LIN32-NEXT:    popl %edi
 ; LIN32-NEXT:    retl
   %a = load <4 x i32>, <4 x i32>* %i

 ; WIN-SSE4-NEXT:    retq
 ;
 ; LIN32-LABEL: old:
 ; LIN32:       # %bb.0:
 ; LIN32-NEXT:    pushl %edi
 ; LIN32-NEXT:    pushl %esi
 ; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; LIN32-NEXT:    movdqa (%edx), %xmm0
-; LIN32-NEXT:    pand (%ecx), %xmm0
+; LIN32-NEXT:    movdqa (%ecx), %xmm0
+; LIN32-NEXT:    pand (%eax), %xmm0
+; LIN32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; LIN32-NEXT:    movd %xmm0, %edx
 ; LIN32-NEXT:    pextrd $1, %xmm0, %esi
-; LIN32-NEXT:    pextrd $2, %xmm0, %ecx
+; LIN32-NEXT:    pextrd $2, %xmm0, %eax
 ; LIN32-NEXT:    pextrd $3, %xmm0, %edi
-; LIN32-NEXT:    andl %eax, %edx
-; LIN32-NEXT:    andl %eax, %esi
-; LIN32-NEXT:    andl %eax, %ecx
-; LIN32-NEXT:    andl %eax, %edi
+; LIN32-NEXT:    andl %ecx, %edx
+; LIN32-NEXT:    andl %ecx, %esi
+; LIN32-NEXT:    andl %ecx, %eax
+; LIN32-NEXT:    andl %ecx, %edi
 ; LIN32-NEXT:    movd %esi, %xmm1
 ; LIN32-NEXT:    movd %edx, %xmm0
 ; LIN32-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
 ; LIN32-NEXT:    movd %edi, %xmm2
-; LIN32-NEXT:    movd %ecx, %xmm1
+; LIN32-NEXT:    movd %eax, %xmm1
 ; LIN32-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; LIN32-NEXT:    popl %esi
 ; LIN32-NEXT:    popl %edi
 ; LIN32-NEXT:    retl
   %a = load <4 x i32>, <4 x i32>* %i
   %b = load <4 x i32>, <4 x i32>* %h
   %j = and <4 x i32> %a, %b
   %d0 = extractelement <4 x i32> %j, i32 0

llvm/test/CodeGen/X86/machine-combiner-int-vec.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 -machine-combiner-verify-pattern-order=true < %s | FileCheck %s --check-prefix=SSE
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx2 -machine-combiner-verify-pattern-order=true < %s | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx512vl,avx512bw -machine-combiner-verify-pattern-order=true < %s | FileCheck %s --check-prefix=AVX --check-prefix=AVX512
 
 ; Verify that 128-bit vector logical ops are reassociated.
 
 define <4 x i32> @reassociate_and_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
 ; SSE-LABEL: reassociate_and_v4i32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddd %xmm1, %xmm0
-; SSE-NEXT:    pand %xmm3, %xmm2
 ; SSE-NEXT:    pand %xmm2, %xmm0
+; SSE-NEXT:    pand %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_and_v4i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpand %xmm3, %xmm2, %xmm1
-; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpand %xmm0, %xmm2, %xmm0
+; AVX2-NEXT:    vpand %xmm0, %xmm3, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_and_v4i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpternlogd $128, %xmm2, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = and <4 x i32> %x2, %t0
   %t2 = and <4 x i32> %x3, %t1
   ret <4 x i32> %t2
 }
 
 define <4 x i32> @reassociate_or_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
 ; SSE-LABEL: reassociate_or_v4i32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddd %xmm1, %xmm0
-; SSE-NEXT:    por %xmm3, %xmm2
 ; SSE-NEXT:    por %xmm2, %xmm0
+; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_or_v4i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpor %xmm3, %xmm2, %xmm1
-; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpor %xmm0, %xmm2, %xmm0
+; AVX2-NEXT:    vpor %xmm0, %xmm3, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_or_v4i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpternlogd $254, %xmm2, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = or <4 x i32> %x2, %t0
   %t2 = or <4 x i32> %x3, %t1
   ret <4 x i32> %t2
 }
 
 define <4 x i32> @reassociate_xor_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
 ; SSE-LABEL: reassociate_xor_v4i32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddd %xmm1, %xmm0
-; SSE-NEXT:    pxor %xmm3, %xmm2
 ; SSE-NEXT:    pxor %xmm2, %xmm0
+; SSE-NEXT:    pxor %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_xor_v4i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpxor %xmm3, %xmm2, %xmm1
-; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpxor %xmm0, %xmm2, %xmm0
+; AVX2-NEXT:    vpxor %xmm0, %xmm3, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_xor_v4i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpternlogd $150, %xmm2, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = xor <4 x i32> %x2, %t0
   %t2 = xor <4 x i32> %x3, %t1
   ret <4 x i32> %t2
 }
 
 ; Verify that 256-bit vector logical ops are reassociated.
 
 define <8 x i32> @reassociate_and_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
 ; SSE-LABEL: reassociate_and_v8i32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddd %xmm2, %xmm0
-; SSE-NEXT:    pand %xmm6, %xmm4
 ; SSE-NEXT:    pand %xmm4, %xmm0
+; SSE-NEXT:    pand %xmm6, %xmm0
 ; SSE-NEXT:    paddd %xmm3, %xmm1
-; SSE-NEXT:    pand %xmm7, %xmm5
 ; SSE-NEXT:    pand %xmm5, %xmm1
+; SSE-NEXT:    pand %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_and_v8i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpand %ymm3, %ymm2, %ymm1
-; AVX2-NEXT:    vpand %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpand %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpand %ymm0, %ymm3, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_and_v8i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX512-NEXT:    vpternlogd $128, %ymm2, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = and <8 x i32> %x2, %t0
   %t2 = and <8 x i32> %x3, %t1
   ret <8 x i32> %t2
 }
 
 define <8 x i32> @reassociate_or_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
 ; SSE-LABEL: reassociate_or_v8i32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddd %xmm2, %xmm0
-; SSE-NEXT:    por %xmm6, %xmm4
 ; SSE-NEXT:    por %xmm4, %xmm0
+; SSE-NEXT:    por %xmm6, %xmm0
 ; SSE-NEXT:    paddd %xmm3, %xmm1
-; SSE-NEXT:    por %xmm7, %xmm5
 ; SSE-NEXT:    por %xmm5, %xmm1
+; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_or_v8i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpor %ymm3, %ymm2, %ymm1
-; AVX2-NEXT:    vpor %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpor %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpor %ymm0, %ymm3, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_or_v8i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX512-NEXT:    vpternlogd $254, %ymm2, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = or <8 x i32> %x2, %t0
   %t2 = or <8 x i32> %x3, %t1
   ret <8 x i32> %t2
 }
 
 define <8 x i32> @reassociate_xor_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
 ; SSE-LABEL: reassociate_xor_v8i32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddd %xmm2, %xmm0
-; SSE-NEXT:    pxor %xmm6, %xmm4
 ; SSE-NEXT:    pxor %xmm4, %xmm0
+; SSE-NEXT:    pxor %xmm6, %xmm0
 ; SSE-NEXT:    paddd %xmm3, %xmm1
-; SSE-NEXT:    pxor %xmm7, %xmm5
 ; SSE-NEXT:    pxor %xmm5, %xmm1
+; SSE-NEXT:    pxor %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_xor_v8i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpxor %ymm3, %ymm2, %ymm1
-; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpxor %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpxor %ymm0, %ymm3, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_xor_v8i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX512-NEXT:    vpternlogd $150, %ymm2, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    pand {{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    pand {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pand {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_and_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpand %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpand %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpand %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpand %ymm0, %ymm6, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpand %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpand %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpand %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpand %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_and_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vpternlogd $128, %zmm2, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    por {{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    por {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    por {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_or_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpor %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpor %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpor %ymm0, %ymm6, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpor %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpor %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpor %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpor %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_or_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vpternlogd $254, %zmm2, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    pxor {{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    pxor {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pxor {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_xor_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpxor %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpxor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpxor %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpxor %ymm0, %ymm6, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpxor %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpxor %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpxor %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpxor %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_xor_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vpternlogd $150, %zmm2, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = xor <16 x i32> %x2, %t0
   %t2 = xor <16 x i32> %x3, %t1
   ret <16 x i32> %t2
 }
 
 ; Verify that 128-bit vector min/max are reassociated.
 
 define <16 x i8> @reassociate_umax_v16i8(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, <16 x i8> %x3) {
 ; SSE-LABEL: reassociate_umax_v16i8:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddb %xmm1, %xmm0
-; SSE-NEXT:    pmaxub %xmm3, %xmm2
 ; SSE-NEXT:    pmaxub %xmm2, %xmm0
+; SSE-NEXT:    pmaxub %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxub %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxub %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxub %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpmaxub %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp ugt <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp ugt <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4
 }
 
 define <8 x i16> @reassociate_umax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
 ; SSE-LABEL: reassociate_umax_v8i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm1, %xmm0
 ; SSE-NEXT:    psubusw %xmm2, %xmm0
 ; SSE-NEXT:    paddw %xmm2, %xmm0
 ; SSE-NEXT:    psubusw %xmm3, %xmm0
 ; SSE-NEXT:    paddw %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxuw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxuw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxuw %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpmaxuw %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp ugt <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp ugt <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm1
 ; SSE-NEXT:    por %xmm3, %xmm1
 ; SSE-NEXT:    movdqa %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxud %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxud %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxud %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpmaxud %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp ugt <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp ugt <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vpxor %xmm1, %xmm3, %xmm1
 ; AVX2-NEXT:    vpcmpgtq %xmm2, %xmm1, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpmaxuq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpmaxuq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpmaxuq %xmm0, %xmm2, %xmm0
+; AVX512-NEXT:    vpmaxuq %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp ugt <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp ugt <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxsb %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxsb %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpmaxsb %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp sgt <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp sgt <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4
 }
 
 define <8 x i16> @reassociate_smax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
 ; SSE-LABEL: reassociate_smax_v8i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm1, %xmm0
-; SSE-NEXT:    pmaxsw %xmm3, %xmm2
 ; SSE-NEXT:    pmaxsw %xmm2, %xmm0
+; SSE-NEXT:    pmaxsw %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxsw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxsw %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpmaxsw %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp sgt <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp sgt <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxsd %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpmaxsd %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp sgt <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp sgt <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm2, %xmm0, %xmm0
 ; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm3, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpmaxsq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpmaxsq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpmaxsq %xmm0, %xmm2, %xmm0
+; AVX512-NEXT:    vpmaxsq %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp sgt <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp sgt <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4
 }
 
 define <16 x i8> @reassociate_umin_v16i8(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, <16 x i8> %x3) {
 ; SSE-LABEL: reassociate_umin_v16i8:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddb %xmm1, %xmm0
-; SSE-NEXT:    pminub %xmm3, %xmm2
 ; SSE-NEXT:    pminub %xmm2, %xmm0
+; SSE-NEXT:    pminub %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminub %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminub %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminub %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpminub %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp ult <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp ult <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4

 ; SSE-NEXT:    psubusw %xmm2, %xmm0
 ; SSE-NEXT:    psubw %xmm0, %xmm3
 ; SSE-NEXT:    movdqa %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminuw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminuw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminuw %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpminuw %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp ult <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp ult <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm5, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminud %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminud %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminud %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpminud %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp ult <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp ult <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vpxor %xmm1, %xmm3, %xmm1
 ; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm2, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpminuq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpminuq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpminuq %xmm0, %xmm2, %xmm0
+; AVX512-NEXT:    vpminuq %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp ult <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp ult <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminsb %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminsb %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpminsb %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp slt <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp slt <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4
 }
 
 define <8 x i16> @reassociate_smin_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
 ; SSE-LABEL: reassociate_smin_v8i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm1, %xmm0
-; SSE-NEXT:    pminsw %xmm3, %xmm2
 ; SSE-NEXT:    pminsw %xmm2, %xmm0
+; SSE-NEXT:    pminsw %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminsw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminsw %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpminsw %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp slt <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp slt <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminsd %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpminsd %xmm0, %xmm3, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp slt <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp slt <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm2, %xmm0, %xmm0
 ; AVX2-NEXT:    vpcmpgtq %xmm3, %xmm0, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpminsq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpminsq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpminsq %xmm0, %xmm2, %xmm0
+; AVX512-NEXT:    vpminsq %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp slt <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp slt <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4
 }
 
 ; Verify that 256-bit vector min/max are reassociated.
 
 define <32 x i8> @reassociate_umax_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) {
 ; SSE-LABEL: reassociate_umax_v32i8:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddb %xmm2, %xmm0
 ; SSE-NEXT:    paddb %xmm3, %xmm1
-; SSE-NEXT:    pmaxub %xmm6, %xmm4
-; SSE-NEXT:    pmaxub %xmm4, %xmm0
-; SSE-NEXT:    pmaxub %xmm7, %xmm5
 ; SSE-NEXT:    pmaxub %xmm5, %xmm1
+; SSE-NEXT:    pmaxub %xmm4, %xmm0
+; SSE-NEXT:    pmaxub %xmm6, %xmm0
+; SSE-NEXT:    pmaxub %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxub %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxub %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxub %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpmaxub %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp ugt <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp ugt <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4

 ; SSE-NEXT:    paddw %xmm6, %xmm0
 ; SSE-NEXT:    psubusw %xmm7, %xmm1
 ; SSE-NEXT:    paddw %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxuw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxuw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxuw %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpmaxuw %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp ugt <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp ugt <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxud %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxud %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxud %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpmaxud %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp ugt <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp ugt <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; SSE-NEXT:    por %xmm5, %xmm1
 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm3, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v4i64:
 ; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm4 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
 ; AVX2-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX2-NEXT:    vpxor %ymm1, %ymm2, %ymm4
-; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm5
-; AVX2-NEXT:    vpcmpgtq %ymm5, %ymm4, %ymm4
-; AVX2-NEXT:    vblendvpd %ymm4, %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vxorpd %ymm1, %ymm0, %ymm2
-; AVX2-NEXT:    vpxor %ymm1, %ymm3, %ymm1
-; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpxor %ymm4, %ymm2, %ymm1
+; AVX2-NEXT:    vpxor %ymm4, %ymm0, %ymm5
+; AVX2-NEXT:    vpcmpgtq %ymm5, %ymm1, %ymm1
+; AVX2-NEXT:    vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vxorpd %ymm4, %ymm0, %ymm1
+; AVX2-NEXT:    vpxor %ymm4, %ymm3, %ymm2
+; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpmaxuq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpmaxuq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpmaxuq %ymm0, %ymm2, %ymm0
+; AVX512-NEXT:    vpmaxuq %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp ugt <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp ugt <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxsb %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxsb %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpmaxsb %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp sgt <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp sgt <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4
 }
 
 define <16 x i16> @reassociate_smax_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
 ; SSE-LABEL: reassociate_smax_v16i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm2, %xmm0
 ; SSE-NEXT:    paddw %xmm3, %xmm1
-; SSE-NEXT:    pmaxsw %xmm6, %xmm4
-; SSE-NEXT:    pmaxsw %xmm4, %xmm0
-; SSE-NEXT:    pmaxsw %xmm7, %xmm5
 ; SSE-NEXT:    pmaxsw %xmm5, %xmm1
+; SSE-NEXT:    pmaxsw %xmm4, %xmm0
+; SSE-NEXT:    pmaxsw %xmm6, %xmm0
+; SSE-NEXT:    pmaxsw %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxsw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxsw %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpmaxsw %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp sgt <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp sgt <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxsd %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxsd %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpmaxsd %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp sgt <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp sgt <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm3, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpmaxsq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpmaxsq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpmaxsq %ymm0, %ymm2, %ymm0
+; AVX512-NEXT:    vpmaxsq %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp sgt <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp sgt <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4
 }
 
 define <32 x i8> @reassociate_umin_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) {
 ; SSE-LABEL: reassociate_umin_v32i8:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddb %xmm2, %xmm0
 ; SSE-NEXT:    paddb %xmm3, %xmm1
-; SSE-NEXT:    pminub %xmm6, %xmm4
-; SSE-NEXT:    pminub %xmm4, %xmm0
-; SSE-NEXT:    pminub %xmm7, %xmm5
 ; SSE-NEXT:    pminub %xmm5, %xmm1
+; SSE-NEXT:    pminub %xmm4, %xmm0
+; SSE-NEXT:    pminub %xmm6, %xmm0
+; SSE-NEXT:    pminub %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminub %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminub %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminub %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpminub %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp ult <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp ult <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4

 ; SSE-NEXT:    psubw %xmm0, %xmm7
 ; SSE-NEXT:    movdqa %xmm6, %xmm0
 ; SSE-NEXT:    movdqa %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminuw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminuw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminuw %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpminuw %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp ult <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp ult <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminud %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminud %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminud %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpminud %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp ult <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp ult <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; SSE-NEXT:    por %xmm5, %xmm1
 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm3, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v4i64:
 ; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm4 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
 ; AVX2-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX2-NEXT:    vpxor %ymm1, %ymm2, %ymm4
-; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm5
-; AVX2-NEXT:    vpcmpgtq %ymm4, %ymm5, %ymm4
-; AVX2-NEXT:    vblendvpd %ymm4, %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vxorpd %ymm1, %ymm0, %ymm2
-; AVX2-NEXT:    vpxor %ymm1, %ymm3, %ymm1
-; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm2, %ymm1
+; AVX2-NEXT:    vpxor %ymm4, %ymm2, %ymm1
+; AVX2-NEXT:    vpxor %ymm4, %ymm0, %ymm5
+; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vxorpd %ymm4, %ymm0, %ymm1
+; AVX2-NEXT:    vpxor %ymm4, %ymm3, %ymm2
+; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm1, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpminuq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpminuq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpminuq %ymm0, %ymm2, %ymm0
+; AVX512-NEXT:    vpminuq %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp ult <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp ult <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminsb %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminsb %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpminsb %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp slt <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp slt <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4
 }
 
 define <16 x i16> @reassociate_smin_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
 ; SSE-LABEL: reassociate_smin_v16i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm2, %xmm0
 ; SSE-NEXT:    paddw %xmm3, %xmm1
-; SSE-NEXT:    pminsw %xmm6, %xmm4
-; SSE-NEXT:    pminsw %xmm4, %xmm0
-; SSE-NEXT:    pminsw %xmm7, %xmm5
 ; SSE-NEXT:    pminsw %xmm5, %xmm1
+; SSE-NEXT:    pminsw %xmm4, %xmm0
+; SSE-NEXT:    pminsw %xmm6, %xmm0
+; SSE-NEXT:    pminsw %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminsw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminsw %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpminsw %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp slt <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp slt <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminsd %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminsd %ymm0, %ymm2, %ymm0
+; AVX-NEXT:    vpminsd %ymm0, %ymm3, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp slt <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp slt <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm0, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpminsq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpminsq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpminsq %ymm0, %ymm2, %ymm0
+; AVX512-NEXT:    vpminsq %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp slt <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp slt <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4

 ; SSE-NEXT:    pmaxub {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pmaxub {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxub %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxub %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxub %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxub %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxub %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpmaxub %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpmaxub %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpmaxub %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxub %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxub %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxub %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxub %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp ugt <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp ugt <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    psubusw %xmm8, %xmm3
 ; SSE-NEXT:    paddw %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxuw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxuw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxuw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxuw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxuw %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpmaxuw %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpmaxuw %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpmaxuw %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxuw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxuw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxuw %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxuw %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp ugt <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp ugt <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm6, %xmm3
 ; SSE-NEXT:    por %xmm5, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxud %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxud %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxud %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxud %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxud %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpmaxud %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpmaxud %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpmaxud %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxud %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxud %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxud %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxud %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp ugt <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp ugt <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; SSE-NEXT:    por %xmm4, %xmm3
 ; SSE-NEXT:    pand %xmm3, %xmm5
 ; SSE-NEXT:    pandn %xmm9, %xmm3
 ; SSE-NEXT:    por %xmm5, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v8i64:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpaddq %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm3 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX2-NEXT:    vpxor %ymm3, %ymm5, %ymm8
-; AVX2-NEXT:    vpxor %ymm3, %ymm1, %ymm9
-; AVX2-NEXT:    vpcmpgtq %ymm9, %ymm8, %ymm8
-; AVX2-NEXT:    vblendvpd %ymm8, %ymm5, %ymm1, %ymm1
 ; AVX2-NEXT:    vpaddq %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpxor %ymm3, %ymm4, %ymm2
-; AVX2-NEXT:    vpxor %ymm3, %ymm0, %ymm5
-; AVX2-NEXT:    vpcmpgtq %ymm5, %ymm2, %ymm2
-; AVX2-NEXT:    vblendvpd %ymm2, %ymm4, %ymm0, %ymm0
-; AVX2-NEXT:    vxorpd %ymm3, %ymm0, %ymm2
-; AVX2-NEXT:    vpxor %ymm3, %ymm6, %ymm4
-; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm4, %ymm2
-; AVX2-NEXT:    vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
-; AVX2-NEXT:    vxorpd %ymm3, %ymm1, %ymm2
-; AVX2-NEXT:    vpxor %ymm3, %ymm7, %ymm3
-; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm3, %ymm2
+; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; AVX2-NEXT:    vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT:    vpxor %ymm2, %ymm5, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm1, %ymm8
+; AVX2-NEXT:    vpcmpgtq %ymm8, %ymm3, %ymm3
+; AVX2-NEXT:    vblendvpd %ymm3, %ymm5, %ymm1, %ymm1
+; AVX2-NEXT:    vpxor %ymm2, %ymm4, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm0, %ymm5
+; AVX2-NEXT:    vpcmpgtq %ymm5, %ymm3, %ymm3
+; AVX2-NEXT:    vblendvpd %ymm3, %ymm4, %ymm0, %ymm0
+; AVX2-NEXT:    vxorpd %ymm2, %ymm0, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm6, %ymm4
+; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm4, %ymm3
+; AVX2-NEXT:    vblendvpd %ymm3, %ymm6, %ymm0, %ymm0
+; AVX2-NEXT:    vxorpd %ymm2, %ymm1, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm7, %ymm2
+; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm2, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxuq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxuq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxuq %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxuq %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp ugt <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp ugt <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smax_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxsb %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxsb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxsb %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxsb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxsb %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpmaxsb %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpmaxsb %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpmaxsb %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsb %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsb %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsb %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxsb %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp sgt <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp sgt <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    pmaxsw {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pmaxsw {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smax_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxsw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxsw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxsw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxsw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxsw %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpmaxsw %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpmaxsw %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpmaxsw %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsw %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxsw %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp sgt <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp sgt <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smax_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxsd %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxsd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxsd %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxsd %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxsd %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpmaxsd %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpmaxsd %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpmaxsd %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsd %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsd %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxsd %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp sgt <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp sgt <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm7, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsq %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpmaxsq %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp sgt <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp sgt <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4

 ; SSE-NEXT:    pminub {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pminub {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminub %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminub %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminub %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminub %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminub %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpminub %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpminub %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpminub %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminub %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminub %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminub %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminub %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp ult <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp ult <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    psubusw %xmm12, %xmm4
 ; SSE-NEXT:    psubw %xmm4, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminuw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminuw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminuw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminuw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminuw %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpminuw %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpminuw %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpminuw %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminuw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminuw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminuw %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminuw %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp ult <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp ult <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminud %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminud %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminud %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminud %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminud %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpminud %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpminud %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpminud %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminud %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminud %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminud %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminud %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp ult <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp ult <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; SSE-NEXT:    por %xmm4, %xmm3
 ; SSE-NEXT:    pand %xmm3, %xmm5
 ; SSE-NEXT:    pandn %xmm9, %xmm3
 ; SSE-NEXT:    por %xmm5, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v8i64:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vpaddq %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm3 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
-; AVX2-NEXT:    vpxor %ymm3, %ymm5, %ymm8
-; AVX2-NEXT:    vpxor %ymm3, %ymm1, %ymm9
-; AVX2-NEXT:    vpcmpgtq %ymm8, %ymm9, %ymm8
-; AVX2-NEXT:    vblendvpd %ymm8, %ymm5, %ymm1, %ymm1
 ; AVX2-NEXT:    vpaddq %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpxor %ymm3, %ymm4, %ymm2
-; AVX2-NEXT:    vpxor %ymm3, %ymm0, %ymm5
-; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm5, %ymm2
-; AVX2-NEXT:    vblendvpd %ymm2, %ymm4, %ymm0, %ymm0
-; AVX2-NEXT:    vxorpd %ymm3, %ymm0, %ymm2
-; AVX2-NEXT:    vpxor %ymm3, %ymm6, %ymm4
-; AVX2-NEXT:    vpcmpgtq %ymm4, %ymm2, %ymm2
-; AVX2-NEXT:    vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
-; AVX2-NEXT:    vxorpd %ymm3, %ymm1, %ymm2
-; AVX2-NEXT:    vpxor %ymm3, %ymm7, %ymm3
-; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm2, %ymm2
+; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; AVX2-NEXT:    vpaddq %ymm3, %ymm1, %ymm1
+; AVX2-NEXT:    vpxor %ymm2, %ymm5, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm1, %ymm8
+; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm8, %ymm3
+; AVX2-NEXT:    vblendvpd %ymm3, %ymm5, %ymm1, %ymm1
+; AVX2-NEXT:    vpxor %ymm2, %ymm4, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm0, %ymm5
+; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm5, %ymm3
+; AVX2-NEXT:    vblendvpd %ymm3, %ymm4, %ymm0, %ymm0
+; AVX2-NEXT:    vxorpd %ymm2, %ymm0, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm6, %ymm4
+; AVX2-NEXT:    vpcmpgtq %ymm4, %ymm3, %ymm3
+; AVX2-NEXT:    vblendvpd %ymm3, %ymm6, %ymm0, %ymm0
+; AVX2-NEXT:    vxorpd %ymm2, %ymm1, %ymm3
+; AVX2-NEXT:    vpxor %ymm2, %ymm7, %ymm2
+; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm3, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminuq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminuq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminuq %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminuq %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp ult <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp ult <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smin_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminsb %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminsb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminsb %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminsb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminsb %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpminsb %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpminsb %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpminsb %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsb %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsb %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsb %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminsb %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp slt <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp slt <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    pminsw {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pminsw {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smin_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminsw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminsw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminsw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminsw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminsw %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpminsw %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpminsw %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpminsw %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsw %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminsw %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp slt <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp slt <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smin_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminsd %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminsd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminsd %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminsd %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminsd %ymm1, %ymm5, %ymm1
+; AVX2-NEXT:    vpminsd %ymm0, %ymm4, %ymm0
+; AVX2-NEXT:    vpminsd %ymm0, %ymm6, %ymm0
+; AVX2-NEXT:    vpminsd %ymm1, %ymm7, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsd %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsd %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminsd %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp slt <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp slt <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm7, %ymm1, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsq %zmm0, %zmm2, %zmm0
+; AVX512-NEXT:    vpminsq %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp slt <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp slt <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4
 }

llvm/test/CodeGen/X86/machine-combiner-int.ll

 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -machine-combiner-verify-pattern-order=true | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after machine-combiner -machine-combiner-verify-pattern-order=true -o - | FileCheck %s --check-prefix=DEAD
 
 ; Verify that integer multiplies are reassociated. The first multiply in 
 ; each test should be independent of the result of the preceding add (lea).
 
 ; TODO: This test does not actually test i16 machine instruction reassociation 
 ; because the operands are being promoted to i32 types.
 
 define i16 @reassociate_muls_i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3) {
 ; CHECK-LABEL: reassociate_muls_i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    leal   (%rdi,%rsi), %eax
-; CHECK-NEXT:    imull  %ecx, %edx
 ; CHECK-NEXT:    imull  %edx, %eax
+; CHECK-NEXT:    imull  %ecx, %eax
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    retq
   %t0 = add i16 %x0, %x1
   %t1 = mul i16 %x2, %t0
   %t2 = mul i16 %x3, %t1
   ret i16 %t2
 }
 
 define i32 @reassociate_muls_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; CHECK-LABEL: reassociate_muls_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    leal   (%rdi,%rsi), %eax
-; CHECK-NEXT:    imull  %ecx, %edx
 ; CHECK-NEXT:    imull  %edx, %eax
+; CHECK-NEXT:    imull  %ecx, %eax
 ; CHECK-NEXT:    retq
 
 ; DEAD:       ADD32rr
 ; DEAD-NEXT:  IMUL32rr{{.*}}implicit-def dead $eflags
 ; DEAD-NEXT:  IMUL32rr{{.*}}implicit-def dead $eflags
 
   %t0 = add i32 %x0, %x1
   %t1 = mul i32 %x2, %t0
   %t2 = mul i32 %x3, %t1
   ret i32 %t2
 }
 
 define i64 @reassociate_muls_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
 ; CHECK-LABEL: reassociate_muls_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    leaq   (%rdi,%rsi), %rax
-; CHECK-NEXT:    imulq  %rcx, %rdx
 ; CHECK-NEXT:    imulq  %rdx, %rax
+; CHECK-NEXT:    imulq  %rcx, %rax
 ; CHECK-NEXT:    retq
   %t0 = add i64 %x0, %x1
   %t1 = mul i64 %x2, %t0
   %t2 = mul i64 %x3, %t1
   ret i64 %t2
 }
 
 ; Verify that integer 'ands' are reassociated. The first 'and' in 
 ; each test should be independent of the result of the preceding sub.
 
 define i8 @reassociate_ands_i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3) {
 ; CHECK-LABEL: reassociate_ands_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl  %edx, %eax
-; CHECK-NEXT:    subb  %sil, %dil
+; CHECK-NEXT:    movl  %edi, %eax
+; CHECK-NEXT:    subb  %sil, %al
+; CHECK-NEXT:    andb  %dl, %al
 ; CHECK-NEXT:    andb  %cl, %al
-; CHECK-NEXT:    andb  %dil, %al
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    retq
   %t0 = sub i8 %x0, %x1
   %t1 = and i8 %x2, %t0
   %t2 = and i8 %x3, %t1
   ret i8 %t2
 }
 
 ; TODO: No way to test i16? These appear to always get promoted to i32.
 
 define i32 @reassociate_ands_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; CHECK-LABEL: reassociate_ands_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl  %edx, %eax
-; CHECK-NEXT:    subl  %esi, %edi
+; CHECK-NEXT:    movl  %edi, %eax
+; CHECK-NEXT:    subl  %esi, %eax
+; CHECK-NEXT:    andl  %edx, %eax
 ; CHECK-NEXT:    andl  %ecx, %eax
-; CHECK-NEXT:    andl  %edi, %eax
 ; CHECK-NEXT:    retq
   %t0 = sub i32 %x0, %x1
   %t1 = and i32 %x2, %t0
   %t2 = and i32 %x3, %t1
   ret i32 %t2
 }
 
 define i64 @reassociate_ands_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
 ; CHECK-LABEL: reassociate_ands_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq  %rdx, %rax
-; CHECK-NEXT:    subq  %rsi, %rdi
+; CHECK-NEXT:    movq  %rdi, %rax
+; CHECK-NEXT:    subq  %rsi, %rax
+; CHECK-NEXT:    andq  %rdx, %rax
 ; CHECK-NEXT:    andq  %rcx, %rax
-; CHECK-NEXT:    andq  %rdi, %rax
 ; CHECK-NEXT:    retq
   %t0 = sub i64 %x0, %x1
   %t1 = and i64 %x2, %t0
   %t2 = and i64 %x3, %t1
   ret i64 %t2
 }
 
 ; Verify that integer 'ors' are reassociated. The first 'or' in 
 ; each test should be independent of the result of the preceding sub.
 
 define i8 @reassociate_ors_i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3) {
 ; CHECK-LABEL: reassociate_ors_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl  %edx, %eax
-; CHECK-NEXT:    subb  %sil, %dil
+; CHECK-NEXT:    movl  %edi, %eax
+; CHECK-NEXT:    subb  %sil, %al
+; CHECK-NEXT:    orb   %dl, %al
 ; CHECK-NEXT:    orb   %cl, %al
-; CHECK-NEXT:    orb   %dil, %al
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    retq
   %t0 = sub i8 %x0, %x1
   %t1 = or i8 %x2, %t0
   %t2 = or i8 %x3, %t1
   ret i8 %t2
 }
 
 ; TODO: No way to test i16? These appear to always get promoted to i32.
 
 define i32 @reassociate_ors_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; CHECK-LABEL: reassociate_ors_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl  %edx, %eax
-; CHECK-NEXT:    subl  %esi, %edi
+; CHECK-NEXT:    movl  %edi, %eax
+; CHECK-NEXT:    subl  %esi, %eax
+; CHECK-NEXT:    orl   %edx, %eax
 ; CHECK-NEXT:    orl   %ecx, %eax
-; CHECK-NEXT:    orl   %edi, %eax
 ; CHECK-NEXT:    retq
   %t0 = sub i32 %x0, %x1
   %t1 = or i32 %x2, %t0
   %t2 = or i32 %x3, %t1
   ret i32 %t2
 }
 
 define i64 @reassociate_ors_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
 ; CHECK-LABEL: reassociate_ors_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq  %rdx, %rax
-; CHECK-NEXT:    subq  %rsi, %rdi
+; CHECK-NEXT:    movq  %rdi, %rax
+; CHECK-NEXT:    subq  %rsi, %rax
+; CHECK-NEXT:    orq   %rdx, %rax
 ; CHECK-NEXT:    orq   %rcx, %rax
-; CHECK-NEXT:    orq   %rdi, %rax
 ; CHECK-NEXT:    retq
   %t0 = sub i64 %x0, %x1
   %t1 = or i64 %x2, %t0
   %t2 = or i64 %x3, %t1
   ret i64 %t2
 }
 
 ; Verify that integer 'xors' are reassociated. The first 'xor' in
 ; each test should be independent of the result of the preceding sub.
 
 define i8 @reassociate_xors_i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3) {
 ; CHECK-LABEL: reassociate_xors_i8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl  %edx, %eax
-; CHECK-NEXT:    subb  %sil, %dil
+; CHECK-NEXT:    movl  %edi, %eax
+; CHECK-NEXT:    subb  %sil, %al
+; CHECK-NEXT:    xorb  %dl, %al
 ; CHECK-NEXT:    xorb  %cl, %al
-; CHECK-NEXT:    xorb  %dil, %al
 ; CHECK-NEXT:    # kill
 ; CHECK-NEXT:    retq
   %t0 = sub i8 %x0, %x1
   %t1 = xor i8 %x2, %t0
   %t2 = xor i8 %x3, %t1
   ret i8 %t2
 }
 
 ; TODO: No way to test i16? These appear to always get promoted to i32.
 
 define i32 @reassociate_xors_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; CHECK-LABEL: reassociate_xors_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl  %edx, %eax
-; CHECK-NEXT:    subl  %esi, %edi
+; CHECK-NEXT:    movl  %edi, %eax
+; CHECK-NEXT:    subl  %esi, %eax
+; CHECK-NEXT:    xorl  %edx, %eax
 ; CHECK-NEXT:    xorl  %ecx, %eax
-; CHECK-NEXT:    xorl  %edi, %eax
 ; CHECK-NEXT:    retq
   %t0 = sub i32 %x0, %x1
   %t1 = xor i32 %x2, %t0
   %t2 = xor i32 %x3, %t1
   ret i32 %t2
 }
 
 define i64 @reassociate_xors_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
 ; CHECK-LABEL: reassociate_xors_i64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq  %rdx, %rax
-; CHECK-NEXT:    subq  %rsi, %rdi
+; CHECK-NEXT:    movq  %rdi, %rax
+; CHECK-NEXT:    subq  %rsi, %rax
+; CHECK-NEXT:    xorq  %rdx, %rax
 ; CHECK-NEXT:    xorq  %rcx, %rax
-; CHECK-NEXT:    xorq  %rdi, %rax
 ; CHECK-NEXT:    retq
   %t0 = sub i64 %x0, %x1
   %t1 = xor i64 %x2, %t0
   %t2 = xor i64 %x3, %t1
   ret i64 %t2
 }
 

llvm/test/CodeGen/X86/recip-fastmath.ll

 ; BTVER2-NEXT:    retq
 ;
 ; SANDY-LABEL: v16f32_one_step:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    vrcpps %ymm0, %ymm2
 ; SANDY-NEXT:    vmulps %ymm2, %ymm0, %ymm0
 ; SANDY-NEXT:    vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; SANDY-NEXT:    vsubps %ymm0, %ymm3, %ymm0
+; SANDY-NEXT:    vrcpps %ymm1, %ymm4
 ; SANDY-NEXT:    vmulps %ymm0, %ymm2, %ymm0
 ; SANDY-NEXT:    vaddps %ymm0, %ymm2, %ymm0
-; SANDY-NEXT:    vrcpps %ymm1, %ymm2
-; SANDY-NEXT:    vmulps %ymm2, %ymm1, %ymm1
+; SANDY-NEXT:    vmulps %ymm4, %ymm1, %ymm1
 ; SANDY-NEXT:    vsubps %ymm1, %ymm3, %ymm1
-; SANDY-NEXT:    vmulps %ymm1, %ymm2, %ymm1
-; SANDY-NEXT:    vaddps %ymm1, %ymm2, %ymm1
+; SANDY-NEXT:    vmulps %ymm1, %ymm4, %ymm1
+; SANDY-NEXT:    vaddps %ymm1, %ymm4, %ymm1
 ; SANDY-NEXT:    retq
 ;
 ; HASWELL-LABEL: v16f32_one_step:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    vrcpps %ymm0, %ymm2
 ; HASWELL-NEXT:    vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; HASWELL-NEXT:    vrcpps %ymm1, %ymm4
 ; HASWELL-NEXT:    vfmsub213ps {{.*#+}} ymm0 = (ymm2 * ymm0) - ymm3

 ; SANDY-NEXT:    vrcpps %ymm0, %ymm2
 ; SANDY-NEXT:    vmulps %ymm2, %ymm0, %ymm3
 ; SANDY-NEXT:    vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; SANDY-NEXT:    vsubps %ymm3, %ymm4, %ymm3
 ; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm3
 ; SANDY-NEXT:    vaddps %ymm3, %ymm2, %ymm2
 ; SANDY-NEXT:    vmulps %ymm2, %ymm0, %ymm0
 ; SANDY-NEXT:    vsubps %ymm0, %ymm4, %ymm0
+; SANDY-NEXT:    vrcpps %ymm1, %ymm3
 ; SANDY-NEXT:    vmulps %ymm0, %ymm2, %ymm0
 ; SANDY-NEXT:    vaddps %ymm0, %ymm2, %ymm0
-; SANDY-NEXT:    vrcpps %ymm1, %ymm2
-; SANDY-NEXT:    vmulps %ymm2, %ymm1, %ymm3
-; SANDY-NEXT:    vsubps %ymm3, %ymm4, %ymm3
-; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm3
-; SANDY-NEXT:    vaddps %ymm3, %ymm2, %ymm2
+; SANDY-NEXT:    vmulps %ymm3, %ymm1, %ymm2
+; SANDY-NEXT:    vsubps %ymm2, %ymm4, %ymm2
+; SANDY-NEXT:    vmulps %ymm2, %ymm3, %ymm2
+; SANDY-NEXT:    vaddps %ymm2, %ymm3, %ymm2
 ; SANDY-NEXT:    vmulps %ymm2, %ymm1, %ymm1
 ; SANDY-NEXT:    vsubps %ymm1, %ymm4, %ymm1
 ; SANDY-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; SANDY-NEXT:    vaddps %ymm1, %ymm2, %ymm1
 ; SANDY-NEXT:    retq
 ;
 ; HASWELL-LABEL: v16f32_two_step:
 ; HASWELL:       # %bb.0:

llvm/test/CodeGen/X86/recip-fastmath2.ll

 ;
 ; SANDY-LABEL: v16f32_one_step2:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    vrcpps %ymm0, %ymm2
 ; SANDY-NEXT:    vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
 ; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm4
 ; SANDY-NEXT:    vmulps %ymm4, %ymm0, %ymm0
 ; SANDY-NEXT:    vsubps %ymm0, %ymm3, %ymm0
-; SANDY-NEXT:    vrcpps %ymm1, %ymm3
 ; SANDY-NEXT:    vmulps %ymm0, %ymm2, %ymm0
 ; SANDY-NEXT:    vaddps %ymm0, %ymm4, %ymm0
-; SANDY-NEXT:    vmovaps {{.*#+}} ymm2 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
-; SANDY-NEXT:    vmulps %ymm2, %ymm3, %ymm4
+; SANDY-NEXT:    vrcpps %ymm1, %ymm2
+; SANDY-NEXT:    vmovaps {{.*#+}} ymm3 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
+; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm4
 ; SANDY-NEXT:    vmulps %ymm4, %ymm1, %ymm1
-; SANDY-NEXT:    vsubps %ymm1, %ymm2, %ymm1
-; SANDY-NEXT:    vmulps %ymm1, %ymm3, %ymm1
+; SANDY-NEXT:    vsubps %ymm1, %ymm3, %ymm1
+; SANDY-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; SANDY-NEXT:    vaddps %ymm1, %ymm4, %ymm1
 ; SANDY-NEXT:    retq
 ;
 ; HASWELL-LABEL: v16f32_one_step2:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    vrcpps %ymm0, %ymm2
 ; HASWELL-NEXT:    vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
 ; HASWELL-NEXT:    vmulps %ymm3, %ymm2, %ymm4

 ; BTVER2-NEXT:    retq
 ;
 ; SANDY-LABEL: v16f32_one_step_2_divs:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    vrcpps %ymm0, %ymm2
 ; SANDY-NEXT:    vmulps %ymm2, %ymm0, %ymm0
 ; SANDY-NEXT:    vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; SANDY-NEXT:    vsubps %ymm0, %ymm3, %ymm0
-; SANDY-NEXT:    vrcpps %ymm1, %ymm4
 ; SANDY-NEXT:    vmulps %ymm0, %ymm2, %ymm0
 ; SANDY-NEXT:    vaddps %ymm0, %ymm2, %ymm0
-; SANDY-NEXT:    vmulps %ymm4, %ymm1, %ymm1
+; SANDY-NEXT:    vrcpps %ymm1, %ymm2
+; SANDY-NEXT:    vmulps %ymm2, %ymm1, %ymm1
 ; SANDY-NEXT:    vsubps %ymm1, %ymm3, %ymm1
-; SANDY-NEXT:    vmulps %ymm1, %ymm4, %ymm1
-; SANDY-NEXT:    vaddps %ymm1, %ymm4, %ymm1
+; SANDY-NEXT:    vmulps %ymm1, %ymm2, %ymm1
+; SANDY-NEXT:    vaddps %ymm1, %ymm2, %ymm1
 ; SANDY-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm2
 ; SANDY-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
 ; SANDY-NEXT:    vmulps %ymm0, %ymm3, %ymm0
 ; SANDY-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; SANDY-NEXT:    retq
 ;
 ; HASWELL-LABEL: v16f32_one_step_2_divs:
 ; HASWELL:       # %bb.0:

 ; SANDY-NEXT:    vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
 ; SANDY-NEXT:    vsubps %ymm3, %ymm4, %ymm3
 ; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm3
 ; SANDY-NEXT:    vaddps %ymm3, %ymm2, %ymm2
 ; SANDY-NEXT:    vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
 ; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm5
 ; SANDY-NEXT:    vmulps %ymm5, %ymm0, %ymm0
 ; SANDY-NEXT:    vsubps %ymm0, %ymm3, %ymm0
-; SANDY-NEXT:    vrcpps %ymm1, %ymm3
 ; SANDY-NEXT:    vmulps %ymm0, %ymm2, %ymm0
 ; SANDY-NEXT:    vaddps %ymm0, %ymm5, %ymm0
-; SANDY-NEXT:    vmulps %ymm3, %ymm1, %ymm2
-; SANDY-NEXT:    vsubps %ymm2, %ymm4, %ymm2
-; SANDY-NEXT:    vmulps %ymm2, %ymm3, %ymm2
-; SANDY-NEXT:    vaddps %ymm2, %ymm3, %ymm2
+; SANDY-NEXT:    vrcpps %ymm1, %ymm2
+; SANDY-NEXT:    vmulps %ymm2, %ymm1, %ymm3
+; SANDY-NEXT:    vsubps %ymm3, %ymm4, %ymm3
+; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm3
+; SANDY-NEXT:    vaddps %ymm3, %ymm2, %ymm2
 ; SANDY-NEXT:    vmovaps {{.*#+}} ymm3 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
 ; SANDY-NEXT:    vmulps %ymm3, %ymm2, %ymm4
 ; SANDY-NEXT:    vmulps %ymm4, %ymm1, %ymm1
 ; SANDY-NEXT:    vsubps %ymm1, %ymm3, %ymm1
 ; SANDY-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; SANDY-NEXT:    vaddps %ymm1, %ymm4, %ymm1
 ; SANDY-NEXT:    retq
 ;

 ; BTVER2-NEXT:    vrcpps %ymm1, %ymm1
 ; BTVER2-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
 ; BTVER2-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
 ; BTVER2-NEXT:    retq
 ;
 ; SANDY-LABEL: v16f32_no_step2:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    vrcpps %ymm0, %ymm0
-; SANDY-NEXT:    vrcpps %ymm1, %ymm1
 ; SANDY-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; SANDY-NEXT:    vrcpps %ymm1, %ymm1
 ; SANDY-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
 ; SANDY-NEXT:    retq
 ;
 ; HASWELL-LABEL: v16f32_no_step2:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    vrcpps %ymm0, %ymm0
 ; HASWELL-NEXT:    vrcpps %ymm1, %ymm1
 ; HASWELL-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0

llvm/test/CodeGen/X86/scheduler-asm-moves.mir

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $eax, $edx
 
     ; CHECK-LABEL: name: synproxy_send_tcp_ipv6
     ; CHECK: liveins: $eax, $edx
     ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY $eax
     ; CHECK-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm $noreg, 1, $noreg, @csum_ipv6_magic_saddr, $noreg :: (dereferenceable load (s8) from `i8* getelementptr inbounds (%struct.in6_addr, %struct.in6_addr* @csum_ipv6_magic_saddr, i32 0, i32 0, i32 0)`)
     ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, @csum_ipv6_magic_daddr, $noreg :: (dereferenceable load (s32) from @csum_ipv6_magic_daddr, !tbaa !4)
     ; CHECK-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, @csum_ipv6_magic_proto, $noreg :: (dereferenceable load (s32) from @csum_ipv6_magic_proto, !tbaa !4)
     ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
     ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 2293771 /* regdef-ec:GR32 */, def early-clobber %2, 65545 /* reguse:GR8 */, [[MOV8rm]], 2293769 /* reguse:GR32 */, [[MOV32rm]], 2293769 /* reguse:GR32 */, [[MOV32r0_]], 2293769 /* reguse:GR32 */, [[MOV32rm1]], 12 /* clobber */, implicit-def dead early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def dead early-clobber $eflags, !8
     ; CHECK-NEXT: MOV32mr $noreg, 1, $noreg, @csum_ipv6_magic_sum, $noreg, %2 :: (store (s32) into @csum_ipv6_magic_sum, !tbaa !4)
     ; CHECK-NEXT: [[MOV32rm2:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, @synproxy_send_tcp_ipv6_nskb, $noreg :: (dereferenceable load (s32) from `i8** bitcast (%struct.sk_buff** @synproxy_send_tcp_ipv6_nskb to i8**)`, !tbaa !9)
     ; CHECK-NEXT: OR8mi [[MOV32rm2]], 1, $noreg, 0, $noreg, 3, implicit-def dead $eflags :: (store (s8) into %ir.4), (load (s8) from %ir.4)
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $eax
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
-    ; CHECK-NEXT: [[MOV8rm1:%[0-9]+]]:gr8 = MOV8rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.5, !tbaa !11)
+    ; CHECK-NEXT: [[MOV8rm1:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.5, !tbaa !11)
     ; CHECK-NEXT: MOV8mr $noreg, 1, $noreg, @synproxy_send_tcp_ipv6_fl6, $noreg, [[MOV8rm1]] :: (store (s8) into `i8* getelementptr inbounds (%struct.in6_addr, %struct.in6_addr* @synproxy_send_tcp_ipv6_fl6, i32 0, i32 0, i32 0)`, !tbaa !11)
-    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]].sub_8bit
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]].sub_8bit
     ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
     ; CHECK-NEXT: TCRETURNdi @fl6nthsecurity_skb_classify_flow, 0, csr_32, implicit $esp, implicit $ssp, implicit $eax
     %1:gr32 = COPY $edx
     %0:gr32_abcd = COPY $eax
     %3:gr8 = MOV8rm $noreg, 1, $noreg, @csum_ipv6_magic_saddr, $noreg :: (dereferenceable load (s8) from `i8* getelementptr inbounds (%struct.in6_addr, %struct.in6_addr* @csum_ipv6_magic_saddr, i32 0, i32 0, i32 0)`)
     %4:gr32 = MOV32rm $noreg, 1, $noreg, @csum_ipv6_magic_daddr, $noreg :: (dereferenceable load (s32) from @csum_ipv6_magic_daddr, !tbaa !5)
     %6:gr32 = MOV32rm $noreg, 1, $noreg, @csum_ipv6_magic_proto, $noreg :: (dereferenceable load (s32) from @csum_ipv6_magic_proto, !tbaa !5)
     %5:gr32 = MOV32r0 implicit-def dead $eflags

llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll

 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtss %xmm0, %xmm1
 ; NHM-NEXT:    movaps %xmm0, %xmm2
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; NHM-NEXT:    mulss %xmm2, %xmm3
 ; NHM-NEXT:    mulss %xmm1, %xmm2
 ; NHM-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    mulss %xmm3, %xmm2
+; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    andnps %xmm2, %xmm0
 ; NHM-NEXT:    retq
 ;
 ; FAST-SCALAR-LABEL: f32_no_daz:
 ; FAST-SCALAR:       # %bb.0:
 ; FAST-SCALAR-NEXT:    vsqrtss %xmm0, %xmm0, %xmm0
 ; FAST-SCALAR-NEXT:    retq
   %call = tail call fast float @llvm.sqrt.f32(float %f) #2
   ret float %call
 }
 
 define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 {
 ; NHM-LABEL: v4f32_no_daz:
 ; NHM:       # %bb.0:
 ; NHM-NEXT:    rsqrtps %xmm0, %xmm1
 ; NHM-NEXT:    movaps %xmm0, %xmm2
 ; NHM-NEXT:    mulps %xmm1, %xmm2
 ; NHM-NEXT:    movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
 ; NHM-NEXT:    mulps %xmm2, %xmm3
 ; NHM-NEXT:    mulps %xmm1, %xmm2
 ; NHM-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    mulps %xmm3, %xmm2
+; NHM-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; NHM-NEXT:    movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
 ; NHM-NEXT:    cmpleps %xmm0, %xmm1
 ; NHM-NEXT:    andps %xmm2, %xmm1
 ; NHM-NEXT:    movaps %xmm1, %xmm0
 ; NHM-NEXT:    retq
 ;
 ; SNB-LABEL: v4f32_no_daz:
 ; SNB:       # %bb.0:
 ; SNB-NEXT:    vrsqrtps %xmm0, %xmm1
 ; SNB-NEXT:    vmulps %xmm1, %xmm0, %xmm2
 ; SNB-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
 ; SNB-NEXT:    vmulps %xmm1, %xmm2, %xmm1
 ; SNB-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; SNB-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; SNB-NEXT:    vmulps %xmm1, %xmm3, %xmm1
+; SNB-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; SNB-NEXT:    vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
 ; SNB-NEXT:    vcmpleps %xmm0, %xmm2, %xmm0
 ; SNB-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; SNB-NEXT:    retq
 ;
 ; BDW-LABEL: v4f32_no_daz:
 ; BDW:       # %bb.0:
 ; BDW-NEXT:    vrsqrtps %xmm0, %xmm1

 ;
 ; SNB-LABEL: v8f32_no_daz:
 ; SNB:       # %bb.0:
 ; SNB-NEXT:    vrsqrtps %ymm0, %ymm1
 ; SNB-NEXT:    vmulps %ymm1, %ymm0, %ymm2
 ; SNB-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm3
 ; SNB-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; SNB-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
-; SNB-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
 ; SNB-NEXT:    vmulps %ymm1, %ymm3, %ymm1
+; SNB-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
 ; SNB-NEXT:    vmovaps {{.*#+}} ymm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
 ; SNB-NEXT:    vcmpleps %ymm0, %ymm2, %ymm0
 ; SNB-NEXT:    vandps %ymm1, %ymm0, %ymm0
 ; SNB-NEXT:    retq
 ;
 ; BDW-LABEL: v8f32_no_daz:
 ; BDW:       # %bb.0:
 ; BDW-NEXT:    vrsqrtps %ymm0, %ymm1

llvm/test/CodeGen/X86/sqrt-fastmath.ll

 ; SSE:       # %bb.0:
 ; SSE-NEXT:    rsqrtss %xmm0, %xmm1
 ; SSE-NEXT:    movaps %xmm0, %xmm2
 ; SSE-NEXT:    mulss %xmm1, %xmm2
 ; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; SSE-NEXT:    mulss %xmm2, %xmm3
 ; SSE-NEXT:    mulss %xmm1, %xmm2
 ; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    mulss %xmm3, %xmm2
+; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    andnps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: finite_f32_estimate_ieee_ninf:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
 ; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
 ; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
 ; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
+; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: finite_f32_estimate_ieee_ninf:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm0
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
-; AVX512-NEXT:    vxorps %xmm0, %xmm0, %xmm0
-; AVX512-NEXT:    vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT:    vmovaps %xmm1, %xmm0
+; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm2
+; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
+; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
+; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
 ; AVX512-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %f) #2
   ret float %call
 }
 
 define float @finite_f32_estimate_daz(float %f) #4 {
 ; SSE-LABEL: finite_f32_estimate_daz:
 ; SSE:       # %bb.0:

 ; SSE:       # %bb.0:
 ; SSE-NEXT:    rsqrtss %xmm0, %xmm1
 ; SSE-NEXT:    movaps %xmm0, %xmm2
 ; SSE-NEXT:    mulss %xmm1, %xmm2
 ; SSE-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; SSE-NEXT:    mulss %xmm2, %xmm3
 ; SSE-NEXT:    mulss %xmm1, %xmm2
 ; SSE-NEXT:    addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    mulss %xmm3, %xmm2
+; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    andnps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: sqrtf_check_denorms_ninf:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
 ; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm2
 ; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
 ; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
+; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: sqrtf_check_denorms_ninf:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm2
-; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX512-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm0
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
-; AVX512-NEXT:    vxorps %xmm0, %xmm0, %xmm0
-; AVX512-NEXT:    vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT:    vmovaps %xmm1, %xmm0
+; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm2
+; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
+; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
+; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
 ; AVX512-NEXT:    retq
   %call = tail call ninf afn float @__sqrtf_finite(float %x) #2
   ret float %call
 }
 
 define <4 x float> @sqrt_v4f32_check_denorms(<4 x float> %x) #3 {
 ; SSE-LABEL: sqrt_v4f32_check_denorms:
 ; SSE:       # %bb.0:

 ; SSE:       # %bb.0:
 ; SSE-NEXT:    rsqrtps %xmm0, %xmm1
 ; SSE-NEXT:    movaps %xmm0, %xmm2
 ; SSE-NEXT:    mulps %xmm1, %xmm2
 ; SSE-NEXT:    movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
 ; SSE-NEXT:    mulps %xmm2, %xmm3
 ; SSE-NEXT:    mulps %xmm1, %xmm2
 ; SSE-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    mulps %xmm3, %xmm2
+; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
 ; SSE-NEXT:    cmpleps %xmm0, %xmm1
 ; SSE-NEXT:    andps %xmm2, %xmm1
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: sqrt_v4f32_check_denorms_ninf:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vrsqrtps %xmm0, %xmm1
 ; AVX1-NEXT:    vmulps %xmm1, %xmm0, %xmm2
 ; AVX1-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm3
 ; AVX1-NEXT:    vmulps %xmm1, %xmm2, %xmm1
 ; AVX1-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vmulps %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX1-NEXT:    vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
 ; AVX1-NEXT:    vcmpleps %xmm0, %xmm2, %xmm0
 ; AVX1-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: sqrt_v4f32_check_denorms_ninf:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vrsqrtps %xmm0, %xmm1

 ; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    andnps %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: f32_estimate2:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
-; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm1
-; AVX1-NEXT:    vandnps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm1
+; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT:    vandnps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: f32_estimate2:
 ; AVX512:       # %bb.0:
-; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm1
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm0
-; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
-; AVX512-NEXT:    vxorps %xmm0, %xmm0, %xmm0
-; AVX512-NEXT:    vmovss %xmm0, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT:    vmovaps %xmm1, %xmm0
+; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
+; AVX512-NEXT:    vrsqrtss %xmm0, %xmm0, %xmm2
+; AVX512-NEXT:    vandps %xmm1, %xmm0, %xmm1
+; AVX512-NEXT:    vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
+; AVX512-NEXT:    vmulss %xmm2, %xmm0, %xmm0
+; AVX512-NEXT:    vxorps %xmm1, %xmm1, %xmm1
+; AVX512-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
 ; AVX512-NEXT:    retq
   %sqrt = tail call fast float @llvm.sqrt.f32(float %x)
   ret float %sqrt
 }
 
 define <4 x float> @v4f32_no_estimate(<4 x float> %x) #0 {
 ; SSE-LABEL: v4f32_no_estimate:
 ; SSE:       # %bb.0:

 ; SSE-NEXT:    cmpleps %xmm0, %xmm1
 ; SSE-NEXT:    andps %xmm2, %xmm1
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: v4f32_estimate2:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vrsqrtps %xmm0, %xmm1
-; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
-; AVX1-NEXT:    vmulps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vmovaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
-; AVX1-NEXT:    vcmpleps %xmm2, %xmm1, %xmm1
-; AVX1-NEXT:    vandps %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vmulps %xmm1, %xmm0, %xmm1
+; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX1-NEXT:    vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
+; AVX1-NEXT:    vcmpleps %xmm0, %xmm2, %xmm0
+; AVX1-NEXT:    vandps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: v4f32_estimate2:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vrsqrtps %xmm0, %xmm1
 ; AVX512-NEXT:    vmulps %xmm1, %xmm0, %xmm1
 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
 ; AVX512-NEXT:    vandps %xmm2, %xmm0, %xmm0

 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vrsqrtps %ymm0, %ymm2
 ; AVX1-NEXT:    vmovaps {{.*#+}} ymm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
 ; AVX1-NEXT:    vmulps %ymm3, %ymm2, %ymm4
 ; AVX1-NEXT:    vmulps %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vmulps %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vmovaps {{.*#+}} ymm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
 ; AVX1-NEXT:    vaddps %ymm2, %ymm0, %ymm0
+; AVX1-NEXT:    vrsqrtps %ymm1, %ymm5
 ; AVX1-NEXT:    vmulps %ymm0, %ymm4, %ymm0
-; AVX1-NEXT:    vrsqrtps %ymm1, %ymm4
-; AVX1-NEXT:    vmulps %ymm3, %ymm4, %ymm3
-; AVX1-NEXT:    vmulps %ymm4, %ymm1, %ymm1
-; AVX1-NEXT:    vmulps %ymm4, %ymm1, %ymm1
+; AVX1-NEXT:    vmulps %ymm3, %ymm5, %ymm3
+; AVX1-NEXT:    vmulps %ymm5, %ymm1, %ymm1
+; AVX1-NEXT:    vmulps %ymm5, %ymm1, %ymm1
 ; AVX1-NEXT:    vaddps %ymm2, %ymm1, %ymm1
 ; AVX1-NEXT:    vmulps %ymm1, %ymm3, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: v16f32_estimate:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vrsqrt14ps %zmm0, %zmm1
 ; AVX512-NEXT:    vmulps %zmm1, %zmm0, %zmm0

 define <4 x float> @div_sqrt_fabs_v4f32_fmf(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
 ; SSE-LABEL: div_sqrt_fabs_v4f32_fmf:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    rsqrtps %xmm2, %xmm3
 ; SSE-NEXT:    mulps %xmm3, %xmm2
 ; SSE-NEXT:    mulps %xmm3, %xmm2
 ; SSE-NEXT:    addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
 ; SSE-NEXT:    mulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE-NEXT:    mulps %xmm2, %xmm3
 ; SSE-NEXT:    andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT:    mulps %xmm2, %xmm3
 ; SSE-NEXT:    divps %xmm1, %xmm3
 ; SSE-NEXT:    mulps %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: div_sqrt_fabs_v4f32_fmf:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vrsqrtps %xmm2, %xmm3
 ; AVX1-NEXT:    vmulps %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vmulps %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
 ; AVX1-NEXT:    vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
-; AVX1-NEXT:    vmulps %xmm2, %xmm3, %xmm2
 ; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT:    vmulps %xmm2, %xmm3, %xmm2
 ; AVX1-NEXT:    vdivps %xmm1, %xmm2, %xmm1
 ; AVX1-NEXT:    vmulps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: div_sqrt_fabs_v4f32_fmf:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vrsqrtps %xmm2, %xmm3
 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
 ; AVX512-NEXT:    vmulps %xmm4, %xmm3, %xmm4
 ; AVX512-NEXT:    vmulps %xmm3, %xmm2, %xmm2
 ; AVX512-NEXT:    vmulps %xmm3, %xmm2, %xmm2
 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
 ; AVX512-NEXT:    vaddps %xmm3, %xmm2, %xmm2
-; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
 ; AVX512-NEXT:    vmulps %xmm2, %xmm4, %xmm2
+; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
 ; AVX512-NEXT:    vandps %xmm3, %xmm1, %xmm1
 ; AVX512-NEXT:    vdivps %xmm1, %xmm2, %xmm1
 ; AVX512-NEXT:    vmulps %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z)
   %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
   %m = fmul <4 x float> %a, %s
   %d = fdiv arcp <4 x float> %x, %m
   ret <4 x float> %d
 }
 
 ; No estimates for f64, so do not convert fabs into an fmul.
 
 define double @div_sqrt_fabs_f64(double %x, double %y, double %z) {
 ; SSE-LABEL: div_sqrt_fabs_f64:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    sqrtsd %xmm2, %xmm2
 ; SSE-NEXT:    andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT:    sqrtsd %xmm2, %xmm2
 ; SSE-NEXT:    mulsd %xmm2, %xmm1
 ; SSE-NEXT:    divsd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: div_sqrt_fabs_f64:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vsqrtsd %xmm2, %xmm2, %xmm2
 ; AVX-NEXT:    vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX-NEXT:    vsqrtsd %xmm2, %xmm2, %xmm2
 ; AVX-NEXT:    vmulsd %xmm1, %xmm2, %xmm1
 ; AVX-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %s = call fast double @llvm.sqrt.f64(double %z)
   %a = call fast double @llvm.fabs.f64(double %y)
   %m = fmul fast double %s, %a
   %d = fdiv fast double %x, %m
   ret double %d

llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll

 }
 
 define double @test_v16f64(double %a0, <16 x double> %a1) {
 ; SSE-LABEL: test_v16f64:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addpd %xmm6, %xmm2
 ; SSE-NEXT:    addpd %xmm7, %xmm3
 ; SSE-NEXT:    addpd %xmm5, %xmm1
-; SSE-NEXT:    addpd %xmm3, %xmm1
 ; SSE-NEXT:    addpd {{[0-9]+}}(%rsp), %xmm4
+; SSE-NEXT:    addpd %xmm3, %xmm1
 ; SSE-NEXT:    addpd %xmm2, %xmm4
 ; SSE-NEXT:    addpd %xmm1, %xmm4
 ; SSE-NEXT:    movapd %xmm4, %xmm1
 ; SSE-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1]
 ; SSE-NEXT:    addsd %xmm4, %xmm1
 ; SSE-NEXT:    addsd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;

llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll

 }
 
 define double @test_v16f64(double %a0, <16 x double> %a1) {
 ; SSE-LABEL: test_v16f64:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    mulpd %xmm6, %xmm2
 ; SSE-NEXT:    mulpd %xmm7, %xmm3
 ; SSE-NEXT:    mulpd %xmm5, %xmm1
-; SSE-NEXT:    mulpd %xmm3, %xmm1
 ; SSE-NEXT:    mulpd {{[0-9]+}}(%rsp), %xmm4
+; SSE-NEXT:    mulpd %xmm3, %xmm1
 ; SSE-NEXT:    mulpd %xmm2, %xmm4
 ; SSE-NEXT:    mulpd %xmm1, %xmm4
 ; SSE-NEXT:    movapd %xmm4, %xmm1
 ; SSE-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1]
 ; SSE-NEXT:    mulsd %xmm4, %xmm1
 ; SSE-NEXT:    mulsd %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;

llvm/test/CodeGen/X86/vector-shuffle-combining.ll

 ; SSE2-NEXT:    retq
 ;
 ; SSSE3-LABEL: PR45604:
 ; SSSE3:       # %bb.0:
 ; SSSE3-NEXT:    movdqa (%rsi), %xmm0
 ; SSSE3-NEXT:    movdqa %xmm0, %xmm1
 ; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,1],zero,zero,zero,zero,zero,zero,xmm1[2,3],zero,zero,zero,zero,zero,zero
 ; SSSE3-NEXT:    movdqa {{.*#+}} xmm2 = [0,0,0,0,11,0,0,0,0,0,0,0,11,0,0,0]
+; SSSE3-NEXT:    por %xmm2, %xmm1
 ; SSSE3-NEXT:    movdqa %xmm0, %xmm3
 ; SSSE3-NEXT:    pshufb {{.*#+}} xmm3 = xmm3[4,5],zero,zero,zero,zero,zero,zero,xmm3[6,7],zero,zero,zero,zero,zero,zero
-; SSSE3-NEXT:    por %xmm2, %xmm1
 ; SSSE3-NEXT:    por %xmm2, %xmm3
 ; SSSE3-NEXT:    movdqa %xmm0, %xmm4
 ; SSSE3-NEXT:    pshufb {{.*#+}} xmm4 = xmm4[8,9],zero,zero,zero,zero,zero,zero,xmm4[10,11],zero,zero,zero,zero,zero,zero
 ; SSSE3-NEXT:    por %xmm2, %xmm4
 ; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[12,13],zero,zero,zero,zero,zero,zero,xmm0[14,15],zero,zero,zero,zero,zero,zero
 ; SSSE3-NEXT:    por %xmm2, %xmm0
 ; SSSE3-NEXT:    movdqa %xmm0, 48(%rdi)
 ; SSSE3-NEXT:    movdqa %xmm4, 32(%rdi)