make getRegPressureLimit arg const NFC

[nickdesaulniers]

I don't plan to land the child patch, so let's "just let sleeping dogs lie."

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

public:
 
   /// Return the register pressure "high water mark" for the specific register
   /// class. The scheduler is in high register pressure mode (for the specific
   /// register class) if it goes over the limit.
   ///
   /// Note: this is the old register pressure model that relies on a manually
   /// specified representative register class per value type.
   virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                                       MachineFunction &MF) const {
+                                       const MachineFunction &MF) const {
     return 0;
   }
 
   /// Return a heuristic for the machine scheduler to compare the profitability
   /// of increasing one register pressure set versus another.  The scheduler
   /// will prefer increasing the register pressure of the set which returns
   /// the largest value for this function.
   virtual unsigned getRegPressureSetScore(const MachineFunction &MF,

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

public:
   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
   bool hasBasePointer(const MachineFunction &MF) const;
   unsigned getBaseRegister() const;
 
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const override;
+                               const MachineFunction &MF) const override;
 
   unsigned getLocalAddressRegister(const MachineFunction &MF) const;
   bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
 
   /// SrcRC and DstRC will be morphed into NewRC if this returns true
   bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
                       unsigned SubReg, const TargetRegisterClass *DstRC,
                       unsigned DstSubReg, const TargetRegisterClass *NewRC,

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   // If we get here, the immediate doesn't fit into the instruction.  We folded
   // as much as possible above.  Handle the rest, providing a register that is
   // SP+LargeImm.
   Register ScratchReg =
       createScratchRegisterForInstruction(MI, FIOperandNum, TII);
   emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
 }
 
-unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
-                                                  MachineFunction &MF) const {
+unsigned
+AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
+                                         const MachineFunction &MF) const {
   const AArch64FrameLowering *TFI = getFrameLowering(MF);
 
   switch (RC->getID()) {
   default:
     return 0;
   case AArch64::GPR32RegClassID:
   case AArch64::GPR32spRegClassID:
   case AArch64::GPR32allRegClassID:

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

bool shouldCoalesce(MachineInstr *MI,
                       const TargetRegisterClass *SrcRC,
                       unsigned SubReg,
                       const TargetRegisterClass *DstRC,
                       unsigned DstSubReg,
                       const TargetRegisterClass *NewRC,
                       LiveIntervals &LIS) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const override;
+                               const MachineFunction &MF) const override;
 
   unsigned getRegPressureSetLimit(const MachineFunction &MF,
                                   unsigned Idx) const override;
 
   const int *getRegUnitPressureSets(unsigned RegUnit) const override;
 
   MCRegister getReturnAddressReg(const MachineFunction &MF) const;
 

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

bool SIRegisterInfo::shouldCoalesce(MachineInstr *MI,
   // Always allow dword coalescing.
   if (SrcSize <= 32 || DstSize <= 32)
     return true;
 
   return NewSize <= DstSize || NewSize <= SrcSize;
 }
 
 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
-                                             MachineFunction &MF) const {
+                                             const MachineFunction &MF) const {
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
   unsigned Occupancy = ST.getOccupancyWithLocalMemSize(MFI->getLDSSize(),
                                                        MF.getFunction());
   switch (RC->getID()) {
   default:
     return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF);
   case AMDGPU::VGPR_32RegClassID:

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

public:
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
   const TargetRegisterClass *
   getLargestLegalSuperClass(const TargetRegisterClass *RC,
                             const MachineFunction &MF) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const override;
+                               const MachineFunction &MF) const override;
 
   bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
                              SmallVectorImpl<MCPhysReg> &Hints,
                              const MachineFunction &MF, const VirtRegMap *VRM,
                              const LiveRegMatrix *Matrix) const override;
 
   void updateRegAllocHint(Register Reg, Register NewReg,
                           MachineFunction &MF) const override;

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
   if (RC == &ARM::CCRRegClass)
     return &ARM::rGPRRegClass;  // Can't copy CCR registers.
   return RC;
 }
 
 unsigned
 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
-                                         MachineFunction &MF) const {
+                                         const MachineFunction &MF) const {
   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
   const ARMFrameLowering *TFI = getFrameLowering(MF);
 
   switch (RC->getID()) {
   default:
     return 0;
   case ARM::tGPRRegClassID: {
     // hasFP ends up calling getMaxCallFrameComputed() which may not be

llvm/lib/Target/Mips/MipsRegisterInfo.h

public:
   /// Get PIC indirect call register
   static unsigned getPICCallReg();
 
   /// Code Generation virtual methods...
   const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
                                                 unsigned Kind) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const override;
+                               const MachineFunction &MF) const override;
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
   static const uint32_t *getMips16RetHelperMask();
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

case MipsPtrClass::GlobalPointer:
     return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
   }
 
   llvm_unreachable("Unknown pointer kind");
 }
 
 unsigned
 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
-                                      MachineFunction &MF) const {
+                                      const MachineFunction &MF) const {
   switch (RC->getID()) {
   default:
     return 0;
   case Mips::GPR32RegClassID:
   case Mips::GPR64RegClassID:
   case Mips::DSPRRegClassID: {
     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
     return 28 - TFI->hasFP(MF);

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

public:
   }
 
   /// getPointerRegClass - Return the register class to use to hold pointers.
   /// This is used for addressing modes.
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const override;
+                               const MachineFunction &MF) const override;
 
   const TargetRegisterClass *
   getLargestLegalSuperClass(const TargetRegisterClass *RC,
                             const MachineFunction &MF) const override;
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

case PPC::BUILD_UACC: {
       break;
     }
     }
   }
   return BaseImplRetVal;
 }
 
 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
-                                              MachineFunction &MF) const {
+                                              const MachineFunction &MF) const {
   const PPCFrameLowering *TFI = getFrameLowering(MF);
   const unsigned DefaultSafety = 1;
 
   switch (RC->getID()) {
   default:
     return 0;
   case PPC::G8RC_NOX0RegClassID:
   case PPC::GPRC_NOR0RegClassID:

llvm/lib/Target/X86/X86RegisterInfo.h

public:
   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
   /// getGPRsForTailCall - Returns a register class with registers that can be
   /// used in forming tail calls.
   const TargetRegisterClass *
   getGPRsForTailCall(const MachineFunction &MF) const;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
-                               MachineFunction &MF) const override;
+                               const MachineFunction &MF) const override;
 
   /// getCalleeSavedRegs - Return a null-terminated list of all of the
   /// callee-save registers on this target.
   const MCPhysReg *
   getCalleeSavedRegs(const MachineFunction* MF) const override;
   const MCPhysReg *
   getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,

llvm/lib/Target/X86/X86RegisterInfo.cpp

if (RC == &X86::CCRRegClass) {
     if (Is64Bit)
       return &X86::GR64RegClass;
     else
       return &X86::GR32RegClass;
   }
   return RC;
 }
 
-unsigned
-X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
-                                     MachineFunction &MF) const {
+unsigned X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
+                                              const MachineFunction &MF) const {
   const X86FrameLowering *TFI = getFrameLowering(MF);
 
   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
   switch (RC->getID()) {
   default:
     return 0;
   case X86::GR32RegClassID:
     return 4 - FPDiff;