The [2/3] Fix mangle problem when variable used in inline asm （Add modifier P for ARR[BaseReg+IndexReg+..]）

[xiangzhangllvm]

Summary

I encounter serval problems about using Global Value (GV) in inline asm. ( both today and before)
I think it is may be a right time to discuss/fix it.

Simply speaking:
We encounter a mangle problem in inlineasm when it directly use Global Value's name.
D113096 once fix the mangle problem. But it cause some other problems.
D115225 and D116090 reverted the D113096 to fix the new fails.
But it didn't fix the mangle problem in inline asm.

So I create 2 patches to fix it.
The first is D120886 (only do revert).
The other is current patch [2/3].
The Next one [3/3] at D121785.

Mangler problem with GV used in inline asm
Currently (and before too) we directly use the GV’s name in inline asm for some cases (I don’t know the early reason, but that doesn’t make sense to me)

For example (Mangler problem)

$cat t.c
int GArr[]={0,1,3,};
int foo(int x) {
  __asm {mov eax, 0};
  __asm {mov DWORD PTR GArr[ecx+eax*2+2], 4};

  return GArr[x];
}

Let’s compile it with clang -fasm-blocks -target i686-windows-msvc t.c -S

15 _foo:                                   # @foo
16 # %bb.0:                                # %entry
…
29         movl    $4, GArr+2(ecx,%eax,2)       # inline asm
...
34         movl    _GArr(,%eax,4), %eax   # read GArr[x] to eax
..
37         retl
…
42 _GArr:
43         .long   0                               # 0x0
44         .long   1                               # 0x1
45         .long   3                               # 0x3

Bug: The Mangler didn’t work on the GArr in inline asm, so it can’t rename to _GArr
(Reason: due to we didn’t connected the GArr with its real value in parse process, it just a string name)

History fix (build fail)
I find Shengchen and Pheobe has fix the relation problem before.
They once try to fix it by connecting the GArr with its real value in parse process, but quickly revert it. Because meet 2 fails:
1st Fail: We can't an’t build upper code.
clang -fasm-blocks t.c -S

test.c:5:3: error: BaseReg/IndexReg already set!
  __asm {mov DWORD PTR GArr[ecx+eax*2+2], 4};
  ^
<inline asm>:2:48: note: instantiated into assembly here
        mov DWORD PTR [rip + offset GArr][ecx + eax * 2 + 2], 4
                                                      ^
1 error generated.

2n Fail: We can’t build upper code in PIC mode even we remove the base reg (this is not a new fail).

int GArr[]={0,1,3,};
int foo(int x) {
  __asm {mov eax, 0};
  __asm {mov DWORD PTR GArr[eax*2+2], 4};
 // __asm {mov DWORD PTR GArr[ecx+eax*2+2], 4};

  return GArr[x];
}

$clang -fasm-blocks t.c -fpic -S

test.c:5:3: error: base register is 64-bit, but index register is not
  __asm {mov DWORD PTR GArr[eax*2+2], 4};
  ^
<inline asm>:2:16: note: instantiated into assembly here
        mov DWORD PTR [rax][eax * 2 + 2], 4
                      ^
1 error generated.

Status of current LLVM: （has relocation problem in fpic/ GCC too）
$clang -fasm-blocks t-pic.c -fpic -S

…
20         movq    GArr@GOTPCREL(%rip), %rax
23         movl    $4, **GArr**+2(,%eax,2)                   # inline asm   (not right code, should accessed from GOT)
26         movslq  -4(%rbp), %rcx
27         movq    GArr@GOTPCREL(%rip), %rax
28         movl    (%rax,%rcx,4), %eax                 # read GArr[x] to eax
31         retq
…

Though current llvm successful generate out the code for inline asm, but it is not right code.
Because in PIC mode, the GArr should be accessed from GOT. This will cause segment fault.

How to fix
For GV in inline asm, I prefer to keep the connection between the GV and its real value, (not just keep a GV name in inline asm).
So the GV can be seen in all the optimization pass.

So 1st step, I will revert the patch D115225 and D116090 at D120886
And then 2nd step, I will fix the upper bug Fail 1 (current patch).

[efriedma]

llvm/lib/MC/MCParser/AsmParser.cpp

5990

If I'm understanding correctly, this is trying to detect two adjacent expressions in a specific form, and then transform one of them so they can be concatenated? This is way too much magic. If we aren't parsing expressions correctly, please fix the initial parse; don't fudge the expressions afterwards.

[xiangzhangllvm]

llvm/lib/MC/MCParser/AsmParser.cpp

5990

I think you understand a part of it.
Here the instruction parsing are finished. The Operands info written into AsmStrRewrites[].
Let me take a example:
Both follow cases will get same Operands info into AsmStrRewrites[i] (ARR) and AsmStrRewrites[i+1] ([edx+eax*4])
Case 1:

mov     eax,ARR[edx+eax*4]

Case 2:

mov     eax,ARR ;   call  dword ptr[edx+eax*4]

So here code (line 5967-5990) is just to distinguish the 2 case.

For Case 1, we can not let ARR be a RIP related address, because it already has base reg and index reg. (We can't use 3 regs for a mem address)
For Case 2, it is no problem let ARR use RIP, the [edx+eax*4] are in another instruction.

[xiangzhangllvm]

llvm/lib/MC/MCParser/AsmParser.cpp

6160

MODIFIER :P will disable ASMPrinter print PC related style for a Global Address.

[LuoYuanke]

clang/test/CodeGen/ms-inline-asm-variables.c

14

Is the ":P" you added fit the below description from https://llvm.org/docs/LangRef.html#asm-template-argument-modifiers?

P: Print a memory reference or operand for use as the argument of a call instruction. (E.g. omit (rip), even though it’s PC-relative.)

Should the ":P" be specified only in -pic mode?

[LuoYuanke]

clang/test/CodeGen/ms-inline-asm-variables.c

14

Would you post the example code lowering from IR to assembly? I can't create an valid IR code with :P flag in https://godbolt.org/z/doP83Wr1a

[pengfei]

llvm/lib/MC/MCParser/AsmParser.cpp

5990

I agree with @efriedma and think the use of :P is hacky. I wrote an experiment patch which seems more concise D121072.

[xiangzhangllvm]

clang/test/CodeGen/ms-inline-asm-variables.c

14

Yes, it fit asm-template-argument-modifiers ,

P: Print a memory reference or operand for use as the argument of a call instruction. (E.g. omit (rip), even though it’s PC-relative.)

In fact, the real implement of "P" is only non-RIP in X86AsmPrinter

14

Try use llc to build it. The fail in https://godbolt.org/z/doP83Wr1a is not relation with "P"
(I can't logon my sever now)

llvm/lib/MC/MCParser/AsmParser.cpp

5990

I have explained that efriedma's understand is not correct. There is not concatenated them, just distinguish. PLS refer my previous explain.

and then transform one of them so they can be concatenated? This is way too much magic. If we ...

D121072 is still try to replace the Global name in IR/MIR, that is not good way to let follow process see it. (for example Mangler), and no reason do it on codegen. Using Modifer ":P", let all process see it, and let exsiting code to handle it, in my eye, is better.

[pengfei]

clang/test/CodeGen/ms-inline-asm-variables.c

14

As you showed, the P is used for call instruction. I don't think it's a good idea to apply it to non call instruction.

llvm/lib/MC/MCParser/AsmParser.cpp

5990

I think you misunderstood efriedma's point. He meant you should distinguish during parsing instead of distinguishing again.
Besides, I think you missed the case when ARR inside [], e.g, [gVar + ecx + ebx]. I agreed with him the logic is magic and not easy to understand.
D121072 intends do the mangling at front end. No following process is needed. I see front end do mangling sometime, so I think we can do it there.

[xiangzhangllvm]

clang/test/CodeGen/ms-inline-asm-variables.c

14

We can modify the description in asm-template-argument-modifiers , because the real implement of it is only print non-RIP in X86AsmPrinter. Now reason show non-rip address can on work on function label. That is not a beautiful design from beginning.

llvm/lib/MC/MCParser/AsmParser.cpp

5990

D121072 intends do the mangling at front end. No following process is needed.

We can't make sure "No following process is needed. "
One problem I can see is a symbol both used for lea and call. Call may @plt (or some others), but lea not.

In fact, D121072 is only the idea of do part print job at codegen. If it can be replaced in MIR why it can be directly repalced in IR ? Just try getSymbol (which will use mangler name)
That is not a good arch for IR/MIR. All the operands should be visible to IR/MIR.

[xiangzhangllvm]

llvm/lib/MC/MCParser/AsmParser.cpp

5990

Besides, I think you missed the case when ARR inside [], e.g, [gVar + ecx + ebx]

Let me refine the code to cover this case,
BTW, that is not a good/standard way to get address in this way.

[xiangzhangllvm]

llvm/lib/MC/MCParser/AsmParser.cpp

5990

I did a test in my local.
I think you mean the line 13 is fail. The fail is directly a “syntax error”， it is not supported by inlineasm before too. (No relation with this patch)

 1 // -fasm-blocks -S -emit-llvm
 2 int ARR[10];
 3 int ARR2[10];
 4 int main()
 5 {
 6         int x;
 7         ARR[6] = 7;
 8     __asm {
 9         mov      eax, 1
10         mov      ecx, 20
11         mov eax, DWORD PTR ARR[ecx + eax * 4]     // OK
12         mov eax, DWORD PTR [ARR + ecx + eax * 4]  // OK
13 //        mov eax, DWORD PTR ARR2[ARR + ecx + eax * 4]  // Err: cannot use more than one symbol in memory operand
14         mov DWORD PTR [x], eax
15     }
16 }

[xiangzhangllvm]

llvm/lib/MC/MCParser/AsmParser.cpp

6160

Let me take a look if here isSpecialIntelExprAppend can be checked earlier and cover case "[ARR + ecx + eax * 4]"

[pengfei]

llvm/lib/MC/MCParser/AsmParser.cpp

5990

One problem I can see is a symbol both used for lea and call. Call may @plt (or some others), but lea not.

I think you mean the problem in D109407? Seems the patch is still arguable. I think we can solve one by one. Since it's already fail, I don't think it's a problem for this one.

I think you mean the line 13 is fail.

No, I meant line 12. Why is it OK? I didn't find you handle it here. How about ARR is the last one, e.g., [ecx + eax * 4 + ARR] ?

My point is you almost do the parsing logic here again. It's redundant and fragile. If there's any update in the parser code, people is not aware they should update here too.

[xiangzhangllvm]

Generate IR for Mem symbol + IntelExpr in inline asm

Still need to fix PIC problem.
The mem ARR in asm(ARR[...]) can not transfer to PC-related style in PIC model.
Because the Parser and Printer will both share inline-asm Parser which can not handle "[ARR-BaseSymbol][...]".

[skan]

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

66

inline asm

67

ARR can be represented a displacement in non-pic mode. The comments need to be more specified.

llvm/lib/MC/MCParser/AsmParser.cpp

5947–5950

This function is unused?

6166–6170

This looks much better than the previous patch.

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

439

accident change?

[xiangzhangllvm]

llvm/lib/MC/MCParser/AsmParser.cpp

6166–6170

Here is similar with previous patch.
The only diff is use "if (AR.IntelExpRestricted)" replace of "if (function call)"
The previous patch can also fix the case "[ARR + ecx + eax * 4]".
The purpose I update the patch is let it more fit to fix PIC problem late.

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

439

I mark here to fix PIC problem in win32, l am writing another patch to fix it. Let me update it and remove the unused "getAffected".

[pengfei]

clang/test/CodeGen/ms-inline-asm-variables.c

6–12

Should these change to ${{{[0-9]}}:P} too?

24–33

How about local variables?

[xiangzhangllvm]

I'll update this patch and commit the [3/3] patch soon. Thanks!

clang/test/CodeGen/ms-inline-asm-variables.c

6–12

Currently Modifier ":P" is only need for function call or GV with both baseReg and IndexReg.
For one reg case, for example

"__asm {mov DWORD PTR GArr[rax*2+2], 4};"

current llvm has ability to handle it by split into 2 steps:

mov     ecx, dword ptr [eax + GArr@GOT]
mov     dword ptr [ecx + 2*eax + GArr+22], 4

24–33

Local variables is not allow use 2 regs in offset "[]", since it always fetch form stack or load. That must introduce extra regs.

[skan]

llvm/lib/MC/MCParser/AsmParser.cpp

6158

I think this is the first new usage of P here, so you update the llvm/docs/LangRef.rst

llvm/lib/Target/X86/AsmParser/X86Operand.h

72

inline asm, specify

[xiangzhangllvm]

llvm/lib/MC/MCParser/AsmParser.cpp

6158

Yes I am planning to, I'll update it in [3/3] patch. https://reviews.llvm.org/D121785

[skan]

LGTM

[xiangzhangllvm]

In D120887#3388196, @skan wrote:

LGTM

Thanks a lot! I'll commit it after [3/3] is accepted too. then push them at same time.

clang/test/CodeGen/ms-inline-asm-variables.c

 // REQUIRES: x86-registered-target
 // RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - | FileCheck %s
 
 int gVar;
 void t1() {
   // CHECK: add eax, dword ptr ${{[0-9]}}[eax]
   __asm add eax, dword ptr gVar[eax]
   // CHECK: add dword ptr ${{[0-9]}}[eax], eax
   __asm add dword ptr [eax+gVar], eax
   // CHECK: add ebx, dword ptr ${{[0-9]}}[ebx + $$270]
   __asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
   // CHECK: add dword ptr ${{[0-9]}}[ebx + $$828], ebx
   __asm add dword ptr [ebx + gVar + 828], ebx
-  // CHECK: add ecx, dword ptr ${{[0-9]}}[ecx + ecx * $$4 + $$4590]
+  // CHECK: add ecx, dword ptr ${{{[0-9]}}:P}[ecx + ecx * $$4 + $$4590]
   __asm add ecx, dword ptr gVar[4590 + ecx + ecx*4]
-  // CHECK: add dword ptr ${{[0-9]}}[ecx + ecx * $$8 + $$73], ecx
+  // CHECK: add dword ptr ${{{[0-9]}}:P}[ecx + ecx * $$8 + $$73], ecx
   __asm add dword ptr [gVar + ecx + 45 + 23 - 53 + 60 - 2 + ecx*8], ecx
-  // CHECK: add ${{[0-9]}}[ecx + ebx + $$7], eax
+  // CHECK: add ${{{[0-9]}}:P}[ecx + ebx + $$7], eax
   __asm add 1 + 1 + 2 + 3[gVar + ecx + ebx], eax
 }
 
 void t2(void) {
   int lVar;
   // CHECK: mov eax, dword ptr ${{[0-9]}}[eax]
   __asm mov eax, dword ptr lVar[eax]
   // CHECK: mov dword ptr ${{[0-9]}}[eax], eax
   __asm mov dword ptr [eax+lVar], eax
   // CHECK: mov ebx, dword ptr ${{[0-9]}}[ebx + $$270]
   __asm mov ebx, dword ptr lVar[271 - 82 + 81 + ebx]
   // CHECK: mov dword ptr ${{[0-9]}}[ebx + $$828], ebx
   __asm mov dword ptr [ebx + lVar + 828], ebx
   // CHECK: mov ${{[0-9]}}[ebx + $$47], eax
   __asm mov 5 + 8 + 13 + 21[lVar + ebx], eax
 }

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

public:
   virtual bool isImm() const = 0;
   /// isReg - Is this a register operand?
   virtual bool isReg() const = 0;
   virtual unsigned getReg() const = 0;
 
   /// isMem - Is this a memory operand?
   virtual bool isMem() const = 0;
 
+  /// isMemUseUpRegs - Is memory operand use up regs, for example, intel MS
+  /// inline asm may use ARR[baseReg + IndexReg + ...] which may use up regs
+  /// in [...] expr, so ARR[baseReg + IndexReg + ...] can not use extra reg
+  /// for ARR. For example, calculating ARR address to a reg or use another
+  /// base reg in PIC model.
+  virtual bool isMemUseUpRegs() const { return false; }
+
   /// getStartLoc - Get the location of the first token of this operand.
   virtual SMLoc getStartLoc() const = 0;
   /// getEndLoc - Get the location of the last token of this operand.
   virtual SMLoc getEndLoc() const = 0;
 
   /// needAddressOf - Do we need to emit code to get the address of the
   /// variable/label?   Only valid when parsing MS-style inline assembly.
   virtual bool needAddressOf() const { return false; }

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

 struct AsmRewrite {
   AsmRewriteKind Kind;
   SMLoc Loc;
   unsigned Len;
   bool Done;
   int64_t Val;
   StringRef Label;
   IntelExpr IntelExp;
+  bool IntelExpRestricted;
 
 public:
-  AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, int64_t val = 0)
-    : Kind(kind), Loc(loc), Len(len), Done(false), Val(val) {}
+  AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, int64_t val = 0,
+             bool Restricted = false)
+      : Kind(kind), Loc(loc), Len(len), Done(false), Val(val) {
+    IntelExpRestricted = Restricted;
+  }
   AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
     : AsmRewrite(kind, loc, len) { Label = label; }
   AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
     : AsmRewrite(AOK_IntelExpr, loc, len) { IntelExp = exp; }
 };
 
 struct ParseInstructionInfo {
   SmallVectorImpl<AsmRewrite> *AsmRewrites = nullptr;

llvm/lib/MC/MCParser/AsmParser.cpp

if (AsmRewritePrecedence[AsmRewriteA->Kind] >
     return -1;
 
   if (AsmRewritePrecedence[AsmRewriteA->Kind] <
       AsmRewritePrecedence[AsmRewriteB->Kind])
     return 1;
   llvm_unreachable("Unstable rewrite sort.");
 }
 
 bool AsmParser::parseMSInlineAsm(
     std::string &AsmString, unsigned &NumOutputs, unsigned &NumInputs,
     SmallVectorImpl<std::pair<void *, bool>> &OpDecls,
     SmallVectorImpl<std::string> &Constraints,
     SmallVectorImpl<std::string> &Clobbers, const MCInstrInfo *MII,
     const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) {
   SmallVector<void *, 4> InputDecls;
   SmallVector<void *, 4> OutputDecls;
   SmallVector<bool, 4> InputDeclsAddressOf;
   SmallVector<bool, 4> OutputDeclsAddressOf;
   SmallVector<std::string, 4> InputConstraints;
   SmallVector<std::string, 4> OutputConstraints;
while (getLexer().isNot(AsmToken::Eof)) {
 
     // No pending error should exist here.
     assert(!hasPendingError() && "unexpected error from parseStatement");
 
     if (Info.Opcode == ~0U)
       continue;
 
     const MCInstrDesc &Desc = MII->get(Info.Opcode);
 
     // Build the list of clobbers, outputs and inputs.
     for (unsigned i = 1, e = Info.ParsedOperands.size(); i != e; ++i) {
       MCParsedAsmOperand &Operand = *Info.ParsedOperands[i];
 
       // Register operand.
       if (Operand.isReg() && !Operand.needAddressOf() &&
           !getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
         unsigned NumDefs = Desc.getNumDefs();
for (unsigned i = 1, e = Info.ParsedOperands.size(); i != e; ++i) {
         // Offset as immediate
         if (Operand.isOffsetOfLocal())
           Constraint = "r";
         else
           Constraint = "i";
       }
 
       bool isOutput = (i == 1) && Desc.mayStore();
+      bool Restricted = Operand.isMemUseUpRegs();
       SMLoc Start = SMLoc::getFromPointer(SymName.data());
       if (isOutput) {
         ++InputIdx;
         OutputDecls.push_back(OpDecl);
         OutputDeclsAddressOf.push_back(Operand.needAddressOf());
         OutputConstraints.push_back(("=" + Constraint).str());
-        AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size());
+        AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size(), 0,
+                                    Restricted);
       } else {
         InputDecls.push_back(OpDecl);
         InputDeclsAddressOf.push_back(Operand.needAddressOf());
         InputConstraints.push_back(Constraint.str());
         if (Desc.OpInfo[i - 1].isBranchTarget())
-          AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size());
+          AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size(), 0,
+                                      Restricted);
         else
-          AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size());
+          AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size(), 0,
+                                      Restricted);
       }
     }
 
     // Consider implicit defs to be clobbers.  Think of cpuid and push.
     ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(),
                                 Desc.getNumImplicitDefs());
     llvm::append_range(ClobberRegs, ImpDefs);
   }
case AOK_IntelExpr:
         OS << (AR.IntelExp.emitImm() ? "$$" : " + $$") << AR.IntelExp.Imm;
       if (AR.IntelExp.NeedBracs)
         OS << "]";
       break;
     case AOK_Label:
       OS << Ctx.getAsmInfo()->getPrivateLabelPrefix() << AR.Label;
       break;
     case AOK_Input:
+      if (AR.IntelExpRestricted)
+        OS << "${" << InputIdx++ << ":P}";
+      else
         OS << '$' << InputIdx++;
       break;
     case AOK_CallInput:
       OS << "${" << InputIdx++ << ":P}";
       break;
     case AOK_Output:
+      if (AR.IntelExpRestricted)
+        OS << "${" << OutputIdx++ << ":P}";
+      else
         OS << '$' << OutputIdx++;
       break;
     case AOK_SizeDirective:
       switch (AR.Val) {
       default: break;
       case 8:  OS << "byte ptr "; break;
       case 16: OS << "word ptr "; break;
       case 32: OS << "dword ptr "; break;
       case 64: OS << "qword ptr "; break;
       case 80: OS << "xword ptr "; break;

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

class IntelExprStateMachine {
     InlineAsmIdentifierInfo Info;
     short BracCount;
     bool MemExpr;
     bool OffsetOperator;
     SMLoc OffsetOperatorLoc;
     AsmTypeInfo CurType;
 
     bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
       if (Sym) {
         ErrMsg = "cannot use more than one symbol in memory operand";
         return true;
       }
       Sym = Val;
       SymName = ID;
       return false;
     }
 
if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
     FrontendSize = Info.Var.Type * 8;
     Decl = Info.Var.Decl;
     IsGlobalLV = Info.Var.IsGlobalLV;
   }
   // It is widely common for MS InlineAsm to use a global variable and one/two
   // registers in a mmory expression, and though unaccessible via rip/eip.
   if (IsGlobalLV && (BaseReg || IndexReg)) {
     Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
-                                             End, Size, Identifier, Decl));
+                                             End, Size, Identifier, Decl, 0,
+                                             BaseReg && IndexReg));
     return false;
   }
   // Otherwise, we set the base register to a non-zero value
   // if we don't know the actual value at this time.  This is necessary to
   // get the matching correct in some cases.
   BaseReg = BaseReg ? BaseReg : 1;
   Operands.push_back(X86Operand::CreateMem(
       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,

llvm/lib/Target/X86/AsmParser/X86Operand.h

struct MemOp {
     unsigned IndexReg;
     unsigned Scale;
     unsigned Size;
     unsigned ModeSize;
 
     /// If the memory operand is unsized and there are multiple instruction
     /// matches, prefer the one with this size.
     unsigned FrontendSize;
+
+    /// This used for inline asm which may specify base reg and index reg for
+    /// MemOp. e.g. ARR[eax + ecx*4], so no extra reg can be used for MemOp.
+    bool UseUpRegs;
   };
 
   union {
     struct TokOp Tok;
     struct RegOp Reg;
     struct ImmOp Imm;
     struct MemOp Mem;
     struct PrefOp Pref;
struct X86Operand final : public MCParsedAsmOperand {
   bool isAVX512RC() const{
       return isImm();
   }
 
   bool isAbsMem16() const {
     return isAbsMem() && Mem.ModeSize == 16;
   }
 
+  bool isMemUseUpRegs() const {
+    return Mem.UseUpRegs;
+  }
+
   bool isSrcIdx() const {
     return !getMemIndexReg() && getMemScale() == 1 &&
       (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
        getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
       cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
   }
   bool isSrcIdx8() const {
     return isMem8() && isSrcIdx();
static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
     Res->AddressOf    = true;
     return Res;
   }
 
   /// Create an absolute memory operand.
   static std::unique_ptr<X86Operand>
   CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
             unsigned Size = 0, StringRef SymName = StringRef(),
-            void *OpDecl = nullptr, unsigned FrontendSize = 0) {
+            void *OpDecl = nullptr, unsigned FrontendSize = 0,
+            bool UseUpRegs = false) {
     auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
     Res->Mem.SegReg   = 0;
     Res->Mem.Disp     = Disp;
     Res->Mem.BaseReg  = 0;
     Res->Mem.DefaultBaseReg = 0;
     Res->Mem.IndexReg = 0;
     Res->Mem.Scale    = 1;
     Res->Mem.Size     = Size;
     Res->Mem.ModeSize = ModeSize;
     Res->Mem.FrontendSize = FrontendSize;
+    Res->Mem.UseUpRegs = UseUpRegs;
     Res->SymName      = SymName;
     Res->OpDecl       = OpDecl;
     Res->AddressOf    = false;
     return Res;
   }
 
   /// Create a generalized memory operand.
   static std::unique_ptr<X86Operand>
   CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
             unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
             SMLoc EndLoc, unsigned Size = 0,
             unsigned DefaultBaseReg = X86::NoRegister,
             StringRef SymName = StringRef(), void *OpDecl = nullptr,
-            unsigned FrontendSize = 0) {
+            unsigned FrontendSize = 0, bool UseUpRegs = false) {
     // We should never just have a displacement, that should be parsed as an
     // absolute memory operand.
     assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
            "Invalid memory operand!");
 
     // The scale should always be one of {1,2,4,8}.
     assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
            "Invalid scale!");
     auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
     Res->Mem.SegReg   = SegReg;
     Res->Mem.Disp     = Disp;
     Res->Mem.BaseReg  = BaseReg;
     Res->Mem.DefaultBaseReg = DefaultBaseReg;
     Res->Mem.IndexReg = IndexReg;
     Res->Mem.Scale    = Scale;
     Res->Mem.Size     = Size;
     Res->Mem.ModeSize = ModeSize;
     Res->Mem.FrontendSize = FrontendSize;
+    Res->Mem.UseUpRegs = UseUpRegs;
     Res->SymName      = SymName;
     Res->OpDecl       = OpDecl;
     Res->AddressOf    = false;
     return Res;
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H