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Differential D118485

[AArch64] Allow strict opcodes in fp->int->fp patterns
ClosedPublic

Authored by john.brawn on Jan 28 2022, 9:37 AM.

Details

Reviewers
SjoerdMeijer
t.p.northover
kpn
dmgreen
bsmith
Commits
rG9d68ed08178d: [AArch64] Allow strict opcodes in fp->int->fp patterns
Summary

These patterns don't change the fundamental instructions that are used, just the variants that are used in order to remove some extra MOVs.

Diff Detail

Event Timeline

john.brawn created this revision.Jan 28 2022, 9:37 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptJan 28 2022, 9:37 AM
john.brawn requested review of this revision.Jan 28 2022, 9:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 28 2022, 9:37 AM
john.brawn mentioned this in D114946: [AArch64] Add instruction selection for strict FP.Jan 28 2022, 9:53 AM
Harbormaster completed remote builds in B146312: Diff 404057.Jan 28 2022, 10:26 AM
john.brawn added a child revision: D115620: [AArch64] Lowering and legalization of strict FP16.Jan 31 2022, 2:42 AM
john.brawn added a parent revision: D114946: [AArch64] Add instruction selection for strict FP.
dmgreen accepted this revision.Feb 7 2022, 3:56 AM

Seems to make sense. LGTM

This revision is now accepted and ready to land.Feb 7 2022, 3:56 AM
This revision was landed with ongoing or failed builds.Feb 17 2022, 5:12 AM
Closed by commit rG9d68ed08178d: [AArch64] Allow strict opcodes in fp->int->fp patterns (authored by john.brawn). · Explain Why
This revision was automatically updated to reflect the committed changes.
john.brawn added a commit: rG9d68ed08178d: [AArch64] Allow strict opcodes in fp->int->fp patterns.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
12 lines
test/
CodeGen/
AArch64/
87 lines

Diff 404057

llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,976 Lines • ▼ Show 20 Linesdef : Pat<(f64 (AArch64frsqrts (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
(FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>; (FRSQRTS64 FPR64:$Rn, FPR64:$Rm)>;
def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))), def : Pat<(v2f64 (AArch64frsqrts (v2f64 FPR128:$Rn), (v2f64 FPR128:$Rm))),
(FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>; (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>;
// Some float -> int -> float conversion patterns for which we want to keep the // Some float -> int -> float conversion patterns for which we want to keep the
// int values in FP registers using the corresponding NEON instructions to // int values in FP registers using the corresponding NEON instructions to
// avoid more costly int <-> fp register transfers. // avoid more costly int <-> fp register transfers.
let Predicates = [HasNEON] in { let Predicates = [HasNEON] in {
def : Pat<(f64 (sint_to_fp (i64 (fp_to_sint f64:$Rn)))), def : Pat<(f64 (any_sint_to_fp (i64 (any_fp_to_sint f64:$Rn)))),
(SCVTFv1i64 (i64 (FCVTZSv1i64 f64:$Rn)))>; (SCVTFv1i64 (i64 (FCVTZSv1i64 f64:$Rn)))>;
def : Pat<(f32 (sint_to_fp (i32 (fp_to_sint f32:$Rn)))), def : Pat<(f32 (any_sint_to_fp (i32 (any_fp_to_sint f32:$Rn)))),
(SCVTFv1i32 (i32 (FCVTZSv1i32 f32:$Rn)))>; (SCVTFv1i32 (i32 (FCVTZSv1i32 f32:$Rn)))>;
def : Pat<(f64 (uint_to_fp (i64 (fp_to_uint f64:$Rn)))), def : Pat<(f64 (any_uint_to_fp (i64 (any_fp_to_uint f64:$Rn)))),
(UCVTFv1i64 (i64 (FCVTZUv1i64 f64:$Rn)))>; (UCVTFv1i64 (i64 (FCVTZUv1i64 f64:$Rn)))>;
def : Pat<(f32 (uint_to_fp (i32 (fp_to_uint f32:$Rn)))), def : Pat<(f32 (any_uint_to_fp (i32 (any_fp_to_uint f32:$Rn)))),
(UCVTFv1i32 (i32 (FCVTZUv1i32 f32:$Rn)))>; (UCVTFv1i32 (i32 (FCVTZUv1i32 f32:$Rn)))>;
let Predicates = [HasFullFP16] in { let Predicates = [HasFullFP16] in {
def : Pat<(f16 (sint_to_fp (i32 (fp_to_sint f16:$Rn)))), def : Pat<(f16 (any_sint_to_fp (i32 (any_fp_to_sint f16:$Rn)))),
(SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>; (SCVTFv1i16 (f16 (FCVTZSv1f16 f16:$Rn)))>;
def : Pat<(f16 (uint_to_fp (i32 (fp_to_uint f16:$Rn)))), def : Pat<(f16 (any_uint_to_fp (i32 (any_fp_to_uint f16:$Rn)))),
(UCVTFv1i16 (f16 (FCVTZUv1f16 f16:$Rn)))>; (UCVTFv1i16 (f16 (FCVTZUv1f16 f16:$Rn)))>;
} }
} }
// If an integer is about to be converted to a floating point value, // If an integer is about to be converted to a floating point value,
// just load it on the floating point unit. // just load it on the floating point unit.
// Here are the patterns for 8 and 16-bits to float. // Here are the patterns for 8 and 16-bits to float.
// 8-bits -> float. // 8-bits -> float.
▲ Show 20 Lines • Show All 3,367 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; CHECK-NEXT: fcvtzu h0, h0 ; CHECK-NEXT: fcvtzu h0, h0
; CHECK-NEXT: ucvtf h0, h0 ; CHECK-NEXT: ucvtf h0, h0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%conv = fptoui half %x to i32 %conv = fptoui half %x to i32
%conv1 = uitofp i32 %conv to half %conv1 = uitofp i32 %conv to half
ret half %conv1 ret half %conv1
} }
define double @t1_strict(double %x) #0 {
; CHECK-LABEL: t1_strict:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: scvtf d0, d0
; CHECK-NEXT: ret
entry:
%conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %x, metadata !"fpexcept.strict") #0
%conv1 = call double @llvm.experimental.constrained.sitofp.i64.f64(i64 %conv, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret double %conv1
}
define float @t2_strict(float %x) #0 {
; CHECK-LABEL: t2_strict:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: scvtf s0, s0
; CHECK-NEXT: ret
entry:
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %x, metadata !"fpexcept.strict") #0
%conv1 = call float @llvm.experimental.constrained.sitofp.i32.f32(i32 %conv, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret float %conv1
}
define half @t3_strict(half %x) #0 {
; CHECK-LABEL: t3_strict:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs h0, h0
; CHECK-NEXT: scvtf h0, h0
; CHECK-NEXT: ret
entry:
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %x, metadata !"fpexcept.strict") #0
%conv1 = call half @llvm.experimental.constrained.sitofp.i32.f16(i32 %conv, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret half %conv1
}
define double @t4_strict(double %x) #0 {
; CHECK-LABEL: t4_strict:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ucvtf d0, d0
; CHECK-NEXT: ret
entry:
%conv = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %x, metadata !"fpexcept.strict") #0
%conv1 = call double @llvm.experimental.constrained.uitofp.i64.f64(i64 %conv, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret double %conv1
}
define float @t5_strict(float %x) #0 {
; CHECK-LABEL: t5_strict:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ucvtf s0, s0
; CHECK-NEXT: ret
entry:
%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict") #0
%conv1 = call float @llvm.experimental.constrained.uitofp.i32.f32(i32 %conv, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret float %conv1
}
define half @t6_strict(half %x) #0 {
; CHECK-LABEL: t6_strict:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu h0, h0
; CHECK-NEXT: ucvtf h0, h0
; CHECK-NEXT: ret
entry:
%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict") #0
%conv1 = call half @llvm.experimental.constrained.uitofp.i32.f16(i32 %conv, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret half %conv1
}
attributes #0 = { strictfp }
declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)
declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)
declare half @llvm.experimental.constrained.sitofp.i32.f16(i32, metadata, metadata)
declare half @llvm.experimental.constrained.uitofp.i32.f16(i32, metadata, metadata)
declare float @llvm.experimental.constrained.sitofp.i32.f32(i32, metadata, metadata)
declare float @llvm.experimental.constrained.uitofp.i32.f32(i32, metadata, metadata)
declare double @llvm.experimental.constrained.sitofp.i64.f64(i64, metadata, metadata)
declare double @llvm.experimental.constrained.uitofp.i64.f64(i64, metadata, metadata)