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Differential D118253

[RISCV] Add the passthru operand for some RVV nomask unary and nullary intrinsics.
ClosedPublic

Authored by khchen on Jan 26 2022, 8:04 AM.

Details

Reviewers
craig.topper
rogfer01
frasercrmck
kito-cheng
arcbbb
monkchiang
eopXD
Commits
rGe8973dd389e7: [RISCV] Add the passthru operand for some RVV nomask unary and nullary…
Summary

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.

My plan is to handle more complex operations in follow-up patches.

Diff Detail

Event Timeline

khchen created this revision.Jan 26 2022, 8:04 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptJan 26 2022, 8:04 AM
khchen requested review of this revision.Jan 26 2022, 8:04 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJan 26 2022, 8:04 AM
Herald added subscribers: llvm-commits, cfe-commits, • pcwang-thead, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B145748: Diff 403269.Jan 26 2022, 8:05 AM
frasercrmck accepted this revision.Jan 27 2022, 2:59 AM

LGTM, thanks.

This revision is now accepted and ready to land.Jan 27 2022, 2:59 AM
khchen added a parent revision: D117989: [RISCV] Add the passthru operand for RVV nomask binary intrinsics..Jan 27 2022, 9:34 PM
jiegec added a subscriber: jiegec.Jan 28 2022, 5:01 PM
This revision was landed with ongoing or failed builds.Feb 15 2022, 11:00 PM
Closed by commit rGe8973dd389e7: [RISCV] Add the passthru operand for some RVV nomask unary and nullary… (authored by khchen). · Explain Why
This revision was automatically updated to reflect the committed changes.
khchen added a commit: rGe8973dd389e7: [RISCV] Add the passthru operand for some RVV nomask unary and nullary….

Revision Contents

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clang/
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clang/
Basic/
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test/
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rvv-intrinsics-overloaded/
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llvm/
include/
llvm/
IR/
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lib/
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RISCV/
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test/
CodeGen/
RISCV/
rvv/
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Diff 409155

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 1,610 Lines • ▼ Show 20 Lines
defm vwsub : RVVSignedWidenOp0BinBuiltinSet; defm vwsub : RVVSignedWidenOp0BinBuiltinSet;
} }
defm vwcvtu_x_x_v : RVVPseudoVWCVTBuiltin<"vwaddu", "vwcvtu_x", "csi", defm vwcvtu_x_x_v : RVVPseudoVWCVTBuiltin<"vwaddu", "vwcvtu_x", "csi",
[["Uw", "UwUv"]]>; [["Uw", "UwUv"]]>;
defm vwcvt_x_x_v : RVVPseudoVWCVTBuiltin<"vwadd", "vwcvt_x", "csi", defm vwcvt_x_x_v : RVVPseudoVWCVTBuiltin<"vwadd", "vwcvt_x", "csi",
[["w", "wv"]]>; [["w", "wv"]]>;
// 12.3. Vector Integer Extension // 12.3. Vector Integer Extension
let HasNoMaskPassThru = true in {
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">; def vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
def vzext_vf2 : RVVIntExt<"vzext", "Uw", "UwUv", "csi">; def vzext_vf2 : RVVIntExt<"vzext", "Uw", "UwUv", "csi">;
} }
let Log2LMUL = [-3, -2, -1, 0, 1] in { let Log2LMUL = [-3, -2, -1, 0, 1] in {
def vsext_vf4 : RVVIntExt<"vsext", "q", "qv", "cs">; def vsext_vf4 : RVVIntExt<"vsext", "q", "qv", "cs">;
def vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">; def vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">;
} }
let Log2LMUL = [-3, -2, -1, 0] in { let Log2LMUL = [-3, -2, -1, 0] in {
def vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">; def vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">;
def vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">; def vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">;
} }
}
// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions // 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
let HasMask = false, HasPolicy = false in { let HasMask = false, HasPolicy = false in {
defm vadc : RVVCarryinBuiltinSet; defm vadc : RVVCarryinBuiltinSet;
defm vmadc : RVVCarryOutInBuiltinSet<"vmadc_carry_in">; defm vmadc : RVVCarryOutInBuiltinSet<"vmadc_carry_in">;
defm vmadc : RVVIntMaskOutBuiltinSet; defm vmadc : RVVIntMaskOutBuiltinSet;
defm vsbc : RVVCarryinBuiltinSet; defm vsbc : RVVCarryinBuiltinSet;
defm vmsbc : RVVCarryOutInBuiltinSet<"vmsbc_borrow_in">; defm vmsbc : RVVCarryOutInBuiltinSet<"vmsbc_borrow_in">;
▲ Show 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm vfwmacc : RVVFloatingWidenTerBuiltinSet; defm vfwmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwnmacc : RVVFloatingWidenTerBuiltinSet; defm vfwnmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwmsac : RVVFloatingWidenTerBuiltinSet; defm vfwmsac : RVVFloatingWidenTerBuiltinSet;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSet; defm vfwnmsac : RVVFloatingWidenTerBuiltinSet;
// 14.8. Vector Floating-Point Square-Root Instruction // 14.8. Vector Floating-Point Square-Root Instruction
let HasNoMaskPassThru = true in {
def vfsqrt : RVVFloatingUnaryVVBuiltin; def vfsqrt : RVVFloatingUnaryVVBuiltin;
// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction // 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
def vfrsqrt7 : RVVFloatingUnaryVVBuiltin; def vfrsqrt7 : RVVFloatingUnaryVVBuiltin;
// 14.10. Vector Floating-Point Reciprocal Estimate Instruction // 14.10. Vector Floating-Point Reciprocal Estimate Instruction
def vfrec7 : RVVFloatingUnaryVVBuiltin; def vfrec7 : RVVFloatingUnaryVVBuiltin;
// 14.11. Vector Floating-Point MIN/MAX Instructions // 14.11. Vector Floating-Point MIN/MAX Instructions
let HasNoMaskPassThru = true in {
defm vfmin : RVVFloatingBinBuiltinSet; defm vfmin : RVVFloatingBinBuiltinSet;
defm vfmax : RVVFloatingBinBuiltinSet; defm vfmax : RVVFloatingBinBuiltinSet;
// 14.12. Vector Floating-Point Sign-Injection Instructions // 14.12. Vector Floating-Point Sign-Injection Instructions
defm vfsgnj : RVVFloatingBinBuiltinSet; defm vfsgnj : RVVFloatingBinBuiltinSet;
defm vfsgnjn : RVVFloatingBinBuiltinSet; defm vfsgnjn : RVVFloatingBinBuiltinSet;
defm vfsgnjx : RVVFloatingBinBuiltinSet; defm vfsgnjx : RVVFloatingBinBuiltinSet;
} }
defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">; defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">;
defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">; defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">;
// 14.13. Vector Floating-Point Compare Instructions // 14.13. Vector Floating-Point Compare Instructions
let HasPolicy = false in { let HasPolicy = false in {
defm vmfeq : RVVFloatingMaskOutBuiltinSet; defm vmfeq : RVVFloatingMaskOutBuiltinSet;
defm vmfne : RVVFloatingMaskOutBuiltinSet; defm vmfne : RVVFloatingMaskOutBuiltinSet;
defm vmflt : RVVFloatingMaskOutBuiltinSet; defm vmflt : RVVFloatingMaskOutBuiltinSet;
defm vmfle : RVVFloatingMaskOutBuiltinSet; defm vmfle : RVVFloatingMaskOutBuiltinSet;
defm vmfgt : RVVFloatingMaskOutBuiltinSet; defm vmfgt : RVVFloatingMaskOutBuiltinSet;
defm vmfge : RVVFloatingMaskOutBuiltinSet; defm vmfge : RVVFloatingMaskOutBuiltinSet;
} }
// 14.14. Vector Floating-Point Classify Instruction // 14.14. Vector Floating-Point Classify Instruction
let Name = "vfclass_v", HasPolicy = false in let Name = "vfclass_v", HasNoMaskPassThru = true in
def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">; def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">;
// 14.15. Vector Floating-Point Merge Instructio // 14.15. Vector Floating-Point Merge Instructio
// C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl) // C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl)
let HasMask = false, HasPolicy = false, let HasMask = false, HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3);
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()};
}] in { }] in {
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "xfd", defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "xfd",
[["vvm", "v", "vmvv"]]>; [["vvm", "v", "vmvv"]]>;
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd", defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
[["vfm", "v", "vmve"]]>; [["vfm", "v", "vmve"]]>;
} }
// 14.16. Vector Floating-Point Move Instruction // 14.16. Vector Floating-Point Move Instruction
let HasMask = false, HasNoMaskedOverloaded = false, HasPolicy = false in let HasMask = false, HasNoMaskedOverloaded = false, HasPolicy = false in
defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd", defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd",
[["f", "v", "ve"]]>; [["f", "v", "ve"]]>;
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
let HasNoMaskPassThru = true in {
def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">; def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">;
def vfcvt_x_f_v : RVVConvToSignedBuiltin<"vfcvt_x">; def vfcvt_x_f_v : RVVConvToSignedBuiltin<"vfcvt_x">;
def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">; def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">;
def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">; def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
def vfcvt_f_xu_v : RVVConvBuiltin<"Fv", "FvUv", "sil", "vfcvt_f">; def vfcvt_f_xu_v : RVVConvBuiltin<"Fv", "FvUv", "sil", "vfcvt_f">;
def vfcvt_f_x_v : RVVConvBuiltin<"Fv", "Fvv", "sil", "vfcvt_f">; def vfcvt_f_x_v : RVVConvBuiltin<"Fv", "Fvv", "sil", "vfcvt_f">;
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
Show All 13 Lineslet Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_x">; def vfncvt_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_x">;
def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">; def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">;
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">; def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">; def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">;
def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">; def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;
def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">; def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">; def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
} }
}
// 15. Vector Reduction Operations // 15. Vector Reduction Operations
// 15.1. Vector Single-Width Integer Reduction Instructions // 15.1. Vector Single-Width Integer Reduction Instructions
let HasPolicy = false in { let HasPolicy = false in {
defm vredsum : RVVIntReductionBuiltinSet; defm vredsum : RVVIntReductionBuiltinSet;
defm vredmaxu : RVVUnsignedReductionBuiltin; defm vredmaxu : RVVUnsignedReductionBuiltin;
defm vredmax : RVVSignedReductionBuiltin; defm vredmax : RVVSignedReductionBuiltin;
defm vredminu : RVVUnsignedReductionBuiltin; defm vredminu : RVVUnsignedReductionBuiltin;
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
def vmsbf : RVVMaskUnaryBuiltin; def vmsbf : RVVMaskUnaryBuiltin;
// 16.5. vmsif.m set-including-first mask bit // 16.5. vmsif.m set-including-first mask bit
def vmsif : RVVMaskUnaryBuiltin; def vmsif : RVVMaskUnaryBuiltin;
// 16.6. vmsof.m set-only-first mask bit // 16.6. vmsof.m set-only-first mask bit
def vmsof : RVVMaskUnaryBuiltin; def vmsof : RVVMaskUnaryBuiltin;
let HasNoMaskedOverloaded = false in { let HasNoMaskPassThru = true, HasNoMaskedOverloaded = false in {
// 16.8. Vector Iota Instruction // 16.8. Vector Iota Instruction
defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>; defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;
// 16.9. Vector Element Index Instruction // 16.9. Vector Element Index Instruction
defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"], defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"],
["v", "Uv", "Uv"]]>; ["v", "Uv", "Uv"]]>;
} }
} }
▲ Show 20 Lines • Show All 194 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2( // CHECK-RV64-LABEL: @test_vfclass_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfclass_v_u32mf2(vfloat32mf2_t op1, size_t vl) { vuint32mf2_t test_vfclass_v_u32mf2(vfloat32mf2_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m1( // CHECK-RV64-LABEL: @test_vfclass_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfclass_v_u32m1(vfloat32m1_t op1, size_t vl) { vuint32m1_t test_vfclass_v_u32m1(vfloat32m1_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m2( // CHECK-RV64-LABEL: @test_vfclass_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfclass_v_u32m2(vfloat32m2_t op1, size_t vl) { vuint32m2_t test_vfclass_v_u32m2(vfloat32m2_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m4( // CHECK-RV64-LABEL: @test_vfclass_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfclass_v_u32m4(vfloat32m4_t op1, size_t vl) { vuint32m4_t test_vfclass_v_u32m4(vfloat32m4_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m8( // CHECK-RV64-LABEL: @test_vfclass_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfclass_v_u32m8(vfloat32m8_t op1, size_t vl) { vuint32m8_t test_vfclass_v_u32m8(vfloat32m8_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m1( // CHECK-RV64-LABEL: @test_vfclass_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfclass_v_u64m1(vfloat64m1_t op1, size_t vl) { vuint64m1_t test_vfclass_v_u64m1(vfloat64m1_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m2( // CHECK-RV64-LABEL: @test_vfclass_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfclass_v_u64m2(vfloat64m2_t op1, size_t vl) { vuint64m2_t test_vfclass_v_u64m2(vfloat64m2_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m4( // CHECK-RV64-LABEL: @test_vfclass_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfclass_v_u64m4(vfloat64m4_t op1, size_t vl) { vuint64m4_t test_vfclass_v_u64m4(vfloat64m4_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m8( // CHECK-RV64-LABEL: @test_vfclass_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfclass_v_u64m8(vfloat64m8_t op1, size_t vl) { vuint64m8_t test_vfclass_v_u64m8(vfloat64m8_t op1, size_t vl) {
return vfclass(op1, vl); return vfclass(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfclass_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t test_vfclass_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m1_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfclass_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t test_vfclass_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
vfloat32m1_t op1, size_t vl) { vfloat32m1_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfclass_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t test_vfclass_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
vfloat32m2_t op1, size_t vl) { vfloat32m2_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m4_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfclass_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t test_vfclass_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
vfloat32m4_t op1, size_t vl) { vfloat32m4_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m8_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfclass_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t test_vfclass_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
vfloat32m8_t op1, size_t vl) { vfloat32m8_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m1_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfclass_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t test_vfclass_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
vfloat64m1_t op1, size_t vl) { vfloat64m1_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfclass_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t test_vfclass_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
vfloat64m2_t op1, size_t vl) { vfloat64m2_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m4_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfclass_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t test_vfclass_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
vfloat64m4_t op1, size_t vl) { vfloat64m4_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m8_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfclass_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t test_vfclass_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
vfloat64m8_t op1, size_t vl) { vfloat64m8_t op1, size_t vl) {
return vfclass(mask, maskedoff, op1, vl); return vfclass(mask, maskedoff, op1, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfcvt_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) { vint32mf2_t test_vfcvt_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32mf2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfcvt_rtz_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) { vint32mf2_t test_vfcvt_rtz_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m1( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfcvt_x_f_v_i32m1(vfloat32m1_t src, size_t vl) { vint32m1_t test_vfcvt_x_f_v_i32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfcvt_rtz_x_f_v_i32m1(vfloat32m1_t src, size_t vl) { vint32m1_t test_vfcvt_rtz_x_f_v_i32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfcvt_x_f_v_i32m2(vfloat32m2_t src, size_t vl) { vint32m2_t test_vfcvt_x_f_v_i32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfcvt_rtz_x_f_v_i32m2(vfloat32m2_t src, size_t vl) { vint32m2_t test_vfcvt_rtz_x_f_v_i32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m4( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfcvt_x_f_v_i32m4(vfloat32m4_t src, size_t vl) { vint32m4_t test_vfcvt_x_f_v_i32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfcvt_rtz_x_f_v_i32m4(vfloat32m4_t src, size_t vl) { vint32m4_t test_vfcvt_rtz_x_f_v_i32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m8( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vfcvt_x_f_v_i32m8(vfloat32m8_t src, size_t vl) { vint32m8_t test_vfcvt_x_f_v_i32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vfcvt_rtz_x_f_v_i32m8(vfloat32m8_t src, size_t vl) { vint32m8_t test_vfcvt_rtz_x_f_v_i32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32mf2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfcvt_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) { vuint32mf2_t test_vfcvt_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32mf2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfcvt_rtz_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) { vuint32mf2_t test_vfcvt_rtz_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m1( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfcvt_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) { vuint32m1_t test_vfcvt_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfcvt_rtz_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) { vuint32m1_t test_vfcvt_rtz_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfcvt_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) { vuint32m2_t test_vfcvt_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfcvt_rtz_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) { vuint32m2_t test_vfcvt_rtz_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m4( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfcvt_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) { vuint32m4_t test_vfcvt_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfcvt_rtz_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) { vuint32m4_t test_vfcvt_rtz_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m8( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfcvt_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) { vuint32m8_t test_vfcvt_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfcvt_rtz_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) { vuint32m8_t test_vfcvt_rtz_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32mf2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfcvt_f_x_v_f32mf2(vint32mf2_t src, size_t vl) { vfloat32mf2_t test_vfcvt_f_x_v_f32mf2(vint32mf2_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m1( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfcvt_f_x_v_f32m1(vint32m1_t src, size_t vl) { vfloat32m1_t test_vfcvt_f_x_v_f32m1(vint32m1_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfcvt_f_x_v_f32m2(vint32m2_t src, size_t vl) { vfloat32m2_t test_vfcvt_f_x_v_f32m2(vint32m2_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m4( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfcvt_f_x_v_f32m4(vint32m4_t src, size_t vl) { vfloat32m4_t test_vfcvt_f_x_v_f32m4(vint32m4_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m8( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfcvt_f_x_v_f32m8(vint32m8_t src, size_t vl) { vfloat32m8_t test_vfcvt_f_x_v_f32m8(vint32m8_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32mf2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2(vuint32mf2_t src, size_t vl) { vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2(vuint32mf2_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m1( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfcvt_f_xu_v_f32m1(vuint32m1_t src, size_t vl) { vfloat32m1_t test_vfcvt_f_xu_v_f32m1(vuint32m1_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfcvt_f_xu_v_f32m2(vuint32m2_t src, size_t vl) { vfloat32m2_t test_vfcvt_f_xu_v_f32m2(vuint32m2_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m4( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfcvt_f_xu_v_f32m4(vuint32m4_t src, size_t vl) { vfloat32m4_t test_vfcvt_f_xu_v_f32m4(vuint32m4_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m8( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfcvt_f_xu_v_f32m8(vuint32m8_t src, size_t vl) { vfloat32m8_t test_vfcvt_f_xu_v_f32m8(vuint32m8_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfcvt_x_f_v_i64m1(vfloat64m1_t src, size_t vl) { vint64m1_t test_vfcvt_x_f_v_i64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfcvt_rtz_x_f_v_i64m1(vfloat64m1_t src, size_t vl) { vint64m1_t test_vfcvt_rtz_x_f_v_i64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfcvt_x_f_v_i64m2(vfloat64m2_t src, size_t vl) { vint64m2_t test_vfcvt_x_f_v_i64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfcvt_rtz_x_f_v_i64m2(vfloat64m2_t src, size_t vl) { vint64m2_t test_vfcvt_rtz_x_f_v_i64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfcvt_x_f_v_i64m4(vfloat64m4_t src, size_t vl) { vint64m4_t test_vfcvt_x_f_v_i64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfcvt_rtz_x_f_v_i64m4(vfloat64m4_t src, size_t vl) { vint64m4_t test_vfcvt_rtz_x_f_v_i64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfcvt_x_f_v_i64m8(vfloat64m8_t src, size_t vl) { vint64m8_t test_vfcvt_x_f_v_i64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_x(src, vl); return vfcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfcvt_rtz_x_f_v_i64m8(vfloat64m8_t src, size_t vl) { vint64m8_t test_vfcvt_rtz_x_f_v_i64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_rtz_x(src, vl); return vfcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfcvt_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) { vuint64m1_t test_vfcvt_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfcvt_rtz_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) { vuint64m1_t test_vfcvt_rtz_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfcvt_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) { vuint64m2_t test_vfcvt_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfcvt_rtz_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) { vuint64m2_t test_vfcvt_rtz_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfcvt_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) { vuint64m4_t test_vfcvt_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfcvt_rtz_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) { vuint64m4_t test_vfcvt_rtz_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfcvt_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) { vuint64m8_t test_vfcvt_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_xu(src, vl); return vfcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfcvt_rtz_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) { vuint64m8_t test_vfcvt_rtz_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_rtz_xu(src, vl); return vfcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m1( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfcvt_f_x_v_f64m1(vint64m1_t src, size_t vl) { vfloat64m1_t test_vfcvt_f_x_v_f64m1(vint64m1_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfcvt_f_x_v_f64m2(vint64m2_t src, size_t vl) { vfloat64m2_t test_vfcvt_f_x_v_f64m2(vint64m2_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m4( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfcvt_f_x_v_f64m4(vint64m4_t src, size_t vl) { vfloat64m4_t test_vfcvt_f_x_v_f64m4(vint64m4_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m8( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfcvt_f_x_v_f64m8(vint64m8_t src, size_t vl) { vfloat64m8_t test_vfcvt_f_x_v_f64m8(vint64m8_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m1( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfcvt_f_xu_v_f64m1(vuint64m1_t src, size_t vl) { vfloat64m1_t test_vfcvt_f_xu_v_f64m1(vuint64m1_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfcvt_f_xu_v_f64m2(vuint64m2_t src, size_t vl) { vfloat64m2_t test_vfcvt_f_xu_v_f64m2(vuint64m2_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m4( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfcvt_f_xu_v_f64m4(vuint64m4_t src, size_t vl) { vfloat64m4_t test_vfcvt_f_xu_v_f64m4(vuint64m4_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m8( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfcvt_f_xu_v_f64m8(vuint64m8_t src, size_t vl) { vfloat64m8_t test_vfcvt_f_xu_v_f64m8(vuint64m8_t src, size_t vl) {
return vfcvt_f(src, vl); return vfcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2_m( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 539 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vfncvt_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) { vint16mf4_t test_vfncvt_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vfncvt_rtz_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) { vint16mf4_t test_vfncvt_rtz_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vfncvt_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) { vint16mf2_t test_vfncvt_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vfncvt_rtz_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) { vint16mf2_t test_vfncvt_rtz_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m1( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vfncvt_x_f_w_i16m1(vfloat32m2_t src, size_t vl) { vint16m1_t test_vfncvt_x_f_w_i16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vfncvt_rtz_x_f_w_i16m1(vfloat32m2_t src, size_t vl) { vint16m1_t test_vfncvt_rtz_x_f_w_i16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vfncvt_x_f_w_i16m2(vfloat32m4_t src, size_t vl) { vint16m2_t test_vfncvt_x_f_w_i16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vfncvt_rtz_x_f_w_i16m2(vfloat32m4_t src, size_t vl) { vint16m2_t test_vfncvt_rtz_x_f_w_i16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vfncvt_x_f_w_i16m4(vfloat32m8_t src, size_t vl) { vint16m4_t test_vfncvt_x_f_w_i16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vfncvt_rtz_x_f_w_i16m4(vfloat32m8_t src, size_t vl) { vint16m4_t test_vfncvt_rtz_x_f_w_i16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfncvt_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) { vuint16mf4_t test_vfncvt_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfncvt_rtz_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) { vuint16mf4_t test_vfncvt_rtz_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfncvt_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) { vuint16mf2_t test_vfncvt_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfncvt_rtz_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) { vuint16mf2_t test_vfncvt_rtz_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m1( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfncvt_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) { vuint16m1_t test_vfncvt_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfncvt_rtz_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) { vuint16m1_t test_vfncvt_rtz_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfncvt_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) { vuint16m2_t test_vfncvt_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfncvt_rtz_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) { vuint16m2_t test_vfncvt_rtz_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfncvt_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) { vuint16m4_t test_vfncvt_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfncvt_rtz_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) { vuint16m4_t test_vfncvt_rtz_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32mf2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfncvt_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) { vint32mf2_t test_vfncvt_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfncvt_rtz_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) { vint32mf2_t test_vfncvt_rtz_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m1( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfncvt_x_f_w_i32m1(vfloat64m2_t src, size_t vl) { vint32m1_t test_vfncvt_x_f_w_i32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfncvt_rtz_x_f_w_i32m1(vfloat64m2_t src, size_t vl) { vint32m1_t test_vfncvt_rtz_x_f_w_i32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfncvt_x_f_w_i32m2(vfloat64m4_t src, size_t vl) { vint32m2_t test_vfncvt_x_f_w_i32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfncvt_rtz_x_f_w_i32m2(vfloat64m4_t src, size_t vl) { vint32m2_t test_vfncvt_rtz_x_f_w_i32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfncvt_x_f_w_i32m4(vfloat64m8_t src, size_t vl) { vint32m4_t test_vfncvt_x_f_w_i32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_x(src, vl); return vfncvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfncvt_rtz_x_f_w_i32m4(vfloat64m8_t src, size_t vl) { vint32m4_t test_vfncvt_rtz_x_f_w_i32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_rtz_x(src, vl); return vfncvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32mf2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfncvt_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) { vuint32mf2_t test_vfncvt_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfncvt_rtz_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) { vuint32mf2_t test_vfncvt_rtz_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m1( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfncvt_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) { vuint32m1_t test_vfncvt_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfncvt_rtz_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) { vuint32m1_t test_vfncvt_rtz_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfncvt_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) { vuint32m2_t test_vfncvt_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfncvt_rtz_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) { vuint32m2_t test_vfncvt_rtz_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfncvt_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) { vuint32m4_t test_vfncvt_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_xu(src, vl); return vfncvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfncvt_rtz_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) { vuint32m4_t test_vfncvt_rtz_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_rtz_xu(src, vl); return vfncvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_f_x_w_f32mf2(vint64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_f_x_w_f32mf2(vint64m1_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_f_x_w_f32m1(vint64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_f_x_w_f32m1(vint64m2_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_f_x_w_f32m2(vint64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_f_x_w_f32m2(vint64m4_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_f_x_w_f32m4(vint64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_f_x_w_f32m4(vint64m8_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2(vuint64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2(vuint64m1_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_f_xu_w_f32m1(vuint64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_f_xu_w_f32m1(vuint64m2_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_f_xu_w_f32m2(vuint64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_f_xu_w_f32m2(vuint64m4_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_f_xu_w_f32m4(vuint64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_f_xu_w_f32m4(vuint64m8_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_rod_f(src, vl); return vfncvt_rod_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_f_f_w_f32m1(vfloat64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_rod_f(src, vl); return vfncvt_rod_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_f_f_w_f32m2(vfloat64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_rod_f(src, vl); return vfncvt_rod_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_f_f_w_f32m4(vfloat64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_f(src, vl); return vfncvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_rod_f(src, vl); return vfncvt_rod_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4_m( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 533 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2( // CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfrec7_v_f32mf2(vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t test_vfrec7_v_f32mf2(vfloat32mf2_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m1( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfrec7_v_f32m1(vfloat32m1_t op1, size_t vl) { vfloat32m1_t test_vfrec7_v_f32m1(vfloat32m1_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m2( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfrec7_v_f32m2(vfloat32m2_t op1, size_t vl) { vfloat32m2_t test_vfrec7_v_f32m2(vfloat32m2_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m4( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfrec7_v_f32m4(vfloat32m4_t op1, size_t vl) { vfloat32m4_t test_vfrec7_v_f32m4(vfloat32m4_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m8( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfrec7_v_f32m8(vfloat32m8_t op1, size_t vl) { vfloat32m8_t test_vfrec7_v_f32m8(vfloat32m8_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m1( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfrec7_v_f64m1(vfloat64m1_t op1, size_t vl) { vfloat64m1_t test_vfrec7_v_f64m1(vfloat64m1_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m2( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfrec7_v_f64m2(vfloat64m2_t op1, size_t vl) { vfloat64m2_t test_vfrec7_v_f64m2(vfloat64m2_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m4( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfrec7_v_f64m4(vfloat64m4_t op1, size_t vl) { vfloat64m4_t test_vfrec7_v_f64m4(vfloat64m4_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m8( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfrec7_v_f64m8(vfloat64m8_t op1, size_t vl) { vfloat64m8_t test_vfrec7_v_f64m8(vfloat64m8_t op1, size_t vl) {
return vfrec7(op1, vl); return vfrec7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfrsqrt7_v_f32mf2(vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t test_vfrsqrt7_v_f32mf2(vfloat32mf2_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m1( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfrsqrt7_v_f32m1(vfloat32m1_t op1, size_t vl) { vfloat32m1_t test_vfrsqrt7_v_f32m1(vfloat32m1_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfrsqrt7_v_f32m2(vfloat32m2_t op1, size_t vl) { vfloat32m2_t test_vfrsqrt7_v_f32m2(vfloat32m2_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m4( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfrsqrt7_v_f32m4(vfloat32m4_t op1, size_t vl) { vfloat32m4_t test_vfrsqrt7_v_f32m4(vfloat32m4_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m8( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfrsqrt7_v_f32m8(vfloat32m8_t op1, size_t vl) { vfloat32m8_t test_vfrsqrt7_v_f32m8(vfloat32m8_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m1( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfrsqrt7_v_f64m1(vfloat64m1_t op1, size_t vl) { vfloat64m1_t test_vfrsqrt7_v_f64m1(vfloat64m1_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfrsqrt7_v_f64m2(vfloat64m2_t op1, size_t vl) { vfloat64m2_t test_vfrsqrt7_v_f64m2(vfloat64m2_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m4( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfrsqrt7_v_f64m4(vfloat64m4_t op1, size_t vl) { vfloat64m4_t test_vfrsqrt7_v_f64m4(vfloat64m4_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m8( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfrsqrt7_v_f64m8(vfloat64m8_t op1, size_t vl) { vfloat64m8_t test_vfrsqrt7_v_f64m8(vfloat64m8_t op1, size_t vl) {
return vfrsqrt7(op1, vl); return vfrsqrt7(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfsqrt_v_f32mf2(vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t test_vfsqrt_v_f32mf2(vfloat32mf2_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m1( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfsqrt_v_f32m1(vfloat32m1_t op1, size_t vl) { vfloat32m1_t test_vfsqrt_v_f32m1(vfloat32m1_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfsqrt_v_f32m2(vfloat32m2_t op1, size_t vl) { vfloat32m2_t test_vfsqrt_v_f32m2(vfloat32m2_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m4( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfsqrt_v_f32m4(vfloat32m4_t op1, size_t vl) { vfloat32m4_t test_vfsqrt_v_f32m4(vfloat32m4_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m8( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfsqrt_v_f32m8(vfloat32m8_t op1, size_t vl) { vfloat32m8_t test_vfsqrt_v_f32m8(vfloat32m8_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m1( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfsqrt_v_f64m1(vfloat64m1_t op1, size_t vl) { vfloat64m1_t test_vfsqrt_v_f64m1(vfloat64m1_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfsqrt_v_f64m2(vfloat64m2_t op1, size_t vl) { vfloat64m2_t test_vfsqrt_v_f64m2(vfloat64m2_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m4( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfsqrt_v_f64m4(vfloat64m4_t op1, size_t vl) { vfloat64m4_t test_vfsqrt_v_f64m4(vfloat64m4_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m8( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfsqrt_v_f64m8(vfloat64m8_t op1, size_t vl) { vfloat64m8_t test_vfsqrt_v_f64m8(vfloat64m8_t op1, size_t vl) {
return vfsqrt(op1, vl); return vfsqrt(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2(vint16mf4_t src, size_t vl) { vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2(vint16mf4_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwcvt_f_x_v_f32m1(vint16mf2_t src, size_t vl) { vfloat32m1_t test_vfwcvt_f_x_v_f32m1(vint16mf2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwcvt_f_x_v_f32m2(vint16m1_t src, size_t vl) { vfloat32m2_t test_vfwcvt_f_x_v_f32m2(vint16m1_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwcvt_f_x_v_f32m4(vint16m2_t src, size_t vl) { vfloat32m4_t test_vfwcvt_f_x_v_f32m4(vint16m2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwcvt_f_x_v_f32m8(vint16m4_t src, size_t vl) { vfloat32m8_t test_vfwcvt_f_x_v_f32m8(vint16m4_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2(vuint16mf4_t src, size_t vl) { vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2(vuint16mf4_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwcvt_f_xu_v_f32m1(vuint16mf2_t src, size_t vl) { vfloat32m1_t test_vfwcvt_f_xu_v_f32m1(vuint16mf2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwcvt_f_xu_v_f32m2(vuint16m1_t src, size_t vl) { vfloat32m2_t test_vfwcvt_f_xu_v_f32m2(vuint16m1_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwcvt_f_xu_v_f32m4(vuint16m2_t src, size_t vl) { vfloat32m4_t test_vfwcvt_f_xu_v_f32m4(vuint16m2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwcvt_f_xu_v_f32m8(vuint16m4_t src, size_t vl) { vfloat32m8_t test_vfwcvt_f_xu_v_f32m8(vuint16m4_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfwcvt_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) { vint64m1_t test_vfwcvt_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_x(src, vl); return vfwcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) { vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_rtz_x(src, vl); return vfwcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfwcvt_x_f_v_i64m2(vfloat32m1_t src, size_t vl) { vint64m2_t test_vfwcvt_x_f_v_i64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_x(src, vl); return vfwcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src, size_t vl) { vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_rtz_x(src, vl); return vfwcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfwcvt_x_f_v_i64m4(vfloat32m2_t src, size_t vl) { vint64m4_t test_vfwcvt_x_f_v_i64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_x(src, vl); return vfwcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src, size_t vl) { vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_rtz_x(src, vl); return vfwcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfwcvt_x_f_v_i64m8(vfloat32m4_t src, size_t vl) { vint64m8_t test_vfwcvt_x_f_v_i64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_x(src, vl); return vfwcvt_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src, size_t vl) { vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_rtz_x(src, vl); return vfwcvt_rtz_x(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfwcvt_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) { vuint64m1_t test_vfwcvt_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_xu(src, vl); return vfwcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) { vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_rtz_xu(src, vl); return vfwcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfwcvt_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) { vuint64m2_t test_vfwcvt_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_xu(src, vl); return vfwcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) { vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_rtz_xu(src, vl); return vfwcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfwcvt_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) { vuint64m4_t test_vfwcvt_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_xu(src, vl); return vfwcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) { vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_rtz_xu(src, vl); return vfwcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfwcvt_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) { vuint64m8_t test_vfwcvt_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_xu(src, vl); return vfwcvt_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) { vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_rtz_xu(src, vl); return vfwcvt_rtz_xu(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwcvt_f_x_v_f64m1(vint32mf2_t src, size_t vl) { vfloat64m1_t test_vfwcvt_f_x_v_f64m1(vint32mf2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwcvt_f_x_v_f64m2(vint32m1_t src, size_t vl) { vfloat64m2_t test_vfwcvt_f_x_v_f64m2(vint32m1_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwcvt_f_x_v_f64m4(vint32m2_t src, size_t vl) { vfloat64m4_t test_vfwcvt_f_x_v_f64m4(vint32m2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwcvt_f_x_v_f64m8(vint32m4_t src, size_t vl) { vfloat64m8_t test_vfwcvt_f_x_v_f64m8(vint32m4_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwcvt_f_xu_v_f64m1(vuint32mf2_t src, size_t vl) { vfloat64m1_t test_vfwcvt_f_xu_v_f64m1(vuint32mf2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwcvt_f_xu_v_f64m2(vuint32m1_t src, size_t vl) { vfloat64m2_t test_vfwcvt_f_xu_v_f64m2(vuint32m1_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwcvt_f_xu_v_f64m4(vuint32m2_t src, size_t vl) { vfloat64m4_t test_vfwcvt_f_xu_v_f64m4(vuint32m2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwcvt_f_xu_v_f64m8(vuint32m4_t src, size_t vl) { vfloat64m8_t test_vfwcvt_f_xu_v_f64m8(vuint32m4_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwcvt_f_f_v_f64m1(vfloat32mf2_t src, size_t vl) { vfloat64m1_t test_vfwcvt_f_f_v_f64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwcvt_f_f_v_f64m2(vfloat32m1_t src, size_t vl) { vfloat64m2_t test_vfwcvt_f_f_v_f64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwcvt_f_f_v_f64m4(vfloat32m2_t src, size_t vl) { vfloat64m4_t test_vfwcvt_f_f_v_f64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwcvt_f_f_v_f64m8(vfloat32m4_t src, size_t vl) { vfloat64m8_t test_vfwcvt_f_f_v_f64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_f(src, vl); return vfwcvt_f(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4( // CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vsext_vf2_i16mf4(vint8mf8_t op1, size_t vl) { vint16mf4_t test_vsext_vf2_i16mf4(vint8mf8_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf2( // CHECK-RV64-LABEL: @test_vsext_vf2_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vsext_vf2_i16mf2(vint8mf4_t op1, size_t vl) { vint16mf2_t test_vsext_vf2_i16mf2(vint8mf4_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m1( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vsext_vf2_i16m1(vint8mf2_t op1, size_t vl) { vint16m1_t test_vsext_vf2_i16m1(vint8mf2_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m2( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vsext_vf2_i16m2(vint8m1_t op1, size_t vl) { vint16m2_t test_vsext_vf2_i16m2(vint8m1_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m4( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vsext_vf2_i16m4(vint8m2_t op1, size_t vl) { vint16m4_t test_vsext_vf2_i16m4(vint8m2_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m8( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vsext_vf2_i16m8(vint8m4_t op1, size_t vl) { vint16m8_t test_vsext_vf2_i16m8(vint8m4_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32mf2( // CHECK-RV64-LABEL: @test_vsext_vf4_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vsext_vf4_i32mf2(vint8mf8_t op1, size_t vl) { vint32mf2_t test_vsext_vf4_i32mf2(vint8mf8_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m1( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vsext_vf4_i32m1(vint8mf4_t op1, size_t vl) { vint32m1_t test_vsext_vf4_i32m1(vint8mf4_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m2( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vsext_vf4_i32m2(vint8mf2_t op1, size_t vl) { vint32m2_t test_vsext_vf4_i32m2(vint8mf2_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m4( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vsext_vf4_i32m4(vint8m1_t op1, size_t vl) { vint32m4_t test_vsext_vf4_i32m4(vint8m1_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m8( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vsext_vf4_i32m8(vint8m2_t op1, size_t vl) { vint32m8_t test_vsext_vf4_i32m8(vint8m2_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m1( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vsext_vf8_i64m1(vint8mf8_t op1, size_t vl) { vint64m1_t test_vsext_vf8_i64m1(vint8mf8_t op1, size_t vl) {
return vsext_vf8(op1, vl); return vsext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m2( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vsext_vf8_i64m2(vint8mf4_t op1, size_t vl) { vint64m2_t test_vsext_vf8_i64m2(vint8mf4_t op1, size_t vl) {
return vsext_vf8(op1, vl); return vsext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m4( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vsext_vf8_i64m4(vint8mf2_t op1, size_t vl) { vint64m4_t test_vsext_vf8_i64m4(vint8mf2_t op1, size_t vl) {
return vsext_vf8(op1, vl); return vsext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m8( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vsext_vf8_i64m8(vint8m1_t op1, size_t vl) { vint64m8_t test_vsext_vf8_i64m8(vint8m1_t op1, size_t vl) {
return vsext_vf8(op1, vl); return vsext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32mf2( // CHECK-RV64-LABEL: @test_vsext_vf2_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vsext_vf2_i32mf2(vint16mf4_t op1, size_t vl) { vint32mf2_t test_vsext_vf2_i32mf2(vint16mf4_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m1( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vsext_vf2_i32m1(vint16mf2_t op1, size_t vl) { vint32m1_t test_vsext_vf2_i32m1(vint16mf2_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m2( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vsext_vf2_i32m2(vint16m1_t op1, size_t vl) { vint32m2_t test_vsext_vf2_i32m2(vint16m1_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m4( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vsext_vf2_i32m4(vint16m2_t op1, size_t vl) { vint32m4_t test_vsext_vf2_i32m4(vint16m2_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m8( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vsext_vf2_i32m8(vint16m4_t op1, size_t vl) { vint32m8_t test_vsext_vf2_i32m8(vint16m4_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m1( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vsext_vf4_i64m1(vint16mf4_t op1, size_t vl) { vint64m1_t test_vsext_vf4_i64m1(vint16mf4_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m2( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vsext_vf4_i64m2(vint16mf2_t op1, size_t vl) { vint64m2_t test_vsext_vf4_i64m2(vint16mf2_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m4( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vsext_vf4_i64m4(vint16m1_t op1, size_t vl) { vint64m4_t test_vsext_vf4_i64m4(vint16m1_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m8( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vsext_vf4_i64m8(vint16m2_t op1, size_t vl) { vint64m8_t test_vsext_vf4_i64m8(vint16m2_t op1, size_t vl) {
return vsext_vf4(op1, vl); return vsext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m1( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vsext_vf2_i64m1(vint32mf2_t op1, size_t vl) { vint64m1_t test_vsext_vf2_i64m1(vint32mf2_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m2( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vsext_vf2_i64m2(vint32m1_t op1, size_t vl) { vint64m2_t test_vsext_vf2_i64m2(vint32m1_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m4( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vsext_vf2_i64m4(vint32m2_t op1, size_t vl) { vint64m4_t test_vsext_vf2_i64m4(vint32m2_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m8( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vsext_vf2_i64m8(vint32m4_t op1, size_t vl) { vint64m8_t test_vsext_vf2_i64m8(vint32m4_t op1, size_t vl) {
return vsext_vf2(op1, vl); return vsext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4_m( // CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4( // CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vzext_vf2_u16mf4(vuint8mf8_t op1, size_t vl) { vuint16mf4_t test_vzext_vf2_u16mf4(vuint8mf8_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf2( // CHECK-RV64-LABEL: @test_vzext_vf2_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vzext_vf2_u16mf2(vuint8mf4_t op1, size_t vl) { vuint16mf2_t test_vzext_vf2_u16mf2(vuint8mf4_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m1( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vzext_vf2_u16m1(vuint8mf2_t op1, size_t vl) { vuint16m1_t test_vzext_vf2_u16m1(vuint8mf2_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m2( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vzext_vf2_u16m2(vuint8m1_t op1, size_t vl) { vuint16m2_t test_vzext_vf2_u16m2(vuint8m1_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m4( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vzext_vf2_u16m4(vuint8m2_t op1, size_t vl) { vuint16m4_t test_vzext_vf2_u16m4(vuint8m2_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m8( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vzext_vf2_u16m8(vuint8m4_t op1, size_t vl) { vuint16m8_t test_vzext_vf2_u16m8(vuint8m4_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32mf2( // CHECK-RV64-LABEL: @test_vzext_vf4_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vzext_vf4_u32mf2(vuint8mf8_t op1, size_t vl) { vuint32mf2_t test_vzext_vf4_u32mf2(vuint8mf8_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m1( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vzext_vf4_u32m1(vuint8mf4_t op1, size_t vl) { vuint32m1_t test_vzext_vf4_u32m1(vuint8mf4_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m2( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vzext_vf4_u32m2(vuint8mf2_t op1, size_t vl) { vuint32m2_t test_vzext_vf4_u32m2(vuint8mf2_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m4( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vzext_vf4_u32m4(vuint8m1_t op1, size_t vl) { vuint32m4_t test_vzext_vf4_u32m4(vuint8m1_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m8( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vzext_vf4_u32m8(vuint8m2_t op1, size_t vl) { vuint32m8_t test_vzext_vf4_u32m8(vuint8m2_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m1( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vzext_vf8_u64m1(vuint8mf8_t op1, size_t vl) { vuint64m1_t test_vzext_vf8_u64m1(vuint8mf8_t op1, size_t vl) {
return vzext_vf8(op1, vl); return vzext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m2( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vzext_vf8_u64m2(vuint8mf4_t op1, size_t vl) { vuint64m2_t test_vzext_vf8_u64m2(vuint8mf4_t op1, size_t vl) {
return vzext_vf8(op1, vl); return vzext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m4( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vzext_vf8_u64m4(vuint8mf2_t op1, size_t vl) { vuint64m4_t test_vzext_vf8_u64m4(vuint8mf2_t op1, size_t vl) {
return vzext_vf8(op1, vl); return vzext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m8( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vzext_vf8_u64m8(vuint8m1_t op1, size_t vl) { vuint64m8_t test_vzext_vf8_u64m8(vuint8m1_t op1, size_t vl) {
return vzext_vf8(op1, vl); return vzext_vf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32mf2( // CHECK-RV64-LABEL: @test_vzext_vf2_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vzext_vf2_u32mf2(vuint16mf4_t op1, size_t vl) { vuint32mf2_t test_vzext_vf2_u32mf2(vuint16mf4_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m1( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vzext_vf2_u32m1(vuint16mf2_t op1, size_t vl) { vuint32m1_t test_vzext_vf2_u32m1(vuint16mf2_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m2( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vzext_vf2_u32m2(vuint16m1_t op1, size_t vl) { vuint32m2_t test_vzext_vf2_u32m2(vuint16m1_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m4( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vzext_vf2_u32m4(vuint16m2_t op1, size_t vl) { vuint32m4_t test_vzext_vf2_u32m4(vuint16m2_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m8( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vzext_vf2_u32m8(vuint16m4_t op1, size_t vl) { vuint32m8_t test_vzext_vf2_u32m8(vuint16m4_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m1( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vzext_vf4_u64m1(vuint16mf4_t op1, size_t vl) { vuint64m1_t test_vzext_vf4_u64m1(vuint16mf4_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m2( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vzext_vf4_u64m2(vuint16mf2_t op1, size_t vl) { vuint64m2_t test_vzext_vf4_u64m2(vuint16mf2_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m4( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vzext_vf4_u64m4(vuint16m1_t op1, size_t vl) { vuint64m4_t test_vzext_vf4_u64m4(vuint16m1_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m8( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vzext_vf4_u64m8(vuint16m2_t op1, size_t vl) { vuint64m8_t test_vzext_vf4_u64m8(vuint16m2_t op1, size_t vl) {
return vzext_vf4(op1, vl); return vzext_vf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m1( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vzext_vf2_u64m1(vuint32mf2_t op1, size_t vl) { vuint64m1_t test_vzext_vf2_u64m1(vuint32mf2_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m2( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vzext_vf2_u64m2(vuint32m1_t op1, size_t vl) { vuint64m2_t test_vzext_vf2_u64m2(vuint32m1_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m4( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vzext_vf2_u64m4(vuint32m2_t op1, size_t vl) { vuint64m4_t test_vzext_vf2_u64m4(vuint32m2_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m8( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vzext_vf2_u64m8(vuint32m4_t op1, size_t vl) { vuint64m8_t test_vzext_vf2_u64m8(vuint32m4_t op1, size_t vl) {
return vzext_vf2(op1, vl); return vzext_vf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4_m( // CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 277 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2( // CHECK-RV64-LABEL: @test_vfclass_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfclass_v_u32mf2(vfloat32mf2_t op1, size_t vl) { vuint32mf2_t test_vfclass_v_u32mf2(vfloat32mf2_t op1, size_t vl) {
return vfclass_v_u32mf2(op1, vl); return vfclass_v_u32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m1( // CHECK-RV64-LABEL: @test_vfclass_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfclass_v_u32m1(vfloat32m1_t op1, size_t vl) { vuint32m1_t test_vfclass_v_u32m1(vfloat32m1_t op1, size_t vl) {
return vfclass_v_u32m1(op1, vl); return vfclass_v_u32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m2( // CHECK-RV64-LABEL: @test_vfclass_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfclass_v_u32m2(vfloat32m2_t op1, size_t vl) { vuint32m2_t test_vfclass_v_u32m2(vfloat32m2_t op1, size_t vl) {
return vfclass_v_u32m2(op1, vl); return vfclass_v_u32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m4( // CHECK-RV64-LABEL: @test_vfclass_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfclass_v_u32m4(vfloat32m4_t op1, size_t vl) { vuint32m4_t test_vfclass_v_u32m4(vfloat32m4_t op1, size_t vl) {
return vfclass_v_u32m4(op1, vl); return vfclass_v_u32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m8( // CHECK-RV64-LABEL: @test_vfclass_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfclass_v_u32m8(vfloat32m8_t op1, size_t vl) { vuint32m8_t test_vfclass_v_u32m8(vfloat32m8_t op1, size_t vl) {
return vfclass_v_u32m8(op1, vl); return vfclass_v_u32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m1( // CHECK-RV64-LABEL: @test_vfclass_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfclass_v_u64m1(vfloat64m1_t op1, size_t vl) { vuint64m1_t test_vfclass_v_u64m1(vfloat64m1_t op1, size_t vl) {
return vfclass_v_u64m1(op1, vl); return vfclass_v_u64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m2( // CHECK-RV64-LABEL: @test_vfclass_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfclass_v_u64m2(vfloat64m2_t op1, size_t vl) { vuint64m2_t test_vfclass_v_u64m2(vfloat64m2_t op1, size_t vl) {
return vfclass_v_u64m2(op1, vl); return vfclass_v_u64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m4( // CHECK-RV64-LABEL: @test_vfclass_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfclass_v_u64m4(vfloat64m4_t op1, size_t vl) { vuint64m4_t test_vfclass_v_u64m4(vfloat64m4_t op1, size_t vl) {
return vfclass_v_u64m4(op1, vl); return vfclass_v_u64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m8( // CHECK-RV64-LABEL: @test_vfclass_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfclass_v_u64m8(vfloat64m8_t op1, size_t vl) { vuint64m8_t test_vfclass_v_u64m8(vfloat64m8_t op1, size_t vl) {
return vfclass_v_u64m8(op1, vl); return vfclass_v_u64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32mf2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1f32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfclass_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t test_vfclass_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff,
vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t op1, size_t vl) {
return vfclass_v_u32mf2_m(mask, maskedoff, op1, vl); return vfclass_v_u32mf2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m1_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2f32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfclass_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t test_vfclass_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff,
vfloat32m1_t op1, size_t vl) { vfloat32m1_t op1, size_t vl) {
return vfclass_v_u32m1_m(mask, maskedoff, op1, vl); return vfclass_v_u32m1_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4f32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfclass_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t test_vfclass_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff,
vfloat32m2_t op1, size_t vl) { vfloat32m2_t op1, size_t vl) {
return vfclass_v_u32m2_m(mask, maskedoff, op1, vl); return vfclass_v_u32m2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m4_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8f32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfclass_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t test_vfclass_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff,
vfloat32m4_t op1, size_t vl) { vfloat32m4_t op1, size_t vl) {
return vfclass_v_u32m4_m(mask, maskedoff, op1, vl); return vfclass_v_u32m4_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u32m8_m( // CHECK-RV64-LABEL: @test_vfclass_v_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16f32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x float> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfclass_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t test_vfclass_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff,
vfloat32m8_t op1, size_t vl) { vfloat32m8_t op1, size_t vl) {
return vfclass_v_u32m8_m(mask, maskedoff, op1, vl); return vfclass_v_u32m8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m1_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1f64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfclass_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t test_vfclass_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff,
vfloat64m1_t op1, size_t vl) { vfloat64m1_t op1, size_t vl) {
return vfclass_v_u64m1_m(mask, maskedoff, op1, vl); return vfclass_v_u64m1_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2f64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfclass_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t test_vfclass_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff,
vfloat64m2_t op1, size_t vl) { vfloat64m2_t op1, size_t vl) {
return vfclass_v_u64m2_m(mask, maskedoff, op1, vl); return vfclass_v_u64m2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m4_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4f64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x double> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfclass_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t test_vfclass_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff,
vfloat64m4_t op1, size_t vl) { vfloat64m4_t op1, size_t vl) {
return vfclass_v_u64m4_m(mask, maskedoff, op1, vl); return vfclass_v_u64m4_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u64m8_m( // CHECK-RV64-LABEL: @test_vfclass_v_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8f64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x double> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfclass_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t test_vfclass_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff,
vfloat64m8_t op1, size_t vl) { vfloat64m8_t op1, size_t vl) {
return vfclass_v_u64m8_m(mask, maskedoff, op1, vl); return vfclass_v_u64m8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16mf4( // CHECK-RV64-LABEL: @test_vfclass_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1f16.i64(<vscale x 1 x i16> undef, <vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfclass_v_u16mf4 (vfloat16mf4_t op1, size_t vl) { vuint16mf4_t test_vfclass_v_u16mf4 (vfloat16mf4_t op1, size_t vl) {
return vfclass_v_u16mf4(op1, vl); return vfclass_v_u16mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16mf2( // CHECK-RV64-LABEL: @test_vfclass_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2f16.i64(<vscale x 2 x i16> undef, <vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfclass_v_u16mf2 (vfloat16mf2_t op1, size_t vl) { vuint16mf2_t test_vfclass_v_u16mf2 (vfloat16mf2_t op1, size_t vl) {
return vfclass_v_u16mf2(op1, vl); return vfclass_v_u16mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m1( // CHECK-RV64-LABEL: @test_vfclass_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4f16.i64(<vscale x 4 x i16> undef, <vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfclass_v_u16m1 (vfloat16m1_t op1, size_t vl) { vuint16m1_t test_vfclass_v_u16m1 (vfloat16m1_t op1, size_t vl) {
return vfclass_v_u16m1(op1, vl); return vfclass_v_u16m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m2( // CHECK-RV64-LABEL: @test_vfclass_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8f16.i64(<vscale x 8 x i16> undef, <vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfclass_v_u16m2 (vfloat16m2_t op1, size_t vl) { vuint16m2_t test_vfclass_v_u16m2 (vfloat16m2_t op1, size_t vl) {
return vfclass_v_u16m2(op1, vl); return vfclass_v_u16m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m4( // CHECK-RV64-LABEL: @test_vfclass_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16f16.i64(<vscale x 16 x i16> undef, <vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfclass_v_u16m4 (vfloat16m4_t op1, size_t vl) { vuint16m4_t test_vfclass_v_u16m4 (vfloat16m4_t op1, size_t vl) {
return vfclass_v_u16m4(op1, vl); return vfclass_v_u16m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m8( // CHECK-RV64-LABEL: @test_vfclass_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32f16.i64(<vscale x 32 x i16> undef, <vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vfclass_v_u16m8 (vfloat16m8_t op1, size_t vl) { vuint16m8_t test_vfclass_v_u16m8 (vfloat16m8_t op1, size_t vl) {
return vfclass_v_u16m8(op1, vl); return vfclass_v_u16m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16mf4_m( // CHECK-RV64-LABEL: @test_vfclass_v_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1f16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x half> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfclass_v_u16mf4_m (vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t op1, size_t vl) { vuint16mf4_t test_vfclass_v_u16mf4_m (vbool64_t mask, vuint16mf4_t maskedoff, vfloat16mf4_t op1, size_t vl) {
return vfclass_v_u16mf4_m(mask, maskedoff, op1, vl); return vfclass_v_u16mf4_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16mf2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2f16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x half> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfclass_v_u16mf2_m (vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t op1, size_t vl) { vuint16mf2_t test_vfclass_v_u16mf2_m (vbool32_t mask, vuint16mf2_t maskedoff, vfloat16mf2_t op1, size_t vl) {
return vfclass_v_u16mf2_m(mask, maskedoff, op1, vl); return vfclass_v_u16mf2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m1_m( // CHECK-RV64-LABEL: @test_vfclass_v_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4f16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfclass_v_u16m1_m (vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t op1, size_t vl) { vuint16m1_t test_vfclass_v_u16m1_m (vbool16_t mask, vuint16m1_t maskedoff, vfloat16m1_t op1, size_t vl) {
return vfclass_v_u16m1_m(mask, maskedoff, op1, vl); return vfclass_v_u16m1_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m2_m( // CHECK-RV64-LABEL: @test_vfclass_v_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8f16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfclass_v_u16m2_m (vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t op1, size_t vl) { vuint16m2_t test_vfclass_v_u16m2_m (vbool8_t mask, vuint16m2_t maskedoff, vfloat16m2_t op1, size_t vl) {
return vfclass_v_u16m2_m(mask, maskedoff, op1, vl); return vfclass_v_u16m2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m4_m( // CHECK-RV64-LABEL: @test_vfclass_v_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16f16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x half> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfclass_v_u16m4_m (vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t op1, size_t vl) { vuint16m4_t test_vfclass_v_u16m4_m (vbool4_t mask, vuint16m4_t maskedoff, vfloat16m4_t op1, size_t vl) {
return vfclass_v_u16m4_m(mask, maskedoff, op1, vl); return vfclass_v_u16m4_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfclass_v_u16m8_m( // CHECK-RV64-LABEL: @test_vfclass_v_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32f16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x half> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vfclass_v_u16m8_m (vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t op1, size_t vl) { vuint16m8_t test_vfclass_v_u16m8_m (vbool2_t mask, vuint16m8_t maskedoff, vfloat16m8_t op1, size_t vl) {
return vfclass_v_u16m8_m(mask, maskedoff, op1, vl); return vfclass_v_u16m8_m(mask, maskedoff, op1, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfcvt_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) { vint32mf2_t test_vfcvt_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_x_f_v_i32mf2(src, vl); return vfcvt_x_f_v_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32mf2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfcvt_rtz_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) { vint32mf2_t test_vfcvt_rtz_x_f_v_i32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i32mf2(src, vl); return vfcvt_rtz_x_f_v_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m1( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfcvt_x_f_v_i32m1(vfloat32m1_t src, size_t vl) { vint32m1_t test_vfcvt_x_f_v_i32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_x_f_v_i32m1(src, vl); return vfcvt_x_f_v_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfcvt_rtz_x_f_v_i32m1(vfloat32m1_t src, size_t vl) { vint32m1_t test_vfcvt_rtz_x_f_v_i32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i32m1(src, vl); return vfcvt_rtz_x_f_v_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfcvt_x_f_v_i32m2(vfloat32m2_t src, size_t vl) { vint32m2_t test_vfcvt_x_f_v_i32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_x_f_v_i32m2(src, vl); return vfcvt_x_f_v_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfcvt_rtz_x_f_v_i32m2(vfloat32m2_t src, size_t vl) { vint32m2_t test_vfcvt_rtz_x_f_v_i32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i32m2(src, vl); return vfcvt_rtz_x_f_v_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m4( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfcvt_x_f_v_i32m4(vfloat32m4_t src, size_t vl) { vint32m4_t test_vfcvt_x_f_v_i32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_x_f_v_i32m4(src, vl); return vfcvt_x_f_v_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfcvt_rtz_x_f_v_i32m4(vfloat32m4_t src, size_t vl) { vint32m4_t test_vfcvt_rtz_x_f_v_i32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i32m4(src, vl); return vfcvt_rtz_x_f_v_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m8( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vfcvt_x_f_v_i32m8(vfloat32m8_t src, size_t vl) { vint32m8_t test_vfcvt_x_f_v_i32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_x_f_v_i32m8(src, vl); return vfcvt_x_f_v_i32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vfcvt_rtz_x_f_v_i32m8(vfloat32m8_t src, size_t vl) { vint32m8_t test_vfcvt_rtz_x_f_v_i32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i32m8(src, vl); return vfcvt_rtz_x_f_v_i32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32mf2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfcvt_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) { vuint32mf2_t test_vfcvt_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_xu_f_v_u32mf2(src, vl); return vfcvt_xu_f_v_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32mf2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32.i64(<vscale x 1 x i32> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfcvt_rtz_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) { vuint32mf2_t test_vfcvt_rtz_xu_f_v_u32mf2(vfloat32mf2_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u32mf2(src, vl); return vfcvt_rtz_xu_f_v_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m1( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfcvt_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) { vuint32m1_t test_vfcvt_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_xu_f_v_u32m1(src, vl); return vfcvt_xu_f_v_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32.i64(<vscale x 2 x i32> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfcvt_rtz_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) { vuint32m1_t test_vfcvt_rtz_xu_f_v_u32m1(vfloat32m1_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u32m1(src, vl); return vfcvt_rtz_xu_f_v_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfcvt_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) { vuint32m2_t test_vfcvt_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_xu_f_v_u32m2(src, vl); return vfcvt_xu_f_v_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32.i64(<vscale x 4 x i32> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfcvt_rtz_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) { vuint32m2_t test_vfcvt_rtz_xu_f_v_u32m2(vfloat32m2_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u32m2(src, vl); return vfcvt_rtz_xu_f_v_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m4( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfcvt_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) { vuint32m4_t test_vfcvt_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_xu_f_v_u32m4(src, vl); return vfcvt_xu_f_v_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32.i64(<vscale x 8 x i32> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfcvt_rtz_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) { vuint32m4_t test_vfcvt_rtz_xu_f_v_u32m4(vfloat32m4_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u32m4(src, vl); return vfcvt_rtz_xu_f_v_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m8( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfcvt_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) { vuint32m8_t test_vfcvt_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_xu_f_v_u32m8(src, vl); return vfcvt_xu_f_v_u32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32.i64(<vscale x 16 x i32> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfcvt_rtz_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) { vuint32m8_t test_vfcvt_rtz_xu_f_v_u32m8(vfloat32m8_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u32m8(src, vl); return vfcvt_rtz_xu_f_v_u32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32mf2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfcvt_f_x_v_f32mf2(vint32mf2_t src, size_t vl) { vfloat32mf2_t test_vfcvt_f_x_v_f32mf2(vint32mf2_t src, size_t vl) {
return vfcvt_f_x_v_f32mf2(src, vl); return vfcvt_f_x_v_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m1( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfcvt_f_x_v_f32m1(vint32m1_t src, size_t vl) { vfloat32m1_t test_vfcvt_f_x_v_f32m1(vint32m1_t src, size_t vl) {
return vfcvt_f_x_v_f32m1(src, vl); return vfcvt_f_x_v_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfcvt_f_x_v_f32m2(vint32m2_t src, size_t vl) { vfloat32m2_t test_vfcvt_f_x_v_f32m2(vint32m2_t src, size_t vl) {
return vfcvt_f_x_v_f32m2(src, vl); return vfcvt_f_x_v_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m4( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfcvt_f_x_v_f32m4(vint32m4_t src, size_t vl) { vfloat32m4_t test_vfcvt_f_x_v_f32m4(vint32m4_t src, size_t vl) {
return vfcvt_f_x_v_f32m4(src, vl); return vfcvt_f_x_v_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m8( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfcvt_f_x_v_f32m8(vint32m8_t src, size_t vl) { vfloat32m8_t test_vfcvt_f_x_v_f32m8(vint32m8_t src, size_t vl) {
return vfcvt_f_x_v_f32m8(src, vl); return vfcvt_f_x_v_f32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32mf2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2(vuint32mf2_t src, size_t vl) { vfloat32mf2_t test_vfcvt_f_xu_v_f32mf2(vuint32mf2_t src, size_t vl) {
return vfcvt_f_xu_v_f32mf2(src, vl); return vfcvt_f_xu_v_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m1( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32.i64(<vscale x 2 x float> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfcvt_f_xu_v_f32m1(vuint32m1_t src, size_t vl) { vfloat32m1_t test_vfcvt_f_xu_v_f32m1(vuint32m1_t src, size_t vl) {
return vfcvt_f_xu_v_f32m1(src, vl); return vfcvt_f_xu_v_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32.i64(<vscale x 4 x float> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfcvt_f_xu_v_f32m2(vuint32m2_t src, size_t vl) { vfloat32m2_t test_vfcvt_f_xu_v_f32m2(vuint32m2_t src, size_t vl) {
return vfcvt_f_xu_v_f32m2(src, vl); return vfcvt_f_xu_v_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m4( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32.i64(<vscale x 8 x float> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfcvt_f_xu_v_f32m4(vuint32m4_t src, size_t vl) { vfloat32m4_t test_vfcvt_f_xu_v_f32m4(vuint32m4_t src, size_t vl) {
return vfcvt_f_xu_v_f32m4(src, vl); return vfcvt_f_xu_v_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m8( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32.i64(<vscale x 16 x float> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfcvt_f_xu_v_f32m8(vuint32m8_t src, size_t vl) { vfloat32m8_t test_vfcvt_f_xu_v_f32m8(vuint32m8_t src, size_t vl) {
return vfcvt_f_xu_v_f32m8(src, vl); return vfcvt_f_xu_v_f32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfcvt_x_f_v_i64m1(vfloat64m1_t src, size_t vl) { vint64m1_t test_vfcvt_x_f_v_i64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_x_f_v_i64m1(src, vl); return vfcvt_x_f_v_i64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfcvt_rtz_x_f_v_i64m1(vfloat64m1_t src, size_t vl) { vint64m1_t test_vfcvt_rtz_x_f_v_i64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i64m1(src, vl); return vfcvt_rtz_x_f_v_i64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfcvt_x_f_v_i64m2(vfloat64m2_t src, size_t vl) { vint64m2_t test_vfcvt_x_f_v_i64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_x_f_v_i64m2(src, vl); return vfcvt_x_f_v_i64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfcvt_rtz_x_f_v_i64m2(vfloat64m2_t src, size_t vl) { vint64m2_t test_vfcvt_rtz_x_f_v_i64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i64m2(src, vl); return vfcvt_rtz_x_f_v_i64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfcvt_x_f_v_i64m4(vfloat64m4_t src, size_t vl) { vint64m4_t test_vfcvt_x_f_v_i64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_x_f_v_i64m4(src, vl); return vfcvt_x_f_v_i64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfcvt_rtz_x_f_v_i64m4(vfloat64m4_t src, size_t vl) { vint64m4_t test_vfcvt_rtz_x_f_v_i64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i64m4(src, vl); return vfcvt_rtz_x_f_v_i64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfcvt_x_f_v_i64m8(vfloat64m8_t src, size_t vl) { vint64m8_t test_vfcvt_x_f_v_i64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_x_f_v_i64m8(src, vl); return vfcvt_x_f_v_i64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfcvt_rtz_x_f_v_i64m8(vfloat64m8_t src, size_t vl) { vint64m8_t test_vfcvt_rtz_x_f_v_i64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i64m8(src, vl); return vfcvt_rtz_x_f_v_i64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfcvt_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) { vuint64m1_t test_vfcvt_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_xu_f_v_u64m1(src, vl); return vfcvt_xu_f_v_u64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64.i64(<vscale x 1 x i64> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfcvt_rtz_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) { vuint64m1_t test_vfcvt_rtz_xu_f_v_u64m1(vfloat64m1_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u64m1(src, vl); return vfcvt_rtz_xu_f_v_u64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfcvt_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) { vuint64m2_t test_vfcvt_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_xu_f_v_u64m2(src, vl); return vfcvt_xu_f_v_u64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64.i64(<vscale x 2 x i64> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfcvt_rtz_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) { vuint64m2_t test_vfcvt_rtz_xu_f_v_u64m2(vfloat64m2_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u64m2(src, vl); return vfcvt_rtz_xu_f_v_u64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfcvt_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) { vuint64m4_t test_vfcvt_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_xu_f_v_u64m4(src, vl); return vfcvt_xu_f_v_u64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64.i64(<vscale x 4 x i64> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfcvt_rtz_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) { vuint64m4_t test_vfcvt_rtz_xu_f_v_u64m4(vfloat64m4_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u64m4(src, vl); return vfcvt_rtz_xu_f_v_u64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfcvt_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) { vuint64m8_t test_vfcvt_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_xu_f_v_u64m8(src, vl); return vfcvt_xu_f_v_u64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64.i64(<vscale x 8 x i64> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfcvt_rtz_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) { vuint64m8_t test_vfcvt_rtz_xu_f_v_u64m8(vfloat64m8_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u64m8(src, vl); return vfcvt_rtz_xu_f_v_u64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m1( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfcvt_f_x_v_f64m1(vint64m1_t src, size_t vl) { vfloat64m1_t test_vfcvt_f_x_v_f64m1(vint64m1_t src, size_t vl) {
return vfcvt_f_x_v_f64m1(src, vl); return vfcvt_f_x_v_f64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfcvt_f_x_v_f64m2(vint64m2_t src, size_t vl) { vfloat64m2_t test_vfcvt_f_x_v_f64m2(vint64m2_t src, size_t vl) {
return vfcvt_f_x_v_f64m2(src, vl); return vfcvt_f_x_v_f64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m4( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfcvt_f_x_v_f64m4(vint64m4_t src, size_t vl) { vfloat64m4_t test_vfcvt_f_x_v_f64m4(vint64m4_t src, size_t vl) {
return vfcvt_f_x_v_f64m4(src, vl); return vfcvt_f_x_v_f64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m8( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfcvt_f_x_v_f64m8(vint64m8_t src, size_t vl) { vfloat64m8_t test_vfcvt_f_x_v_f64m8(vint64m8_t src, size_t vl) {
return vfcvt_f_x_v_f64m8(src, vl); return vfcvt_f_x_v_f64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m1( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64.i64(<vscale x 1 x double> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfcvt_f_xu_v_f64m1(vuint64m1_t src, size_t vl) { vfloat64m1_t test_vfcvt_f_xu_v_f64m1(vuint64m1_t src, size_t vl) {
return vfcvt_f_xu_v_f64m1(src, vl); return vfcvt_f_xu_v_f64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64.i64(<vscale x 2 x double> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfcvt_f_xu_v_f64m2(vuint64m2_t src, size_t vl) { vfloat64m2_t test_vfcvt_f_xu_v_f64m2(vuint64m2_t src, size_t vl) {
return vfcvt_f_xu_v_f64m2(src, vl); return vfcvt_f_xu_v_f64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m4( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64.i64(<vscale x 4 x double> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfcvt_f_xu_v_f64m4(vuint64m4_t src, size_t vl) { vfloat64m4_t test_vfcvt_f_xu_v_f64m4(vuint64m4_t src, size_t vl) {
return vfcvt_f_xu_v_f64m4(src, vl); return vfcvt_f_xu_v_f64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m8( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64.i64(<vscale x 8 x double> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfcvt_f_xu_v_f64m8(vuint64m8_t src, size_t vl) { vfloat64m8_t test_vfcvt_f_xu_v_f64m8(vuint64m8_t src, size_t vl) {
return vfcvt_f_xu_v_f64m8(src, vl); return vfcvt_f_xu_v_f64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2_m( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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// //
vfloat64m8_t test_vfcvt_f_xu_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t test_vfcvt_f_xu_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
vuint64m8_t src, size_t vl) { vuint64m8_t src, size_t vl) {
return vfcvt_f_xu_v_f64m8_m(mask, maskedoff, src, vl); return vfcvt_f_xu_v_f64m8_m(mask, maskedoff, src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16mf4( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vfcvt_x_f_v_i16mf4 (vfloat16mf4_t src, size_t vl) { vint16mf4_t test_vfcvt_x_f_v_i16mf4 (vfloat16mf4_t src, size_t vl) {
return vfcvt_x_f_v_i16mf4(src, vl); return vfcvt_x_f_v_i16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16mf4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vfcvt_rtz_x_f_v_i16mf4 (vfloat16mf4_t src, size_t vl) { vint16mf4_t test_vfcvt_rtz_x_f_v_i16mf4 (vfloat16mf4_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i16mf4(src, vl); return vfcvt_rtz_x_f_v_i16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16mf2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vfcvt_x_f_v_i16mf2 (vfloat16mf2_t src, size_t vl) { vint16mf2_t test_vfcvt_x_f_v_i16mf2 (vfloat16mf2_t src, size_t vl) {
return vfcvt_x_f_v_i16mf2(src, vl); return vfcvt_x_f_v_i16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16mf2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vfcvt_rtz_x_f_v_i16mf2 (vfloat16mf2_t src, size_t vl) { vint16mf2_t test_vfcvt_rtz_x_f_v_i16mf2 (vfloat16mf2_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i16mf2(src, vl); return vfcvt_rtz_x_f_v_i16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m1( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vfcvt_x_f_v_i16m1 (vfloat16m1_t src, size_t vl) { vint16m1_t test_vfcvt_x_f_v_i16m1 (vfloat16m1_t src, size_t vl) {
return vfcvt_x_f_v_i16m1(src, vl); return vfcvt_x_f_v_i16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vfcvt_rtz_x_f_v_i16m1 (vfloat16m1_t src, size_t vl) { vint16m1_t test_vfcvt_rtz_x_f_v_i16m1 (vfloat16m1_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i16m1(src, vl); return vfcvt_rtz_x_f_v_i16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m2( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vfcvt_x_f_v_i16m2 (vfloat16m2_t src, size_t vl) { vint16m2_t test_vfcvt_x_f_v_i16m2 (vfloat16m2_t src, size_t vl) {
return vfcvt_x_f_v_i16m2(src, vl); return vfcvt_x_f_v_i16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vfcvt_rtz_x_f_v_i16m2 (vfloat16m2_t src, size_t vl) { vint16m2_t test_vfcvt_rtz_x_f_v_i16m2 (vfloat16m2_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i16m2(src, vl); return vfcvt_rtz_x_f_v_i16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m4( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vfcvt_x_f_v_i16m4 (vfloat16m4_t src, size_t vl) { vint16m4_t test_vfcvt_x_f_v_i16m4 (vfloat16m4_t src, size_t vl) {
return vfcvt_x_f_v_i16m4(src, vl); return vfcvt_x_f_v_i16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vfcvt_rtz_x_f_v_i16m4 (vfloat16m4_t src, size_t vl) { vint16m4_t test_vfcvt_rtz_x_f_v_i16m4 (vfloat16m4_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i16m4(src, vl); return vfcvt_rtz_x_f_v_i16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m8( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vfcvt_x_f_v_i16m8 (vfloat16m8_t src, size_t vl) { vint16m8_t test_vfcvt_x_f_v_i16m8 (vfloat16m8_t src, size_t vl) {
return vfcvt_x_f_v_i16m8(src, vl); return vfcvt_x_f_v_i16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_x_f_v_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vfcvt_rtz_x_f_v_i16m8 (vfloat16m8_t src, size_t vl) { vint16m8_t test_vfcvt_rtz_x_f_v_i16m8 (vfloat16m8_t src, size_t vl) {
return vfcvt_rtz_x_f_v_i16m8(src, vl); return vfcvt_rtz_x_f_v_i16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16mf4( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfcvt_xu_f_v_u16mf4 (vfloat16mf4_t src, size_t vl) { vuint16mf4_t test_vfcvt_xu_f_v_u16mf4 (vfloat16mf4_t src, size_t vl) {
return vfcvt_xu_f_v_u16mf4(src, vl); return vfcvt_xu_f_v_u16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16mf4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(<vscale x 1 x i16> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfcvt_rtz_xu_f_v_u16mf4 (vfloat16mf4_t src, size_t vl) { vuint16mf4_t test_vfcvt_rtz_xu_f_v_u16mf4 (vfloat16mf4_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u16mf4(src, vl); return vfcvt_rtz_xu_f_v_u16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16mf2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfcvt_xu_f_v_u16mf2 (vfloat16mf2_t src, size_t vl) { vuint16mf2_t test_vfcvt_xu_f_v_u16mf2 (vfloat16mf2_t src, size_t vl) {
return vfcvt_xu_f_v_u16mf2(src, vl); return vfcvt_xu_f_v_u16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16mf2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(<vscale x 2 x i16> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfcvt_rtz_xu_f_v_u16mf2 (vfloat16mf2_t src, size_t vl) { vuint16mf2_t test_vfcvt_rtz_xu_f_v_u16mf2 (vfloat16mf2_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u16mf2(src, vl); return vfcvt_rtz_xu_f_v_u16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m1( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfcvt_xu_f_v_u16m1 (vfloat16m1_t src, size_t vl) { vuint16m1_t test_vfcvt_xu_f_v_u16m1 (vfloat16m1_t src, size_t vl) {
return vfcvt_xu_f_v_u16m1(src, vl); return vfcvt_xu_f_v_u16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m1( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(<vscale x 4 x i16> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfcvt_rtz_xu_f_v_u16m1 (vfloat16m1_t src, size_t vl) { vuint16m1_t test_vfcvt_rtz_xu_f_v_u16m1 (vfloat16m1_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u16m1(src, vl); return vfcvt_rtz_xu_f_v_u16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m2( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfcvt_xu_f_v_u16m2 (vfloat16m2_t src, size_t vl) { vuint16m2_t test_vfcvt_xu_f_v_u16m2 (vfloat16m2_t src, size_t vl) {
return vfcvt_xu_f_v_u16m2(src, vl); return vfcvt_xu_f_v_u16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m2( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(<vscale x 8 x i16> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfcvt_rtz_xu_f_v_u16m2 (vfloat16m2_t src, size_t vl) { vuint16m2_t test_vfcvt_rtz_xu_f_v_u16m2 (vfloat16m2_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u16m2(src, vl); return vfcvt_rtz_xu_f_v_u16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m4( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfcvt_xu_f_v_u16m4 (vfloat16m4_t src, size_t vl) { vuint16m4_t test_vfcvt_xu_f_v_u16m4 (vfloat16m4_t src, size_t vl) {
return vfcvt_xu_f_v_u16m4(src, vl); return vfcvt_xu_f_v_u16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m4( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(<vscale x 16 x i16> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfcvt_rtz_xu_f_v_u16m4 (vfloat16m4_t src, size_t vl) { vuint16m4_t test_vfcvt_rtz_xu_f_v_u16m4 (vfloat16m4_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u16m4(src, vl); return vfcvt_rtz_xu_f_v_u16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m8( // CHECK-RV64-LABEL: @test_vfcvt_xu_f_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vfcvt_xu_f_v_u16m8 (vfloat16m8_t src, size_t vl) { vuint16m8_t test_vfcvt_xu_f_v_u16m8 (vfloat16m8_t src, size_t vl) {
return vfcvt_xu_f_v_u16m8(src, vl); return vfcvt_xu_f_v_u16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m8( // CHECK-RV64-LABEL: @test_vfcvt_rtz_xu_f_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64(<vscale x 32 x i16> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vfcvt_rtz_xu_f_v_u16m8 (vfloat16m8_t src, size_t vl) { vuint16m8_t test_vfcvt_rtz_xu_f_v_u16m8 (vfloat16m8_t src, size_t vl) {
return vfcvt_rtz_xu_f_v_u16m8(src, vl); return vfcvt_rtz_xu_f_v_u16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16mf4( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfcvt_f_x_v_f16mf4 (vint16mf4_t src, size_t vl) { vfloat16mf4_t test_vfcvt_f_x_v_f16mf4 (vint16mf4_t src, size_t vl) {
return vfcvt_f_x_v_f16mf4(src, vl); return vfcvt_f_x_v_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16mf2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfcvt_f_x_v_f16mf2 (vint16mf2_t src, size_t vl) { vfloat16mf2_t test_vfcvt_f_x_v_f16mf2 (vint16mf2_t src, size_t vl) {
return vfcvt_f_x_v_f16mf2(src, vl); return vfcvt_f_x_v_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m1( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfcvt_f_x_v_f16m1 (vint16m1_t src, size_t vl) { vfloat16m1_t test_vfcvt_f_x_v_f16m1 (vint16m1_t src, size_t vl) {
return vfcvt_f_x_v_f16m1(src, vl); return vfcvt_f_x_v_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m2( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfcvt_f_x_v_f16m2 (vint16m2_t src, size_t vl) { vfloat16m2_t test_vfcvt_f_x_v_f16m2 (vint16m2_t src, size_t vl) {
return vfcvt_f_x_v_f16m2(src, vl); return vfcvt_f_x_v_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m4( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfcvt_f_x_v_f16m4 (vint16m4_t src, size_t vl) { vfloat16m4_t test_vfcvt_f_x_v_f16m4 (vint16m4_t src, size_t vl) {
return vfcvt_f_x_v_f16m4(src, vl); return vfcvt_f_x_v_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m8( // CHECK-RV64-LABEL: @test_vfcvt_f_x_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16.i64(<vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> undef, <vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfcvt_f_x_v_f16m8 (vint16m8_t src, size_t vl) { vfloat16m8_t test_vfcvt_f_x_v_f16m8 (vint16m8_t src, size_t vl) {
return vfcvt_f_x_v_f16m8(src, vl); return vfcvt_f_x_v_f16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16mf4( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16.i64(<vscale x 1 x half> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4 (vuint16mf4_t src, size_t vl) { vfloat16mf4_t test_vfcvt_f_xu_v_f16mf4 (vuint16mf4_t src, size_t vl) {
return vfcvt_f_xu_v_f16mf4(src, vl); return vfcvt_f_xu_v_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16mf2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16.i64(<vscale x 2 x half> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2 (vuint16mf2_t src, size_t vl) { vfloat16mf2_t test_vfcvt_f_xu_v_f16mf2 (vuint16mf2_t src, size_t vl) {
return vfcvt_f_xu_v_f16mf2(src, vl); return vfcvt_f_xu_v_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m1( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16.i64(<vscale x 4 x half> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfcvt_f_xu_v_f16m1 (vuint16m1_t src, size_t vl) { vfloat16m1_t test_vfcvt_f_xu_v_f16m1 (vuint16m1_t src, size_t vl) {
return vfcvt_f_xu_v_f16m1(src, vl); return vfcvt_f_xu_v_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m2( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16.i64(<vscale x 8 x half> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfcvt_f_xu_v_f16m2 (vuint16m2_t src, size_t vl) { vfloat16m2_t test_vfcvt_f_xu_v_f16m2 (vuint16m2_t src, size_t vl) {
return vfcvt_f_xu_v_f16m2(src, vl); return vfcvt_f_xu_v_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m4( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16.i64(<vscale x 16 x half> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfcvt_f_xu_v_f16m4 (vuint16m4_t src, size_t vl) { vfloat16m4_t test_vfcvt_f_xu_v_f16m4 (vuint16m4_t src, size_t vl) {
return vfcvt_f_xu_v_f16m4(src, vl); return vfcvt_f_xu_v_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m8( // CHECK-RV64-LABEL: @test_vfcvt_f_xu_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16.i64(<vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16.i64(<vscale x 32 x half> undef, <vscale x 32 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfcvt_f_xu_v_f16m8 (vuint16m8_t src, size_t vl) { vfloat16m8_t test_vfcvt_f_xu_v_f16m8 (vuint16m8_t src, size_t vl) {
return vfcvt_f_xu_v_f16m8(src, vl); return vfcvt_f_xu_v_f16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16mf4_m( // CHECK-RV64-LABEL: @test_vfcvt_x_f_v_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vfncvt_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) { vint16mf4_t test_vfncvt_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_x_f_w_i16mf4(src, vl); return vfncvt_x_f_w_i16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vfncvt_rtz_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) { vint16mf4_t test_vfncvt_rtz_x_f_w_i16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i16mf4(src, vl); return vfncvt_rtz_x_f_w_i16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vfncvt_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) { vint16mf2_t test_vfncvt_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_x_f_w_i16mf2(src, vl); return vfncvt_x_f_w_i16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vfncvt_rtz_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) { vint16mf2_t test_vfncvt_rtz_x_f_w_i16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i16mf2(src, vl); return vfncvt_rtz_x_f_w_i16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m1( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vfncvt_x_f_w_i16m1(vfloat32m2_t src, size_t vl) { vint16m1_t test_vfncvt_x_f_w_i16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_x_f_w_i16m1(src, vl); return vfncvt_x_f_w_i16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vfncvt_rtz_x_f_w_i16m1(vfloat32m2_t src, size_t vl) { vint16m1_t test_vfncvt_rtz_x_f_w_i16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i16m1(src, vl); return vfncvt_rtz_x_f_w_i16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vfncvt_x_f_w_i16m2(vfloat32m4_t src, size_t vl) { vint16m2_t test_vfncvt_x_f_w_i16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_x_f_w_i16m2(src, vl); return vfncvt_x_f_w_i16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vfncvt_rtz_x_f_w_i16m2(vfloat32m4_t src, size_t vl) { vint16m2_t test_vfncvt_rtz_x_f_w_i16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i16m2(src, vl); return vfncvt_rtz_x_f_w_i16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vfncvt_x_f_w_i16m4(vfloat32m8_t src, size_t vl) { vint16m4_t test_vfncvt_x_f_w_i16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_x_f_w_i16m4(src, vl); return vfncvt_x_f_w_i16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vfncvt_rtz_x_f_w_i16m4(vfloat32m8_t src, size_t vl) { vint16m4_t test_vfncvt_rtz_x_f_w_i16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i16m4(src, vl); return vfncvt_rtz_x_f_w_i16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfncvt_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) { vuint16mf4_t test_vfncvt_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_xu_f_w_u16mf4(src, vl); return vfncvt_xu_f_w_u16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32.i64(<vscale x 1 x i16> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vfncvt_rtz_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) { vuint16mf4_t test_vfncvt_rtz_xu_f_w_u16mf4(vfloat32mf2_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u16mf4(src, vl); return vfncvt_rtz_xu_f_w_u16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfncvt_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) { vuint16mf2_t test_vfncvt_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_xu_f_w_u16mf2(src, vl); return vfncvt_xu_f_w_u16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32.i64(<vscale x 2 x i16> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vfncvt_rtz_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) { vuint16mf2_t test_vfncvt_rtz_xu_f_w_u16mf2(vfloat32m1_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u16mf2(src, vl); return vfncvt_rtz_xu_f_w_u16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m1( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfncvt_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) { vuint16m1_t test_vfncvt_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_xu_f_w_u16m1(src, vl); return vfncvt_xu_f_w_u16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32.i64(<vscale x 4 x i16> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vfncvt_rtz_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) { vuint16m1_t test_vfncvt_rtz_xu_f_w_u16m1(vfloat32m2_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u16m1(src, vl); return vfncvt_rtz_xu_f_w_u16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfncvt_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) { vuint16m2_t test_vfncvt_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_xu_f_w_u16m2(src, vl); return vfncvt_xu_f_w_u16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32.i64(<vscale x 8 x i16> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vfncvt_rtz_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) { vuint16m2_t test_vfncvt_rtz_xu_f_w_u16m2(vfloat32m4_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u16m2(src, vl); return vfncvt_rtz_xu_f_w_u16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfncvt_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) { vuint16m4_t test_vfncvt_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_xu_f_w_u16m4(src, vl); return vfncvt_xu_f_w_u16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32.i64(<vscale x 16 x i16> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vfncvt_rtz_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) { vuint16m4_t test_vfncvt_rtz_xu_f_w_u16m4(vfloat32m8_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u16m4(src, vl); return vfncvt_rtz_xu_f_w_u16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32mf2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfncvt_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) { vint32mf2_t test_vfncvt_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_x_f_w_i32mf2(src, vl); return vfncvt_x_f_w_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfncvt_rtz_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) { vint32mf2_t test_vfncvt_rtz_x_f_w_i32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i32mf2(src, vl); return vfncvt_rtz_x_f_w_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m1( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfncvt_x_f_w_i32m1(vfloat64m2_t src, size_t vl) { vint32m1_t test_vfncvt_x_f_w_i32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_x_f_w_i32m1(src, vl); return vfncvt_x_f_w_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfncvt_rtz_x_f_w_i32m1(vfloat64m2_t src, size_t vl) { vint32m1_t test_vfncvt_rtz_x_f_w_i32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i32m1(src, vl); return vfncvt_rtz_x_f_w_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfncvt_x_f_w_i32m2(vfloat64m4_t src, size_t vl) { vint32m2_t test_vfncvt_x_f_w_i32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_x_f_w_i32m2(src, vl); return vfncvt_x_f_w_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfncvt_rtz_x_f_w_i32m2(vfloat64m4_t src, size_t vl) { vint32m2_t test_vfncvt_rtz_x_f_w_i32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i32m2(src, vl); return vfncvt_rtz_x_f_w_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfncvt_x_f_w_i32m4(vfloat64m8_t src, size_t vl) { vint32m4_t test_vfncvt_x_f_w_i32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_x_f_w_i32m4(src, vl); return vfncvt_x_f_w_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfncvt_rtz_x_f_w_i32m4(vfloat64m8_t src, size_t vl) { vint32m4_t test_vfncvt_rtz_x_f_w_i32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i32m4(src, vl); return vfncvt_rtz_x_f_w_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32mf2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfncvt_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) { vuint32mf2_t test_vfncvt_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_xu_f_w_u32mf2(src, vl); return vfncvt_xu_f_w_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64.i64(<vscale x 1 x i32> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfncvt_rtz_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) { vuint32mf2_t test_vfncvt_rtz_xu_f_w_u32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u32mf2(src, vl); return vfncvt_rtz_xu_f_w_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m1( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfncvt_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) { vuint32m1_t test_vfncvt_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_xu_f_w_u32m1(src, vl); return vfncvt_xu_f_w_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64.i64(<vscale x 2 x i32> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfncvt_rtz_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) { vuint32m1_t test_vfncvt_rtz_xu_f_w_u32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u32m1(src, vl); return vfncvt_rtz_xu_f_w_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfncvt_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) { vuint32m2_t test_vfncvt_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_xu_f_w_u32m2(src, vl); return vfncvt_xu_f_w_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64.i64(<vscale x 4 x i32> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfncvt_rtz_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) { vuint32m2_t test_vfncvt_rtz_xu_f_w_u32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u32m2(src, vl); return vfncvt_rtz_xu_f_w_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfncvt_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) { vuint32m4_t test_vfncvt_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_xu_f_w_u32m4(src, vl); return vfncvt_xu_f_w_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64.i64(<vscale x 8 x i32> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfncvt_rtz_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) { vuint32m4_t test_vfncvt_rtz_xu_f_w_u32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u32m4(src, vl); return vfncvt_rtz_xu_f_w_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_f_x_w_f32mf2(vint64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_f_x_w_f32mf2(vint64m1_t src, size_t vl) {
return vfncvt_f_x_w_f32mf2(src, vl); return vfncvt_f_x_w_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_f_x_w_f32m1(vint64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_f_x_w_f32m1(vint64m2_t src, size_t vl) {
return vfncvt_f_x_w_f32m1(src, vl); return vfncvt_f_x_w_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_f_x_w_f32m2(vint64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_f_x_w_f32m2(vint64m4_t src, size_t vl) {
return vfncvt_f_x_w_f32m2(src, vl); return vfncvt_f_x_w_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_f_x_w_f32m4(vint64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_f_x_w_f32m4(vint64m8_t src, size_t vl) {
return vfncvt_f_x_w_f32m4(src, vl); return vfncvt_f_x_w_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64.i64(<vscale x 1 x float> undef, <vscale x 1 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2(vuint64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_f_xu_w_f32mf2(vuint64m1_t src, size_t vl) {
return vfncvt_f_xu_w_f32mf2(src, vl); return vfncvt_f_xu_w_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64.i64(<vscale x 2 x float> undef, <vscale x 2 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_f_xu_w_f32m1(vuint64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_f_xu_w_f32m1(vuint64m2_t src, size_t vl) {
return vfncvt_f_xu_w_f32m1(src, vl); return vfncvt_f_xu_w_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64.i64(<vscale x 4 x float> undef, <vscale x 4 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_f_xu_w_f32m2(vuint64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_f_xu_w_f32m2(vuint64m4_t src, size_t vl) {
return vfncvt_f_xu_w_f32m2(src, vl); return vfncvt_f_xu_w_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64.i64(<vscale x 8 x float> undef, <vscale x 8 x i64> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_f_xu_w_f32m4(vuint64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_f_xu_w_f32m4(vuint64m8_t src, size_t vl) {
return vfncvt_f_xu_w_f32m4(src, vl); return vfncvt_f_xu_w_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_f_f_w_f32mf2(src, vl); return vfncvt_f_f_w_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32mf2( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(<vscale x 1 x float> undef, <vscale x 1 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) { vfloat32mf2_t test_vfncvt_rod_f_f_w_f32mf2(vfloat64m1_t src, size_t vl) {
return vfncvt_rod_f_f_w_f32mf2(src, vl); return vfncvt_rod_f_f_w_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_f_f_w_f32m1(vfloat64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_f_f_w_f32m1(src, vl); return vfncvt_f_f_w_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m1( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(<vscale x 2 x float> undef, <vscale x 2 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) { vfloat32m1_t test_vfncvt_rod_f_f_w_f32m1(vfloat64m2_t src, size_t vl) {
return vfncvt_rod_f_f_w_f32m1(src, vl); return vfncvt_rod_f_f_w_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_f_f_w_f32m2(vfloat64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_f_f_w_f32m2(src, vl); return vfncvt_f_f_w_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m2( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(<vscale x 4 x float> undef, <vscale x 4 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) { vfloat32m2_t test_vfncvt_rod_f_f_w_f32m2(vfloat64m4_t src, size_t vl) {
return vfncvt_rod_f_f_w_f32m2(src, vl); return vfncvt_rod_f_f_w_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_f_f_w_f32m4(vfloat64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_f_f_w_f32m4(src, vl); return vfncvt_f_f_w_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m4( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(<vscale x 8 x float> undef, <vscale x 8 x double> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) { vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4(vfloat64m8_t src, size_t vl) {
return vfncvt_rod_f_f_w_f32m4(src, vl); return vfncvt_rod_f_f_w_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4_m( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask, vfloat32m4_t test_vfncvt_rod_f_f_w_f32m4_m(vbool8_t mask,
vfloat32m4_t maskedoff, vfloat32m4_t maskedoff,
vfloat64m8_t src, size_t vl) { vfloat64m8_t src, size_t vl) {
return vfncvt_rod_f_f_w_f32m4_m(mask, maskedoff, src, vl); return vfncvt_rod_f_f_w_f32m4_m(mask, maskedoff, src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf8( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vfncvt_x_f_w_i8mf8 (vfloat16mf4_t src, size_t vl) { vint8mf8_t test_vfncvt_x_f_w_i8mf8 (vfloat16mf4_t src, size_t vl) {
return vfncvt_x_f_w_i8mf8(src, vl); return vfncvt_x_f_w_i8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8mf8( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vfncvt_rtz_x_f_w_i8mf8 (vfloat16mf4_t src, size_t vl) { vint8mf8_t test_vfncvt_rtz_x_f_w_i8mf8 (vfloat16mf4_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i8mf8(src, vl); return vfncvt_rtz_x_f_w_i8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vfncvt_x_f_w_i8mf4 (vfloat16mf2_t src, size_t vl) { vint8mf4_t test_vfncvt_x_f_w_i8mf4 (vfloat16mf2_t src, size_t vl) {
return vfncvt_x_f_w_i8mf4(src, vl); return vfncvt_x_f_w_i8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8mf4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vfncvt_rtz_x_f_w_i8mf4 (vfloat16mf2_t src, size_t vl) { vint8mf4_t test_vfncvt_rtz_x_f_w_i8mf4 (vfloat16mf2_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i8mf4(src, vl); return vfncvt_rtz_x_f_w_i8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vfncvt_x_f_w_i8mf2 (vfloat16m1_t src, size_t vl) { vint8mf2_t test_vfncvt_x_f_w_i8mf2 (vfloat16m1_t src, size_t vl) {
return vfncvt_x_f_w_i8mf2(src, vl); return vfncvt_x_f_w_i8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vfncvt_rtz_x_f_w_i8mf2 (vfloat16m1_t src, size_t vl) { vint8mf2_t test_vfncvt_rtz_x_f_w_i8mf2 (vfloat16m1_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i8mf2(src, vl); return vfncvt_rtz_x_f_w_i8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8m1( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vfncvt_x_f_w_i8m1 (vfloat16m2_t src, size_t vl) { vint8m1_t test_vfncvt_x_f_w_i8m1 (vfloat16m2_t src, size_t vl) {
return vfncvt_x_f_w_i8m1(src, vl); return vfncvt_x_f_w_i8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vfncvt_rtz_x_f_w_i8m1 (vfloat16m2_t src, size_t vl) { vint8m1_t test_vfncvt_rtz_x_f_w_i8m1 (vfloat16m2_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i8m1(src, vl); return vfncvt_rtz_x_f_w_i8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8m2( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vfncvt_x_f_w_i8m2 (vfloat16m4_t src, size_t vl) { vint8m2_t test_vfncvt_x_f_w_i8m2 (vfloat16m4_t src, size_t vl) {
return vfncvt_x_f_w_i8m2(src, vl); return vfncvt_x_f_w_i8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vfncvt_rtz_x_f_w_i8m2 (vfloat16m4_t src, size_t vl) { vint8m2_t test_vfncvt_rtz_x_f_w_i8m2 (vfloat16m4_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i8m2(src, vl); return vfncvt_rtz_x_f_w_i8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8m4( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vfncvt_x_f_w_i8m4 (vfloat16m8_t src, size_t vl) { vint8m4_t test_vfncvt_x_f_w_i8m4 (vfloat16m8_t src, size_t vl) {
return vfncvt_x_f_w_i8m4(src, vl); return vfncvt_x_f_w_i8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_x_f_w_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vfncvt_rtz_x_f_w_i8m4 (vfloat16m8_t src, size_t vl) { vint8m4_t test_vfncvt_rtz_x_f_w_i8m4 (vfloat16m8_t src, size_t vl) {
return vfncvt_rtz_x_f_w_i8m4(src, vl); return vfncvt_rtz_x_f_w_i8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8mf8( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vfncvt_xu_f_w_u8mf8 (vfloat16mf4_t src, size_t vl) { vuint8mf8_t test_vfncvt_xu_f_w_u8mf8 (vfloat16mf4_t src, size_t vl) {
return vfncvt_xu_f_w_u8mf8(src, vl); return vfncvt_xu_f_w_u8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8mf8( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(<vscale x 1 x i8> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vfncvt_rtz_xu_f_w_u8mf8 (vfloat16mf4_t src, size_t vl) { vuint8mf8_t test_vfncvt_rtz_xu_f_w_u8mf8 (vfloat16mf4_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u8mf8(src, vl); return vfncvt_rtz_xu_f_w_u8mf8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8mf4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vfncvt_xu_f_w_u8mf4 (vfloat16mf2_t src, size_t vl) { vuint8mf4_t test_vfncvt_xu_f_w_u8mf4 (vfloat16mf2_t src, size_t vl) {
return vfncvt_xu_f_w_u8mf4(src, vl); return vfncvt_xu_f_w_u8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8mf4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(<vscale x 2 x i8> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vfncvt_rtz_xu_f_w_u8mf4 (vfloat16mf2_t src, size_t vl) { vuint8mf4_t test_vfncvt_rtz_xu_f_w_u8mf4 (vfloat16mf2_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u8mf4(src, vl); return vfncvt_rtz_xu_f_w_u8mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8mf2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vfncvt_xu_f_w_u8mf2 (vfloat16m1_t src, size_t vl) { vuint8mf2_t test_vfncvt_xu_f_w_u8mf2 (vfloat16m1_t src, size_t vl) {
return vfncvt_xu_f_w_u8mf2(src, vl); return vfncvt_xu_f_w_u8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8mf2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(<vscale x 4 x i8> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vfncvt_rtz_xu_f_w_u8mf2 (vfloat16m1_t src, size_t vl) { vuint8mf2_t test_vfncvt_rtz_xu_f_w_u8mf2 (vfloat16m1_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u8mf2(src, vl); return vfncvt_rtz_xu_f_w_u8mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8m1( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vfncvt_xu_f_w_u8m1 (vfloat16m2_t src, size_t vl) { vuint8m1_t test_vfncvt_xu_f_w_u8m1 (vfloat16m2_t src, size_t vl) {
return vfncvt_xu_f_w_u8m1(src, vl); return vfncvt_xu_f_w_u8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8m1( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(<vscale x 8 x i8> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vfncvt_rtz_xu_f_w_u8m1 (vfloat16m2_t src, size_t vl) { vuint8m1_t test_vfncvt_rtz_xu_f_w_u8m1 (vfloat16m2_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u8m1(src, vl); return vfncvt_rtz_xu_f_w_u8m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8m2( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vfncvt_xu_f_w_u8m2 (vfloat16m4_t src, size_t vl) { vuint8m2_t test_vfncvt_xu_f_w_u8m2 (vfloat16m4_t src, size_t vl) {
return vfncvt_xu_f_w_u8m2(src, vl); return vfncvt_xu_f_w_u8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8m2( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(<vscale x 16 x i8> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vfncvt_rtz_xu_f_w_u8m2 (vfloat16m4_t src, size_t vl) { vuint8m2_t test_vfncvt_rtz_xu_f_w_u8m2 (vfloat16m4_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u8m2(src, vl); return vfncvt_rtz_xu_f_w_u8m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8m4( // CHECK-RV64-LABEL: @test_vfncvt_xu_f_w_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vfncvt_xu_f_w_u8m4 (vfloat16m8_t src, size_t vl) { vuint8m4_t test_vfncvt_xu_f_w_u8m4 (vfloat16m8_t src, size_t vl) {
return vfncvt_xu_f_w_u8m4(src, vl); return vfncvt_xu_f_w_u8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8m4( // CHECK-RV64-LABEL: @test_vfncvt_rtz_xu_f_w_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(<vscale x 32 x i8> undef, <vscale x 32 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vfncvt_rtz_xu_f_w_u8m4 (vfloat16m8_t src, size_t vl) { vuint8m4_t test_vfncvt_rtz_xu_f_w_u8m4 (vfloat16m8_t src, size_t vl) {
return vfncvt_rtz_xu_f_w_u8m4(src, vl); return vfncvt_rtz_xu_f_w_u8m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16mf4( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfncvt_f_x_w_f16mf4 (vint32mf2_t src, size_t vl) { vfloat16mf4_t test_vfncvt_f_x_w_f16mf4 (vint32mf2_t src, size_t vl) {
return vfncvt_f_x_w_f16mf4(src, vl); return vfncvt_f_x_w_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfncvt_f_x_w_f16mf2 (vint32m1_t src, size_t vl) { vfloat16mf2_t test_vfncvt_f_x_w_f16mf2 (vint32m1_t src, size_t vl) {
return vfncvt_f_x_w_f16mf2(src, vl); return vfncvt_f_x_w_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16m1( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfncvt_f_x_w_f16m1 (vint32m2_t src, size_t vl) { vfloat16m1_t test_vfncvt_f_x_w_f16m1 (vint32m2_t src, size_t vl) {
return vfncvt_f_x_w_f16m1(src, vl); return vfncvt_f_x_w_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16m2( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfncvt_f_x_w_f16m2 (vint32m4_t src, size_t vl) { vfloat16m2_t test_vfncvt_f_x_w_f16m2 (vint32m4_t src, size_t vl) {
return vfncvt_f_x_w_f16m2(src, vl); return vfncvt_f_x_w_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16m4( // CHECK-RV64-LABEL: @test_vfncvt_f_x_w_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfncvt_f_x_w_f16m4 (vint32m8_t src, size_t vl) { vfloat16m4_t test_vfncvt_f_x_w_f16m4 (vint32m8_t src, size_t vl) {
return vfncvt_f_x_w_f16m4(src, vl); return vfncvt_f_x_w_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16mf4( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32.i64(<vscale x 1 x half> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4 (vuint32mf2_t src, size_t vl) { vfloat16mf4_t test_vfncvt_f_xu_w_f16mf4 (vuint32mf2_t src, size_t vl) {
return vfncvt_f_xu_w_f16mf4(src, vl); return vfncvt_f_xu_w_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32.i64(<vscale x 2 x half> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2 (vuint32m1_t src, size_t vl) { vfloat16mf2_t test_vfncvt_f_xu_w_f16mf2 (vuint32m1_t src, size_t vl) {
return vfncvt_f_xu_w_f16mf2(src, vl); return vfncvt_f_xu_w_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16m1( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32.i64(<vscale x 4 x half> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfncvt_f_xu_w_f16m1 (vuint32m2_t src, size_t vl) { vfloat16m1_t test_vfncvt_f_xu_w_f16m1 (vuint32m2_t src, size_t vl) {
return vfncvt_f_xu_w_f16m1(src, vl); return vfncvt_f_xu_w_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16m2( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32.i64(<vscale x 8 x half> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfncvt_f_xu_w_f16m2 (vuint32m4_t src, size_t vl) { vfloat16m2_t test_vfncvt_f_xu_w_f16m2 (vuint32m4_t src, size_t vl) {
return vfncvt_f_xu_w_f16m2(src, vl); return vfncvt_f_xu_w_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16m4( // CHECK-RV64-LABEL: @test_vfncvt_f_xu_w_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32.i64(<vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32.i64(<vscale x 16 x half> undef, <vscale x 16 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfncvt_f_xu_w_f16m4 (vuint32m8_t src, size_t vl) { vfloat16m4_t test_vfncvt_f_xu_w_f16m4 (vuint32m8_t src, size_t vl) {
return vfncvt_f_xu_w_f16m4(src, vl); return vfncvt_f_xu_w_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16mf4( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4 (vfloat32mf2_t src, size_t vl) { vfloat16mf4_t test_vfncvt_f_f_w_f16mf4 (vfloat32mf2_t src, size_t vl) {
return vfncvt_f_f_w_f16mf4(src, vl); return vfncvt_f_f_w_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16mf4( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(<vscale x 1 x half> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4 (vfloat32mf2_t src, size_t vl) { vfloat16mf4_t test_vfncvt_rod_f_f_w_f16mf4 (vfloat32mf2_t src, size_t vl) {
return vfncvt_rod_f_f_w_f16mf4(src, vl); return vfncvt_rod_f_f_w_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16mf2( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfncvt_f_f_w_f16mf2 (vfloat32m1_t src, size_t vl) { vfloat16mf2_t test_vfncvt_f_f_w_f16mf2 (vfloat32m1_t src, size_t vl) {
return vfncvt_f_f_w_f16mf2(src, vl); return vfncvt_f_f_w_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16mf2( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(<vscale x 2 x half> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2 (vfloat32m1_t src, size_t vl) { vfloat16mf2_t test_vfncvt_rod_f_f_w_f16mf2 (vfloat32m1_t src, size_t vl) {
return vfncvt_rod_f_f_w_f16mf2(src, vl); return vfncvt_rod_f_f_w_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16m1( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfncvt_f_f_w_f16m1 (vfloat32m2_t src, size_t vl) { vfloat16m1_t test_vfncvt_f_f_w_f16m1 (vfloat32m2_t src, size_t vl) {
return vfncvt_f_f_w_f16m1(src, vl); return vfncvt_f_f_w_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16m1( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1 (vfloat32m2_t src, size_t vl) { vfloat16m1_t test_vfncvt_rod_f_f_w_f16m1 (vfloat32m2_t src, size_t vl) {
return vfncvt_rod_f_f_w_f16m1(src, vl); return vfncvt_rod_f_f_w_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16m2( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfncvt_f_f_w_f16m2 (vfloat32m4_t src, size_t vl) { vfloat16m2_t test_vfncvt_f_f_w_f16m2 (vfloat32m4_t src, size_t vl) {
return vfncvt_f_f_w_f16m2(src, vl); return vfncvt_f_f_w_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16m2( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(<vscale x 8 x half> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2 (vfloat32m4_t src, size_t vl) { vfloat16m2_t test_vfncvt_rod_f_f_w_f16m2 (vfloat32m4_t src, size_t vl) {
return vfncvt_rod_f_f_w_f16m2(src, vl); return vfncvt_rod_f_f_w_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16m4( // CHECK-RV64-LABEL: @test_vfncvt_f_f_w_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfncvt_f_f_w_f16m4 (vfloat32m8_t src, size_t vl) { vfloat16m4_t test_vfncvt_f_f_w_f16m4 (vfloat32m8_t src, size_t vl) {
return vfncvt_f_f_w_f16m4(src, vl); return vfncvt_f_f_w_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16m4( // CHECK-RV64-LABEL: @test_vfncvt_rod_f_f_w_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(<vscale x 16 x half> undef, <vscale x 16 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4 (vfloat32m8_t src, size_t vl) { vfloat16m4_t test_vfncvt_rod_f_f_w_f16m4 (vfloat32m8_t src, size_t vl) {
return vfncvt_rod_f_f_w_f16m4(src, vl); return vfncvt_rod_f_f_w_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf8_m( // CHECK-RV64-LABEL: @test_vfncvt_x_f_w_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2( // CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfrec7_v_f32mf2(vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t test_vfrec7_v_f32mf2(vfloat32mf2_t op1, size_t vl) {
return vfrec7_v_f32mf2(op1, vl); return vfrec7_v_f32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m1( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfrec7_v_f32m1(vfloat32m1_t op1, size_t vl) { vfloat32m1_t test_vfrec7_v_f32m1(vfloat32m1_t op1, size_t vl) {
return vfrec7_v_f32m1(op1, vl); return vfrec7_v_f32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m2( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfrec7_v_f32m2(vfloat32m2_t op1, size_t vl) { vfloat32m2_t test_vfrec7_v_f32m2(vfloat32m2_t op1, size_t vl) {
return vfrec7_v_f32m2(op1, vl); return vfrec7_v_f32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m4( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfrec7_v_f32m4(vfloat32m4_t op1, size_t vl) { vfloat32m4_t test_vfrec7_v_f32m4(vfloat32m4_t op1, size_t vl) {
return vfrec7_v_f32m4(op1, vl); return vfrec7_v_f32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32m8( // CHECK-RV64-LABEL: @test_vfrec7_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfrec7_v_f32m8(vfloat32m8_t op1, size_t vl) { vfloat32m8_t test_vfrec7_v_f32m8(vfloat32m8_t op1, size_t vl) {
return vfrec7_v_f32m8(op1, vl); return vfrec7_v_f32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m1( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfrec7_v_f64m1(vfloat64m1_t op1, size_t vl) { vfloat64m1_t test_vfrec7_v_f64m1(vfloat64m1_t op1, size_t vl) {
return vfrec7_v_f64m1(op1, vl); return vfrec7_v_f64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m2( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfrec7_v_f64m2(vfloat64m2_t op1, size_t vl) { vfloat64m2_t test_vfrec7_v_f64m2(vfloat64m2_t op1, size_t vl) {
return vfrec7_v_f64m2(op1, vl); return vfrec7_v_f64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m4( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfrec7_v_f64m4(vfloat64m4_t op1, size_t vl) { vfloat64m4_t test_vfrec7_v_f64m4(vfloat64m4_t op1, size_t vl) {
return vfrec7_v_f64m4(op1, vl); return vfrec7_v_f64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f64m8( // CHECK-RV64-LABEL: @test_vfrec7_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfrec7_v_f64m8(vfloat64m8_t op1, size_t vl) { vfloat64m8_t test_vfrec7_v_f64m8(vfloat64m8_t op1, size_t vl) {
return vfrec7_v_f64m8(op1, vl); return vfrec7_v_f64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfrec7_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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// //
vfloat64m8_t test_vfrec7_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t test_vfrec7_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
vfloat64m8_t op1, size_t vl) { vfloat64m8_t op1, size_t vl) {
return vfrec7_v_f64m8_m(mask, maskedoff, op1, vl); return vfrec7_v_f64m8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f16mf4( // CHECK-RV64-LABEL: @test_vfrec7_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfrec7_v_f16mf4 (vfloat16mf4_t op1, size_t vl) { vfloat16mf4_t test_vfrec7_v_f16mf4 (vfloat16mf4_t op1, size_t vl) {
return vfrec7_v_f16mf4(op1, vl); return vfrec7_v_f16mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f16mf2( // CHECK-RV64-LABEL: @test_vfrec7_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfrec7_v_f16mf2 (vfloat16mf2_t op1, size_t vl) { vfloat16mf2_t test_vfrec7_v_f16mf2 (vfloat16mf2_t op1, size_t vl) {
return vfrec7_v_f16mf2(op1, vl); return vfrec7_v_f16mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f16m1( // CHECK-RV64-LABEL: @test_vfrec7_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfrec7_v_f16m1 (vfloat16m1_t op1, size_t vl) { vfloat16m1_t test_vfrec7_v_f16m1 (vfloat16m1_t op1, size_t vl) {
return vfrec7_v_f16m1(op1, vl); return vfrec7_v_f16m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f16m2( // CHECK-RV64-LABEL: @test_vfrec7_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfrec7_v_f16m2 (vfloat16m2_t op1, size_t vl) { vfloat16m2_t test_vfrec7_v_f16m2 (vfloat16m2_t op1, size_t vl) {
return vfrec7_v_f16m2(op1, vl); return vfrec7_v_f16m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f16m4( // CHECK-RV64-LABEL: @test_vfrec7_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfrec7_v_f16m4 (vfloat16m4_t op1, size_t vl) { vfloat16m4_t test_vfrec7_v_f16m4 (vfloat16m4_t op1, size_t vl) {
return vfrec7_v_f16m4(op1, vl); return vfrec7_v_f16m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f16m8( // CHECK-RV64-LABEL: @test_vfrec7_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfrec7_v_f16m8 (vfloat16m8_t op1, size_t vl) { vfloat16m8_t test_vfrec7_v_f16m8 (vfloat16m8_t op1, size_t vl) {
return vfrec7_v_f16m8(op1, vl); return vfrec7_v_f16m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrec7_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vfrec7_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfrsqrt7_v_f32mf2(vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t test_vfrsqrt7_v_f32mf2(vfloat32mf2_t op1, size_t vl) {
return vfrsqrt7_v_f32mf2(op1, vl); return vfrsqrt7_v_f32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m1( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfrsqrt7_v_f32m1(vfloat32m1_t op1, size_t vl) { vfloat32m1_t test_vfrsqrt7_v_f32m1(vfloat32m1_t op1, size_t vl) {
return vfrsqrt7_v_f32m1(op1, vl); return vfrsqrt7_v_f32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfrsqrt7_v_f32m2(vfloat32m2_t op1, size_t vl) { vfloat32m2_t test_vfrsqrt7_v_f32m2(vfloat32m2_t op1, size_t vl) {
return vfrsqrt7_v_f32m2(op1, vl); return vfrsqrt7_v_f32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m4( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfrsqrt7_v_f32m4(vfloat32m4_t op1, size_t vl) { vfloat32m4_t test_vfrsqrt7_v_f32m4(vfloat32m4_t op1, size_t vl) {
return vfrsqrt7_v_f32m4(op1, vl); return vfrsqrt7_v_f32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m8( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfrsqrt7_v_f32m8(vfloat32m8_t op1, size_t vl) { vfloat32m8_t test_vfrsqrt7_v_f32m8(vfloat32m8_t op1, size_t vl) {
return vfrsqrt7_v_f32m8(op1, vl); return vfrsqrt7_v_f32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m1( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfrsqrt7_v_f64m1(vfloat64m1_t op1, size_t vl) { vfloat64m1_t test_vfrsqrt7_v_f64m1(vfloat64m1_t op1, size_t vl) {
return vfrsqrt7_v_f64m1(op1, vl); return vfrsqrt7_v_f64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfrsqrt7_v_f64m2(vfloat64m2_t op1, size_t vl) { vfloat64m2_t test_vfrsqrt7_v_f64m2(vfloat64m2_t op1, size_t vl) {
return vfrsqrt7_v_f64m2(op1, vl); return vfrsqrt7_v_f64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m4( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfrsqrt7_v_f64m4(vfloat64m4_t op1, size_t vl) { vfloat64m4_t test_vfrsqrt7_v_f64m4(vfloat64m4_t op1, size_t vl) {
return vfrsqrt7_v_f64m4(op1, vl); return vfrsqrt7_v_f64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m8( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfrsqrt7_v_f64m8(vfloat64m8_t op1, size_t vl) { vfloat64m8_t test_vfrsqrt7_v_f64m8(vfloat64m8_t op1, size_t vl) {
return vfrsqrt7_v_f64m8(op1, vl); return vfrsqrt7_v_f64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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// //
vfloat64m8_t test_vfrsqrt7_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t test_vfrsqrt7_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
vfloat64m8_t op1, size_t vl) { vfloat64m8_t op1, size_t vl) {
return vfrsqrt7_v_f64m8_m(mask, maskedoff, op1, vl); return vfrsqrt7_v_f64m8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16mf4( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfrsqrt7_v_f16mf4 (vfloat16mf4_t op1, size_t vl) { vfloat16mf4_t test_vfrsqrt7_v_f16mf4 (vfloat16mf4_t op1, size_t vl) {
return vfrsqrt7_v_f16mf4(op1, vl); return vfrsqrt7_v_f16mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16mf2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfrsqrt7_v_f16mf2 (vfloat16mf2_t op1, size_t vl) { vfloat16mf2_t test_vfrsqrt7_v_f16mf2 (vfloat16mf2_t op1, size_t vl) {
return vfrsqrt7_v_f16mf2(op1, vl); return vfrsqrt7_v_f16mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m1( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfrsqrt7_v_f16m1 (vfloat16m1_t op1, size_t vl) { vfloat16m1_t test_vfrsqrt7_v_f16m1 (vfloat16m1_t op1, size_t vl) {
return vfrsqrt7_v_f16m1(op1, vl); return vfrsqrt7_v_f16m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m2( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfrsqrt7_v_f16m2 (vfloat16m2_t op1, size_t vl) { vfloat16m2_t test_vfrsqrt7_v_f16m2 (vfloat16m2_t op1, size_t vl) {
return vfrsqrt7_v_f16m2(op1, vl); return vfrsqrt7_v_f16m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m4( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfrsqrt7_v_f16m4 (vfloat16m4_t op1, size_t vl) { vfloat16m4_t test_vfrsqrt7_v_f16m4 (vfloat16m4_t op1, size_t vl) {
return vfrsqrt7_v_f16m4(op1, vl); return vfrsqrt7_v_f16m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m8( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfrsqrt7_v_f16m8 (vfloat16m8_t op1, size_t vl) { vfloat16m8_t test_vfrsqrt7_v_f16m8 (vfloat16m8_t op1, size_t vl) {
return vfrsqrt7_v_f16m8(op1, vl); return vfrsqrt7_v_f16m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vfrsqrt7_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfsqrt_v_f32mf2(vfloat32mf2_t op1, size_t vl) { vfloat32mf2_t test_vfsqrt_v_f32mf2(vfloat32mf2_t op1, size_t vl) {
return vfsqrt_v_f32mf2(op1, vl); return vfsqrt_v_f32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m1( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfsqrt_v_f32m1(vfloat32m1_t op1, size_t vl) { vfloat32m1_t test_vfsqrt_v_f32m1(vfloat32m1_t op1, size_t vl) {
return vfsqrt_v_f32m1(op1, vl); return vfsqrt_v_f32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32.i64(<vscale x 4 x float> undef, <vscale x 4 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfsqrt_v_f32m2(vfloat32m2_t op1, size_t vl) { vfloat32m2_t test_vfsqrt_v_f32m2(vfloat32m2_t op1, size_t vl) {
return vfsqrt_v_f32m2(op1, vl); return vfsqrt_v_f32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m4( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32.i64(<vscale x 8 x float> undef, <vscale x 8 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfsqrt_v_f32m4(vfloat32m4_t op1, size_t vl) { vfloat32m4_t test_vfsqrt_v_f32m4(vfloat32m4_t op1, size_t vl) {
return vfsqrt_v_f32m4(op1, vl); return vfsqrt_v_f32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32m8( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfsqrt_v_f32m8(vfloat32m8_t op1, size_t vl) { vfloat32m8_t test_vfsqrt_v_f32m8(vfloat32m8_t op1, size_t vl) {
return vfsqrt_v_f32m8(op1, vl); return vfsqrt_v_f32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m1( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64.i64(<vscale x 1 x double> undef, <vscale x 1 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfsqrt_v_f64m1(vfloat64m1_t op1, size_t vl) { vfloat64m1_t test_vfsqrt_v_f64m1(vfloat64m1_t op1, size_t vl) {
return vfsqrt_v_f64m1(op1, vl); return vfsqrt_v_f64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64.i64(<vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64.i64(<vscale x 2 x double> undef, <vscale x 2 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfsqrt_v_f64m2(vfloat64m2_t op1, size_t vl) { vfloat64m2_t test_vfsqrt_v_f64m2(vfloat64m2_t op1, size_t vl) {
return vfsqrt_v_f64m2(op1, vl); return vfsqrt_v_f64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m4( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64.i64(<vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64.i64(<vscale x 4 x double> undef, <vscale x 4 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfsqrt_v_f64m4(vfloat64m4_t op1, size_t vl) { vfloat64m4_t test_vfsqrt_v_f64m4(vfloat64m4_t op1, size_t vl) {
return vfsqrt_v_f64m4(op1, vl); return vfsqrt_v_f64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f64m8( // CHECK-RV64-LABEL: @test_vfsqrt_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64.i64(<vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64.i64(<vscale x 8 x double> undef, <vscale x 8 x double> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfsqrt_v_f64m8(vfloat64m8_t op1, size_t vl) { vfloat64m8_t test_vfsqrt_v_f64m8(vfloat64m8_t op1, size_t vl) {
return vfsqrt_v_f64m8(op1, vl); return vfsqrt_v_f64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfsqrt_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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// //
vfloat64m8_t test_vfsqrt_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t test_vfsqrt_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
vfloat64m8_t op1, size_t vl) { vfloat64m8_t op1, size_t vl) {
return vfsqrt_v_f64m8_m(mask, maskedoff, op1, vl); return vfsqrt_v_f64m8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f16mf4( // CHECK-RV64-LABEL: @test_vfsqrt_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfsqrt_v_f16mf4 (vfloat16mf4_t op1, size_t vl) { vfloat16mf4_t test_vfsqrt_v_f16mf4 (vfloat16mf4_t op1, size_t vl) {
return vfsqrt_v_f16mf4(op1, vl); return vfsqrt_v_f16mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f16mf2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfsqrt_v_f16mf2 (vfloat16mf2_t op1, size_t vl) { vfloat16mf2_t test_vfsqrt_v_f16mf2 (vfloat16mf2_t op1, size_t vl) {
return vfsqrt_v_f16mf2(op1, vl); return vfsqrt_v_f16mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f16m1( // CHECK-RV64-LABEL: @test_vfsqrt_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfsqrt_v_f16m1 (vfloat16m1_t op1, size_t vl) { vfloat16m1_t test_vfsqrt_v_f16m1 (vfloat16m1_t op1, size_t vl) {
return vfsqrt_v_f16m1(op1, vl); return vfsqrt_v_f16m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f16m2( // CHECK-RV64-LABEL: @test_vfsqrt_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfsqrt_v_f16m2 (vfloat16m2_t op1, size_t vl) { vfloat16m2_t test_vfsqrt_v_f16m2 (vfloat16m2_t op1, size_t vl) {
return vfsqrt_v_f16m2(op1, vl); return vfsqrt_v_f16m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f16m4( // CHECK-RV64-LABEL: @test_vfsqrt_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfsqrt_v_f16m4 (vfloat16m4_t op1, size_t vl) { vfloat16m4_t test_vfsqrt_v_f16m4 (vfloat16m4_t op1, size_t vl) {
return vfsqrt_v_f16m4(op1, vl); return vfsqrt_v_f16m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f16m8( // CHECK-RV64-LABEL: @test_vfsqrt_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfsqrt_v_f16m8 (vfloat16m8_t op1, size_t vl) { vfloat16m8_t test_vfsqrt_v_f16m8 (vfloat16m8_t op1, size_t vl) {
return vfsqrt_v_f16m8(op1, vl); return vfsqrt_v_f16m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vfsqrt_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vfsqrt_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh \ // RUN: -target-feature +v -target-feature +zfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2(vint16mf4_t src, size_t vl) { vfloat32mf2_t test_vfwcvt_f_x_v_f32mf2(vint16mf4_t src, size_t vl) {
return vfwcvt_f_x_v_f32mf2(src, vl); return vfwcvt_f_x_v_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwcvt_f_x_v_f32m1(vint16mf2_t src, size_t vl) { vfloat32m1_t test_vfwcvt_f_x_v_f32m1(vint16mf2_t src, size_t vl) {
return vfwcvt_f_x_v_f32m1(src, vl); return vfwcvt_f_x_v_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwcvt_f_x_v_f32m2(vint16m1_t src, size_t vl) { vfloat32m2_t test_vfwcvt_f_x_v_f32m2(vint16m1_t src, size_t vl) {
return vfwcvt_f_x_v_f32m2(src, vl); return vfwcvt_f_x_v_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwcvt_f_x_v_f32m4(vint16m2_t src, size_t vl) { vfloat32m4_t test_vfwcvt_f_x_v_f32m4(vint16m2_t src, size_t vl) {
return vfwcvt_f_x_v_f32m4(src, vl); return vfwcvt_f_x_v_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwcvt_f_x_v_f32m8(vint16m4_t src, size_t vl) { vfloat32m8_t test_vfwcvt_f_x_v_f32m8(vint16m4_t src, size_t vl) {
return vfwcvt_f_x_v_f32m8(src, vl); return vfwcvt_f_x_v_f32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16.i64(<vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16.i64(<vscale x 1 x float> undef, <vscale x 1 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2(vuint16mf4_t src, size_t vl) { vfloat32mf2_t test_vfwcvt_f_xu_v_f32mf2(vuint16mf4_t src, size_t vl) {
return vfwcvt_f_xu_v_f32mf2(src, vl); return vfwcvt_f_xu_v_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16.i64(<vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16.i64(<vscale x 2 x float> undef, <vscale x 2 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwcvt_f_xu_v_f32m1(vuint16mf2_t src, size_t vl) { vfloat32m1_t test_vfwcvt_f_xu_v_f32m1(vuint16mf2_t src, size_t vl) {
return vfwcvt_f_xu_v_f32m1(src, vl); return vfwcvt_f_xu_v_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i64(<vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16.i64(<vscale x 4 x float> undef, <vscale x 4 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwcvt_f_xu_v_f32m2(vuint16m1_t src, size_t vl) { vfloat32m2_t test_vfwcvt_f_xu_v_f32m2(vuint16m1_t src, size_t vl) {
return vfwcvt_f_xu_v_f32m2(src, vl); return vfwcvt_f_xu_v_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i64(<vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16.i64(<vscale x 8 x float> undef, <vscale x 8 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwcvt_f_xu_v_f32m4(vuint16m2_t src, size_t vl) { vfloat32m4_t test_vfwcvt_f_xu_v_f32m4(vuint16m2_t src, size_t vl) {
return vfwcvt_f_xu_v_f32m4(src, vl); return vfwcvt_f_xu_v_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i64(<vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16.i64(<vscale x 16 x float> undef, <vscale x 16 x i16> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwcvt_f_xu_v_f32m8(vuint16m4_t src, size_t vl) { vfloat32m8_t test_vfwcvt_f_xu_v_f32m8(vuint16m4_t src, size_t vl) {
return vfwcvt_f_xu_v_f32m8(src, vl); return vfwcvt_f_xu_v_f32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfwcvt_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) { vint64m1_t test_vfwcvt_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_x_f_v_i64m1(src, vl); return vfwcvt_x_f_v_i64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) { vint64m1_t test_vfwcvt_rtz_x_f_v_i64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i64m1(src, vl); return vfwcvt_rtz_x_f_v_i64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfwcvt_x_f_v_i64m2(vfloat32m1_t src, size_t vl) { vint64m2_t test_vfwcvt_x_f_v_i64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_x_f_v_i64m2(src, vl); return vfwcvt_x_f_v_i64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src, size_t vl) { vint64m2_t test_vfwcvt_rtz_x_f_v_i64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i64m2(src, vl); return vfwcvt_rtz_x_f_v_i64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfwcvt_x_f_v_i64m4(vfloat32m2_t src, size_t vl) { vint64m4_t test_vfwcvt_x_f_v_i64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_x_f_v_i64m4(src, vl); return vfwcvt_x_f_v_i64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src, size_t vl) { vint64m4_t test_vfwcvt_rtz_x_f_v_i64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i64m4(src, vl); return vfwcvt_rtz_x_f_v_i64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfwcvt_x_f_v_i64m8(vfloat32m4_t src, size_t vl) { vint64m8_t test_vfwcvt_x_f_v_i64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_x_f_v_i64m8(src, vl); return vfwcvt_x_f_v_i64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src, size_t vl) { vint64m8_t test_vfwcvt_rtz_x_f_v_i64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i64m8(src, vl); return vfwcvt_rtz_x_f_v_i64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfwcvt_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) { vuint64m1_t test_vfwcvt_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_xu_f_v_u64m1(src, vl); return vfwcvt_xu_f_v_u64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32.i64(<vscale x 1 x i64> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) { vuint64m1_t test_vfwcvt_rtz_xu_f_v_u64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u64m1(src, vl); return vfwcvt_rtz_xu_f_v_u64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfwcvt_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) { vuint64m2_t test_vfwcvt_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_xu_f_v_u64m2(src, vl); return vfwcvt_xu_f_v_u64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32.i64(<vscale x 2 x i64> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) { vuint64m2_t test_vfwcvt_rtz_xu_f_v_u64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u64m2(src, vl); return vfwcvt_rtz_xu_f_v_u64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfwcvt_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) { vuint64m4_t test_vfwcvt_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_xu_f_v_u64m4(src, vl); return vfwcvt_xu_f_v_u64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32.i64(<vscale x 4 x i64> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) { vuint64m4_t test_vfwcvt_rtz_xu_f_v_u64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u64m4(src, vl); return vfwcvt_rtz_xu_f_v_u64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfwcvt_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) { vuint64m8_t test_vfwcvt_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_xu_f_v_u64m8(src, vl); return vfwcvt_xu_f_v_u64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32.i64(<vscale x 8 x i64> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) { vuint64m8_t test_vfwcvt_rtz_xu_f_v_u64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u64m8(src, vl); return vfwcvt_rtz_xu_f_v_u64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwcvt_f_x_v_f64m1(vint32mf2_t src, size_t vl) { vfloat64m1_t test_vfwcvt_f_x_v_f64m1(vint32mf2_t src, size_t vl) {
return vfwcvt_f_x_v_f64m1(src, vl); return vfwcvt_f_x_v_f64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwcvt_f_x_v_f64m2(vint32m1_t src, size_t vl) { vfloat64m2_t test_vfwcvt_f_x_v_f64m2(vint32m1_t src, size_t vl) {
return vfwcvt_f_x_v_f64m2(src, vl); return vfwcvt_f_x_v_f64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwcvt_f_x_v_f64m4(vint32m2_t src, size_t vl) { vfloat64m4_t test_vfwcvt_f_x_v_f64m4(vint32m2_t src, size_t vl) {
return vfwcvt_f_x_v_f64m4(src, vl); return vfwcvt_f_x_v_f64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwcvt_f_x_v_f64m8(vint32m4_t src, size_t vl) { vfloat64m8_t test_vfwcvt_f_x_v_f64m8(vint32m4_t src, size_t vl) {
return vfwcvt_f_x_v_f64m8(src, vl); return vfwcvt_f_x_v_f64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32.i64(<vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32.i64(<vscale x 1 x double> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwcvt_f_xu_v_f64m1(vuint32mf2_t src, size_t vl) { vfloat64m1_t test_vfwcvt_f_xu_v_f64m1(vuint32mf2_t src, size_t vl) {
return vfwcvt_f_xu_v_f64m1(src, vl); return vfwcvt_f_xu_v_f64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i64(<vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32.i64(<vscale x 2 x double> undef, <vscale x 2 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwcvt_f_xu_v_f64m2(vuint32m1_t src, size_t vl) { vfloat64m2_t test_vfwcvt_f_xu_v_f64m2(vuint32m1_t src, size_t vl) {
return vfwcvt_f_xu_v_f64m2(src, vl); return vfwcvt_f_xu_v_f64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i64(<vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32.i64(<vscale x 4 x double> undef, <vscale x 4 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwcvt_f_xu_v_f64m4(vuint32m2_t src, size_t vl) { vfloat64m4_t test_vfwcvt_f_xu_v_f64m4(vuint32m2_t src, size_t vl) {
return vfwcvt_f_xu_v_f64m4(src, vl); return vfwcvt_f_xu_v_f64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i64(<vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32.i64(<vscale x 8 x double> undef, <vscale x 8 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwcvt_f_xu_v_f64m8(vuint32m4_t src, size_t vl) { vfloat64m8_t test_vfwcvt_f_xu_v_f64m8(vuint32m4_t src, size_t vl) {
return vfwcvt_f_xu_v_f64m8(src, vl); return vfwcvt_f_xu_v_f64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfwcvt_f_f_v_f64m1(vfloat32mf2_t src, size_t vl) { vfloat64m1_t test_vfwcvt_f_f_v_f64m1(vfloat32mf2_t src, size_t vl) {
return vfwcvt_f_f_v_f64m1(src, vl); return vfwcvt_f_f_v_f64m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(<vscale x 2 x double> undef, <vscale x 2 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfwcvt_f_f_v_f64m2(vfloat32m1_t src, size_t vl) { vfloat64m2_t test_vfwcvt_f_f_v_f64m2(vfloat32m1_t src, size_t vl) {
return vfwcvt_f_f_v_f64m2(src, vl); return vfwcvt_f_f_v_f64m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(<vscale x 4 x double> undef, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfwcvt_f_f_v_f64m4(vfloat32m2_t src, size_t vl) { vfloat64m4_t test_vfwcvt_f_f_v_f64m4(vfloat32m2_t src, size_t vl) {
return vfwcvt_f_f_v_f64m4(src, vl); return vfwcvt_f_f_v_f64m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(<vscale x 8 x double> undef, <vscale x 8 x float> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfwcvt_f_f_v_f64m8(vfloat32m4_t src, size_t vl) { vfloat64m8_t test_vfwcvt_f_f_v_f64m8(vfloat32m4_t src, size_t vl) {
return vfwcvt_f_f_v_f64m8(src, vl); return vfwcvt_f_f_v_f64m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2_m( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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// //
vfloat64m8_t test_vfwcvt_f_f_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, vfloat64m8_t test_vfwcvt_f_f_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
vfloat32m4_t src, size_t vl) { vfloat32m4_t src, size_t vl) {
return vfwcvt_f_f_v_f64m8_m(mask, maskedoff, src, vl); return vfwcvt_f_f_v_f64m8_m(mask, maskedoff, src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16mf4( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> undef, <vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfwcvt_f_x_v_f16mf4 (vint8mf8_t src, size_t vl) { vfloat16mf4_t test_vfwcvt_f_x_v_f16mf4 (vint8mf8_t src, size_t vl) {
return vfwcvt_f_x_v_f16mf4(src, vl); return vfwcvt_f_x_v_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16mf2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> undef, <vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfwcvt_f_x_v_f16mf2 (vint8mf4_t src, size_t vl) { vfloat16mf2_t test_vfwcvt_f_x_v_f16mf2 (vint8mf4_t src, size_t vl) {
return vfwcvt_f_x_v_f16mf2(src, vl); return vfwcvt_f_x_v_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> undef, <vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfwcvt_f_x_v_f16m1 (vint8mf2_t src, size_t vl) { vfloat16m1_t test_vfwcvt_f_x_v_f16m1 (vint8mf2_t src, size_t vl) {
return vfwcvt_f_x_v_f16m1(src, vl); return vfwcvt_f_x_v_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> undef, <vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfwcvt_f_x_v_f16m2 (vint8m1_t src, size_t vl) { vfloat16m2_t test_vfwcvt_f_x_v_f16m2 (vint8m1_t src, size_t vl) {
return vfwcvt_f_x_v_f16m2(src, vl); return vfwcvt_f_x_v_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> undef, <vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfwcvt_f_x_v_f16m4 (vint8m2_t src, size_t vl) { vfloat16m4_t test_vfwcvt_f_x_v_f16m4 (vint8m2_t src, size_t vl) {
return vfwcvt_f_x_v_f16m4(src, vl); return vfwcvt_f_x_v_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> undef, <vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfwcvt_f_x_v_f16m8 (vint8m4_t src, size_t vl) { vfloat16m8_t test_vfwcvt_f_x_v_f16m8 (vint8m4_t src, size_t vl) {
return vfwcvt_f_x_v_f16m8(src, vl); return vfwcvt_f_x_v_f16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16mf4( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(<vscale x 1 x half> undef, <vscale x 1 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfwcvt_f_xu_v_f16mf4 (vuint8mf8_t src, size_t vl) { vfloat16mf4_t test_vfwcvt_f_xu_v_f16mf4 (vuint8mf8_t src, size_t vl) {
return vfwcvt_f_xu_v_f16mf4(src, vl); return vfwcvt_f_xu_v_f16mf4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16mf2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(<vscale x 2 x half> undef, <vscale x 2 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfwcvt_f_xu_v_f16mf2 (vuint8mf4_t src, size_t vl) { vfloat16mf2_t test_vfwcvt_f_xu_v_f16mf2 (vuint8mf4_t src, size_t vl) {
return vfwcvt_f_xu_v_f16mf2(src, vl); return vfwcvt_f_xu_v_f16mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(<vscale x 4 x half> undef, <vscale x 4 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfwcvt_f_xu_v_f16m1 (vuint8mf2_t src, size_t vl) { vfloat16m1_t test_vfwcvt_f_xu_v_f16m1 (vuint8mf2_t src, size_t vl) {
return vfwcvt_f_xu_v_f16m1(src, vl); return vfwcvt_f_xu_v_f16m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(<vscale x 8 x half> undef, <vscale x 8 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfwcvt_f_xu_v_f16m2 (vuint8m1_t src, size_t vl) { vfloat16m2_t test_vfwcvt_f_xu_v_f16m2 (vuint8m1_t src, size_t vl) {
return vfwcvt_f_xu_v_f16m2(src, vl); return vfwcvt_f_xu_v_f16m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(<vscale x 16 x half> undef, <vscale x 16 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfwcvt_f_xu_v_f16m4 (vuint8m2_t src, size_t vl) { vfloat16m4_t test_vfwcvt_f_xu_v_f16m4 (vuint8m2_t src, size_t vl) {
return vfwcvt_f_xu_v_f16m4(src, vl); return vfwcvt_f_xu_v_f16m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_xu_v_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(<vscale x 32 x half> undef, <vscale x 32 x i8> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfwcvt_f_xu_v_f16m8 (vuint8m4_t src, size_t vl) { vfloat16m8_t test_vfwcvt_f_xu_v_f16m8 (vuint8m4_t src, size_t vl) {
return vfwcvt_f_xu_v_f16m8(src, vl); return vfwcvt_f_xu_v_f16m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfwcvt_x_f_v_i32mf2 (vfloat16mf4_t src, size_t vl) { vint32mf2_t test_vfwcvt_x_f_v_i32mf2 (vfloat16mf4_t src, size_t vl) {
return vfwcvt_x_f_v_i32mf2(src, vl); return vfwcvt_x_f_v_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vfwcvt_rtz_x_f_v_i32mf2 (vfloat16mf4_t src, size_t vl) { vint32mf2_t test_vfwcvt_rtz_x_f_v_i32mf2 (vfloat16mf4_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i32mf2(src, vl); return vfwcvt_rtz_x_f_v_i32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m1( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfwcvt_x_f_v_i32m1 (vfloat16mf2_t src, size_t vl) { vint32m1_t test_vfwcvt_x_f_v_i32m1 (vfloat16mf2_t src, size_t vl) {
return vfwcvt_x_f_v_i32m1(src, vl); return vfwcvt_x_f_v_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m1( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vfwcvt_rtz_x_f_v_i32m1 (vfloat16mf2_t src, size_t vl) { vint32m1_t test_vfwcvt_rtz_x_f_v_i32m1 (vfloat16mf2_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i32m1(src, vl); return vfwcvt_rtz_x_f_v_i32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m2( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfwcvt_x_f_v_i32m2 (vfloat16m1_t src, size_t vl) { vint32m2_t test_vfwcvt_x_f_v_i32m2 (vfloat16m1_t src, size_t vl) {
return vfwcvt_x_f_v_i32m2(src, vl); return vfwcvt_x_f_v_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vfwcvt_rtz_x_f_v_i32m2 (vfloat16m1_t src, size_t vl) { vint32m2_t test_vfwcvt_rtz_x_f_v_i32m2 (vfloat16m1_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i32m2(src, vl); return vfwcvt_rtz_x_f_v_i32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m4( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfwcvt_x_f_v_i32m4 (vfloat16m2_t src, size_t vl) { vint32m4_t test_vfwcvt_x_f_v_i32m4 (vfloat16m2_t src, size_t vl) {
return vfwcvt_x_f_v_i32m4(src, vl); return vfwcvt_x_f_v_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m4( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vfwcvt_rtz_x_f_v_i32m4 (vfloat16m2_t src, size_t vl) { vint32m4_t test_vfwcvt_rtz_x_f_v_i32m4 (vfloat16m2_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i32m4(src, vl); return vfwcvt_rtz_x_f_v_i32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m8( // CHECK-RV64-LABEL: @test_vfwcvt_x_f_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vfwcvt_x_f_v_i32m8 (vfloat16m4_t src, size_t vl) { vint32m8_t test_vfwcvt_x_f_v_i32m8 (vfloat16m4_t src, size_t vl) {
return vfwcvt_x_f_v_i32m8(src, vl); return vfwcvt_x_f_v_i32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m8( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_x_f_v_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vfwcvt_rtz_x_f_v_i32m8 (vfloat16m4_t src, size_t vl) { vint32m8_t test_vfwcvt_rtz_x_f_v_i32m8 (vfloat16m4_t src, size_t vl) {
return vfwcvt_rtz_x_f_v_i32m8(src, vl); return vfwcvt_rtz_x_f_v_i32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2 (vfloat16mf4_t src, size_t vl) { vuint32mf2_t test_vfwcvt_xu_f_v_u32mf2 (vfloat16mf4_t src, size_t vl) {
return vfwcvt_xu_f_v_u32mf2(src, vl); return vfwcvt_xu_f_v_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(<vscale x 1 x i32> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vfwcvt_rtz_xu_f_v_u32mf2 (vfloat16mf4_t src, size_t vl) { vuint32mf2_t test_vfwcvt_rtz_xu_f_v_u32mf2 (vfloat16mf4_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u32mf2(src, vl); return vfwcvt_rtz_xu_f_v_u32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m1( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfwcvt_xu_f_v_u32m1 (vfloat16mf2_t src, size_t vl) { vuint32m1_t test_vfwcvt_xu_f_v_u32m1 (vfloat16mf2_t src, size_t vl) {
return vfwcvt_xu_f_v_u32m1(src, vl); return vfwcvt_xu_f_v_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m1( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(<vscale x 2 x i32> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vfwcvt_rtz_xu_f_v_u32m1 (vfloat16mf2_t src, size_t vl) { vuint32m1_t test_vfwcvt_rtz_xu_f_v_u32m1 (vfloat16mf2_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u32m1(src, vl); return vfwcvt_rtz_xu_f_v_u32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m2( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfwcvt_xu_f_v_u32m2 (vfloat16m1_t src, size_t vl) { vuint32m2_t test_vfwcvt_xu_f_v_u32m2 (vfloat16m1_t src, size_t vl) {
return vfwcvt_xu_f_v_u32m2(src, vl); return vfwcvt_xu_f_v_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m2( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(<vscale x 4 x i32> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vfwcvt_rtz_xu_f_v_u32m2 (vfloat16m1_t src, size_t vl) { vuint32m2_t test_vfwcvt_rtz_xu_f_v_u32m2 (vfloat16m1_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u32m2(src, vl); return vfwcvt_rtz_xu_f_v_u32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m4( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfwcvt_xu_f_v_u32m4 (vfloat16m2_t src, size_t vl) { vuint32m4_t test_vfwcvt_xu_f_v_u32m4 (vfloat16m2_t src, size_t vl) {
return vfwcvt_xu_f_v_u32m4(src, vl); return vfwcvt_xu_f_v_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m4( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(<vscale x 8 x i32> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vfwcvt_rtz_xu_f_v_u32m4 (vfloat16m2_t src, size_t vl) { vuint32m4_t test_vfwcvt_rtz_xu_f_v_u32m4 (vfloat16m2_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u32m4(src, vl); return vfwcvt_rtz_xu_f_v_u32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m8( // CHECK-RV64-LABEL: @test_vfwcvt_xu_f_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfwcvt_xu_f_v_u32m8 (vfloat16m4_t src, size_t vl) { vuint32m8_t test_vfwcvt_xu_f_v_u32m8 (vfloat16m4_t src, size_t vl) {
return vfwcvt_xu_f_v_u32m8(src, vl); return vfwcvt_xu_f_v_u32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m8( // CHECK-RV64-LABEL: @test_vfwcvt_rtz_xu_f_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(<vscale x 16 x i32> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vfwcvt_rtz_xu_f_v_u32m8 (vfloat16m4_t src, size_t vl) { vuint32m8_t test_vfwcvt_rtz_xu_f_v_u32m8 (vfloat16m4_t src, size_t vl) {
return vfwcvt_rtz_xu_f_v_u32m8(src, vl); return vfwcvt_rtz_xu_f_v_u32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32mf2( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(<vscale x 1 x float> undef, <vscale x 1 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2 (vfloat16mf4_t src, size_t vl) { vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2 (vfloat16mf4_t src, size_t vl) {
return vfwcvt_f_f_v_f32mf2(src, vl); return vfwcvt_f_f_v_f32mf2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m1( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(<vscale x 2 x float> undef, <vscale x 2 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfwcvt_f_f_v_f32m1 (vfloat16mf2_t src, size_t vl) { vfloat32m1_t test_vfwcvt_f_f_v_f32m1 (vfloat16mf2_t src, size_t vl) {
return vfwcvt_f_f_v_f32m1(src, vl); return vfwcvt_f_f_v_f32m1(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m2( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> undef, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfwcvt_f_f_v_f32m2 (vfloat16m1_t src, size_t vl) { vfloat32m2_t test_vfwcvt_f_f_v_f32m2 (vfloat16m1_t src, size_t vl) {
return vfwcvt_f_f_v_f32m2(src, vl); return vfwcvt_f_f_v_f32m2(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m4( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(<vscale x 8 x float> undef, <vscale x 8 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfwcvt_f_f_v_f32m4 (vfloat16m2_t src, size_t vl) { vfloat32m4_t test_vfwcvt_f_f_v_f32m4 (vfloat16m2_t src, size_t vl) {
return vfwcvt_f_f_v_f32m4(src, vl); return vfwcvt_f_f_v_f32m4(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m8( // CHECK-RV64-LABEL: @test_vfwcvt_f_f_v_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(<vscale x 16 x float> undef, <vscale x 16 x half> [[SRC:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfwcvt_f_f_v_f32m8 (vfloat16m4_t src, size_t vl) { vfloat32m8_t test_vfwcvt_f_f_v_f32m8 (vfloat16m4_t src, size_t vl) {
return vfwcvt_f_f_v_f32m8(src, vl); return vfwcvt_f_f_v_f32m8(src, vl);
} }
// CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16mf4_m( // CHECK-RV64-LABEL: @test_vfwcvt_f_x_v_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vid.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vid_v_u8mf8( // CHECK-RV64-LABEL: @test_vid_v_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8.i64(<vscale x 1 x i8> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vid_v_u8mf8(size_t vl) { return vid_v_u8mf8(vl); } vuint8mf8_t test_vid_v_u8mf8(size_t vl) { return vid_v_u8mf8(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u8mf4( // CHECK-RV64-LABEL: @test_vid_v_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8.i64(<vscale x 2 x i8> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vid_v_u8mf4(size_t vl) { return vid_v_u8mf4(vl); } vuint8mf4_t test_vid_v_u8mf4(size_t vl) { return vid_v_u8mf4(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u8mf2( // CHECK-RV64-LABEL: @test_vid_v_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8.i64(<vscale x 4 x i8> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vid_v_u8mf2(size_t vl) { return vid_v_u8mf2(vl); } vuint8mf2_t test_vid_v_u8mf2(size_t vl) { return vid_v_u8mf2(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u8m1( // CHECK-RV64-LABEL: @test_vid_v_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8.i64(<vscale x 8 x i8> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vid_v_u8m1(size_t vl) { return vid_v_u8m1(vl); } vuint8m1_t test_vid_v_u8m1(size_t vl) { return vid_v_u8m1(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u8m2( // CHECK-RV64-LABEL: @test_vid_v_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8.i64(<vscale x 16 x i8> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vid_v_u8m2(size_t vl) { return vid_v_u8m2(vl); } vuint8m2_t test_vid_v_u8m2(size_t vl) { return vid_v_u8m2(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u8m4( // CHECK-RV64-LABEL: @test_vid_v_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8.i64(<vscale x 32 x i8> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vid_v_u8m4(size_t vl) { return vid_v_u8m4(vl); } vuint8m4_t test_vid_v_u8m4(size_t vl) { return vid_v_u8m4(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u8m8( // CHECK-RV64-LABEL: @test_vid_v_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vid.nxv64i8.i64(<vscale x 64 x i8> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vid_v_u8m8(size_t vl) { return vid_v_u8m8(vl); } vuint8m8_t test_vid_v_u8m8(size_t vl) { return vid_v_u8m8(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u16mf4( // CHECK-RV64-LABEL: @test_vid_v_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16.i64(<vscale x 1 x i16> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vid_v_u16mf4(size_t vl) { return vid_v_u16mf4(vl); } vuint16mf4_t test_vid_v_u16mf4(size_t vl) { return vid_v_u16mf4(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u16mf2( // CHECK-RV64-LABEL: @test_vid_v_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16.i64(<vscale x 2 x i16> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vid_v_u16mf2(size_t vl) { return vid_v_u16mf2(vl); } vuint16mf2_t test_vid_v_u16mf2(size_t vl) { return vid_v_u16mf2(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u16m1( // CHECK-RV64-LABEL: @test_vid_v_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16.i64(<vscale x 4 x i16> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vid_v_u16m1(size_t vl) { return vid_v_u16m1(vl); } vuint16m1_t test_vid_v_u16m1(size_t vl) { return vid_v_u16m1(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u16m2( // CHECK-RV64-LABEL: @test_vid_v_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16.i64(<vscale x 8 x i16> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vid_v_u16m2(size_t vl) { return vid_v_u16m2(vl); } vuint16m2_t test_vid_v_u16m2(size_t vl) { return vid_v_u16m2(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u16m4( // CHECK-RV64-LABEL: @test_vid_v_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16.i64(<vscale x 16 x i16> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vid_v_u16m4(size_t vl) { return vid_v_u16m4(vl); } vuint16m4_t test_vid_v_u16m4(size_t vl) { return vid_v_u16m4(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u16m8( // CHECK-RV64-LABEL: @test_vid_v_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16.i64(<vscale x 32 x i16> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vid_v_u16m8(size_t vl) { return vid_v_u16m8(vl); } vuint16m8_t test_vid_v_u16m8(size_t vl) { return vid_v_u16m8(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u32mf2( // CHECK-RV64-LABEL: @test_vid_v_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32.i64(<vscale x 1 x i32> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vid_v_u32mf2(size_t vl) { return vid_v_u32mf2(vl); } vuint32mf2_t test_vid_v_u32mf2(size_t vl) { return vid_v_u32mf2(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u32m1( // CHECK-RV64-LABEL: @test_vid_v_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32.i64(<vscale x 2 x i32> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vid_v_u32m1(size_t vl) { return vid_v_u32m1(vl); } vuint32m1_t test_vid_v_u32m1(size_t vl) { return vid_v_u32m1(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u32m2( // CHECK-RV64-LABEL: @test_vid_v_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32.i64(<vscale x 4 x i32> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vid_v_u32m2(size_t vl) { return vid_v_u32m2(vl); } vuint32m2_t test_vid_v_u32m2(size_t vl) { return vid_v_u32m2(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u32m4( // CHECK-RV64-LABEL: @test_vid_v_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32.i64(<vscale x 8 x i32> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vid_v_u32m4(size_t vl) { return vid_v_u32m4(vl); } vuint32m4_t test_vid_v_u32m4(size_t vl) { return vid_v_u32m4(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u32m8( // CHECK-RV64-LABEL: @test_vid_v_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32.i64(<vscale x 16 x i32> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vid_v_u32m8(size_t vl) { return vid_v_u32m8(vl); } vuint32m8_t test_vid_v_u32m8(size_t vl) { return vid_v_u32m8(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u64m1( // CHECK-RV64-LABEL: @test_vid_v_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64.i64(<vscale x 1 x i64> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vid_v_u64m1(size_t vl) { return vid_v_u64m1(vl); } vuint64m1_t test_vid_v_u64m1(size_t vl) { return vid_v_u64m1(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u64m2( // CHECK-RV64-LABEL: @test_vid_v_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64.i64(<vscale x 2 x i64> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vid_v_u64m2(size_t vl) { return vid_v_u64m2(vl); } vuint64m2_t test_vid_v_u64m2(size_t vl) { return vid_v_u64m2(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u64m4( // CHECK-RV64-LABEL: @test_vid_v_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64.i64(<vscale x 4 x i64> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vid_v_u64m4(size_t vl) { return vid_v_u64m4(vl); } vuint64m4_t test_vid_v_u64m4(size_t vl) { return vid_v_u64m4(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u64m8( // CHECK-RV64-LABEL: @test_vid_v_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64.i64(i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64.i64(<vscale x 8 x i64> undef, i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vid_v_u64m8(size_t vl) { return vid_v_u64m8(vl); } vuint64m8_t test_vid_v_u64m8(size_t vl) { return vid_v_u64m8(vl); }
// CHECK-RV64-LABEL: @test_vid_v_u8mf8_m( // CHECK-RV64-LABEL: @test_vid_v_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
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clang/test/CodeGen/RISCV/rvv-intrinsics/viota.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_viota_m_u8mf8( // CHECK-RV64-LABEL: @test_viota_m_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_viota_m_u8mf8(vbool64_t op1, size_t vl) { vuint8mf8_t test_viota_m_u8mf8(vbool64_t op1, size_t vl) {
return viota_m_u8mf8(op1, vl); return viota_m_u8mf8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u8mf4( // CHECK-RV64-LABEL: @test_viota_m_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8.i64(<vscale x 2 x i8> undef, <vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_viota_m_u8mf4(vbool32_t op1, size_t vl) { vuint8mf4_t test_viota_m_u8mf4(vbool32_t op1, size_t vl) {
return viota_m_u8mf4(op1, vl); return viota_m_u8mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u8mf2( // CHECK-RV64-LABEL: @test_viota_m_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8.i64(<vscale x 4 x i8> undef, <vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_viota_m_u8mf2(vbool16_t op1, size_t vl) { vuint8mf2_t test_viota_m_u8mf2(vbool16_t op1, size_t vl) {
return viota_m_u8mf2(op1, vl); return viota_m_u8mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u8m1( // CHECK-RV64-LABEL: @test_viota_m_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8.i64(<vscale x 8 x i8> undef, <vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_viota_m_u8m1(vbool8_t op1, size_t vl) { vuint8m1_t test_viota_m_u8m1(vbool8_t op1, size_t vl) {
return viota_m_u8m1(op1, vl); return viota_m_u8m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u8m2( // CHECK-RV64-LABEL: @test_viota_m_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8.i64(<vscale x 16 x i8> undef, <vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_viota_m_u8m2(vbool4_t op1, size_t vl) { vuint8m2_t test_viota_m_u8m2(vbool4_t op1, size_t vl) {
return viota_m_u8m2(op1, vl); return viota_m_u8m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u8m4( // CHECK-RV64-LABEL: @test_viota_m_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8.i64(<vscale x 32 x i8> undef, <vscale x 32 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_viota_m_u8m4(vbool2_t op1, size_t vl) { vuint8m4_t test_viota_m_u8m4(vbool2_t op1, size_t vl) {
return viota_m_u8m4(op1, vl); return viota_m_u8m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u8m8( // CHECK-RV64-LABEL: @test_viota_m_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8.i64(<vscale x 64 x i8> undef, <vscale x 64 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_viota_m_u8m8(vbool1_t op1, size_t vl) { vuint8m8_t test_viota_m_u8m8(vbool1_t op1, size_t vl) {
return viota_m_u8m8(op1, vl); return viota_m_u8m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u16mf4( // CHECK-RV64-LABEL: @test_viota_m_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16.i64(<vscale x 1 x i16> undef, <vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_viota_m_u16mf4(vbool64_t op1, size_t vl) { vuint16mf4_t test_viota_m_u16mf4(vbool64_t op1, size_t vl) {
return viota_m_u16mf4(op1, vl); return viota_m_u16mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u16mf2( // CHECK-RV64-LABEL: @test_viota_m_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16.i64(<vscale x 2 x i16> undef, <vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_viota_m_u16mf2(vbool32_t op1, size_t vl) { vuint16mf2_t test_viota_m_u16mf2(vbool32_t op1, size_t vl) {
return viota_m_u16mf2(op1, vl); return viota_m_u16mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u16m1( // CHECK-RV64-LABEL: @test_viota_m_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16.i64(<vscale x 4 x i16> undef, <vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_viota_m_u16m1(vbool16_t op1, size_t vl) { vuint16m1_t test_viota_m_u16m1(vbool16_t op1, size_t vl) {
return viota_m_u16m1(op1, vl); return viota_m_u16m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u16m2( // CHECK-RV64-LABEL: @test_viota_m_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16.i64(<vscale x 8 x i16> undef, <vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_viota_m_u16m2(vbool8_t op1, size_t vl) { vuint16m2_t test_viota_m_u16m2(vbool8_t op1, size_t vl) {
return viota_m_u16m2(op1, vl); return viota_m_u16m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u16m4( // CHECK-RV64-LABEL: @test_viota_m_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16.i64(<vscale x 16 x i16> undef, <vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_viota_m_u16m4(vbool4_t op1, size_t vl) { vuint16m4_t test_viota_m_u16m4(vbool4_t op1, size_t vl) {
return viota_m_u16m4(op1, vl); return viota_m_u16m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u16m8( // CHECK-RV64-LABEL: @test_viota_m_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16.i64(<vscale x 32 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_viota_m_u16m8(vbool2_t op1, size_t vl) { vuint16m8_t test_viota_m_u16m8(vbool2_t op1, size_t vl) {
return viota_m_u16m8(op1, vl); return viota_m_u16m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u32mf2( // CHECK-RV64-LABEL: @test_viota_m_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_viota_m_u32mf2(vbool64_t op1, size_t vl) { vuint32mf2_t test_viota_m_u32mf2(vbool64_t op1, size_t vl) {
return viota_m_u32mf2(op1, vl); return viota_m_u32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u32m1( // CHECK-RV64-LABEL: @test_viota_m_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32.i64(<vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32.i64(<vscale x 2 x i32> undef, <vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_viota_m_u32m1(vbool32_t op1, size_t vl) { vuint32m1_t test_viota_m_u32m1(vbool32_t op1, size_t vl) {
return viota_m_u32m1(op1, vl); return viota_m_u32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u32m2( // CHECK-RV64-LABEL: @test_viota_m_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32.i64(<vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32.i64(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_viota_m_u32m2(vbool16_t op1, size_t vl) { vuint32m2_t test_viota_m_u32m2(vbool16_t op1, size_t vl) {
return viota_m_u32m2(op1, vl); return viota_m_u32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u32m4( // CHECK-RV64-LABEL: @test_viota_m_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32.i64(<vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32.i64(<vscale x 8 x i32> undef, <vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_viota_m_u32m4(vbool8_t op1, size_t vl) { vuint32m4_t test_viota_m_u32m4(vbool8_t op1, size_t vl) {
return viota_m_u32m4(op1, vl); return viota_m_u32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u32m8( // CHECK-RV64-LABEL: @test_viota_m_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32.i64(<vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32.i64(<vscale x 16 x i32> undef, <vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_viota_m_u32m8(vbool4_t op1, size_t vl) { vuint32m8_t test_viota_m_u32m8(vbool4_t op1, size_t vl) {
return viota_m_u32m8(op1, vl); return viota_m_u32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u64m1( // CHECK-RV64-LABEL: @test_viota_m_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_viota_m_u64m1(vbool64_t op1, size_t vl) { vuint64m1_t test_viota_m_u64m1(vbool64_t op1, size_t vl) {
return viota_m_u64m1(op1, vl); return viota_m_u64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u64m2( // CHECK-RV64-LABEL: @test_viota_m_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64.i64(<vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64.i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_viota_m_u64m2(vbool32_t op1, size_t vl) { vuint64m2_t test_viota_m_u64m2(vbool32_t op1, size_t vl) {
return viota_m_u64m2(op1, vl); return viota_m_u64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u64m4( // CHECK-RV64-LABEL: @test_viota_m_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64.i64(<vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64.i64(<vscale x 4 x i64> undef, <vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_viota_m_u64m4(vbool16_t op1, size_t vl) { vuint64m4_t test_viota_m_u64m4(vbool16_t op1, size_t vl) {
return viota_m_u64m4(op1, vl); return viota_m_u64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u64m8( // CHECK-RV64-LABEL: @test_viota_m_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64.i64(<vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64.i64(<vscale x 8 x i64> undef, <vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_viota_m_u64m8(vbool8_t op1, size_t vl) { vuint64m8_t test_viota_m_u64m8(vbool8_t op1, size_t vl) {
return viota_m_u64m8(op1, vl); return viota_m_u64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_viota_m_u8mf8_m( // CHECK-RV64-LABEL: @test_viota_m_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 217 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4( // CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vsext_vf2_i16mf4(vint8mf8_t op1, size_t vl) { vint16mf4_t test_vsext_vf2_i16mf4(vint8mf8_t op1, size_t vl) {
return vsext_vf2_i16mf4(op1, vl); return vsext_vf2_i16mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf2( // CHECK-RV64-LABEL: @test_vsext_vf2_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vsext_vf2_i16mf2(vint8mf4_t op1, size_t vl) { vint16mf2_t test_vsext_vf2_i16mf2(vint8mf4_t op1, size_t vl) {
return vsext_vf2_i16mf2(op1, vl); return vsext_vf2_i16mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m1( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vsext_vf2_i16m1(vint8mf2_t op1, size_t vl) { vint16m1_t test_vsext_vf2_i16m1(vint8mf2_t op1, size_t vl) {
return vsext_vf2_i16m1(op1, vl); return vsext_vf2_i16m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m2( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vsext_vf2_i16m2(vint8m1_t op1, size_t vl) { vint16m2_t test_vsext_vf2_i16m2(vint8m1_t op1, size_t vl) {
return vsext_vf2_i16m2(op1, vl); return vsext_vf2_i16m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m4( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vsext_vf2_i16m4(vint8m2_t op1, size_t vl) { vint16m4_t test_vsext_vf2_i16m4(vint8m2_t op1, size_t vl) {
return vsext_vf2_i16m4(op1, vl); return vsext_vf2_i16m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16m8( // CHECK-RV64-LABEL: @test_vsext_vf2_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vsext_vf2_i16m8(vint8m4_t op1, size_t vl) { vint16m8_t test_vsext_vf2_i16m8(vint8m4_t op1, size_t vl) {
return vsext_vf2_i16m8(op1, vl); return vsext_vf2_i16m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32mf2( // CHECK-RV64-LABEL: @test_vsext_vf4_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vsext_vf4_i32mf2(vint8mf8_t op1, size_t vl) { vint32mf2_t test_vsext_vf4_i32mf2(vint8mf8_t op1, size_t vl) {
return vsext_vf4_i32mf2(op1, vl); return vsext_vf4_i32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m1( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vsext_vf4_i32m1(vint8mf4_t op1, size_t vl) { vint32m1_t test_vsext_vf4_i32m1(vint8mf4_t op1, size_t vl) {
return vsext_vf4_i32m1(op1, vl); return vsext_vf4_i32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m2( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vsext_vf4_i32m2(vint8mf2_t op1, size_t vl) { vint32m2_t test_vsext_vf4_i32m2(vint8mf2_t op1, size_t vl) {
return vsext_vf4_i32m2(op1, vl); return vsext_vf4_i32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m4( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vsext_vf4_i32m4(vint8m1_t op1, size_t vl) { vint32m4_t test_vsext_vf4_i32m4(vint8m1_t op1, size_t vl) {
return vsext_vf4_i32m4(op1, vl); return vsext_vf4_i32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i32m8( // CHECK-RV64-LABEL: @test_vsext_vf4_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vsext_vf4_i32m8(vint8m2_t op1, size_t vl) { vint32m8_t test_vsext_vf4_i32m8(vint8m2_t op1, size_t vl) {
return vsext_vf4_i32m8(op1, vl); return vsext_vf4_i32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m1( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vsext_vf8_i64m1(vint8mf8_t op1, size_t vl) { vint64m1_t test_vsext_vf8_i64m1(vint8mf8_t op1, size_t vl) {
return vsext_vf8_i64m1(op1, vl); return vsext_vf8_i64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m2( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vsext_vf8_i64m2(vint8mf4_t op1, size_t vl) { vint64m2_t test_vsext_vf8_i64m2(vint8mf4_t op1, size_t vl) {
return vsext_vf8_i64m2(op1, vl); return vsext_vf8_i64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m4( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vsext_vf8_i64m4(vint8mf2_t op1, size_t vl) { vint64m4_t test_vsext_vf8_i64m4(vint8mf2_t op1, size_t vl) {
return vsext_vf8_i64m4(op1, vl); return vsext_vf8_i64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf8_i64m8( // CHECK-RV64-LABEL: @test_vsext_vf8_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vsext_vf8_i64m8(vint8m1_t op1, size_t vl) { vint64m8_t test_vsext_vf8_i64m8(vint8m1_t op1, size_t vl) {
return vsext_vf8_i64m8(op1, vl); return vsext_vf8_i64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32mf2( // CHECK-RV64-LABEL: @test_vsext_vf2_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vsext_vf2_i32mf2(vint16mf4_t op1, size_t vl) { vint32mf2_t test_vsext_vf2_i32mf2(vint16mf4_t op1, size_t vl) {
return vsext_vf2_i32mf2(op1, vl); return vsext_vf2_i32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m1( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vsext_vf2_i32m1(vint16mf2_t op1, size_t vl) { vint32m1_t test_vsext_vf2_i32m1(vint16mf2_t op1, size_t vl) {
return vsext_vf2_i32m1(op1, vl); return vsext_vf2_i32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m2( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vsext_vf2_i32m2(vint16m1_t op1, size_t vl) { vint32m2_t test_vsext_vf2_i32m2(vint16m1_t op1, size_t vl) {
return vsext_vf2_i32m2(op1, vl); return vsext_vf2_i32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m4( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vsext_vf2_i32m4(vint16m2_t op1, size_t vl) { vint32m4_t test_vsext_vf2_i32m4(vint16m2_t op1, size_t vl) {
return vsext_vf2_i32m4(op1, vl); return vsext_vf2_i32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i32m8( // CHECK-RV64-LABEL: @test_vsext_vf2_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vsext_vf2_i32m8(vint16m4_t op1, size_t vl) { vint32m8_t test_vsext_vf2_i32m8(vint16m4_t op1, size_t vl) {
return vsext_vf2_i32m8(op1, vl); return vsext_vf2_i32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m1( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vsext_vf4_i64m1(vint16mf4_t op1, size_t vl) { vint64m1_t test_vsext_vf4_i64m1(vint16mf4_t op1, size_t vl) {
return vsext_vf4_i64m1(op1, vl); return vsext_vf4_i64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m2( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vsext_vf4_i64m2(vint16mf2_t op1, size_t vl) { vint64m2_t test_vsext_vf4_i64m2(vint16mf2_t op1, size_t vl) {
return vsext_vf4_i64m2(op1, vl); return vsext_vf4_i64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m4( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vsext_vf4_i64m4(vint16m1_t op1, size_t vl) { vint64m4_t test_vsext_vf4_i64m4(vint16m1_t op1, size_t vl) {
return vsext_vf4_i64m4(op1, vl); return vsext_vf4_i64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf4_i64m8( // CHECK-RV64-LABEL: @test_vsext_vf4_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vsext_vf4_i64m8(vint16m2_t op1, size_t vl) { vint64m8_t test_vsext_vf4_i64m8(vint16m2_t op1, size_t vl) {
return vsext_vf4_i64m8(op1, vl); return vsext_vf4_i64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m1( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vsext_vf2_i64m1(vint32mf2_t op1, size_t vl) { vint64m1_t test_vsext_vf2_i64m1(vint32mf2_t op1, size_t vl) {
return vsext_vf2_i64m1(op1, vl); return vsext_vf2_i64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m2( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vsext_vf2_i64m2(vint32m1_t op1, size_t vl) { vint64m2_t test_vsext_vf2_i64m2(vint32m1_t op1, size_t vl) {
return vsext_vf2_i64m2(op1, vl); return vsext_vf2_i64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m4( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vsext_vf2_i64m4(vint32m2_t op1, size_t vl) { vint64m4_t test_vsext_vf2_i64m4(vint32m2_t op1, size_t vl) {
return vsext_vf2_i64m4(op1, vl); return vsext_vf2_i64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i64m8( // CHECK-RV64-LABEL: @test_vsext_vf2_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vsext_vf2_i64m8(vint32m4_t op1, size_t vl) { vint64m8_t test_vsext_vf2_i64m8(vint32m4_t op1, size_t vl) {
return vsext_vf2_i64m8(op1, vl); return vsext_vf2_i64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4_m( // CHECK-RV64-LABEL: @test_vsext_vf2_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
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clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4( // CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vzext_vf2_u16mf4(vuint8mf8_t op1, size_t vl) { vuint16mf4_t test_vzext_vf2_u16mf4(vuint8mf8_t op1, size_t vl) {
return vzext_vf2_u16mf4(op1, vl); return vzext_vf2_u16mf4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf2( // CHECK-RV64-LABEL: @test_vzext_vf2_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vzext_vf2_u16mf2(vuint8mf4_t op1, size_t vl) { vuint16mf2_t test_vzext_vf2_u16mf2(vuint8mf4_t op1, size_t vl) {
return vzext_vf2_u16mf2(op1, vl); return vzext_vf2_u16mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m1( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vzext_vf2_u16m1(vuint8mf2_t op1, size_t vl) { vuint16m1_t test_vzext_vf2_u16m1(vuint8mf2_t op1, size_t vl) {
return vzext_vf2_u16m1(op1, vl); return vzext_vf2_u16m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m2( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vzext_vf2_u16m2(vuint8m1_t op1, size_t vl) { vuint16m2_t test_vzext_vf2_u16m2(vuint8m1_t op1, size_t vl) {
return vzext_vf2_u16m2(op1, vl); return vzext_vf2_u16m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m4( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vzext_vf2_u16m4(vuint8m2_t op1, size_t vl) { vuint16m4_t test_vzext_vf2_u16m4(vuint8m2_t op1, size_t vl) {
return vzext_vf2_u16m4(op1, vl); return vzext_vf2_u16m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16m8( // CHECK-RV64-LABEL: @test_vzext_vf2_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> undef, <vscale x 32 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vzext_vf2_u16m8(vuint8m4_t op1, size_t vl) { vuint16m8_t test_vzext_vf2_u16m8(vuint8m4_t op1, size_t vl) {
return vzext_vf2_u16m8(op1, vl); return vzext_vf2_u16m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32mf2( // CHECK-RV64-LABEL: @test_vzext_vf4_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vzext_vf4_u32mf2(vuint8mf8_t op1, size_t vl) { vuint32mf2_t test_vzext_vf4_u32mf2(vuint8mf8_t op1, size_t vl) {
return vzext_vf4_u32mf2(op1, vl); return vzext_vf4_u32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m1( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vzext_vf4_u32m1(vuint8mf4_t op1, size_t vl) { vuint32m1_t test_vzext_vf4_u32m1(vuint8mf4_t op1, size_t vl) {
return vzext_vf4_u32m1(op1, vl); return vzext_vf4_u32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m2( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vzext_vf4_u32m2(vuint8mf2_t op1, size_t vl) { vuint32m2_t test_vzext_vf4_u32m2(vuint8mf2_t op1, size_t vl) {
return vzext_vf4_u32m2(op1, vl); return vzext_vf4_u32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m4( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vzext_vf4_u32m4(vuint8m1_t op1, size_t vl) { vuint32m4_t test_vzext_vf4_u32m4(vuint8m1_t op1, size_t vl) {
return vzext_vf4_u32m4(op1, vl); return vzext_vf4_u32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u32m8( // CHECK-RV64-LABEL: @test_vzext_vf4_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> undef, <vscale x 16 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vzext_vf4_u32m8(vuint8m2_t op1, size_t vl) { vuint32m8_t test_vzext_vf4_u32m8(vuint8m2_t op1, size_t vl) {
return vzext_vf4_u32m8(op1, vl); return vzext_vf4_u32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m1( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> undef, <vscale x 1 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vzext_vf8_u64m1(vuint8mf8_t op1, size_t vl) { vuint64m1_t test_vzext_vf8_u64m1(vuint8mf8_t op1, size_t vl) {
return vzext_vf8_u64m1(op1, vl); return vzext_vf8_u64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m2( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> undef, <vscale x 2 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vzext_vf8_u64m2(vuint8mf4_t op1, size_t vl) { vuint64m2_t test_vzext_vf8_u64m2(vuint8mf4_t op1, size_t vl) {
return vzext_vf8_u64m2(op1, vl); return vzext_vf8_u64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m4( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> undef, <vscale x 4 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vzext_vf8_u64m4(vuint8mf2_t op1, size_t vl) { vuint64m4_t test_vzext_vf8_u64m4(vuint8mf2_t op1, size_t vl) {
return vzext_vf8_u64m4(op1, vl); return vzext_vf8_u64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf8_u64m8( // CHECK-RV64-LABEL: @test_vzext_vf8_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> undef, <vscale x 8 x i8> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vzext_vf8_u64m8(vuint8m1_t op1, size_t vl) { vuint64m8_t test_vzext_vf8_u64m8(vuint8m1_t op1, size_t vl) {
return vzext_vf8_u64m8(op1, vl); return vzext_vf8_u64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32mf2( // CHECK-RV64-LABEL: @test_vzext_vf2_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vzext_vf2_u32mf2(vuint16mf4_t op1, size_t vl) { vuint32mf2_t test_vzext_vf2_u32mf2(vuint16mf4_t op1, size_t vl) {
return vzext_vf2_u32mf2(op1, vl); return vzext_vf2_u32mf2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m1( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vzext_vf2_u32m1(vuint16mf2_t op1, size_t vl) { vuint32m1_t test_vzext_vf2_u32m1(vuint16mf2_t op1, size_t vl) {
return vzext_vf2_u32m1(op1, vl); return vzext_vf2_u32m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m2( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vzext_vf2_u32m2(vuint16m1_t op1, size_t vl) { vuint32m2_t test_vzext_vf2_u32m2(vuint16m1_t op1, size_t vl) {
return vzext_vf2_u32m2(op1, vl); return vzext_vf2_u32m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m4( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vzext_vf2_u32m4(vuint16m2_t op1, size_t vl) { vuint32m4_t test_vzext_vf2_u32m4(vuint16m2_t op1, size_t vl) {
return vzext_vf2_u32m4(op1, vl); return vzext_vf2_u32m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u32m8( // CHECK-RV64-LABEL: @test_vzext_vf2_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> undef, <vscale x 16 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vzext_vf2_u32m8(vuint16m4_t op1, size_t vl) { vuint32m8_t test_vzext_vf2_u32m8(vuint16m4_t op1, size_t vl) {
return vzext_vf2_u32m8(op1, vl); return vzext_vf2_u32m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m1( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> undef, <vscale x 1 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vzext_vf4_u64m1(vuint16mf4_t op1, size_t vl) { vuint64m1_t test_vzext_vf4_u64m1(vuint16mf4_t op1, size_t vl) {
return vzext_vf4_u64m1(op1, vl); return vzext_vf4_u64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m2( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> undef, <vscale x 2 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vzext_vf4_u64m2(vuint16mf2_t op1, size_t vl) { vuint64m2_t test_vzext_vf4_u64m2(vuint16mf2_t op1, size_t vl) {
return vzext_vf4_u64m2(op1, vl); return vzext_vf4_u64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m4( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> undef, <vscale x 4 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vzext_vf4_u64m4(vuint16m1_t op1, size_t vl) { vuint64m4_t test_vzext_vf4_u64m4(vuint16m1_t op1, size_t vl) {
return vzext_vf4_u64m4(op1, vl); return vzext_vf4_u64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf4_u64m8( // CHECK-RV64-LABEL: @test_vzext_vf4_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> undef, <vscale x 8 x i16> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vzext_vf4_u64m8(vuint16m2_t op1, size_t vl) { vuint64m8_t test_vzext_vf4_u64m8(vuint16m2_t op1, size_t vl) {
return vzext_vf4_u64m8(op1, vl); return vzext_vf4_u64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m1( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vzext_vf2_u64m1(vuint32mf2_t op1, size_t vl) { vuint64m1_t test_vzext_vf2_u64m1(vuint32mf2_t op1, size_t vl) {
return vzext_vf2_u64m1(op1, vl); return vzext_vf2_u64m1(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m2( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> undef, <vscale x 2 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vzext_vf2_u64m2(vuint32m1_t op1, size_t vl) { vuint64m2_t test_vzext_vf2_u64m2(vuint32m1_t op1, size_t vl) {
return vzext_vf2_u64m2(op1, vl); return vzext_vf2_u64m2(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m4( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> undef, <vscale x 4 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vzext_vf2_u64m4(vuint32m2_t op1, size_t vl) { vuint64m4_t test_vzext_vf2_u64m4(vuint32m2_t op1, size_t vl) {
return vzext_vf2_u64m4(op1, vl); return vzext_vf2_u64m4(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u64m8( // CHECK-RV64-LABEL: @test_vzext_vf2_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> undef, <vscale x 8 x i32> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vzext_vf2_u64m8(vuint32m4_t op1, size_t vl) { vuint64m8_t test_vzext_vf2_u64m8(vuint32m4_t op1, size_t vl) {
return vzext_vf2_u64m8(op1, vl); return vzext_vf2_u64m8(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4_m( // CHECK-RV64-LABEL: @test_vzext_vf2_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 277 Lines • Show Last 20 Lines

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 344 Lines • ▼ Show 20 Lines class RISCVIStoreMask
: Intrinsic<[], : Intrinsic<[],
[llvm_anyvector_ty, [llvm_anyvector_ty,
LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic { [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic {
let VLOperand = 4; let VLOperand = 4;
} }
// For destination vector type is the same as source vector. // For destination vector type is the same as source vector.
// Input: (vector_in, vl) // Input: (passthru, vector_in, vl)
class RISCVUnaryAANoMask class RISCVUnaryAANoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
// For destination vector type is the same as first source vector (with mask). // For destination vector type is the same as first source vector (with mask).
// Input: (vector_in, mask, vl, ta) // Input: (vector_in, mask, vl, ta)
class RISCVUnaryAAMask class RISCVUnaryAAMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, [LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<1>], LLVMMatchType<1>],
[ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic { [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
class RISCVUnaryAAMaskNoTA class RISCVUnaryAAMaskTU
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, [LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// For destination vector type is the same as first and second source vector. // For destination vector type is the same as first and second source vector.
// Input: (vector_in, vector_in, vl) // Input: (vector_in, vector_in, vl)
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines class RISCVCompareMask
llvm_anyvector_ty, llvm_any_ty, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let SplatOperand = 2; let SplatOperand = 2;
let VLOperand = 4; let VLOperand = 4;
} }
// For FP classify operations. // For FP classify operations.
// Output: (bit mask type output) // Output: (bit mask type output)
// Input: (vector_in, vl) // Input: (passthru, vector_in, vl)
class RISCVClassifyNoMask class RISCVClassifyNoMask
: Intrinsic<[LLVMVectorOfBitcastsToInt<0>], : Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
[llvm_anyvector_ty, llvm_anyint_ty], [LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 1;
} }
// For FP classify operations with mask. // For FP classify operations with mask.
// Output: (bit mask type output) // Output: (bit mask type output)
// Input: (maskedoff, vector_in, mask, vl) // Input: (maskedoff, vector_in, mask, vl, policy)
class RISCVClassifyMask class RISCVClassifyMask
: Intrinsic<[LLVMVectorOfBitcastsToInt<0>], : Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
[LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty, [LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
[IntrNoMem]>, RISCVVIntrinsic { llvm_anyint_ty, LLVMMatchType<1>],
[IntrNoMem, ImmArg<ArgIndex<4>>]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// For Saturating binary operations. // For Saturating binary operations.
// The destination vector type is the same as first source vector. // The destination vector type is the same as first source vector.
// Input: (passthru, vector_in, vector_in/scalar_in, vl) // Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVSaturatingBinaryAAXNoMask class RISCVSaturatingBinaryAAXNoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty, [LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
// Input: (vector_in, mask, vl) // Input: (vector_in, mask, vl)
class RISCVMaskUnarySOutMask class RISCVMaskUnarySOutMask
: Intrinsic<[LLVMMatchType<1>], : Intrinsic<[LLVMMatchType<1>],
[llvm_anyvector_ty, LLVMMatchType<0>, llvm_anyint_ty], [llvm_anyvector_ty, LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2; let VLOperand = 2;
} }
// For destination vector type is NOT the same as source vector. // For destination vector type is NOT the same as source vector.
// Input: (vector_in, vl) // Input: (passthru, vector_in, vl)
class RISCVUnaryABNoMask class RISCVUnaryABNoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, llvm_anyint_ty], [LLVMMatchType<0>, llvm_anyvector_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
// For destination vector type is NOT the same as source vector (with mask). // For destination vector type is NOT the same as source vector (with mask).
// Input: (maskedoff, vector_in, mask, vl, ta) // Input: (maskedoff, vector_in, mask, vl, ta)
class RISCVUnaryABMask class RISCVUnaryABMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, [LLVMMatchType<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<2>], llvm_anyint_ty, LLVMMatchType<2>],
Show All 18 Lines class RISCVMaskUnaryMOutMask
LLVMMatchType<0>, llvm_anyint_ty], LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// Output: (vector) // Output: (vector)
// Input: (vl) // Input: (vl)
class RISCVNullaryIntrinsic class RISCVNullaryIntrinsic
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1;
}
// Output: (vector)
// Input: (passthru, vl)
class RISCVNullaryIntrinsicTU
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 0; let VLOperand = 1;
} }
// For Conversion unary operations. // For Conversion unary operations.
// Input: (vector_in, vl) // Input: (passthru, vector_in, vl)
class RISCVConversionNoMask class RISCVConversionNoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, llvm_anyint_ty], [LLVMMatchType<0>, llvm_anyvector_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
// For Conversion unary operations with mask. // For Conversion unary operations with mask.
// Input: (maskedoff, vector_in, mask, vl, ta) // Input: (maskedoff, vector_in, mask, vl, ta)
class RISCVConversionMask class RISCVConversionMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, [LLVMMatchType<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<2>], LLVMMatchType<2>],
▲ Show 20 Lines • Show All 441 Lines • ▼ Show 20 Lines def int_riscv_vmv_v_v : Intrinsic<[llvm_anyvector_ty],
let VLOperand = 1; let VLOperand = 1;
} }
def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty], def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty],
[LLVMVectorElementType<0>, llvm_anyint_ty], [LLVMVectorElementType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 1;
} }
def int_riscv_vfmv_v_f : Intrinsic<[llvm_anyfloat_ty], def int_riscv_vfmv_v_f : Intrinsic<[llvm_anyfloat_ty],
[LLVMVectorElementType<0>, llvm_anyint_ty], [LLVMVectorElementType<0>,llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 1;
} }
def int_riscv_vmv_x_s : Intrinsic<[LLVMVectorElementType<0>], def int_riscv_vmv_x_s : Intrinsic<[LLVMVectorElementType<0>],
[llvm_anyint_ty], [llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic; [IntrNoMem]>, RISCVVIntrinsic;
def int_riscv_vmv_s_x : Intrinsic<[llvm_anyint_ty], def int_riscv_vmv_s_x : Intrinsic<[llvm_anyint_ty],
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
defm vslide1down : RISCVBinaryAAX; defm vslide1down : RISCVBinaryAAX;
defm vfslide1up : RISCVBinaryAAX; defm vfslide1up : RISCVBinaryAAX;
defm vfslide1down : RISCVBinaryAAX; defm vfslide1down : RISCVBinaryAAX;
defm vrgather_vv : RISCVRGatherVV; defm vrgather_vv : RISCVRGatherVV;
defm vrgather_vx : RISCVRGatherVX; defm vrgather_vx : RISCVRGatherVX;
defm vrgatherei16_vv : RISCVRGatherEI16VV; defm vrgatherei16_vv : RISCVRGatherEI16VV;
def "int_riscv_vcompress" : RISCVUnaryAAMaskNoTA; def "int_riscv_vcompress" : RISCVUnaryAAMaskTU;
defm vaaddu : RISCVSaturatingBinaryAAX; defm vaaddu : RISCVSaturatingBinaryAAX;
defm vaadd : RISCVSaturatingBinaryAAX; defm vaadd : RISCVSaturatingBinaryAAX;
defm vasubu : RISCVSaturatingBinaryAAX; defm vasubu : RISCVSaturatingBinaryAAX;
defm vasub : RISCVSaturatingBinaryAAX; defm vasub : RISCVSaturatingBinaryAAX;
defm vsmul : RISCVSaturatingBinaryAAX; defm vsmul : RISCVSaturatingBinaryAAX;
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
defm vfncvt_xu_f_w : RISCVConversion; defm vfncvt_xu_f_w : RISCVConversion;
defm vfncvt_x_f_w : RISCVConversion; defm vfncvt_x_f_w : RISCVConversion;
defm vfncvt_rtz_xu_f_w : RISCVConversion; defm vfncvt_rtz_xu_f_w : RISCVConversion;
defm vfncvt_rtz_x_f_w : RISCVConversion; defm vfncvt_rtz_x_f_w : RISCVConversion;
defm vfncvt_f_f_w : RISCVConversion; defm vfncvt_f_f_w : RISCVConversion;
defm vfncvt_rod_f_f_w : RISCVConversion; defm vfncvt_rod_f_f_w : RISCVConversion;
// Output: (vector) // Output: (vector)
// Input: (mask type input, vl) // Input: (passthru, mask type input, vl)
def int_riscv_viota : Intrinsic<[llvm_anyvector_ty], def int_riscv_viota : Intrinsic<[llvm_anyvector_ty],
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, [LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty], llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 2;
} }
// Output: (vector) // Output: (vector)
// Input: (maskedoff, mask type vector_in, mask, vl) // Input: (maskedoff, mask type vector_in, mask, vl)
def int_riscv_viota_mask : Intrinsic<[llvm_anyvector_ty], def int_riscv_viota_mask : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, [LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty], llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// Output: (vector) // Output: (vector)
// Input: (vl) // Input: (passthru, vl)
def int_riscv_vid : RISCVNullaryIntrinsic; def int_riscv_vid : RISCVNullaryIntrinsicTU;
// Output: (vector) // Output: (vector)
// Input: (maskedoff, mask, vl) // Input: (maskedoff, mask, vl)
def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty], def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, [LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty], llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
▲ Show 20 Lines • Show All 116 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 866 Lines • ▼ Show 20 Linesclass VPseudoNullaryNoMask<VReg RegClass>:
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasDummyMask = 1; let HasDummyMask = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoNullaryNoMaskTU<VReg RegClass>:
Pseudo<(outs RegClass:$rd),
(ins RegClass:$merge, AVL:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = "$rd = $merge";
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoNullaryMask<VReg RegClass>: class VPseudoNullaryMask<VReg RegClass>:
Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
(ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl, (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
ixlenimm:$sew), []>, RISCVVPseudo { ixlenimm:$sew), []>, RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints ="$rd = $merge"; let Constraints ="$rd = $merge";
Show All 28 Linesclass VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = Constraint; let Constraints = Constraint;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasDummyMask = 1; let HasDummyMask = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
// RetClass could be GPR or VReg.
class VPseudoUnaryNoMaskTU<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasDummyMask = 1;
let HasMergeOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> : class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
▲ Show 20 Lines • Show All 715 Lines • ▼ Show 20 Linesmulticlass VPseudoVSFS_M {
} }
} }
multiclass VPseudoVID_V { multiclass VPseudoVID_V {
foreach m = MxList in { foreach m = MxList in {
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>, def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
Sched<[WriteVMIdxV, ReadVMask]>; Sched<[WriteVMIdxV, ReadVMask]>;
def "_V_" # m.MX # "_TU": VPseudoNullaryNoMaskTU<m.vrclass>,
Sched<[WriteVMIdxV, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>, def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
Sched<[WriteVMIdxV, ReadVMask]>; Sched<[WriteVMIdxV, ReadVMask]>;
} }
} }
} }
multiclass VPseudoNullaryPseudoM <string BaseInst> { multiclass VPseudoNullaryPseudoM <string BaseInst> {
foreach mti = AllMasks in { foreach mti = AllMasks in {
let VLMul = mti.LMul.value in { let VLMul = mti.LMul.value in {
def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">; def "_M_" # mti.BX : VPseudoNullaryPseudoM<BaseInst # "_MM">;
} }
} }
} }
multiclass VPseudoVIOT_M { multiclass VPseudoVIOT_M {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList in { foreach m = MxList in {
let VLMul = m.value in { let VLMul = m.value in {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>, def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
def "_" # m.MX # "_TU" : VPseudoUnaryNoMaskTU<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>, def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVCPR_V { multiclass VPseudoVCPR_V {
foreach m = MxList in { foreach m = MxList in {
▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Linesmulticlass VPseudoVMV_F {
} }
} }
multiclass VPseudoVCLS_V { multiclass VPseudoVCLS_V {
foreach m = MxListF in { foreach m = MxListF in {
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>; Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>, def "_V_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>; Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVSQR_V { multiclass VPseudoVSQR_V {
foreach m = MxListF in { foreach m = MxListF in {
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>; Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>;
def "_V_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>, def "_V_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>,
Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>; Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVRCP_V { multiclass VPseudoVRCP_V {
foreach m = MxListF in { foreach m = MxListF in {
let VLMul = m.value in { let VLMul = m.value in {
def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>, def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>; Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>;
def "_V_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>, def "_V_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>; Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>;
} }
} }
} }
multiclass PseudoVEXT_VF2 { multiclass PseudoVEXT_VF2 {
defvar constraints = "@earlyclobber $rd"; defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF2 in foreach m = MxListVF2 in
{ {
let VLMul = m.value in { let VLMul = m.value in {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>, def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f2vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_MASK" : def "_" # m.MX # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f2vrclass, constraints>, VPseudoUnaryMaskTA<m.vrclass, m.f2vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
} }
} }
} }
multiclass PseudoVEXT_VF4 { multiclass PseudoVEXT_VF4 {
defvar constraints = "@earlyclobber $rd"; defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF4 in foreach m = MxListVF4 in
{ {
let VLMul = m.value in { let VLMul = m.value in {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>, def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f4vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_MASK" : def "_" # m.MX # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f4vrclass, constraints>, VPseudoUnaryMaskTA<m.vrclass, m.f4vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
} }
} }
} }
multiclass PseudoVEXT_VF8 { multiclass PseudoVEXT_VF8 {
defvar constraints = "@earlyclobber $rd"; defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF8 in foreach m = MxListVF8 in
{ {
let VLMul = m.value in { let VLMul = m.value in {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>, def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_TU": VPseudoUnaryNoMaskTU<m.vrclass, m.f8vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
def "_" # m.MX # "_MASK" : def "_" # m.MX # "_MASK" :
VPseudoUnaryMaskTA<m.vrclass, m.f8vrclass, constraints>, VPseudoUnaryMaskTA<m.vrclass, m.f8vrclass, constraints>,
Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
} }
} }
} }
// The destination EEW is 1 since "For the purposes of register group overlap // The destination EEW is 1 since "For the purposes of register group overlap
▲ Show 20 Lines • Show All 507 Lines • ▼ Show 20 Lines
} }
multiclass VPseudoConversion<VReg RetClass, multiclass VPseudoConversion<VReg RetClass,
VReg Op1Class, VReg Op1Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>; def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class, def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class,
Constraint>; Constraint>;
} }
} }
multiclass VPseudoVCVTI_V { multiclass VPseudoVCVTI_V {
foreach m = MxListF in foreach m = MxListF in
defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>, defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Linesclass VPatUnaryNoMask<string intrinsic_name,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op2_type, ValueType op2_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg op2_reg_class> : VReg op2_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name) Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type undef),
(op2_type op2_reg_class:$rs2), (op2_type op2_reg_class:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
(op2_type op2_reg_class:$rs2), (op2_type op2_reg_class:$rs2),
GPR:$vl, sew)>; GPR:$vl, sew)>;
class VPatUnaryNoMaskTU<string intrinsic_name,
string inst,
string kind,
ValueType result_type,
ValueType op2_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
VReg op2_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2),
VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_TU")
(result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2),
GPR:$vl, sew)>;
class VPatUnaryMask<string intrinsic_name, class VPatUnaryMask<string intrinsic_name,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
▲ Show 20 Lines • Show All 394 Lines • ▼ Show 20 Linesmulticlass VPatUnaryM_M<string intrinsic,
} }
} }
multiclass VPatUnaryV_M<string intrinsic, string instruction> multiclass VPatUnaryV_M<string intrinsic, string instruction>
{ {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask, def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, VR>; vti.Log2SEW, vti.LMul, VR>;
def : VPatUnaryNoMaskTU<intrinsic, instruction, "M", vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,VR>;
def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask, def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>; vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
} }
} }
multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix, multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,
list<VTypeInfoToFraction> fractionList> list<VTypeInfoToFraction> fractionList>
{ {
foreach vtiTofti = fractionList in foreach vtiTofti = fractionList in
{ {
defvar vti = vtiTofti.Vti; defvar vti = vtiTofti.Vti;
defvar fti = vtiTofti.Fti; defvar fti = vtiTofti.Fti;
def : VPatUnaryNoMask<intrinsic, instruction, suffix, def : VPatUnaryNoMask<intrinsic, instruction, suffix,
vti.Vector, fti.Vector, vti.Vector, fti.Vector,
vti.Log2SEW, vti.LMul, fti.RegClass>; vti.Log2SEW, vti.LMul, fti.RegClass>;
def : VPatUnaryNoMaskTU<intrinsic, instruction, suffix,
vti.Vector, fti.Vector,
vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;
def : VPatUnaryMaskTA<intrinsic, instruction, suffix, def : VPatUnaryMaskTA<intrinsic, instruction, suffix,
vti.Vector, fti.Vector, vti.Mask, vti.Vector, fti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>; vti.Log2SEW, vti.LMul, vti.RegClass, fti.RegClass>;
} }
} }
multiclass VPatUnaryV_V<string intrinsic, string instruction, multiclass VPatUnaryV_V<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in { foreach vti = vtilist in {
def : VPatUnaryNoMask<intrinsic, instruction, "V", def : VPatUnaryNoMask<intrinsic, instruction, "V",
vti.Vector, vti.Vector, vti.Vector, vti.Vector,
vti.Log2SEW, vti.LMul, vti.RegClass>; vti.Log2SEW, vti.LMul, vti.RegClass>;
def : VPatUnaryNoMaskTU<intrinsic, instruction, "V",
vti.Vector, vti.Vector,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>;
def : VPatUnaryMaskTA<intrinsic, instruction, "V", def : VPatUnaryMaskTA<intrinsic, instruction, "V",
vti.Vector, vti.Vector, vti.Mask, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>;
} }
} }
multiclass VPatNullaryV<string intrinsic, string instruction> multiclass VPatNullaryV<string intrinsic, string instruction>
{ {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic) def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
(vti.Vector undef),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction#"_V_" # vti.LMul.MX) (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)
GPR:$vl, vti.Log2SEW)>; GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
(vti.Vector vti.RegClass:$merge),
VLOpFrag)),
(!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_TU")
vti.RegClass:$merge, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask") def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")
(vti.Vector vti.RegClass:$merge), (vti.Vector vti.RegClass:$merge),
(vti.Mask V0), VLOpFrag)), (vti.Mask V0), VLOpFrag)),
(!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK") (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK")
vti.RegClass:$merge, (vti.Mask V0), vti.RegClass:$merge, (vti.Mask V0),
GPR:$vl, vti.Log2SEW)>; GPR:$vl, vti.Log2SEW)>;
} }
} }
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Linesmulticlass VPatConversionTA<string intrinsic,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class> VReg op1_reg_class>
{ {
def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type, def : VPatUnaryNoMask<intrinsic, inst, kind, result_type, op1_type,
sew, vlmul, op1_reg_class>; sew, vlmul, op1_reg_class>;
def : VPatUnaryNoMaskTU<intrinsic, inst, kind, result_type, op1_type,
sew, vlmul, result_reg_class, op1_reg_class>;
def : VPatUnaryMaskTA<intrinsic, inst, kind, result_type, op1_type, def : VPatUnaryMaskTA<intrinsic, inst, kind, result_type, op1_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class>; mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
} }
multiclass VPatBinaryV_VV<string intrinsic, string instruction, multiclass VPatBinaryV_VV<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatBinaryTA<intrinsic, instruction # "_VV_" # vti.LMul.MX, defm : VPatBinaryTA<intrinsic, instruction # "_VV_" # vti.LMul.MX,
▲ Show 20 Lines • Show All 513 Lines • ▼ Show 20 Lines if !le(wtiSEW, 64) then {
wtiM1.Vector, vti.Mask, wtiM1.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.Log2SEW, vti.LMul,
wtiM1.RegClass, vti.RegClass, wtiM1.RegClass, vti.RegClass,
wtiM1.RegClass>; wtiM1.RegClass>;
} }
} }
} }
multiclass VPatClassifyVI_VF<string intrinsic,
string instruction>
{
foreach fvti = AllFloatVectors in
{
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
defm : VPatConversion<intrinsic, instruction, "V",
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
fvti.LMul, ivti.RegClass, fvti.RegClass>;
}
}
multiclass VPatConversionVI_VF<string intrinsic, multiclass VPatConversionVI_VF<string intrinsic,
string instruction> string instruction>
{ {
foreach fvti = AllFloatVectors in foreach fvti = AllFloatVectors in
{ {
defvar ivti = GetIntVTypeInfo<fvti>.Vti; defvar ivti = GetIntVTypeInfo<fvti>.Vti;
defm : VPatConversionTA<intrinsic, instruction, "V", defm : VPatConversionTA<intrinsic, instruction, "V",
▲ Show 20 Lines • Show All 1,122 Lines • ▼ Show 20 Lines
defm : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT", AllFloatVectors>; defm : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT", AllFloatVectors>;
defm : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>; defm : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>;
defm : VPatBinarySwappedM_VV<"int_riscv_vmfgt", "PseudoVMFLT", AllFloatVectors>; defm : VPatBinarySwappedM_VV<"int_riscv_vmfgt", "PseudoVMFLT", AllFloatVectors>;
defm : VPatBinarySwappedM_VV<"int_riscv_vmfge", "PseudoVMFLE", AllFloatVectors>; defm : VPatBinarySwappedM_VV<"int_riscv_vmfge", "PseudoVMFLE", AllFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.14. Vector Floating-Point Classify Instruction // 14.14. Vector Floating-Point Classify Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatClassifyVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">; defm : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.15. Vector Floating-Point Merge Instruction // 14.15. Vector Floating-Point Merge Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// We can use vmerge.vvm to support vector-vector vfmerge. // We can use vmerge.vvm to support vector-vector vfmerge.
// NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses // NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses
// int_riscv_vmerge. Support both for compatibility. // int_riscv_vmerge. Support both for compatibility.
defm : VPatBinaryV_VM<"int_riscv_vmerge", "PseudoVMERGE", defm : VPatBinaryV_VM<"int_riscv_vmerge", "PseudoVMERGE",
▲ Show 20 Lines • Show All 228 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll

Show First 20 Lines • Show All 2,197 Lines • ▼ Show 20 Linesentry:
%a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
iXLen %3) iXLen %3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i8>,
iXLen);
define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vsext_vf8_nxv1i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; RV32-NEXT: vsext.vf8 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vsext_vf8_nxv1i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; RV64-NEXT: vsext.vf8 v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
<vscale x 1 x i64> %0,
<vscale x 1 x i8> %1,
iXLen %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i8>,
iXLen);
define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vzext_vf8_nxv1i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; RV32-NEXT: vzext.vf8 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vzext_vf8_nxv1i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; RV64-NEXT: vzext.vf8 v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
<vscale x 1 x i64> %0,
<vscale x 1 x i8> %1,
iXLen %2)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16>,
<vscale x 2 x float>,
iXLen);
define <vscale x 2 x i16> @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( <vscale x 2 x i16> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; RV32-NEXT: vfncvt.x.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; RV64-NEXT: vfncvt.x.f.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16> %0,
<vscale x 2 x float> %1,
iXLen %2)
ret <vscale x 2 x i16> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
<vscale x 1 x i8>,
iXLen);
define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; RV32-LABEL: intrinsic_vid_v_nxv1i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vid.v v8
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vid_v_nxv1i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vid.v v8
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
<vscale x 1 x i8> %0,
iXLen %1)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1f16(
; RV32-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfclass.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfclass.v v8, v9
; RV64-NEXT: ret
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
iXLen %2) nounwind {
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x i16>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfcvt.f.x.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfcvt.f.x.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16(
<vscale x 1 x half> %0,
<vscale x 1 x i16> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x i16>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfcvt.f.xu.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfcvt.f.xu.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16(
<vscale x 1 x half> %0,
<vscale x 1 x i16> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfcvt.rtz.x.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfcvt.rtz.x.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfcvt.rtz.xu.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfcvt.rtz.xu.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfcvt.x.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half>,
<vscale x 1 x float>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x half> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfncvt.f.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfncvt.f.f.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half> %0,
<vscale x 1 x float> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfcvt.xu.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfcvt.xu.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x i32>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfncvt.f.x.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfncvt.f.x.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32(
<vscale x 1 x half> %0,
<vscale x 1 x i32> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x i32>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfncvt.f.xu.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfncvt.f.xu.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(
<vscale x 1 x half> %0,
<vscale x 1 x i32> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half>,
<vscale x 1 x float>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32(<vscale x 1 x half> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfncvt.rod.f.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfncvt.rod.f.f.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half> %0,
<vscale x 1 x float> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vfncvt.rtz.x.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vfncvt.rtz.x.f.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vfncvt.rtz.xu.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vfncvt.rtz.xu.f.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vfncvt.x.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vfncvt.x.f.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vfncvt.xu.f.w v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vfncvt.xu.f.w v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfrec7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfrec7.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfrec7.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfrsqrt7.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfrsqrt7.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfsqrt.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfsqrt.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfwcvt.f.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfwcvt.f.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
<vscale x 1 x float> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x float> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x i8>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vfwcvt.f.x.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vfwcvt.f.x.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8(
<vscale x 1 x half> %0,
<vscale x 1 x i8> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x i8>,
iXLen);
define <vscale x 1 x half> @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: vfwcvt.f.xu.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: vfwcvt.f.xu.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8(
<vscale x 1 x half> %0,
<vscale x 1 x i8> %1,
iXLen %2)
ret <vscale x 1 x half> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfwcvt.rtz.x.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfwcvt.rtz.x.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfwcvt.x.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfwcvt.x.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>,
iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV32-NEXT: vfwcvt.xu.f.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; RV64-NEXT: vfwcvt.xu.f.v v8, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> %0,
<vscale x 1 x half> %1,
iXLen %2)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i1>,
iXLen);
define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV32-NEXT: viota.m v8, v0
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
; RV64-NEXT: viota.m v8, v0
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i1> %1,
iXLen %2)
ret <vscale x 1 x i8> %a
}

llvm/test/CodeGen/RISCV/rvv/vfclass.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1f16( define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16: ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1f16( define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: vfclass.v v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfclass_v_nxv2i16_nxv2f16( define <vscale x 2 x i16> @intrinsic_vfclass_v_nxv2i16_nxv2f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2f16: ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i16> @intrinsic_vfclass_mask_v_nxv2i16_nxv2f16( define <vscale x 2 x i16> @intrinsic_vfclass_mask_v_nxv2i16_nxv2f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2f16: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: vfclass.v v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfclass_v_nxv4i16_nxv4f16( define <vscale x 4 x i16> @intrinsic_vfclass_v_nxv4i16_nxv4f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4f16: ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i16> @intrinsic_vfclass_mask_v_nxv4i16_nxv4f16( define <vscale x 4 x i16> @intrinsic_vfclass_mask_v_nxv4i16_nxv4f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4f16: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: vfclass.v v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfclass_v_nxv8i16_nxv8f16( define <vscale x 8 x i16> @intrinsic_vfclass_v_nxv8i16_nxv8f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8f16: ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i16> @intrinsic_vfclass_mask_v_nxv8i16_nxv8f16( define <vscale x 8 x i16> @intrinsic_vfclass_mask_v_nxv8i16_nxv8f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8f16: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: vfclass.v v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfclass_v_nxv16i16_nxv16f16( define <vscale x 16 x i16> @intrinsic_vfclass_v_nxv16i16_nxv16f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16f16: ; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i16> @intrinsic_vfclass_mask_v_nxv16i16_nxv16f16( define <vscale x 16 x i16> @intrinsic_vfclass_mask_v_nxv16i16_nxv16f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16f16: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: vfclass.v v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i16> @intrinsic_vfclass_v_nxv32i16_nxv32f16( define <vscale x 32 x i16> @intrinsic_vfclass_v_nxv32i16_nxv32f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32f16: ; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 32 x i16> @intrinsic_vfclass_mask_v_nxv32i16_nxv32f16( define <vscale x 32 x i16> @intrinsic_vfclass_mask_v_nxv32i16_nxv32f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32f16: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: vfclass.v v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfclass_v_nxv1i32_nxv1f32( define <vscale x 1 x i32> @intrinsic_vfclass_v_nxv1i32_nxv1f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i32_nxv1f32: ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i32> @intrinsic_vfclass_mask_v_nxv1i32_nxv1f32( define <vscale x 1 x i32> @intrinsic_vfclass_mask_v_nxv1i32_nxv1f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i32_nxv1f32: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: vfclass.v v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfclass_v_nxv2i32_nxv2f32( define <vscale x 2 x i32> @intrinsic_vfclass_v_nxv2i32_nxv2f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i32_nxv2f32: ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i32> @intrinsic_vfclass_mask_v_nxv2i32_nxv2f32( define <vscale x 2 x i32> @intrinsic_vfclass_mask_v_nxv2i32_nxv2f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i32_nxv2f32: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: vfclass.v v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfclass_v_nxv4i32_nxv4f32( define <vscale x 4 x i32> @intrinsic_vfclass_v_nxv4i32_nxv4f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i32_nxv4f32: ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i32> @intrinsic_vfclass_mask_v_nxv4i32_nxv4f32( define <vscale x 4 x i32> @intrinsic_vfclass_mask_v_nxv4i32_nxv4f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i32_nxv4f32: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: vfclass.v v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfclass_v_nxv8i32_nxv8f32( define <vscale x 8 x i32> @intrinsic_vfclass_v_nxv8i32_nxv8f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i32_nxv8f32: ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i32> @intrinsic_vfclass_mask_v_nxv8i32_nxv8f32( define <vscale x 8 x i32> @intrinsic_vfclass_mask_v_nxv8i32_nxv8f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i32_nxv8f32: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: vfclass.v v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfclass_v_nxv16i32_nxv16f32( define <vscale x 16 x i32> @intrinsic_vfclass_v_nxv16i32_nxv16f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv16i32_nxv16f32: ; CHECK-LABEL: intrinsic_vfclass_v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i32> @intrinsic_vfclass_mask_v_nxv16i32_nxv16f32( define <vscale x 16 x i32> @intrinsic_vfclass_mask_v_nxv16i32_nxv16f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i32_nxv16f32: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: vfclass.v v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfclass_v_nxv1i64_nxv1f64( define <vscale x 1 x i64> @intrinsic_vfclass_v_nxv1i64_nxv1f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i64_nxv1f64: ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i64> @intrinsic_vfclass_mask_v_nxv1i64_nxv1f64( define <vscale x 1 x i64> @intrinsic_vfclass_mask_v_nxv1i64_nxv1f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i64_nxv1f64: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: vfclass.v v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfclass_v_nxv2i64_nxv2f64( define <vscale x 2 x i64> @intrinsic_vfclass_v_nxv2i64_nxv2f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i64_nxv2f64: ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i64> @intrinsic_vfclass_mask_v_nxv2i64_nxv2f64( define <vscale x 2 x i64> @intrinsic_vfclass_mask_v_nxv2i64_nxv2f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i64_nxv2f64: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: vfclass.v v8, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfclass_v_nxv4i64_nxv4f64( define <vscale x 4 x i64> @intrinsic_vfclass_v_nxv4i64_nxv4f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i64_nxv4f64: ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i64> @intrinsic_vfclass_mask_v_nxv4i64_nxv4f64( define <vscale x 4 x i64> @intrinsic_vfclass_mask_v_nxv4i64_nxv4f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i64_nxv4f64: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: vfclass.v v8, v12, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfclass_v_nxv8i64_nxv8f64( define <vscale x 8 x i64> @intrinsic_vfclass_v_nxv8i64_nxv8f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i64_nxv8f64: ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) nounwind { iXLen %1) nounwind {
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i64> @intrinsic_vfclass_mask_v_nxv8i64_nxv8f64( define <vscale x 8 x i64> @intrinsic_vfclass_mask_v_nxv8i64_nxv8f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i64_nxv8f64: ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: vfclass.v v8, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) nounwind { iXLen %3) nounwind {
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) iXLen %3, iXLen 0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16(
<vscale x 1 x half> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16(
<vscale x 2 x half>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( %a = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16(
<vscale x 2 x half> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16(
<vscale x 4 x half>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( %a = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16(
<vscale x 4 x half> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16(
<vscale x 8 x half>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( %a = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16(
<vscale x 8 x half> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16(
<vscale x 16 x half>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( %a = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16(
<vscale x 16 x half> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16(
<vscale x 32 x half>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16(
<vscale x 32 x half> undef,
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 14 Lines %a = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16(
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32(
<vscale x 1 x float>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( %a = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32(
<vscale x 1 x float> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32(
<vscale x 2 x float>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( %a = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32(
<vscale x 2 x float> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32(
<vscale x 4 x float>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( %a = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32(
<vscale x 4 x float> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32(
<vscale x 8 x float>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( %a = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32(
<vscale x 8 x float> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 14 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32(
<vscale x 16 x float>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32(
<vscale x 16 x float> undef,
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 14 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64(
<vscale x 1 x double>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64( %a = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64(
<vscale x 1 x double> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 14 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64(
<vscale x 2 x double>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64( %a = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64(
<vscale x 2 x double> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 14 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64(
<vscale x 4 x double>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64( %a = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64(
<vscale x 4 x double> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 14 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64(
<vscale x 8 x double>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64: ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: vfcvt.f.x.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64( %a = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64(
<vscale x 8 x double> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16(
<vscale x 1 x half>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16(
<vscale x 1 x half> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16( declare <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16(
<vscale x 2 x half>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( %a = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16(
<vscale x 2 x half> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16( declare <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16(
<vscale x 4 x half>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( %a = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16(
<vscale x 4 x half> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16( declare <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16(
<vscale x 8 x half>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( %a = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16(
<vscale x 8 x half> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16( declare <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16(
<vscale x 16 x half>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( %a = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16(
<vscale x 16 x half> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16( declare <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16(
<vscale x 32 x half>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16(
<vscale x 32 x half> undef,
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16( declare <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 14 Lines %a = call <vscale x 32 x half> @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16(
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32(
<vscale x 1 x float>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( %a = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32(
<vscale x 1 x float> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32( declare <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32(
<vscale x 2 x float>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( %a = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32(
<vscale x 2 x float> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32( declare <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32(
<vscale x 4 x float>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( %a = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32(
<vscale x 4 x float> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32( declare <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32(
<vscale x 8 x float>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( %a = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32(
<vscale x 8 x float> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32( declare <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 14 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32(
<vscale x 16 x float>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32(
<vscale x 16 x float> undef,
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32( declare <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 14 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64(
<vscale x 1 x double>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64( %a = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64(
<vscale x 1 x double> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64( declare <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 14 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64(
<vscale x 2 x double>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64( %a = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64(
<vscale x 2 x double> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64( declare <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 14 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64(
<vscale x 4 x double>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64( %a = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64(
<vscale x 4 x double> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64( declare <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 14 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64(
<vscale x 8 x double>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64: ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64( %a = call <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64(
<vscale x 8 x double> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64( declare <vscale x 8 x double> @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16( %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16( %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16( %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16( %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16( %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 14 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32( %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32( %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32( %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32( %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32( %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64( %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64( %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64( %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64( %a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16( %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16( %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16( %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16( %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16( %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 14 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32( %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32( %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32( %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32( %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32( %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64( %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64( %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64( %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64: ; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64( %a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i16> @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i16> @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 14 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64( %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64( %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64( %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64: ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64( %a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x i16> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16( declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x i16> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16( declare <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x i16> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16( declare <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x i16> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16( declare <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x i16> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16( declare <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i16> @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i16> @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x i16> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16( declare <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 14 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x i32> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32( declare <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x i32> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32( declare <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x i32> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32( declare <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x i32> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32( declare <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x i32> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32( declare <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64( %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x i64> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64( declare <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64( %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x i64> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64( declare <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64( %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x i64> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64( declare <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64: ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64( %a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x i64> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64( declare <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v9, v8 ; CHECK-NEXT: vfncvt.f.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32(
<vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v9, v8 ; CHECK-NEXT: vfncvt.f.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32(
<vscale x 2 x half> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32(
<vscale x 4 x half>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v10, v8 ; CHECK-NEXT: vfncvt.f.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32(
<vscale x 4 x half> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32(
<vscale x 8 x half>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v12, v8 ; CHECK-NEXT: vfncvt.f.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32(
<vscale x 8 x half> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32(
<vscale x 16 x half>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v16, v8 ; CHECK-NEXT: vfncvt.f.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32(
<vscale x 16 x half> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64(
<vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v9, v8 ; CHECK-NEXT: vfncvt.f.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64(
<vscale x 1 x float> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64(
<vscale x 2 x float>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v10, v8 ; CHECK-NEXT: vfncvt.f.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64(
<vscale x 2 x float> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64(
<vscale x 4 x float>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v12, v8 ; CHECK-NEXT: vfncvt.f.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64(
<vscale x 4 x float> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64(
<vscale x 8 x float>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64: ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v16, v8 ; CHECK-NEXT: vfncvt.f.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64(
<vscale x 8 x float> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v9, v8 ; CHECK-NEXT: vfncvt.f.x.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32(
<vscale x 1 x half> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32(
<vscale x 2 x half>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v9, v8 ; CHECK-NEXT: vfncvt.f.x.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32(
<vscale x 2 x half> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32(
<vscale x 4 x half>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v10, v8 ; CHECK-NEXT: vfncvt.f.x.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32(
<vscale x 4 x half> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32(
<vscale x 8 x half>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v12, v8 ; CHECK-NEXT: vfncvt.f.x.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32(
<vscale x 8 x half> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32(
<vscale x 16 x half>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v16, v8 ; CHECK-NEXT: vfncvt.f.x.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32(
<vscale x 16 x half> undef,
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64(
<vscale x 1 x float>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v9, v8 ; CHECK-NEXT: vfncvt.f.x.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64( %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64(
<vscale x 1 x float> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64(
<vscale x 2 x float>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v10, v8 ; CHECK-NEXT: vfncvt.f.x.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64( %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64(
<vscale x 2 x float> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64(
<vscale x 4 x float>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v12, v8 ; CHECK-NEXT: vfncvt.f.x.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64( %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64(
<vscale x 4 x float> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64(
<vscale x 8 x float>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64: ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.f.x.w v16, v8 ; CHECK-NEXT: vfncvt.f.x.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64( %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64(
<vscale x 8 x float> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(
<vscale x 1 x half>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v9, v8 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(
<vscale x 1 x half> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32(
<vscale x 2 x half>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v9, v8 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32(
<vscale x 2 x half> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32(
<vscale x 4 x half>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v10, v8 ; CHECK-NEXT: vfncvt.f.xu.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32(
<vscale x 4 x half> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32(
<vscale x 8 x half>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v12, v8 ; CHECK-NEXT: vfncvt.f.xu.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32(
<vscale x 8 x half> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32(
<vscale x 16 x half>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v16, v8 ; CHECK-NEXT: vfncvt.f.xu.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32(
<vscale x 16 x half> undef,
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32(
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64(
<vscale x 1 x float>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v9, v8 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64( %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64(
<vscale x 1 x float> undef,
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64(
<vscale x 2 x float>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v10, v8 ; CHECK-NEXT: vfncvt.f.xu.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64( %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64(
<vscale x 2 x float> undef,
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64(
<vscale x 4 x float>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v12, v8 ; CHECK-NEXT: vfncvt.f.xu.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64( %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64(
<vscale x 4 x float> undef,
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64(
<vscale x 8 x float>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64: ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.f.xu.w v16, v8 ; CHECK-NEXT: vfncvt.f.xu.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64( %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64(
<vscale x 8 x float> undef,
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32( declare <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32(
<vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32( %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32(
<vscale x 2 x half> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32( declare <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32(
<vscale x 4 x half>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32( %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32(
<vscale x 4 x half> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f16.nxv4f32( declare <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f16.nxv4f32(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f16.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32(
<vscale x 8 x half>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32( %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32(
<vscale x 8 x half> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f16.nxv8f32( declare <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f16.nxv8f32(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f16.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32(
<vscale x 16 x half>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32( %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32(
<vscale x 16 x half> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16f16.nxv16f32( declare <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16f16.nxv16f32(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16f16.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64(
<vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64( %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64(
<vscale x 1 x float> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f32.nxv1f64( declare <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f32.nxv1f64(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f32.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64(
<vscale x 2 x float>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64( %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64(
<vscale x 2 x float> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f32.nxv2f64( declare <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f32.nxv2f64(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f32.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64(
<vscale x 4 x float>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64( %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64(
<vscale x 4 x float> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f32.nxv4f64( declare <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f32.nxv4f64(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f32.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64(
<vscale x 8 x float>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64: ; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8 ; CHECK-NEXT: vfncvt.rod.f.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64( %a = call <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64(
<vscale x 8 x float> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f32.nxv8f64( declare <vscale x 8 x float> @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f32.nxv8f64(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 14 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16( %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 14 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16( %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 14 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16( %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 14 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16( %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 14 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16( %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 14 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32( %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32( %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32( %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32( %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32( %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64( %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64( %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64( %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64( %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i32.nxv8f64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 14 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16( %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 14 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16( %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 14 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16( %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 14 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16( %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 14 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16( %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 14 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32( %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32( %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32( %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32( %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32( %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64( %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64( %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64( %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64: ; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64( %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i32.nxv8f64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 14 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i8> @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i8> @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 14 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i8> @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i8> @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 14 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i8> @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i8> @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.x.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 14 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i8> @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i8> @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.x.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 14 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i8> @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i8> @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.x.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 14 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.x.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.x.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.x.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: vfncvt.x.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v10, v8 ; CHECK-NEXT: vfncvt.x.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v12, v8 ; CHECK-NEXT: vfncvt.x.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64: ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.x.f.w v16, v8 ; CHECK-NEXT: vfncvt.x.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i8> @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16(
<vscale x 1 x i8> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16( declare <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 14 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i8> @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i8> @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16(
<vscale x 2 x i8> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16( declare <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 14 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i8> @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i8> @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16(
<vscale x 4 x i8> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16( declare <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 14 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i8> @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i8> @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16(
<vscale x 8 x i8> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16( declare <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 14 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i8> @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i8> @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16(
<vscale x 16 x i8> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16( declare <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 14 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8>,
<vscale x 32 x half>, <vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x i8> @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x i8> @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16(
<vscale x 32 x i8> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16( declare <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 14 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16(
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32(
<vscale x 1 x i16> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32( declare <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32(
<vscale x 2 x i16> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32( declare <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32(
<vscale x 4 x i16> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32( declare <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32(
<vscale x 8 x i16> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32( declare <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16>,
<vscale x 16 x float>, <vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32(
<vscale x 16 x i16> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32( declare <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32(
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64(
<vscale x 1 x i32> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64( declare <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v10, v8 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64(
<vscale x 2 x i32> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64( declare <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v12, v8 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64(
<vscale x 4 x i32> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64( declare <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32>,
<vscale x 8 x double>, <vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64: ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfncvt.xu.f.w v16, v8 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( %a = call <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64(
<vscale x 8 x i32> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64( declare <vscale x 8 x i32> @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfrec7.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfrec7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfrec7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfrec7.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfrec7.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfrec7.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfrec7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfrec7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfrec7.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfrec7.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfrec7.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfrec7.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfrec7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfrec7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfrec7.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfrec7.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfrec7.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfrec7.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfrec7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfrec7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfrec7.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfrec7.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfrec7.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfrec7.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfrec7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfrec7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfrec7.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfrec7.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfrec7.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfrec7.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfrec7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfrec7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfrec7.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfrec7.mask.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vfrec7.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 15 Lines %a = call <vscale x 32 x half> @llvm.riscv.vfrec7.mask.nxv32f16(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfrec7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfrec7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfrec7.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfrec7.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfrec7.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfrec7.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfrec7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfrec7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfrec7.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfrec7.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfrec7.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfrec7.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfrec7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfrec7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfrec7.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfrec7.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfrec7.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfrec7.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfrec7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfrec7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfrec7.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfrec7.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfrec7.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfrec7.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfrec7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfrec7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfrec7.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfrec7.mask.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vfrec7.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 15 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfrec7.mask.nxv16f32(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfrec7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfrec7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfrec7.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfrec7.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfrec7.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfrec7.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfrec7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfrec7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfrec7.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfrec7.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfrec7.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfrec7.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfrec7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfrec7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfrec7.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfrec7.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfrec7.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfrec7.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfrec7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfrec7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfrec7.v v8, v8 ; CHECK-NEXT: vfrec7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfrec7.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfrec7.mask.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vfrec7.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfrsqrt7.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfrsqrt7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfrsqrt7_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfrsqrt7.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfrsqrt7.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfrsqrt7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfrsqrt7_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfrsqrt7.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfrsqrt7.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfrsqrt7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfrsqrt7_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfrsqrt7.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfrsqrt7.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfrsqrt7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfrsqrt7_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfrsqrt7.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfrsqrt7.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfrsqrt7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfrsqrt7_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.mask.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vfrsqrt7.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 15 Lines %a = call <vscale x 32 x half> @llvm.riscv.vfrsqrt7.mask.nxv32f16(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfrsqrt7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfrsqrt7_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfrsqrt7.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfrsqrt7.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfrsqrt7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfrsqrt7_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfrsqrt7.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfrsqrt7.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfrsqrt7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfrsqrt7_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfrsqrt7.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfrsqrt7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfrsqrt7_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfrsqrt7.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfrsqrt7.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfrsqrt7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfrsqrt7_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.mask.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vfrsqrt7.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 15 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfrsqrt7.mask.nxv16f32(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfrsqrt7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfrsqrt7_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfrsqrt7.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfrsqrt7.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfrsqrt7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfrsqrt7_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfrsqrt7.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfrsqrt7.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfrsqrt7.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfrsqrt7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfrsqrt7_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfrsqrt7.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfrsqrt7.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfrsqrt7.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfrsqrt7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfrsqrt7_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfrsqrt7.v v8, v8 ; CHECK-NEXT: vfrsqrt7.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfrsqrt7.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfrsqrt7.mask.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vfrsqrt7.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
<vscale x 1 x half> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 15 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfsqrt_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfsqrt_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
<vscale x 2 x half> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 15 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfsqrt_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfsqrt_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
<vscale x 4 x half> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 15 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfsqrt_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfsqrt_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
<vscale x 8 x half> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 15 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfsqrt_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfsqrt_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
<vscale x 16 x half> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 15 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfsqrt_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfsqrt_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
<vscale x 32 x half> undef,
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16( declare <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 15 Lines %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfsqrt_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfsqrt_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
<vscale x 1 x float> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 15 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfsqrt_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfsqrt_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
<vscale x 2 x float> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 15 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfsqrt_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfsqrt_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
<vscale x 4 x float> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 15 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfsqrt_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfsqrt_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
<vscale x 8 x float> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 15 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfsqrt_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfsqrt_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
<vscale x 16 x float> undef,
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32( declare <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 15 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfsqrt_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfsqrt_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
<vscale x 1 x double> undef,
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 15 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfsqrt_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfsqrt_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
<vscale x 2 x double> undef,
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 15 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfsqrt_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfsqrt_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
<vscale x 4 x double> undef,
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 15 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfsqrt_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfsqrt_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
<vscale x 8 x double> undef,
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64( declare <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
<vscale x 1 x float> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16(
<vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16(
<vscale x 2 x float> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16(
<vscale x 4 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16(
<vscale x 4 x float> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16( declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16(
<vscale x 8 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vfwcvt.f.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16(
<vscale x 8 x float> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16( declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 14 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16(
<vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16(
<vscale x 16 x float> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16( declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 14 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32(
<vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32(
<vscale x 1 x double> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 14 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32(
<vscale x 2 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32(
<vscale x 2 x double> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32( declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 14 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32(
<vscale x 4 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v12, v8 ; CHECK-NEXT: vfwcvt.f.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32(
<vscale x 4 x double> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32( declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 14 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32(
<vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.f.v v16, v8 ; CHECK-NEXT: vfwcvt.f.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32(
<vscale x 8 x double> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32( declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8(
<vscale x 1 x half> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8(
<vscale x 2 x half>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8(<vscale x 2 x i8> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8( %a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8(
<vscale x 2 x half> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8(
<vscale x 4 x half>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8(<vscale x 4 x i8> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8( %a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8(
<vscale x 4 x half> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8(
<vscale x 8 x half>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8(<vscale x 8 x i8> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v10, v8 ; CHECK-NEXT: vfwcvt.f.x.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8( %a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8(
<vscale x 8 x half> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8(
<vscale x 16 x half>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8(<vscale x 16 x i8> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v12, v8 ; CHECK-NEXT: vfwcvt.f.x.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8( %a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8(
<vscale x 16 x half> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8(
<vscale x 32 x half>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8(<vscale x 32 x i8> %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v16, v8 ; CHECK-NEXT: vfwcvt.f.x.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8( %a = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8(
<vscale x 32 x half> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 14 Lines %a = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16(
<vscale x 1 x float>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16( %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16(
<vscale x 1 x float> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16(
<vscale x 2 x float>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16( %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16(
<vscale x 2 x float> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16(
<vscale x 4 x float>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v10, v8 ; CHECK-NEXT: vfwcvt.f.x.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16( %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16(
<vscale x 4 x float> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16(
<vscale x 8 x float>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v12, v8 ; CHECK-NEXT: vfwcvt.f.x.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16( %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16(
<vscale x 8 x float> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 14 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16(
<vscale x 16 x float>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v16, v8 ; CHECK-NEXT: vfwcvt.f.x.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16(
<vscale x 16 x float> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 14 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32(
<vscale x 1 x double>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32( %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32(
<vscale x 1 x double> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 14 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32(
<vscale x 2 x double>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v10, v8 ; CHECK-NEXT: vfwcvt.f.x.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32( %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32(
<vscale x 2 x double> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 14 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32(
<vscale x 4 x double>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v12, v8 ; CHECK-NEXT: vfwcvt.f.x.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32( %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32(
<vscale x 4 x double> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 14 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32(
<vscale x 8 x double>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.x.v v16, v8 ; CHECK-NEXT: vfwcvt.f.x.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32( %a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32(
<vscale x 8 x double> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8(
<vscale x 1 x half>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
iXLen); iXLen);
define <vscale x 1 x half> @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind { define <vscale x 1 x half> @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8(
<vscale x 1 x half> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8( declare <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8(
<vscale x 1 x half>, <vscale x 1 x half>,
Show All 14 Lines %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8(
<vscale x 2 x half>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
iXLen); iXLen);
define <vscale x 2 x half> @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8(<vscale x 2 x i8> %0, iXLen %1) nounwind { define <vscale x 2 x half> @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8( %a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8(
<vscale x 2 x half> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8( declare <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8(
<vscale x 2 x half>, <vscale x 2 x half>,
Show All 14 Lines %a = call <vscale x 2 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8(
<vscale x 4 x half>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
iXLen); iXLen);
define <vscale x 4 x half> @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8(<vscale x 4 x i8> %0, iXLen %1) nounwind { define <vscale x 4 x half> @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8( %a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8(
<vscale x 4 x half> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8( declare <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8(
<vscale x 4 x half>, <vscale x 4 x half>,
Show All 14 Lines %a = call <vscale x 4 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8(
<vscale x 8 x half>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
iXLen); iXLen);
define <vscale x 8 x half> @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8(<vscale x 8 x i8> %0, iXLen %1) nounwind { define <vscale x 8 x half> @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8( %a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8(
<vscale x 8 x half> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8( declare <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8(
<vscale x 8 x half>, <vscale x 8 x half>,
Show All 14 Lines %a = call <vscale x 8 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8(
<vscale x 16 x half>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
iXLen); iXLen);
define <vscale x 16 x half> @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8(<vscale x 16 x i8> %0, iXLen %1) nounwind { define <vscale x 16 x half> @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8( %a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8(
<vscale x 16 x half> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8( declare <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8(
<vscale x 16 x half>, <vscale x 16 x half>,
Show All 14 Lines %a = call <vscale x 16 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8(
<vscale x 32 x half>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
iXLen); iXLen);
define <vscale x 32 x half> @intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8(<vscale x 32 x i8> %0, iXLen %1) nounwind { define <vscale x 32 x half> @intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8( %a = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8(
<vscale x 32 x half> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8( declare <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8(
<vscale x 32 x half>, <vscale x 32 x half>,
Show All 14 Lines %a = call <vscale x 32 x half> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16(
<vscale x 1 x float>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
iXLen); iXLen);
define <vscale x 1 x float> @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind { define <vscale x 1 x float> @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16( %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16(
<vscale x 1 x float> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16( declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16(
<vscale x 1 x float>, <vscale x 1 x float>,
Show All 14 Lines %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16(
<vscale x 2 x float>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
iXLen); iXLen);
define <vscale x 2 x float> @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind { define <vscale x 2 x float> @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16( %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16(
<vscale x 2 x float> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16( declare <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16(
<vscale x 2 x float>, <vscale x 2 x float>,
Show All 14 Lines %a = call <vscale x 2 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16(
<vscale x 4 x float>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
iXLen); iXLen);
define <vscale x 4 x float> @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind { define <vscale x 4 x float> @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16( %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16(
<vscale x 4 x float> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16( declare <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16(
<vscale x 4 x float>, <vscale x 4 x float>,
Show All 14 Lines %a = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16(
<vscale x 8 x float>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
iXLen); iXLen);
define <vscale x 8 x float> @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind { define <vscale x 8 x float> @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16( %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16(
<vscale x 8 x float> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16( declare <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16(
<vscale x 8 x float>, <vscale x 8 x float>,
Show All 14 Lines %a = call <vscale x 8 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16(
<vscale x 16 x float>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
iXLen); iXLen);
define <vscale x 16 x float> @intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind { define <vscale x 16 x float> @intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16(
<vscale x 16 x float> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16( declare <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16(
<vscale x 16 x float>, <vscale x 16 x float>,
Show All 14 Lines %a = call <vscale x 16 x float> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32(
<vscale x 1 x double>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
iXLen); iXLen);
define <vscale x 1 x double> @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind { define <vscale x 1 x double> @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32( %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32(
<vscale x 1 x double> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32( declare <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32(
<vscale x 1 x double>, <vscale x 1 x double>,
Show All 14 Lines %a = call <vscale x 1 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32(
<vscale x 2 x double>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
iXLen); iXLen);
define <vscale x 2 x double> @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind { define <vscale x 2 x double> @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32( %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32(
<vscale x 2 x double> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32( declare <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32(
<vscale x 2 x double>, <vscale x 2 x double>,
Show All 14 Lines %a = call <vscale x 2 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32(
<vscale x 4 x double>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
iXLen); iXLen);
define <vscale x 4 x double> @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind { define <vscale x 4 x double> @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32( %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32(
<vscale x 4 x double> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32( declare <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32(
<vscale x 4 x double>, <vscale x 4 x double>,
Show All 14 Lines %a = call <vscale x 4 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32(
<vscale x 8 x double>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
iXLen); iXLen);
define <vscale x 8 x double> @intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind { define <vscale x 8 x double> @intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32: ; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32( %a = call <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32(
<vscale x 8 x double> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32( declare <vscale x 8 x double> @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32(
<vscale x 8 x double>, <vscale x 8 x double>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16( %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16( %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16( %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16( %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32( %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32( %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32( %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfwcvt_rtz.x.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.rtz.x.f.v v16, v8 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32( %a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i64.nxv8f32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16( %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16( %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16( %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v16, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16( %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32( %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32( %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32( %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v16, v8 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32( %a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v10, v8 ; CHECK-NEXT: vfwcvt.x.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v12, v8 ; CHECK-NEXT: vfwcvt.x.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v16, v8 ; CHECK-NEXT: vfwcvt.x.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16( %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v9, v8 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32( %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v10, v8 ; CHECK-NEXT: vfwcvt.x.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32( %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v12, v8 ; CHECK-NEXT: vfwcvt.x.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32( %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.x.f.v v16, v8 ; CHECK-NEXT: vfwcvt.x.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32( %a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16(
<vscale x 1 x i32> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16( declare <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16(
<vscale x 2 x i32> undef,
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16( declare <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16(
<vscale x 4 x i32> undef,
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16( declare <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v12, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16(
<vscale x 8 x i32> undef,
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16( declare <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16( %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16(
<vscale x 16 x i32> undef,
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16( declare <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32( %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32(
<vscale x 1 x i64> undef,
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32( declare <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32( %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32(
<vscale x 2 x i64> undef,
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32( declare <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v12, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v12, v8
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32( %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32(
<vscale x 4 x i64> undef,
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32( declare <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3, iXLen 1) iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 ; CHECK-NEXT: vfwcvt.xu.f.v v16, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32( %a = call <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32(
<vscale x 8 x i64> undef,
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32( declare <vscale x 8 x i64> @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vid.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
<vscale x 1 x i8>,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(iXLen %0) nounwind { define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i8: ; CHECK-LABEL: intrinsic_vid_v_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
<vscale x 1 x i8> undef,
iXLen %0) iXLen %0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
Show All 10 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
<vscale x 2 x i8>,
iXLen); iXLen);
define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(iXLen %0) nounwind { define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i8: ; CHECK-LABEL: intrinsic_vid_v_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
<vscale x 2 x i8> undef,
iXLen %0) iXLen %0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
Show All 10 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
<vscale x 4 x i8>,
iXLen); iXLen);
define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(iXLen %0) nounwind { define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i8: ; CHECK-LABEL: intrinsic_vid_v_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
<vscale x 4 x i8> undef,
iXLen %0) iXLen %0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
Show All 10 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
<vscale x 8 x i8>,
iXLen); iXLen);
define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(iXLen %0) nounwind { define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i8: ; CHECK-LABEL: intrinsic_vid_v_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
<vscale x 8 x i8> undef,
iXLen %0) iXLen %0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
Show All 10 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
<vscale x 16 x i8>,
iXLen); iXLen);
define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(iXLen %0) nounwind { define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i8: ; CHECK-LABEL: intrinsic_vid_v_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
<vscale x 16 x i8> undef,
iXLen %0) iXLen %0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
Show All 10 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
<vscale x 32 x i8>,
iXLen); iXLen);
define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(iXLen %0) nounwind { define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv32i8: ; CHECK-LABEL: intrinsic_vid_v_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
<vscale x 32 x i8> undef,
iXLen %0) iXLen %0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
Show All 10 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
<vscale x 1 x i16>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(iXLen %0) nounwind { define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i16: ; CHECK-LABEL: intrinsic_vid_v_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
<vscale x 1 x i16> undef,
iXLen %0) iXLen %0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
Show All 10 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
<vscale x 2 x i16>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(iXLen %0) nounwind { define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i16: ; CHECK-LABEL: intrinsic_vid_v_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
<vscale x 2 x i16> undef,
iXLen %0) iXLen %0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
Show All 10 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
<vscale x 4 x i16>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(iXLen %0) nounwind { define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i16: ; CHECK-LABEL: intrinsic_vid_v_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
<vscale x 4 x i16> undef,
iXLen %0) iXLen %0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
Show All 10 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
<vscale x 8 x i16>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(iXLen %0) nounwind { define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i16: ; CHECK-LABEL: intrinsic_vid_v_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
<vscale x 8 x i16> undef,
iXLen %0) iXLen %0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
Show All 10 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
<vscale x 16 x i16>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(iXLen %0) nounwind { define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i16: ; CHECK-LABEL: intrinsic_vid_v_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
<vscale x 16 x i16> undef,
iXLen %0) iXLen %0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
Show All 10 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
<vscale x 32 x i16>,
iXLen); iXLen);
define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(iXLen %0) nounwind { define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv32i16: ; CHECK-LABEL: intrinsic_vid_v_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
<vscale x 32 x i16> undef,
iXLen %0) iXLen %0)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
Show All 10 Lines %a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
<vscale x 1 x i32>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(iXLen %0) nounwind { define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i32: ; CHECK-LABEL: intrinsic_vid_v_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
<vscale x 1 x i32> undef,
iXLen %0) iXLen %0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
Show All 10 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
<vscale x 2 x i32>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(iXLen %0) nounwind { define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i32: ; CHECK-LABEL: intrinsic_vid_v_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
<vscale x 2 x i32> undef,
iXLen %0) iXLen %0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
Show All 10 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
<vscale x 4 x i32>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(iXLen %0) nounwind { define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i32: ; CHECK-LABEL: intrinsic_vid_v_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
<vscale x 4 x i32> undef,
iXLen %0) iXLen %0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
Show All 10 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
<vscale x 8 x i32>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(iXLen %0) nounwind { define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i32: ; CHECK-LABEL: intrinsic_vid_v_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
<vscale x 8 x i32> undef,
iXLen %0) iXLen %0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
Show All 10 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
<vscale x 16 x i32>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(iXLen %0) nounwind { define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv16i32: ; CHECK-LABEL: intrinsic_vid_v_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
<vscale x 16 x i32> undef,
iXLen %0) iXLen %0)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
Show All 10 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
<vscale x 1 x i64>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_vid_v_nxv1i64(iXLen %0) nounwind { define <vscale x 1 x i64> @intrinsic_vid_v_nxv1i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv1i64: ; CHECK-LABEL: intrinsic_vid_v_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
<vscale x 1 x i64> undef,
iXLen %0) iXLen %0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
Show All 10 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
<vscale x 2 x i64>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_vid_v_nxv2i64(iXLen %0) nounwind { define <vscale x 2 x i64> @intrinsic_vid_v_nxv2i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv2i64: ; CHECK-LABEL: intrinsic_vid_v_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
<vscale x 2 x i64> undef,
iXLen %0) iXLen %0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
Show All 10 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
<vscale x 4 x i64>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_vid_v_nxv4i64(iXLen %0) nounwind { define <vscale x 4 x i64> @intrinsic_vid_v_nxv4i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv4i64: ; CHECK-LABEL: intrinsic_vid_v_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
<vscale x 4 x i64> undef,
iXLen %0) iXLen %0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
Show All 10 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
<vscale x 8 x i64>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_vid_v_nxv8i64(iXLen %0) nounwind { define <vscale x 8 x i64> @intrinsic_vid_v_nxv8i64(iXLen %0) nounwind {
; CHECK-LABEL: intrinsic_vid_v_nxv8i64: ; CHECK-LABEL: intrinsic_vid_v_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
<vscale x 8 x i64> undef,
iXLen %0) iXLen %0)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
Show All 16 Lines

llvm/test/CodeGen/RISCV/rvv/viota.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind { define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
Show All 13 Lines %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
<vscale x 2 x i8> undef,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
Show All 13 Lines %a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen);
define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
<vscale x 4 x i8> undef,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
Show All 13 Lines %a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen);
define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
<vscale x 8 x i8> undef,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
Show All 13 Lines %a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen);
define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind { define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1: ; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
<vscale x 16 x i8> undef,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
Show All 13 Lines %a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen);
define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind { define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1: ; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
<vscale x 32 x i8> undef,
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
Show All 13 Lines %a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
iXLen); iXLen);
define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind { define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1: ; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
<vscale x 64 x i8> undef,
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
Show All 13 Lines %a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen);
define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind { define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
<vscale x 1 x i16> undef,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 13 Lines %a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
<vscale x 2 x i16> undef,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 13 Lines %a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen);
define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
<vscale x 4 x i16> undef,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 13 Lines %a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen);
define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
<vscale x 8 x i16> undef,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 13 Lines %a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen);
define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind { define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1: ; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
<vscale x 16 x i16> undef,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 13 Lines %a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen);
define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind { define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1: ; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
<vscale x 32 x i16> undef,
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16( declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 13 Lines %a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen);
define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind { define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
<vscale x 1 x i32> undef,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 13 Lines %a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
<vscale x 2 x i32> undef,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 13 Lines %a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen);
define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 13 Lines %a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen);
define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 13 Lines %a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen);
define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind { define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1: ; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32( declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 13 Lines %a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen);
define <vscale x 1 x i64> @intrinsic_viota_m_nxv1i64_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_viota_m_nxv1i64_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1: ; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 13 Lines %a = call <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define <vscale x 2 x i64> @intrinsic_viota_m_nxv2i64_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define <vscale x 2 x i64> @intrinsic_viota_m_nxv2i64_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1: ; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 13 Lines %a = call <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen);
define <vscale x 4 x i64> @intrinsic_viota_m_nxv4i64_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { define <vscale x 4 x i64> @intrinsic_viota_m_nxv4i64_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1: ; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 13 Lines %a = call <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
iXLen %2) iXLen %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen);
define <vscale x 8 x i64> @intrinsic_viota_m_nxv8i64_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { define <vscale x 8 x i64> @intrinsic_viota_m_nxv8i64_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1: ; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: viota.m v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64( declare <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 19 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Show All 28 Lines--- |
define void @load_zext_or_sext(i8 zeroext %cond, <vscale x 1 x i32>* %0, <vscale x 1 x i64>* %1, i64 %2) #0 { define void @load_zext_or_sext(i8 zeroext %cond, <vscale x 1 x i32>* %0, <vscale x 1 x i64>* %1, i64 %2) #0 {
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* %0, i64 %2) %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* %0, i64 %2)
%tobool = icmp eq i8 %cond, 0 %tobool = icmp eq i8 %cond, 0
br i1 %tobool, label %if.else, label %if.then br i1 %tobool, label %if.else, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %2) %b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %2)
br label %if.end br label %if.end
if.else: ; preds = %entry if.else: ; preds = %entry
%c = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %2) %c = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %2)
br label %if.end br label %if.end
if.end: ; preds = %if.else, %if.then if.end: ; preds = %if.else, %if.then
%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ] %d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> %d, <vscale x 1 x i64>* %1, i64 %2) call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> %d, <vscale x 1 x i64>* %1, i64 %2)
ret void ret void
} }
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines--- |
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #3 declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #3
; Function Attrs: nounwind writeonly ; Function Attrs: nounwind writeonly
declare void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4 declare void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
attributes #0 = { "target-features"="+v" } attributes #0 = { "target-features"="+v" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind } attributes #2 = { nounwind }
attributes #3 = { nounwind readonly } attributes #3 = { nounwind readonly }
attributes #4 = { nounwind writeonly } attributes #4 = { nounwind writeonly }
... ...
▲ Show 20 Lines • Show All 583 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

Show All 18 Lines entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %0, i64 %2) %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64>* %0, i64 %2)
%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2) %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
define <vscale x 1 x i64> @load_zext(<vscale x 1 x i32>* %0, i64 %1) #0 { define <vscale x 1 x i64> @load_zext(<vscale x 1 x i32>* %0, i64 %1) #0 {
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* %0, i64 %1) %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* %0, i64 %1)
%b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %1) %b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %1)
ret <vscale x 1 x i64> %b ret <vscale x 1 x i64> %b
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1 declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1
define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 { define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 {
entry: entry:
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines--- |
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4 declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #4 declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #4
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1 declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
attributes #0 = { "target-features"="+v" } attributes #0 = { "target-features"="+v" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nofree nosync nounwind readnone willreturn } attributes #2 = { nofree nosync nounwind readnone willreturn }
attributes #3 = { nounwind } attributes #3 = { nounwind }
attributes #4 = { nounwind readonly } attributes #4 = { nounwind readonly }
... ...
▲ Show 20 Lines • Show All 315 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vsext.vf8 v9, v8 ; CHECK-NEXT: vsext.vf8 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsext_vf8_nxv2i64(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsext_vf8_nxv2i64(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vsext.vf8 v10, v8 ; CHECK-NEXT: vsext.vf8 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsext_vf8_nxv4i64(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsext_vf8_nxv4i64(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vsext.vf8 v12, v8 ; CHECK-NEXT: vsext.vf8 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsext_vf8_nxv8i64(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsext_vf8_nxv8i64(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv8i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vsext.vf8 v16, v8 ; CHECK-NEXT: vsext.vf8 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vsext_vf4_nxv1i64(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsext_vf4_nxv1i64(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vsext.vf4 v9, v8 ; CHECK-NEXT: vsext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vsext_vf4_nxv2i64(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsext_vf4_nxv2i64(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vsext.vf4 v10, v8 ; CHECK-NEXT: vsext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vsext_vf4_nxv4i64(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsext_vf4_nxv4i64(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vsext.vf4 v12, v8 ; CHECK-NEXT: vsext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vsext_vf4_nxv8i64(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsext_vf4_nxv8i64(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vsext.vf4 v16, v8 ; CHECK-NEXT: vsext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsext_vf4_nxv1i32(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsext_vf4_nxv1i32(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vsext.vf4 v9, v8 ; CHECK-NEXT: vsext.vf4 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsext_vf4_nxv2i32(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsext_vf4_nxv2i32(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vsext.vf4 v9, v8 ; CHECK-NEXT: vsext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsext_vf4_nxv4i32(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsext_vf4_nxv4i32(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vsext.vf4 v10, v8 ; CHECK-NEXT: vsext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsext_vf4_nxv8i32(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsext_vf4_nxv8i32(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vsext.vf4 v12, v8 ; CHECK-NEXT: vsext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsext_vf4_nxv16i32(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsext_vf4_nxv16i32(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv16i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vsext.vf4 v16, v8 ; CHECK-NEXT: vsext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vsext_vf2_nxv1i32(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsext_vf2_nxv1i32(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vsext_vf2_nxv2i32(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsext_vf2_nxv2i32(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vsext_vf2_nxv4i32(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsext_vf2_nxv4i32(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vsext_vf2_nxv8i32(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsext_vf2_nxv8i32(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vsext.vf2 v12, v8 ; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsext_vf2_nxv16i32(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsext_vf2_nxv16i32(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vsext.vf2 v16, v8 ; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vsext_vf2_nxv1i16(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsext_vf2_nxv1i16(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsext.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vsext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vsext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vsext_vf2_nxv2i16(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsext_vf2_nxv2i16(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsext.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vsext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vsext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vsext_vf2_nxv4i16(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsext_vf2_nxv4i16(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsext.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vsext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vsext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vsext_vf2_nxv8i16(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsext_vf2_nxv8i16(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vsext_vf2_nxv16i16(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsext_vf2_nxv16i16(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vsext.vf2 v12, v8 ; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsext.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vsext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vsext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsext_vf2_nxv32i16(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsext_vf2_nxv32i16(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv32i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vsext.vf2 v16, v8 ; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsext.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vsext.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vsext.vf8 v9, v8 ; CHECK-NEXT: vsext.vf8 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsext_vf8_nxv2i64(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsext_vf8_nxv2i64(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vsext.vf8 v10, v8 ; CHECK-NEXT: vsext.vf8 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsext_vf8_nxv4i64(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsext_vf8_nxv4i64(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vsext.vf8 v12, v8 ; CHECK-NEXT: vsext.vf8 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsext_vf8_nxv8i64(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsext_vf8_nxv8i64(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf8_nxv8i64: ; CHECK-LABEL: intrinsic_vsext_vf8_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vsext.vf8 v16, v8 ; CHECK-NEXT: vsext.vf8 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsext_vf4_nxv1i64(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsext_vf4_nxv1i64(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vsext.vf4 v9, v8 ; CHECK-NEXT: vsext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsext_vf4_nxv2i64(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsext_vf4_nxv2i64(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vsext.vf4 v10, v8 ; CHECK-NEXT: vsext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsext_vf4_nxv4i64(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsext_vf4_nxv4i64(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vsext.vf4 v12, v8 ; CHECK-NEXT: vsext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsext_vf4_nxv8i64(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsext_vf4_nxv8i64(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i64: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vsext.vf4 v16, v8 ; CHECK-NEXT: vsext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsext_vf4_nxv1i32(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsext_vf4_nxv1i32(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vsext.vf4 v9, v8 ; CHECK-NEXT: vsext.vf4 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsext_vf4_nxv2i32(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsext_vf4_nxv2i32(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vsext.vf4 v9, v8 ; CHECK-NEXT: vsext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsext_vf4_nxv4i32(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsext_vf4_nxv4i32(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vsext.vf4 v10, v8 ; CHECK-NEXT: vsext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsext_vf4_nxv8i32(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsext_vf4_nxv8i32(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vsext.vf4 v12, v8 ; CHECK-NEXT: vsext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsext_vf4_nxv16i32(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsext_vf4_nxv16i32(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf4_nxv16i32: ; CHECK-LABEL: intrinsic_vsext_vf4_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vsext.vf4 v16, v8 ; CHECK-NEXT: vsext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32(
<vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vsext_vf2_nxv1i64(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vsext_vf2_nxv1i64(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i64: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vsext_vf2_nxv2i64(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vsext_vf2_nxv2i64(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i64: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32(
<vscale x 2 x i64> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vsext_vf2_nxv4i64(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vsext_vf2_nxv4i64(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i64: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vsext.vf2 v12, v8 ; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32(
<vscale x 4 x i64> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsext_vf2_nxv8i64(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vsext_vf2_nxv8i64(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i64: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vsext.vf2 v16, v8 ; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32(
<vscale x 8 x i64> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vsext_vf2_nxv1i32(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vsext_vf2_nxv1i32(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vsext_vf2_nxv2i32(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vsext_vf2_nxv2i32(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vsext_vf2_nxv4i32(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vsext_vf2_nxv4i32(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vsext_vf2_nxv8i32(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vsext_vf2_nxv8i32(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vsext.vf2 v12, v8 ; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsext_vf2_nxv16i32(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vsext_vf2_nxv16i32(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i32: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vsext.vf2 v16, v8 ; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vsext_vf2_nxv1i16(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vsext_vf2_nxv1i16(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vsext.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vsext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vsext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vsext_vf2_nxv2i16(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vsext_vf2_nxv2i16(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vsext.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vsext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vsext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vsext_vf2_nxv4i16(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vsext_vf2_nxv4i16(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vsext.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vsext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vsext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vsext_vf2_nxv8i16(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vsext_vf2_nxv8i16(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vsext_vf2_nxv16i16(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vsext_vf2_nxv16i16(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vsext.vf2 v12, v8 ; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vsext.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vsext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vsext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsext_vf2_nxv32i16(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vsext_vf2_nxv32i16(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsext_vf2_nxv32i16: ; CHECK-LABEL: intrinsic_vsext_vf2_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vsext.vf2 v16, v8 ; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vsext.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vsext.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vzext.vf8 v9, v8 ; CHECK-NEXT: vzext.vf8 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vzext_vf8_nxv2i64(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vzext_vf8_nxv2i64(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzext.vf8 v10, v8 ; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vzext_vf8_nxv4i64(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vzext_vf8_nxv4i64(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzext.vf8 v12, v8 ; CHECK-NEXT: vzext.vf8 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vzext_vf8_nxv8i64(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vzext_vf8_nxv8i64(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv8i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzext.vf8 v16, v8 ; CHECK-NEXT: vzext.vf8 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vzext_vf4_nxv1i64(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vzext_vf4_nxv1i64(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vzext.vf4 v9, v8 ; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vzext_vf4_nxv2i64(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vzext_vf4_nxv2i64(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzext.vf4 v10, v8 ; CHECK-NEXT: vzext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vzext_vf4_nxv4i64(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vzext_vf4_nxv4i64(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzext.vf4 v12, v8 ; CHECK-NEXT: vzext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vzext_vf4_nxv8i64(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vzext_vf4_nxv8i64(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzext.vf4 v16, v8 ; CHECK-NEXT: vzext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vzext_vf4_nxv1i32(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vzext_vf4_nxv1i32(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vzext.vf4 v9, v8 ; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vzext_vf4_nxv2i32(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vzext_vf4_nxv2i32(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vzext.vf4 v9, v8 ; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vzext_vf4_nxv4i32(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vzext_vf4_nxv4i32(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vzext.vf4 v10, v8 ; CHECK-NEXT: vzext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vzext_vf4_nxv8i32(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vzext_vf4_nxv8i32(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vzext.vf4 v12, v8 ; CHECK-NEXT: vzext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vzext_vf4_nxv16i32(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vzext_vf4_nxv16i32(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv16i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vzext.vf4 v16, v8 ; CHECK-NEXT: vzext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32(
<vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vzext_vf2_nxv1i64(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vzext_vf2_nxv1i64(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vzext_vf2_nxv2i64(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vzext_vf2_nxv2i64(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32(
<vscale x 2 x i64> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vzext_vf2_nxv4i64(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vzext_vf2_nxv4i64(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzext.vf2 v12, v8 ; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32(
<vscale x 4 x i64> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vzext_vf2_nxv8i64(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vzext_vf2_nxv8i64(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzext.vf2 v16, v8 ; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32(
<vscale x 8 x i64> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vzext_vf2_nxv1i32(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vzext_vf2_nxv1i32(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vzext_vf2_nxv2i32(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vzext_vf2_nxv2i32(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vzext_vf2_nxv4i32(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vzext_vf2_nxv4i32(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vzext_vf2_nxv8i32(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vzext_vf2_nxv8i32(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vzext.vf2 v12, v8 ; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vzext_vf2_nxv16i32(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vzext_vf2_nxv16i32(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vzext.vf2 v16, v8 ; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vzext_vf2_nxv1i16(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vzext_vf2_nxv1i16(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vzext_vf2_nxv2i16(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vzext_vf2_nxv2i16(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vzext_vf2_nxv4i16(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vzext_vf2_nxv4i16(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vzext_vf2_nxv8i16(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vzext_vf2_nxv8i16(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vzext_vf2_nxv16i16(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vzext_vf2_nxv16i16(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vzext.vf2 v12, v8 ; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vzext_vf2_nxv32i16(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vzext_vf2_nxv32i16(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv32i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vzext.vf2 v16, v8 ; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i32 %1) i32 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vzext.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vzext.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
<vscale x 1 x i64>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vzext.vf8 v9, v8 ; CHECK-NEXT: vzext.vf8 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8( %a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(
<vscale x 1 x i64> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8( declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8(
<vscale x 2 x i64>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vzext_vf8_nxv2i64(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vzext_vf8_nxv2i64(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzext.vf8 v10, v8 ; CHECK-NEXT: vzext.vf8 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8( %a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i8(
<vscale x 2 x i64> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8( declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8(
<vscale x 4 x i64>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vzext_vf8_nxv4i64(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vzext_vf8_nxv4i64(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzext.vf8 v12, v8 ; CHECK-NEXT: vzext.vf8 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8( %a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i8(
<vscale x 4 x i64> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8( declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8(
<vscale x 8 x i64>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vzext_vf8_nxv8i64(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vzext_vf8_nxv8i64(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf8_nxv8i64: ; CHECK-LABEL: intrinsic_vzext_vf8_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzext.vf8 v16, v8 ; CHECK-NEXT: vzext.vf8 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8( %a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i8(
<vscale x 8 x i64> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8( declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16(
<vscale x 1 x i64>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vzext_vf4_nxv1i64(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vzext_vf4_nxv1i64(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vzext.vf4 v9, v8 ; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16( %a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i16(
<vscale x 1 x i64> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16( declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16(
<vscale x 2 x i64>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vzext_vf4_nxv2i64(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vzext_vf4_nxv2i64(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzext.vf4 v10, v8 ; CHECK-NEXT: vzext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16( %a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i16(
<vscale x 2 x i64> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i16( declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16(
<vscale x 4 x i64>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vzext_vf4_nxv4i64(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vzext_vf4_nxv4i64(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzext.vf4 v12, v8 ; CHECK-NEXT: vzext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16( %a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i16(
<vscale x 4 x i64> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i16( declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16(
<vscale x 8 x i64>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vzext_vf4_nxv8i64(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vzext_vf4_nxv8i64(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i64: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzext.vf4 v16, v8 ; CHECK-NEXT: vzext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i16(
<vscale x 8 x i64> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i16( declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8(
<vscale x 1 x i32>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vzext_vf4_nxv1i32(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vzext_vf4_nxv1i32(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vzext.vf4 v9, v8 ; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8( %a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i8(
<vscale x 1 x i32> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8( declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8(
<vscale x 2 x i32>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vzext_vf4_nxv2i32(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vzext_vf4_nxv2i32(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vzext.vf4 v9, v8 ; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8( %a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i8(
<vscale x 2 x i32> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8( declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8(
<vscale x 4 x i32>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vzext_vf4_nxv4i32(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vzext_vf4_nxv4i32(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vzext.vf4 v10, v8 ; CHECK-NEXT: vzext.vf4 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8( %a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i8(
<vscale x 4 x i32> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8( declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vzext_vf4_nxv8i32(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vzext_vf4_nxv8i32(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vzext.vf4 v12, v8 ; CHECK-NEXT: vzext.vf4 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8( %a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i8(
<vscale x 8 x i32> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i8( declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8(
<vscale x 16 x i32>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vzext_vf4_nxv16i32(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vzext_vf4_nxv16i32(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf4_nxv16i32: ; CHECK-LABEL: intrinsic_vzext_vf4_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vzext.vf4 v16, v8 ; CHECK-NEXT: vzext.vf4 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8( %a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i8(
<vscale x 16 x i32> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i8( declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32(
<vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vzext_vf2_nxv1i64(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i64> @intrinsic_vzext_vf2_nxv1i64(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
Show All 14 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vzext.mask.nxv1i64.nxv1i32(
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32(
<vscale x 2 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vzext_vf2_nxv2i64(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i64> @intrinsic_vzext_vf2_nxv2i64(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32( %a = call <vscale x 2 x i64> @llvm.riscv.vzext.nxv2i64.nxv2i32(
<vscale x 2 x i64> undef,
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32( declare <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
Show All 14 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vzext.mask.nxv2i64.nxv2i32(
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32(
<vscale x 4 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vzext_vf2_nxv4i64(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i64> @intrinsic_vzext_vf2_nxv4i64(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vzext.vf2 v12, v8 ; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32( %a = call <vscale x 4 x i64> @llvm.riscv.vzext.nxv4i64.nxv4i32(
<vscale x 4 x i64> undef,
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32( declare <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
Show All 14 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vzext.mask.nxv4i64.nxv4i32(
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32(
<vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vzext_vf2_nxv8i64(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i64> @intrinsic_vzext_vf2_nxv8i64(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i64: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vzext.vf2 v16, v8 ; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vzext.nxv8i64.nxv8i32(
<vscale x 8 x i64> undef,
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32( declare <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
Show All 14 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vzext.mask.nxv8i64.nxv8i32(
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16(
<vscale x 1 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vzext_vf2_nxv1i32(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i32> @intrinsic_vzext_vf2_nxv1i32(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16( %a = call <vscale x 1 x i32> @llvm.riscv.vzext.nxv1i32.nxv1i16(
<vscale x 1 x i32> undef,
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16( declare <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
Show All 14 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vzext.mask.nxv1i32.nxv1i16(
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16(
<vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vzext_vf2_nxv2i32(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i32> @intrinsic_vzext_vf2_nxv2i32(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vzext.nxv2i32.nxv2i16(
<vscale x 2 x i32> undef,
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
Show All 14 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vzext.mask.nxv2i32.nxv2i16(
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16(
<vscale x 4 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vzext_vf2_nxv4i32(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i32> @intrinsic_vzext_vf2_nxv4i32(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16( %a = call <vscale x 4 x i32> @llvm.riscv.vzext.nxv4i32.nxv4i16(
<vscale x 4 x i32> undef,
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16( declare <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
Show All 14 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vzext.mask.nxv4i32.nxv4i16(
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16(
<vscale x 8 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vzext_vf2_nxv8i32(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i32> @intrinsic_vzext_vf2_nxv8i32(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vzext.vf2 v12, v8 ; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16( %a = call <vscale x 8 x i32> @llvm.riscv.vzext.nxv8i32.nxv8i16(
<vscale x 8 x i32> undef,
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16( declare <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
Show All 14 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vzext.mask.nxv8i32.nxv8i16(
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16(
<vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vzext_vf2_nxv16i32(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i32> @intrinsic_vzext_vf2_nxv16i32(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i32: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vzext.vf2 v16, v8 ; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vzext.nxv16i32.nxv16i16(
<vscale x 16 x i32> undef,
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16( declare <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
Show All 14 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vzext.mask.nxv16i32.nxv16i16(
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8(
<vscale x 1 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vzext_vf2_nxv1i16(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i16> @intrinsic_vzext_vf2_nxv1i16(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8( %a = call <vscale x 1 x i16> @llvm.riscv.vzext.nxv1i16.nxv1i8(
<vscale x 1 x i16> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8( declare <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
Show All 14 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vzext.mask.nxv1i16.nxv1i8(
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8(
<vscale x 2 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vzext_vf2_nxv2i16(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i16> @intrinsic_vzext_vf2_nxv2i16(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8( %a = call <vscale x 2 x i16> @llvm.riscv.vzext.nxv2i16.nxv2i8(
<vscale x 2 x i16> undef,
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8( declare <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
Show All 14 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vzext.mask.nxv2i16.nxv2i8(
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8(
<vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vzext_vf2_nxv4i16(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i16> @intrinsic_vzext_vf2_nxv4i16(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vzext.nxv4i16.nxv4i8(
<vscale x 4 x i16> undef,
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
Show All 14 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vzext.mask.nxv4i16.nxv4i8(
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8(
<vscale x 8 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vzext_vf2_nxv8i16(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i16> @intrinsic_vzext_vf2_nxv8i16(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8( %a = call <vscale x 8 x i16> @llvm.riscv.vzext.nxv8i16.nxv8i8(
<vscale x 8 x i16> undef,
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8( declare <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
Show All 14 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vzext.mask.nxv8i16.nxv8i8(
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8(
<vscale x 16 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vzext_vf2_nxv16i16(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i16> @intrinsic_vzext_vf2_nxv16i16(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vzext.vf2 v12, v8 ; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8( %a = call <vscale x 16 x i16> @llvm.riscv.vzext.nxv16i16.nxv16i8(
<vscale x 16 x i16> undef,
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8( declare <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
Show All 14 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vzext.mask.nxv16i16.nxv16i8(
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8(
<vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vzext_vf2_nxv32i16(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i16> @intrinsic_vzext_vf2_nxv32i16(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vzext_vf2_nxv32i16: ; CHECK-LABEL: intrinsic_vzext_vf2_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vzext.vf2 v16, v8 ; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vzext.nxv32i16.nxv32i8(
<vscale x 32 x i16> undef,
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
i64 %1) i64 %1)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vzext.mask.nxv32i16.nxv32i8( declare <vscale x 32 x i16> @llvm.riscv.vzext.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
Show All 20 Lines