[AArch64] Modeling NZCV read/write for MOPS instructions

[tyb0807]

Summary

According to the specification, MOPS instructions define/use NZCV flags as
part of their semantics (see discussion in
https://reviews.llvm.org/D116157).

More specifically, the specification of the MOPS extension states that
each memcpy/memset/memmov operation will be performed by a series
of three MOPS instructions P, M and E. The P instruction writes to the
NZCV flags, while the others (M and E) reads from the NZCV flags.

This is part 2/4 of a series of patches split from
https://reviews.llvm.org/D117405 to facilitate reviewing.

[dmgreen]

Usually it would be good to have a test for these kinds of changes, but these instructions are never used anywhere (we will use the pseudos for codegen), and I'm not sure of a way to test it otherwise.

For these instructions, marking them as Def NZCV will show that they clobber nzcv which is good. As far as I understand the "P" instruction Defs' and the other ("M", "E") will read the value. Is it worth trying to specify that more precisely? It might not alter a lot atm, but may be good to make sure the info is correct.

[tyb0807]

Be more precise about the behaviors of MOPS instructions w.r.t. NZCV flags. Update commit message accordingly

[dmgreen]

Thanks. LGTM

llvm/lib/Target/AArch64/AArch64InstrInfo.td

: Pat<(intrinsic GPR64sp:$addr, GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3, GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7),
           (instruction (REG_SEQUENCE GPR64x8Class, $x0, x8sub_0, $x1, x8sub_1, $x2, x8sub_2, $x3, x8sub_3, $x4, x8sub_4, $x5, x8sub_5, $x6, x8sub_6, $x7, x8sub_7), $addr)>;
 
   def : ST64BPattern<int_aarch64_st64b, ST64B>;
   def : ST64BPattern<int_aarch64_st64bv, ST64BV>;
   def : ST64BPattern<int_aarch64_st64bv0, ST64BV0>;
 }
 
 let Predicates = [HasMOPS] in {
+  let Defs = [NZCV] in {
     defm CPYFP : MOPSMemoryCopyInsns<0b00, "cpyfp">;
+
+    defm CPYP : MOPSMemoryMoveInsns<0b00, "cpyp">;
+
+    defm SETP : MOPSMemorySetInsns<0b00, "setp">;
+  }
+  let Uses = [NZCV] in {
     defm CPYFM : MOPSMemoryCopyInsns<0b01, "cpyfm">;
     defm CPYFE : MOPSMemoryCopyInsns<0b10, "cpyfe">;
 
-  defm CPYP : MOPSMemoryMoveInsns<0b00, "cpyp">;
     defm CPYM : MOPSMemoryMoveInsns<0b01, "cpym">;
     defm CPYE : MOPSMemoryMoveInsns<0b10, "cpye">;
 
-  defm SETP : MOPSMemorySetInsns<0b00, "setp">;
     defm SETM : MOPSMemorySetInsns<0b01, "setm">;
     defm SETE : MOPSMemorySetInsns<0b10, "sete">;
   }
+}
 let Predicates = [HasMOPS, HasMTE] in {
+  let Defs = [NZCV] in {
     defm SETGP     : MOPSMemorySetTaggingInsns<0b00, "setgp">;
+  }
+  let Uses = [NZCV] in {
     defm SETGM     : MOPSMemorySetTaggingInsns<0b01, "setgm">;
     // Can't use SETGE because it's a reserved name in TargetSelectionDAG.td
     defm MOPSSETGE : MOPSMemorySetTaggingInsns<0b10, "setge">;
   }
+}
 
 let Defs = [X16, X17], mayStore = 1, isCodeGenOnly = 1 in
 def StoreSwiftAsyncContext
       : Pseudo<(outs), (ins GPR64:$ctx, GPR64sp:$base, simm9:$offset),
                []>, Sched<[]>;
 
 def AArch64AssertZExtBool : SDNode<"AArch64ISD::ASSERT_ZEXT_BOOL", SDT_assert>;
 def : Pat<(AArch64AssertZExtBool GPR32:$op),
           (i32 GPR32:$op)>;
 
 include "AArch64InstrAtomics.td"
 include "AArch64SVEInstrInfo.td"
 include "AArch64SMEInstrInfo.td"
 include "AArch64InstrGISel.td"