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Restrict performPostLD1Combine to 64 and 128 bit vectors
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Authored by mgabka on Jan 19 2022, 6:24 AM.

Details

Summary

When wider vectors are used, for example fixed width SVE,
there is no patterns to select AArch64ISD::LD1LANEpost
nodes, so we should do an early exit.

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Event Timeline

mgabka created this revision.Jan 19 2022, 6:24 AM
mgabka requested review of this revision.Jan 19 2022, 6:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 19 2022, 6:24 AM
paulwalker-arm accepted this revision.Jan 25 2022, 2:52 AM
This revision is now accepted and ready to land.Jan 25 2022, 2:52 AM
Matt added a subscriber: Matt.Jan 25 2022, 3:15 PM
This revision was automatically updated to reflect the committed changes.