[DAG] Extend SearchForAndLoads with any_extend handling

[dmgreen]

Summary

This extends the code in SearchForAndLoads to be able to look through ANY_EXTEND nodes, which can be created from mismatching IR types where the AND node we begin from only demands the low parts of the register. That turns zext and sext into any_extends as only the low bits are demanded. To be able to look through ANY_EXTEND nodes we need to handle mismatching types in a few places, potentially truncating the mask to the size of the final load.

[samparker]

LGTM

[RKSimon]

X86 change LGTM

[hans]

This is causing builds to fail with an assert:

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5638: bool (anonymous namespace)::DAGCombiner::BackwardsPropagateMask(llvm::SDNode *): Assertion `NewLoad && "Shouldn't be masking the load if it can't be narrowed"' failed.

See https://bugs.chromium.org/p/chromium/issues/detail?id=1288202#c1 for a reproducer.

I'll revert this until it can be fixed.

[dmgreen]

Thanks for the report. I've recommitted with a fix. Please let me know if there are any other issues that come up.

[jonpa]

Unfortunately I think this is causing wrong code: https://github.com/llvm/llvm-project/issues/53528

[dmgreen]

Oh I see yes. That is essentially the same as the multiple_load_or case here - I was trying to get that to go wrong but couldn't. On AArch64 we implicitly zext (in the orr w0, w9, w8, the top bits of x0 are set to 0 as it writes w0). In the case you have it doesn't get the zext.

I will try and sort out a fix, and make sure this is either fixed or reverted on the branch (depending on which revision that gets created from).

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

bool DAGCombiner::SearchForAndLoads(SDNode *N,
   // Recursively search for the operands, looking for loads which can be
   // narrowed.
   for (SDValue Op : N->op_values()) {
     if (Op.getValueType().isVector())
       return false;
 
     // Some constants may need fixing up later if they are too large.
     if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
+      if (Mask->getValueType(0) != C->getValueType(0))
+        return false;
       if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
           (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
         NodesWithConsts.insert(N);
       continue;
     }
 
     if (!Op.hasOneUse())
       return false;
case ISD::LOAD: {
         continue;
       }
       return false;
     }
     case ISD::ZERO_EXTEND:
     case ISD::AssertZext: {
       unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
       EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
-      EVT VT = Op.getOpcode() == ISD::AssertZext ?
-        cast<VTSDNode>(Op.getOperand(1))->getVT() :
-        Op.getOperand(0).getValueType();
+      EVT VT = Op.getOpcode() == ISD::AssertZext
+                   ? cast<VTSDNode>(Op.getOperand(1))->getVT()
+                   : Op.getOperand(0).getValueType();
 
       // We can accept extending nodes if the mask is wider or an equal
       // width to the original type.
       if (ExtVT.bitsGE(VT))
         continue;
       break;
     }
+    case ISD::ANY_EXTEND:
     case ISD::OR:
     case ISD::XOR:
     case ISD::AND:
       if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
                              NodeToMask))
         return false;
       continue;
     }
if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
 
     LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump());
     SDValue MaskOp = N->getOperand(1);
 
     // If it exists, fixup the single node we allow in the tree that needs
     // masking.
     if (FixupNode) {
       LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump());
-      SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
-                                FixupNode->getValueType(0),
-                                SDValue(FixupNode, 0), MaskOp);
+      SDValue MaskOpT = DAG.getZExtOrTrunc(MaskOp, SDLoc(FixupNode),
+                                           FixupNode->getValueType(0));
+      SDValue And =
+          DAG.getNode(ISD::AND, SDLoc(FixupNode), FixupNode->getValueType(0),
+                      SDValue(FixupNode, 0), MaskOpT);
       DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
       if (And.getOpcode() == ISD ::AND)
-        DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
+        DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOpT);
     }
 
     // Narrow any constants that need it.
     for (auto *LogicN : NodesWithConsts) {
       SDValue Op0 = LogicN->getOperand(0);
       SDValue Op1 = LogicN->getOperand(1);
 
       if (isa<ConstantSDNode>(Op0))
-          std::swap(Op0, Op1);
 
-      SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
-                                Op1, MaskOp);
+      SDValue MaskOpT =
+          DAG.getZExtOrTrunc(MaskOp, SDLoc(Op1), Op1.getValueType());
+      SDValue And =
+          DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(), Op1, MaskOpT);
 
       DAG.UpdateNodeOperands(LogicN, Op0, And);
     }
 
     // Create narrow loads.
     for (auto *Load : Loads) {
       LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump());
+      SDValue MaskOpT =
+          DAG.getZExtOrTrunc(MaskOp, SDLoc(Load), Load->getValueType(0));
       SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
-                                SDValue(Load, 0), MaskOp);
+                                SDValue(Load, 0), MaskOpT);
       DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
       if (And.getOpcode() == ISD ::AND)
         And = SDValue(
-            DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
+            DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOpT), 0);
       SDValue NewLoad = reduceLoadWidth(And.getNode());
       assert(NewLoad &&
              "Shouldn't be masking the load if it can't be narrowed");
       CombineTo(Load, NewLoad, NewLoad.getValue(1));
     }
     DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
     return true;
   }

llvm/test/CodeGen/AArch64/combine-andintoload.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-eabi -o - | FileCheck %s
 ; RUN: llc < %s -mtriple=aarch64_be-none-eabi -o - | FileCheck %s --check-prefix=CHECKBE
 
 define i64 @load32_and16_and(i32* %p, i64 %y) {
 ; CHECK-LABEL: load32_and16_and:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    and w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xffff
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    and w0, w1, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load32_and16_and:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldr w8, [x0]
-; CHECKBE-NEXT:    and w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xffff
+; CHECKBE-NEXT:    ldrh w8, [x0, #2]
+; CHECKBE-NEXT:    and w0, w1, w8
 ; CHECKBE-NEXT:    ret
   %x = load i32, i32* %p, align 4
   %xz = zext i32 %x to i64
   %ym = and i64 %y, 65535
   %r = and i64 %ym, %xz
   ret i64 %r
 }
 
 define i64 @load32_and16_andr(i32* %p, i64 %y) {
 ; CHECK-LABEL: load32_and16_andr:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    and w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xffff
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    and w0, w1, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load32_and16_andr:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldr w8, [x0]
-; CHECKBE-NEXT:    and w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xffff
+; CHECKBE-NEXT:    ldrh w8, [x0, #2]
+; CHECKBE-NEXT:    and w0, w1, w8
 ; CHECKBE-NEXT:    ret
   %x = load i32, i32* %p, align 4
   %xz = zext i32 %x to i64
   %a = and i64 %y, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }
 
 define i64 @load32_and16_and_sext(i32* %p, i64 %y) {
 ; CHECK-LABEL: load32_and16_and_sext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    and w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xffff
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    and w0, w1, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load32_and16_and_sext:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldr w8, [x0]
-; CHECKBE-NEXT:    and w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xffff
+; CHECKBE-NEXT:    ldrh w8, [x0, #2]
+; CHECKBE-NEXT:    and w0, w1, w8
 ; CHECKBE-NEXT:    ret
   %x = load i32, i32* %p, align 4
   %xz = sext i32 %x to i64
   %a = and i64 %y, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }
 
 define i64 @load32_and16_or(i32* %p, i64 %y) {
 ; CHECK-LABEL: load32_and16_or:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xffff
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    and w9, w1, #0xffff
+; CHECK-NEXT:    orr w0, w9, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load32_and16_or:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldr w8, [x0]
-; CHECKBE-NEXT:    orr w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xffff
+; CHECKBE-NEXT:    ldrh w8, [x0, #2]
+; CHECKBE-NEXT:    and w9, w1, #0xffff
+; CHECKBE-NEXT:    orr w0, w9, w8
 ; CHECKBE-NEXT:    ret
   %x = load i32, i32* %p, align 4
   %xz = zext i32 %x to i64
   %a = or i64 %y, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }
 
; CHECKBE-NEXT:    ret
   %a = and i64 %y, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }
 
 define i64 @load16_and8(i16* %p, i64 %y) {
 ; CHECK-LABEL: load16_and8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    and w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xff
+; CHECK-NEXT:    ldrb w8, [x0]
+; CHECK-NEXT:    and w0, w1, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load16_and8:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldrh w8, [x0]
-; CHECKBE-NEXT:    and w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xff
+; CHECKBE-NEXT:    ldrb w8, [x0, #1]
+; CHECKBE-NEXT:    and w0, w1, w8
 ; CHECKBE-NEXT:    ret
   %x = load i16, i16* %p, align 4
   %xz = zext i16 %x to i64
   %a = and i64 %y, %xz
   %r = and i64 %a, 255
   ret i64 %r
 }
 
; CHECKBE-NEXT:    ret
   %r = and i64 %a, 65535
   ret i64 %r
 }
 
 define i64 @load8_and16_zext(i8* %p, i8 %y) {
 ; CHECK-LABEL: load8_and16_zext:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldrb w8, [x0]
-; CHECK-NEXT:    and w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xff
+; CHECK-NEXT:    and w0, w1, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load8_and16_zext:
 ; CHECKBE:       // %bb.0:
 ; CHECKBE-NEXT:    ldrb w8, [x0]
-; CHECKBE-NEXT:    and w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xff
+; CHECKBE-NEXT:    and w0, w1, w8
 ; CHECKBE-NEXT:    ret
   %x = load i8, i8* %p, align 4
   %xz = zext i8 %x to i64
   %yz = zext i8 %y to i64
   %a = and i64 %yz, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }
; CHECKBE-NEXT:    ret
   %a = or i64 %y, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }
 
 define i64 @load16_and8_manyext(i16* %p, i32 %y) {
 ; CHECK-LABEL: load16_and8_manyext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    and w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xff
+; CHECK-NEXT:    ldrb w8, [x0]
+; CHECK-NEXT:    and w0, w1, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load16_and8_manyext:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldrh w8, [x0]
-; CHECKBE-NEXT:    and w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xff
+; CHECKBE-NEXT:    ldrb w8, [x0, #1]
+; CHECKBE-NEXT:    and w0, w1, w8
 ; CHECKBE-NEXT:    ret
   %x = load i16, i16* %p, align 4
   %xz = zext i16 %x to i32
   %a = and i32 %y, %xz
   %az = zext i32 %a to i64
   %r = and i64 %az, 255
   ret i64 %r
 }
 
 define i64 @multiple_load(i16* %p, i32* %q) {
 ; CHECK-LABEL: multiple_load:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    ldr w9, [x1]
-; CHECK-NEXT:    and w8, w9, w8
-; CHECK-NEXT:    and x0, x8, #0xff
+; CHECK-NEXT:    ldrb w8, [x0]
+; CHECK-NEXT:    ldrb w9, [x1]
+; CHECK-NEXT:    and w0, w9, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: multiple_load:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldrh w8, [x0]
-; CHECKBE-NEXT:    ldr w9, [x1]
-; CHECKBE-NEXT:    and w8, w9, w8
-; CHECKBE-NEXT:    and x0, x8, #0xff
+; CHECKBE-NEXT:    ldrb w8, [x0, #1]
+; CHECKBE-NEXT:    ldrb w9, [x1, #3]
+; CHECKBE-NEXT:    and w0, w9, w8
 ; CHECKBE-NEXT:    ret
   %x = load i16, i16* %p, align 4
   %xz = zext i16 %x to i64
   %y = load i32, i32* %q, align 4
   %yz = zext i32 %y to i64
   %a = and i64 %yz, %xz
   %r = and i64 %a, 255
   ret i64 %r
 }
 
 define i64 @multiple_load_or(i16* %p, i32* %q) {
 ; CHECK-LABEL: multiple_load_or:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    ldr w9, [x1]
-; CHECK-NEXT:    orr w8, w9, w8
-; CHECK-NEXT:    and x0, x8, #0xff
+; CHECK-NEXT:    ldrb w8, [x0]
+; CHECK-NEXT:    ldrb w9, [x1]
+; CHECK-NEXT:    orr w0, w9, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: multiple_load_or:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldrh w8, [x0]
-; CHECKBE-NEXT:    ldr w9, [x1]
-; CHECKBE-NEXT:    orr w8, w9, w8
-; CHECKBE-NEXT:    and x0, x8, #0xff
+; CHECKBE-NEXT:    ldrb w8, [x0, #1]
+; CHECKBE-NEXT:    ldrb w9, [x1, #3]
+; CHECKBE-NEXT:    orr w0, w9, w8
 ; CHECKBE-NEXT:    ret
   %x = load i16, i16* %p, align 4
   %xz = zext i16 %x to i64
   %y = load i32, i32* %q, align 4
   %yz = zext i32 %y to i64
   %a = or i64 %yz, %xz
   %r = and i64 %a, 255
   ret i64 %r
 }
 
 define i64 @load32_and16_zexty(i32* %p, i32 %y) {
 ; CHECK-LABEL: load32_and16_zexty:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xffff
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    and w9, w1, #0xffff
+; CHECK-NEXT:    orr w0, w9, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load32_and16_zexty:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldr w8, [x0]
-; CHECKBE-NEXT:    orr w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xffff
+; CHECKBE-NEXT:    ldrh w8, [x0, #2]
+; CHECKBE-NEXT:    and w9, w1, #0xffff
+; CHECKBE-NEXT:    orr w0, w9, w8
 ; CHECKBE-NEXT:    ret
   %x = load i32, i32* %p, align 4
   %xz = zext i32 %x to i64
   %yz = zext i32 %y to i64
   %a = or i64 %yz, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }
 
 define i64 @load32_and16_sexty(i32* %p, i32 %y) {
 ; CHECK-LABEL: load32_and16_sexty:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr w8, [x0]
-; CHECK-NEXT:    orr w8, w1, w8
-; CHECK-NEXT:    and x0, x8, #0xffff
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    and w9, w1, #0xffff
+; CHECK-NEXT:    orr w0, w9, w8
 ; CHECK-NEXT:    ret
 ;
 ; CHECKBE-LABEL: load32_and16_sexty:
 ; CHECKBE:       // %bb.0:
-; CHECKBE-NEXT:    ldr w8, [x0]
-; CHECKBE-NEXT:    orr w8, w1, w8
-; CHECKBE-NEXT:    and x0, x8, #0xffff
+; CHECKBE-NEXT:    ldrh w8, [x0, #2]
+; CHECKBE-NEXT:    and w9, w1, #0xffff
+; CHECKBE-NEXT:    orr w0, w9, w8
 ; CHECKBE-NEXT:    ret
   %x = load i32, i32* %p, align 4
   %xz = zext i32 %x to i64
   %yz = sext i32 %y to i64
   %a = or i64 %yz, %xz
   %r = and i64 %a, 65535
   ret i64 %r
 }

llvm/test/CodeGen/X86/pr35763.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s
 
 %struct.S = type <{ i16, i24, [5 x i8], i8, i16, [2 x i8] }>
 
 @z = dso_local global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8
 @tf_3_var_136 = dso_local global i64 0, align 8
 @.str = private unnamed_addr constant [6 x i8] c"%llu\0A\00", align 1
 
 define dso_local void @PR35763() {
 ; CHECK-LABEL: PR35763:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movl z(%rip), %eax
-; CHECK-NEXT:    orl z+2(%rip), %eax
-; CHECK-NEXT:    movzwl %ax, %eax
-; CHECK-NEXT:    movq %rax, tf_3_var_136(%rip)
+; CHECK-NEXT:    movzwl z(%rip), %eax
+; CHECK-NEXT:    movzwl z+2(%rip), %ecx
+; CHECK-NEXT:    orl %eax, %ecx
+; CHECK-NEXT:    movq %rcx, tf_3_var_136(%rip)
 ; CHECK-NEXT:    movl z+6(%rip), %eax
 ; CHECK-NEXT:    movzbl z+10(%rip), %ecx
 ; CHECK-NEXT:    shlq $32, %rcx
 ; CHECK-NEXT:    orq %rax, %rcx
 ; CHECK-NEXT:    movabsq $1090921758719, %rax # imm = 0xFE0000FFFF
 ; CHECK-NEXT:    andq %rcx, %rax
 ; CHECK-NEXT:    movl %eax, z+6(%rip)
 ; CHECK-NEXT:    shrq $32, %rax

llvm/test/CodeGen/X86/pr35765.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
 
 @ll = dso_local local_unnamed_addr global i64 0, align 8
 @x = dso_local local_unnamed_addr global i64 2651237805702985558, align 8
 @s1 = dso_local local_unnamed_addr global { i8, i8 } { i8 123, i8 5 }, align 2
 @s2 = dso_local local_unnamed_addr global { i8, i8 } { i8 -122, i8 3 }, align 2
 
 define dso_local void @PR35765() {
 ; CHECK-LABEL: PR35765:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movb s1(%rip), %cl
 ; CHECK-NEXT:    addb $-118, %cl
 ; CHECK-NEXT:    movl $4, %eax
 ; CHECK-NEXT:    shll %cl, %eax
-; CHECK-NEXT:    movzwl x(%rip), %ecx
-; CHECK-NEXT:    movzwl s2(%rip), %edx
-; CHECK-NEXT:    notl %edx
-; CHECK-NEXT:    orl $63488, %edx # imm = 0xF800
-; CHECK-NEXT:    movzwl %dx, %edx
-; CHECK-NEXT:    orl %ecx, %edx
-; CHECK-NEXT:    xorl %eax, %edx
-; CHECK-NEXT:    movslq %edx, %rax
+; CHECK-NEXT:    movzwl s2(%rip), %ecx
+; CHECK-NEXT:    notl %ecx
+; CHECK-NEXT:    orl x(%rip), %ecx
+; CHECK-NEXT:    orl $63488, %ecx # imm = 0xF800
+; CHECK-NEXT:    movzwl %cx, %ecx
+; CHECK-NEXT:    xorl %eax, %ecx
+; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    movq %rax, ll(%rip)
 ; CHECK-NEXT:    retq
 entry:
   %bf.load.i = load i16, i16* bitcast ({ i8, i8 }* @s1 to i16*), align 2
   %bf.clear.i = and i16 %bf.load.i, 2047
   %conv.i = zext i16 %bf.clear.i to i32
   %sub.i = add nsw i32 %conv.i, -1398
   %shl.i = shl i32 4, %sub.i