Paths
| Differential D116677
[2/4] [MC][NFC] Add an optional PreviousInst argument to MCInstrAnalysis::evaluateBranch Needs ReviewPublic Authored by asb on Jan 5 2022, 10:33 AM.
Details Summary evaluateBranch currently takes a single instruction. This works for most This patch simply adds the argument, and modifies llvm-objdump to pass This isn't a pretty solution, so if you have alternate proposals I'd be keen to discuss.
Diff Detail Event Timelineasb added a parent revision: D116676: [1/4] [llvm-objdump][test] Add RISC-V objdump test case.Jan 5 2022, 10:34 AM Comment Actions Checking the consecutive pair of instructions likely works for the majority of cases for some architectures. It fails when a RISC architecture interleaves the high and low parts with an unrelated instruction. This pattern is pretty common on AArch64. % cat a.c
int a, b;
int foo() { return a + b; }
% clang --target=aarch64-linux-gnu -nostdlib -fuse-ld=lld -O1 a.c -o a
% llvm-objdump -d a
...
000000000021022c <foo>:
21022c: 88 00 00 90 adrp x8, 0x220000 <foo+0x40>
210230: 89 00 00 90 adrp x9, 0x220000 <foo+0x44>
210234: 08 45 42 b9 ldr w8, [x8, #580]
210238: 29 49 42 b9 ldr w9, [x9, #584]
21023c: 20 01 08 0b add w0, w9, w8
210240: c0 03 5f d6 retTo obtain the addresses of a and b, we need to have states, which can be in MCInstrAnalysis itself. Comment Actions Thanks for the review @MaskRay, I had thought about options such as adding state to MCInstrAnalysis, but perhaps was too quick to dismiss it (obviously partly influenced by the fact that the current RISC-V backend doesn't seem to generate output where just checking instruction pairs doesn't work!). As you suggest, an issue will be around tracking/clearing state upon basic block boundaries, but perhaps a simple heuristic will work well enough. So perhaps:
What do you think? (Especially on the last bulletpoint)? Comment Actions
Sounds good! jobnoorman mentioned this in D159114: [llvm-objdump][RISCV] Print target of auipc+jalr calls.Sep 6 2023, 6:48 AM Comment Actions
I've opened #65479 to implement this state idea and #65480 to implement it for auipc+jalr on RISC-V.
Revision Contents
Diff 397635 llvm/include/llvm/MC/MCInstrAnalysis.h
llvm/lib/MC/MCInstrAnalysis.cpp
llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
llvm/tools/llvm-cfi-verify/lib/GraphBuilder.cpp
llvm/tools/llvm-objdump/llvm-objdump.cpp
llvm/tools/sancov/sancov.cpp
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||