This is an archive of the discontinued LLVM Phabricator instance.

Differential D113193

[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
ClosedPublic

Authored by Carrot on Nov 4 2021, 8:40 AM.

Details

Reviewers
craig.topper
pengfei
RKSimon
stoklund
sjarus
Commits
rGf1d8345a2ab3: [TwoAddressInstructionPass] Create register mapping for registers with multiple…
Summary

Currently we create register mappings for registers used only once in current MBB. For registers with multiple uses, when all the uses are in the current MBB, we can also create mappings for them similarly according to the last use. For example

%reg101 = ...
                = ... reg101
%reg103 = ADD %reg101, %reg102

We can create mapping between %reg101 and %reg103.

Diff Detail

Event Timeline

Carrot created this revision.Nov 4 2021, 8:40 AM
Herald added subscribers: mstorsjo, hiraditya. · View Herald TranscriptNov 4 2021, 8:40 AM
Carrot requested review of this revision.Nov 4 2021, 8:40 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 4 2021, 8:40 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B132467: Diff 384760.Nov 4 2021, 8:40 AM
Carrot updated this revision to Diff 385992.Nov 9 2021, 3:25 PM

Rebase.

Harbormaster completed remote builds in B133368: Diff 385992.Nov 9 2021, 4:23 PM
Carrot added a comment.Nov 12 2021, 3:42 PM

ping

pengfei added inline comments.Nov 12 2021, 6:18 PM
llvm/test/CodeGen/X86/uadd_sat_vec.ll
1079

The tests in this file seem all become bad. Do you have any idea to optimizate for them?

Carrot added inline comments.Nov 15 2021, 12:04 PM
llvm/test/CodeGen/X86/uadd_sat_vec.ll
1079

Let's take function v4i32 as an example

With this patch

liveins: $xmm0, $xmm1
%1:vr128 = COPY killed $xmm1
%0:vr128 = COPY killed $xmm0
%2:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
%3:vr128 = COPY %0:vr128
%3:vr128 = PXORrr %3:vr128(tied-def 0), %2:vr128
%4:vr128 = COPY killed %0:vr128
%4:vr128 = PADDDrr %4:vr128(tied-def 0), killed %1:vr128
%5:vr128 = COPY killed %2:vr128
%5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
%6:vr128 = COPY killed %3:vr128
%6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), killed %5:vr128
%7:vr128 = COPY killed %4:vr128
%7:vr128 = PORrr %7:vr128(tied-def 0), killed %6:vr128
$xmm0 = COPY killed %7:vr128
RET 0, killed $xmm0

The final extra movdqa comes from

3:vr128 = COPY %0:vr128

It can't be deleted because %0 is not kill at this point. All other COPY instructions can be coalesced and deleted.

Without this patch

liveins: $xmm0, $xmm1
%1:vr128 = COPY killed $xmm1
%0:vr128 = COPY killed $xmm0
%2:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
%3:vr128 = COPY %0:vr128
%3:vr128 = PXORrr %3:vr128(tied-def 0), %2:vr128
%4:vr128 = COPY killed %1:vr128
%4:vr128 = PADDDrr %4:vr128(tied-def 0), killed %0:vr128
%5:vr128 = COPY killed %2:vr128
%5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
%6:vr128 = COPY killed %3:vr128
%6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), killed %5:vr128
%7:vr128 = COPY killed %6:vr128
%7:vr128 = PORrr %7:vr128(tied-def 0), killed %4:vr128
$xmm0 = COPY killed %7:vr128
RET 0, killed $xmm0

It also contains

3:vr128 = COPY %0:vr128

and %0 is not killed, so %3 is not xmm0 and this COPY is a real MOV at this point. The SrcRegMap contains %7 -> %6 -> %3, so %7 can't be coalesced with xmm0, and the last COPY is also a real MOV.

It can seen clearly after coalescing

0B      bb.0 (%ir-block.0):
          liveins: $xmm0, $xmm1
16B       %4:vr128 = COPY $xmm1
32B       %0:vr128 = COPY $xmm0
48B       %5:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
64B       %6:vr128 = COPY %0:vr128
80B       %6:vr128 = PXORrr %6:vr128(tied-def 0), %5:vr128
112B      %4:vr128 = PADDDrr %4:vr128(tied-def 0), %0:vr128
144B      %5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
176B      %6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), %5:vr128
208B      %6:vr128 = PORrr %6:vr128(tied-def 0), %4:vr128
224B      $xmm0 = COPY %6:vr128
240B      RET 0, $xmm0

So the two address conversion result is actually better with my new patch.

But after scheduling, the %0 in the COPY instruction becomes killed operand, so now %6 and %0 and xmm0 can be coalesced, and both COPY instructions can be deleted.

0B      bb.0 (%ir-block.0):
          liveins: $xmm0, $xmm1
16B       %4:vr128 = COPY $xmm1
32B       %0:vr128 = COPY $xmm0
48B       %5:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
112B      %4:vr128 = PADDDrr %4:vr128(tied-def 0), %0:vr128
116B      %6:vr128 = COPY %0:vr128
120B      %6:vr128 = PXORrr %6:vr128(tied-def 0), %5:vr128
144B      %5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
176B      %6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), %5:vr128
208B      %6:vr128 = PORrr %6:vr128(tied-def 0), %4:vr128
224B      $xmm0 = COPY %6:vr128
240B      RET 0, $xmm0

So this is another pass order problem between scheduling/TwoAddressInstructionPass.

Carrot added a comment.Nov 22 2021, 5:35 PM

ping

pengfei accepted this revision.Nov 22 2021, 11:19 PM

LGTM.

This revision is now accepted and ready to land.Nov 22 2021, 11:19 PM
This revision was landed with ongoing or failed builds.Nov 29 2021, 7:05 PM
Closed by commit rGf1d8345a2ab3: [TwoAddressInstructionPass] Create register mapping for registers with multiple… (authored by Carrot). · Explain Why
This revision was automatically updated to reflect the committed changes.
Carrot added a commit: rGf1d8345a2ab3: [TwoAddressInstructionPass] Create register mapping for registers with multiple….
Herald added a reviewer: sjarus. · View Herald TranscriptNov 29 2021, 7:05 PM
Herald added subscribers: armkevincheng, jsmolens, eric-k256. · View Herald Transcript
dongAxis1944 added a subscriber: dongAxis1944.Feb 15 2022, 12:24 AM
dongAxis1944 added inline comments.
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
389

hi, I have a question, why does the code not break here directly?

pengfei added inline comments.Feb 15 2022, 5:59 AM
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
389

It finds the last use in BB, see comments above.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
28 lines
test/
CodeGen/
ARM/
479 lines
48 lines
24 lines
106 lines
51 lines
SystemZ/
3 lines
6 lines
6 lines
3 lines
Thumb/
4 lines
X86/
3 lines
37 lines
9 lines
avx512-shuffles/
32 lines
24 lines
8 lines
10 lines
13 lines
275 lines
10 lines
7 lines
114 lines
12 lines
4 lines
84 lines
69 lines
83 lines
14 lines
8 lines
8 lines
58 lines
218 lines
28 lines
19 lines
11 lines
129 lines
9 lines
14 lines
7 lines
132 lines
80 lines
229 lines
112 lines
5 lines
11 lines
313 lines
5 lines
36 lines
17 lines
176 lines
208 lines
130 lines
38 lines
84 lines
64 lines
191 lines
212 lines
63 lines
704 lines
61 lines
6 lines
1486 lines
111 lines
72 lines
72 lines
46 lines
92 lines
46 lines
92 lines
12 lines
12 lines
84 lines
12 lines
339 lines
516 lines
96 lines
108 lines
15 lines

Diff 390549

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

Show First 20 Lines • Show All 367 Lines • ▼ Show 20 Lines for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
if (MI.isRegTiedToDefOperand(i, &ti)) { if (MI.isRegTiedToDefOperand(i, &ti)) {
DstReg = MI.getOperand(ti).getReg(); DstReg = MI.getOperand(ti).getReg();
return true; return true;
} }
} }
return false; return false;
} }
/// Given a register, if has a single in-basic block use, return the use /// Given a register, if all its uses are in the same basic block, return the
/// instruction if it's a copy or a two-address use. /// last use instruction if it's a copy or a two-address use.
static MachineInstr * static MachineInstr *
findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB, findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
MachineRegisterInfo *MRI, const TargetInstrInfo *TII, MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
bool &IsCopy, Register &DstReg, bool &IsDstPhys) { bool &IsCopy, Register &DstReg, bool &IsDstPhys,
if (!MRI->hasOneNonDBGUse(Reg)) LiveIntervals *LIS) {
// None or more than one use. MachineOperand *UseOp = nullptr;
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
MachineInstr *MI = MO.getParent();
if (MI->getParent() != MBB)
return nullptr; return nullptr;
MachineOperand &UseOp = *MRI->use_nodbg_begin(Reg); if (isPlainlyKilled(MI, Reg, LIS))
MachineInstr &UseMI = *UseOp.getParent(); UseOp = &MO;
dongAxis1944Unsubmitted
Not Done
ReplyInline Actions

hi, I have a question, why does the code not break here directly?

dongAxis1944: hi, I have a question, why does the code not break here directly?
pengfeiUnsubmitted
Not Done
ReplyInline Actions

It finds the last use in BB, see comments above.

pengfei: It finds the last use in BB, see comments above.
if (UseMI.getParent() != MBB) }
if (!UseOp)
return nullptr; return nullptr;
MachineInstr &UseMI = *UseOp->getParent();
Register SrcReg; Register SrcReg;
bool IsSrcPhys; bool IsSrcPhys;
if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
IsCopy = true; IsCopy = true;
return &UseMI; return &UseMI;
} }
IsDstPhys = false; IsDstPhys = false;
if (isTwoAddrUse(UseMI, Reg, DstReg)) { if (isTwoAddrUse(UseMI, Reg, DstReg)) {
IsDstPhys = DstReg.isPhysical(); IsDstPhys = DstReg.isPhysical();
return &UseMI; return &UseMI;
} }
if (UseMI.isCommutable()) { if (UseMI.isCommutable()) {
unsigned Src1 = TargetInstrInfo::CommuteAnyOperandIndex; unsigned Src1 = TargetInstrInfo::CommuteAnyOperandIndex;
unsigned Src2 = UseMI.getOperandNo(&UseOp); unsigned Src2 = UseMI.getOperandNo(UseOp);
if (TII->findCommutedOpIndices(UseMI, Src1, Src2)) { if (TII->findCommutedOpIndices(UseMI, Src1, Src2)) {
MachineOperand &MO = UseMI.getOperand(Src1); MachineOperand &MO = UseMI.getOperand(Src1);
if (MO.isReg() && MO.isUse() && if (MO.isReg() && MO.isUse() &&
isTwoAddrUse(UseMI, MO.getReg(), DstReg)) { isTwoAddrUse(UseMI, MO.getReg(), DstReg)) {
IsDstPhys = DstReg.isPhysical(); IsDstPhys = DstReg.isPhysical();
return &UseMI; return &UseMI;
} }
} }
▲ Show 20 Lines • Show All 306 Lines • ▼ Show 20 Lines
/// a two-address instruction. /// a two-address instruction.
void TwoAddressInstructionPass::scanUses(Register DstReg) { void TwoAddressInstructionPass::scanUses(Register DstReg) {
SmallVector<Register, 4> VirtRegPairs; SmallVector<Register, 4> VirtRegPairs;
bool IsDstPhys; bool IsDstPhys;
bool IsCopy = false; bool IsCopy = false;
Register NewReg; Register NewReg;
Register Reg = DstReg; Register Reg = DstReg;
while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy, while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
NewReg, IsDstPhys)) { NewReg, IsDstPhys, LIS)) {
if (IsCopy && !Processed.insert(UseMI).second) if (IsCopy && !Processed.insert(UseMI).second)
break; break;
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
if (DI != DistanceMap.end()) if (DI != DistanceMap.end())
// Earlier in the same MBB.Reached via a back edge. // Earlier in the same MBB.Reached via a back edge.
break; break;
▲ Show 20 Lines • Show All 1,134 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/fpclamptosat.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP2-LABEL: stest_f64i32: ; VFP2-LABEL: stest_f64i32:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
; VFP2-NEXT: push {r7, lr} ; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, r1, d0 ; VFP2-NEXT: vmov r0, r1, d0
; VFP2-NEXT: bl __aeabi_d2lz ; VFP2-NEXT: bl __aeabi_d2lz
; VFP2-NEXT: mvn r2, #-2147483648 ; VFP2-NEXT: mvn r12, #-2147483648
; VFP2-NEXT: subs r3, r0, r2 ; VFP2-NEXT: subs.w r3, r0, r12
; VFP2-NEXT: mov.w r12, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: sbcs r3, r1, #0 ; VFP2-NEXT: sbcs r3, r1, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w r12, #1 ; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp.w r12, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: itt ne ; VFP2-NEXT: ite ne
; VFP2-NEXT: movne r12, r1 ; VFP2-NEXT: movne r2, r1
; VFP2-NEXT: movne r2, r0 ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: mov.w r0, #-1 ; VFP2-NEXT: mov.w r1, #-1
; VFP2-NEXT: rsbs.w r1, r2, #-2147483648 ; VFP2-NEXT: rsbs.w r3, r0, #-2147483648
; VFP2-NEXT: sbcs.w r0, r0, r12 ; VFP2-NEXT: sbcs r1, r2
; VFP2-NEXT: it ge ; VFP2-NEXT: it ge
; VFP2-NEXT: movge.w r2, #-2147483648 ; VFP2-NEXT: movge.w r0, #-2147483648
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: stest_f64i32: ; FULL-LABEL: stest_f64i32:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov r0, r1, d0 ; FULL-NEXT: vmov r0, r1, d0
; FULL-NEXT: bl __aeabi_d2lz ; FULL-NEXT: bl __aeabi_d2lz
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Lines
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP2-LABEL: stest_f32i32: ; VFP2-LABEL: stest_f32i32:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
; VFP2-NEXT: push {r7, lr} ; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, s0 ; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_f2lz ; VFP2-NEXT: bl __aeabi_f2lz
; VFP2-NEXT: mvn r2, #-2147483648 ; VFP2-NEXT: mvn r12, #-2147483648
; VFP2-NEXT: subs r3, r0, r2 ; VFP2-NEXT: subs.w r3, r0, r12
; VFP2-NEXT: mov.w r12, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: sbcs r3, r1, #0 ; VFP2-NEXT: sbcs r3, r1, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w r12, #1 ; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp.w r12, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: itt ne ; VFP2-NEXT: ite ne
; VFP2-NEXT: movne r12, r1 ; VFP2-NEXT: movne r2, r1
; VFP2-NEXT: movne r2, r0 ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: mov.w r0, #-1 ; VFP2-NEXT: mov.w r1, #-1
; VFP2-NEXT: rsbs.w r1, r2, #-2147483648 ; VFP2-NEXT: rsbs.w r3, r0, #-2147483648
; VFP2-NEXT: sbcs.w r0, r0, r12 ; VFP2-NEXT: sbcs r1, r2
; VFP2-NEXT: it ge ; VFP2-NEXT: it ge
; VFP2-NEXT: movge.w r2, #-2147483648 ; VFP2-NEXT: movge.w r0, #-2147483648
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: stest_f32i32: ; FULL-LABEL: stest_f32i32:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov r0, s0 ; FULL-NEXT: vmov r0, s0
; FULL-NEXT: bl __aeabi_f2lz ; FULL-NEXT: bl __aeabi_f2lz
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
; ;
; VFP2-LABEL: stest_f16i32: ; VFP2-LABEL: stest_f16i32:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
; VFP2-NEXT: push {r7, lr} ; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, s0 ; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_h2f ; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: bl __aeabi_f2lz ; VFP2-NEXT: bl __aeabi_f2lz
; VFP2-NEXT: mvn r2, #-2147483648 ; VFP2-NEXT: mvn r12, #-2147483648
; VFP2-NEXT: subs r3, r0, r2 ; VFP2-NEXT: subs.w r3, r0, r12
; VFP2-NEXT: mov.w r12, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: sbcs r3, r1, #0 ; VFP2-NEXT: sbcs r3, r1, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w r12, #1 ; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp.w r12, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: itt ne ; VFP2-NEXT: ite ne
; VFP2-NEXT: movne r12, r1 ; VFP2-NEXT: movne r2, r1
; VFP2-NEXT: movne r2, r0 ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: mov.w r0, #-1 ; VFP2-NEXT: mov.w r1, #-1
; VFP2-NEXT: rsbs.w r1, r2, #-2147483648 ; VFP2-NEXT: rsbs.w r3, r0, #-2147483648
; VFP2-NEXT: sbcs.w r0, r0, r12 ; VFP2-NEXT: sbcs r1, r2
; VFP2-NEXT: it ge ; VFP2-NEXT: it ge
; VFP2-NEXT: movge.w r2, #-2147483648 ; VFP2-NEXT: movge.w r0, #-2147483648
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: stest_f16i32: ; FULL-LABEL: stest_f16i32:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov.f16 r0, s0 ; FULL-NEXT: vmov.f16 r0, s0
; FULL-NEXT: vmov s0, r0 ; FULL-NEXT: vmov s0, r0
▲ Show 20 Lines • Show All 692 Lines • ▼ Show 20 Lines
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP2-LABEL: stest_f64i64: ; VFP2-LABEL: stest_f64i64:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r4, r5, r7, lr} ; VFP2-NEXT: .save {r4, r5, r7, lr}
; VFP2-NEXT: push {r4, r5, r7, lr} ; VFP2-NEXT: push {r4, r5, r7, lr}
; VFP2-NEXT: bl __fixdfti ; VFP2-NEXT: bl __fixdfti
; VFP2-NEXT: subs.w r4, r0, #-1 ; VFP2-NEXT: subs.w r4, r0, #-1
; VFP2-NEXT: mov r12, r1 ; VFP2-NEXT: mvn lr, #-2147483648
; VFP2-NEXT: mvn r1, #-2147483648 ; VFP2-NEXT: sbcs.w r4, r1, lr
; VFP2-NEXT: sbcs.w r4, r12, r1 ; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: sbcs r4, r2, #0 ; VFP2-NEXT: sbcs r4, r2, #0
; VFP2-NEXT: mov.w lr, #0
; VFP2-NEXT: sbcs r4, r3, #0 ; VFP2-NEXT: sbcs r4, r3, #0
; VFP2-NEXT: mov.w r4, #0 ; VFP2-NEXT: mov.w r4, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r4, #1 ; VFP2-NEXT: movlt r4, #1
; VFP2-NEXT: cmp r4, #0 ; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: itee eq ; VFP2-NEXT: itet eq
; VFP2-NEXT: moveq r3, r4 ; VFP2-NEXT: moveq r3, r4
; VFP2-NEXT: movne r4, r2 ; VFP2-NEXT: movne r4, r2
; VFP2-NEXT: movne r1, r12 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: mov.w r2, #-1 ; VFP2-NEXT: mov.w r2, #-1
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: moveq r0, r2
; VFP2-NEXT: rsbs r5, r0, #0 ; VFP2-NEXT: rsbs r5, r0, #0
; VFP2-NEXT: mov.w r12, #-2147483648 ; VFP2-NEXT: mov.w lr, #-2147483648
; VFP2-NEXT: sbcs.w r5, r12, r1 ; VFP2-NEXT: sbcs.w r5, lr, r1
; VFP2-NEXT: sbcs.w r4, r2, r4 ; VFP2-NEXT: sbcs.w r4, r2, r4
; VFP2-NEXT: sbcs r2, r3 ; VFP2-NEXT: sbcs r2, r3
; VFP2-NEXT: mov.w r2, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #1 ; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp r2, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: itt eq ; VFP2-NEXT: itt eq
; VFP2-NEXT: moveq r0, lr ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: moveq r1, r12 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: pop {r4, r5, r7, pc} ; VFP2-NEXT: pop {r4, r5, r7, pc}
; ;
; FULL-LABEL: stest_f64i64: ; FULL-LABEL: stest_f64i64:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, r5, r7, lr} ; FULL-NEXT: .save {r4, r5, r7, lr}
; FULL-NEXT: push {r4, r5, r7, lr} ; FULL-NEXT: push {r4, r5, r7, lr}
; FULL-NEXT: bl __fixdfti ; FULL-NEXT: bl __fixdfti
; FULL-NEXT: subs.w lr, r0, #-1 ; FULL-NEXT: subs.w lr, r0, #-1
▲ Show 20 Lines • Show All 322 Lines • ▼ Show 20 Lines
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP2-LABEL: stest_f32i64: ; VFP2-LABEL: stest_f32i64:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r4, r5, r7, lr} ; VFP2-NEXT: .save {r4, r5, r7, lr}
; VFP2-NEXT: push {r4, r5, r7, lr} ; VFP2-NEXT: push {r4, r5, r7, lr}
; VFP2-NEXT: bl __fixsfti ; VFP2-NEXT: bl __fixsfti
; VFP2-NEXT: subs.w r4, r0, #-1 ; VFP2-NEXT: subs.w r4, r0, #-1
; VFP2-NEXT: mov r12, r1 ; VFP2-NEXT: mvn lr, #-2147483648
; VFP2-NEXT: mvn r1, #-2147483648 ; VFP2-NEXT: sbcs.w r4, r1, lr
; VFP2-NEXT: sbcs.w r4, r12, r1 ; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: sbcs r4, r2, #0 ; VFP2-NEXT: sbcs r4, r2, #0
; VFP2-NEXT: mov.w lr, #0
; VFP2-NEXT: sbcs r4, r3, #0 ; VFP2-NEXT: sbcs r4, r3, #0
; VFP2-NEXT: mov.w r4, #0 ; VFP2-NEXT: mov.w r4, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r4, #1 ; VFP2-NEXT: movlt r4, #1
; VFP2-NEXT: cmp r4, #0 ; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: itee eq ; VFP2-NEXT: itet eq
; VFP2-NEXT: moveq r3, r4 ; VFP2-NEXT: moveq r3, r4
; VFP2-NEXT: movne r4, r2 ; VFP2-NEXT: movne r4, r2
; VFP2-NEXT: movne r1, r12 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: mov.w r2, #-1 ; VFP2-NEXT: mov.w r2, #-1
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: moveq r0, r2
; VFP2-NEXT: rsbs r5, r0, #0 ; VFP2-NEXT: rsbs r5, r0, #0
; VFP2-NEXT: mov.w r12, #-2147483648 ; VFP2-NEXT: mov.w lr, #-2147483648
; VFP2-NEXT: sbcs.w r5, r12, r1 ; VFP2-NEXT: sbcs.w r5, lr, r1
; VFP2-NEXT: sbcs.w r4, r2, r4 ; VFP2-NEXT: sbcs.w r4, r2, r4
; VFP2-NEXT: sbcs r2, r3 ; VFP2-NEXT: sbcs r2, r3
; VFP2-NEXT: mov.w r2, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #1 ; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp r2, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: itt eq ; VFP2-NEXT: itt eq
; VFP2-NEXT: moveq r0, lr ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: moveq r1, r12 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: pop {r4, r5, r7, pc} ; VFP2-NEXT: pop {r4, r5, r7, pc}
; ;
; FULL-LABEL: stest_f32i64: ; FULL-LABEL: stest_f32i64:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, r5, r7, lr} ; FULL-NEXT: .save {r4, r5, r7, lr}
; FULL-NEXT: push {r4, r5, r7, lr} ; FULL-NEXT: push {r4, r5, r7, lr}
; FULL-NEXT: bl __fixsfti ; FULL-NEXT: bl __fixsfti
; FULL-NEXT: subs.w lr, r0, #-1 ; FULL-NEXT: subs.w lr, r0, #-1
▲ Show 20 Lines • Show All 327 Lines • ▼ Show 20 Lines
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r4, r5, r7, lr} ; VFP2-NEXT: .save {r4, r5, r7, lr}
; VFP2-NEXT: push {r4, r5, r7, lr} ; VFP2-NEXT: push {r4, r5, r7, lr}
; VFP2-NEXT: vmov r0, s0 ; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_h2f ; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: vmov s0, r0 ; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: bl __fixsfti ; VFP2-NEXT: bl __fixsfti
; VFP2-NEXT: subs.w r4, r0, #-1 ; VFP2-NEXT: subs.w r4, r0, #-1
; VFP2-NEXT: mov r12, r1 ; VFP2-NEXT: mvn lr, #-2147483648
; VFP2-NEXT: mvn r1, #-2147483648 ; VFP2-NEXT: sbcs.w r4, r1, lr
; VFP2-NEXT: sbcs.w r4, r12, r1 ; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: sbcs r4, r2, #0 ; VFP2-NEXT: sbcs r4, r2, #0
; VFP2-NEXT: mov.w lr, #0
; VFP2-NEXT: sbcs r4, r3, #0 ; VFP2-NEXT: sbcs r4, r3, #0
; VFP2-NEXT: mov.w r4, #0 ; VFP2-NEXT: mov.w r4, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r4, #1 ; VFP2-NEXT: movlt r4, #1
; VFP2-NEXT: cmp r4, #0 ; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: itee eq ; VFP2-NEXT: itet eq
; VFP2-NEXT: moveq r3, r4 ; VFP2-NEXT: moveq r3, r4
; VFP2-NEXT: movne r4, r2 ; VFP2-NEXT: movne r4, r2
; VFP2-NEXT: movne r1, r12 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: mov.w r2, #-1 ; VFP2-NEXT: mov.w r2, #-1
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: moveq r0, r2
; VFP2-NEXT: rsbs r5, r0, #0 ; VFP2-NEXT: rsbs r5, r0, #0
; VFP2-NEXT: mov.w r12, #-2147483648 ; VFP2-NEXT: mov.w lr, #-2147483648
; VFP2-NEXT: sbcs.w r5, r12, r1 ; VFP2-NEXT: sbcs.w r5, lr, r1
; VFP2-NEXT: sbcs.w r4, r2, r4 ; VFP2-NEXT: sbcs.w r4, r2, r4
; VFP2-NEXT: sbcs r2, r3 ; VFP2-NEXT: sbcs r2, r3
; VFP2-NEXT: mov.w r2, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #1 ; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp r2, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: itt eq ; VFP2-NEXT: itt eq
; VFP2-NEXT: moveq r0, lr ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: moveq r1, r12 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: pop {r4, r5, r7, pc} ; VFP2-NEXT: pop {r4, r5, r7, pc}
; ;
; FULL-LABEL: stest_f16i64: ; FULL-LABEL: stest_f16i64:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, r5, r7, lr} ; FULL-NEXT: .save {r4, r5, r7, lr}
; FULL-NEXT: push {r4, r5, r7, lr} ; FULL-NEXT: push {r4, r5, r7, lr}
; FULL-NEXT: vmov.f16 r0, s0 ; FULL-NEXT: vmov.f16 r0, s0
; FULL-NEXT: vmov s0, r0 ; FULL-NEXT: vmov s0, r0
▲ Show 20 Lines • Show All 325 Lines • ▼ Show 20 Lines
; VFP2-NEXT: vmov r0, r1, d0 ; VFP2-NEXT: vmov r0, r1, d0
; VFP2-NEXT: bl __aeabi_d2lz ; VFP2-NEXT: bl __aeabi_d2lz
; VFP2-NEXT: mvn r2, #-2147483648 ; VFP2-NEXT: mvn r2, #-2147483648
; VFP2-NEXT: cmp r0, r2 ; VFP2-NEXT: cmp r0, r2
; VFP2-NEXT: mvn r3, #-2147483648 ; VFP2-NEXT: mvn r3, #-2147483648
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r3, r0 ; VFP2-NEXT: movlo r3, r0
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it pl
; VFP2-NEXT: movmi r2, r0 ; VFP2-NEXT: movpl r0, r2
; VFP2-NEXT: mov.w r0, #-2147483648 ; VFP2-NEXT: mov.w r2, #-2147483648
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r3 ; VFP2-NEXT: moveq r0, r3
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r1, #0 ; VFP2-NEXT: movpl r1, #0
; VFP2-NEXT: cmp.w r1, #-1 ; VFP2-NEXT: cmp.w r1, #-1
; VFP2-NEXT: mov.w r3, #-2147483648 ; VFP2-NEXT: mov.w r3, #-2147483648
; VFP2-NEXT: it gt ; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r3, r2 ; VFP2-NEXT: movgt r3, r0
; VFP2-NEXT: cmp.w r2, #-2147483648 ; VFP2-NEXT: cmp.w r0, #-2147483648
; VFP2-NEXT: it ls ; VFP2-NEXT: it ls
; VFP2-NEXT: movls r2, r0 ; VFP2-NEXT: movls r0, r2
; VFP2-NEXT: adds r0, r1, #1 ; VFP2-NEXT: adds r1, #1
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r2, r3 ; VFP2-NEXT: movne r0, r3
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: stest_f64i32_mm: ; FULL-LABEL: stest_f64i32_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov r0, r1, d0 ; FULL-NEXT: vmov r0, r1, d0
; FULL-NEXT: bl __aeabi_d2lz ; FULL-NEXT: bl __aeabi_d2lz
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
; VFP2-NEXT: push {r7, lr} ; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, r1, d0 ; VFP2-NEXT: vmov r0, r1, d0
; VFP2-NEXT: bl __aeabi_d2lz ; VFP2-NEXT: bl __aeabi_d2lz
; VFP2-NEXT: mov r2, r0 ; VFP2-NEXT: mov r2, r0
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl.w r2, #-1 ; VFP2-NEXT: movpl.w r2, #-1
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r2, r0 ; VFP2-NEXT: movne r0, r2
; VFP2-NEXT: mov.w r0, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r1, r0 ; VFP2-NEXT: movpl r1, r2
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it gt ; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r0, r2 ; VFP2-NEXT: movgt r2, r0
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: movne r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: ustest_f64i32_mm: ; FULL-LABEL: ustest_f64i32_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov r0, r1, d0 ; FULL-NEXT: vmov r0, r1, d0
; FULL-NEXT: bl __aeabi_d2lz ; FULL-NEXT: bl __aeabi_d2lz
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; VFP2-NEXT: vmov r0, s0 ; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_f2lz ; VFP2-NEXT: bl __aeabi_f2lz
; VFP2-NEXT: mvn r2, #-2147483648 ; VFP2-NEXT: mvn r2, #-2147483648
; VFP2-NEXT: cmp r0, r2 ; VFP2-NEXT: cmp r0, r2
; VFP2-NEXT: mvn r3, #-2147483648 ; VFP2-NEXT: mvn r3, #-2147483648
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r3, r0 ; VFP2-NEXT: movlo r3, r0
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it pl
; VFP2-NEXT: movmi r2, r0 ; VFP2-NEXT: movpl r0, r2
; VFP2-NEXT: mov.w r0, #-2147483648 ; VFP2-NEXT: mov.w r2, #-2147483648
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r3 ; VFP2-NEXT: moveq r0, r3
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r1, #0 ; VFP2-NEXT: movpl r1, #0
; VFP2-NEXT: cmp.w r1, #-1 ; VFP2-NEXT: cmp.w r1, #-1
; VFP2-NEXT: mov.w r3, #-2147483648 ; VFP2-NEXT: mov.w r3, #-2147483648
; VFP2-NEXT: it gt ; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r3, r2 ; VFP2-NEXT: movgt r3, r0
; VFP2-NEXT: cmp.w r2, #-2147483648 ; VFP2-NEXT: cmp.w r0, #-2147483648
; VFP2-NEXT: it ls ; VFP2-NEXT: it ls
; VFP2-NEXT: movls r2, r0 ; VFP2-NEXT: movls r0, r2
; VFP2-NEXT: adds r0, r1, #1 ; VFP2-NEXT: adds r1, #1
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r2, r3 ; VFP2-NEXT: movne r0, r3
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: stest_f32i32_mm: ; FULL-LABEL: stest_f32i32_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov r0, s0 ; FULL-NEXT: vmov r0, s0
; FULL-NEXT: bl __aeabi_f2lz ; FULL-NEXT: bl __aeabi_f2lz
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
; VFP2-NEXT: push {r7, lr} ; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, s0 ; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_f2lz ; VFP2-NEXT: bl __aeabi_f2lz
; VFP2-NEXT: mov r2, r0 ; VFP2-NEXT: mov r2, r0
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl.w r2, #-1 ; VFP2-NEXT: movpl.w r2, #-1
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r2, r0 ; VFP2-NEXT: movne r0, r2
; VFP2-NEXT: mov.w r0, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r1, r0 ; VFP2-NEXT: movpl r1, r2
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it gt ; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r0, r2 ; VFP2-NEXT: movgt r2, r0
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: movne r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: ustest_f32i32_mm: ; FULL-LABEL: ustest_f32i32_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov r0, s0 ; FULL-NEXT: vmov r0, s0
; FULL-NEXT: bl __aeabi_f2lz ; FULL-NEXT: bl __aeabi_f2lz
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; VFP2-NEXT: bl __aeabi_h2f ; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: bl __aeabi_f2lz ; VFP2-NEXT: bl __aeabi_f2lz
; VFP2-NEXT: mvn r2, #-2147483648 ; VFP2-NEXT: mvn r2, #-2147483648
; VFP2-NEXT: cmp r0, r2 ; VFP2-NEXT: cmp r0, r2
; VFP2-NEXT: mvn r3, #-2147483648 ; VFP2-NEXT: mvn r3, #-2147483648
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r3, r0 ; VFP2-NEXT: movlo r3, r0
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it pl
; VFP2-NEXT: movmi r2, r0 ; VFP2-NEXT: movpl r0, r2
; VFP2-NEXT: mov.w r0, #-2147483648 ; VFP2-NEXT: mov.w r2, #-2147483648
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r3 ; VFP2-NEXT: moveq r0, r3
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r1, #0 ; VFP2-NEXT: movpl r1, #0
; VFP2-NEXT: cmp.w r1, #-1 ; VFP2-NEXT: cmp.w r1, #-1
; VFP2-NEXT: mov.w r3, #-2147483648 ; VFP2-NEXT: mov.w r3, #-2147483648
; VFP2-NEXT: it gt ; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r3, r2 ; VFP2-NEXT: movgt r3, r0
; VFP2-NEXT: cmp.w r2, #-2147483648 ; VFP2-NEXT: cmp.w r0, #-2147483648
; VFP2-NEXT: it ls ; VFP2-NEXT: it ls
; VFP2-NEXT: movls r2, r0 ; VFP2-NEXT: movls r0, r2
; VFP2-NEXT: adds r0, r1, #1 ; VFP2-NEXT: adds r1, #1
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r2, r3 ; VFP2-NEXT: movne r0, r3
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: stest_f16i32_mm: ; FULL-LABEL: stest_f16i32_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov.f16 r0, s0 ; FULL-NEXT: vmov.f16 r0, s0
; FULL-NEXT: vmov s0, r0 ; FULL-NEXT: vmov s0, r0
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; VFP2-NEXT: push {r7, lr} ; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, s0 ; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_h2f ; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: bl __aeabi_f2lz ; VFP2-NEXT: bl __aeabi_f2lz
; VFP2-NEXT: mov r2, r0 ; VFP2-NEXT: mov r2, r0
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl.w r2, #-1 ; VFP2-NEXT: movpl.w r2, #-1
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r2, r0 ; VFP2-NEXT: movne r0, r2
; VFP2-NEXT: mov.w r0, #0 ; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r1, r0 ; VFP2-NEXT: movpl r1, r2
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: it gt ; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r0, r2 ; VFP2-NEXT: movgt r2, r0
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: movne r0, r2
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: ustest_f16i32_mm: ; FULL-LABEL: ustest_f16i32_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r7, lr} ; FULL-NEXT: .save {r7, lr}
; FULL-NEXT: push {r7, lr} ; FULL-NEXT: push {r7, lr}
; FULL-NEXT: vmov.f16 r0, s0 ; FULL-NEXT: vmov.f16 r0, s0
; FULL-NEXT: vmov s0, r0 ; FULL-NEXT: vmov s0, r0
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; VFP2-LABEL: stest_f64i16_mm: ; VFP2-LABEL: stest_f64i16_mm:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r7, lr} ; VFP2-NEXT: .save {r7, lr}
; VFP2-NEXT: push {r7, lr} ; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, r1, d0 ; VFP2-NEXT: vmov r0, r1, d0
; VFP2-NEXT: bl __aeabi_d2iz ; VFP2-NEXT: bl __aeabi_d2iz
; VFP2-NEXT: movw r1, #32767 ; VFP2-NEXT: movw r1, #32767
; VFP2-NEXT: cmp r0, r1 ; VFP2-NEXT: cmp r0, r1
; VFP2-NEXT: it lt ; VFP2-NEXT: it ge
; VFP2-NEXT: movlt r1, r0 ; VFP2-NEXT: movge r0, r1
; VFP2-NEXT: movw r0, #32768 ; VFP2-NEXT: movw r1, #32768
; VFP2-NEXT: movt r0, #65535 ; VFP2-NEXT: movt r1, #65535
; VFP2-NEXT: cmn.w r1, #32768 ; VFP2-NEXT: cmn.w r0, #32768
; VFP2-NEXT: it gt ; VFP2-NEXT: it le
; VFP2-NEXT: movgt r0, r1 ; VFP2-NEXT: movle r0, r1
; VFP2-NEXT: pop {r7, pc} ; VFP2-NEXT: pop {r7, pc}
; ;
; FULL-LABEL: stest_f64i16_mm: ; FULL-LABEL: stest_f64i16_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: vcvt.s32.f64 s0, d0 ; FULL-NEXT: vcvt.s32.f64 s0, d0
; FULL-NEXT: movw r1, #32767 ; FULL-NEXT: movw r1, #32767
; FULL-NEXT: vmov r0, s0 ; FULL-NEXT: vmov r0, s0
; FULL-NEXT: cmp r0, r1 ; FULL-NEXT: cmp r0, r1
▲ Show 20 Lines • Show All 597 Lines • ▼ Show 20 Lines
; VFP2-NEXT: cmp.w r4, #-2147483648 ; VFP2-NEXT: cmp.w r4, #-2147483648
; VFP2-NEXT: mov r6, r3 ; VFP2-NEXT: mov r6, r3
; VFP2-NEXT: it hi ; VFP2-NEXT: it hi
; VFP2-NEXT: movhi r1, r4 ; VFP2-NEXT: movhi r1, r4
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: andne.w r6, r2, r6, asr #31 ; VFP2-NEXT: andne.w r6, r2, r6, asr #31
; VFP2-NEXT: and.w r2, r6, r5 ; VFP2-NEXT: and.w r2, r6, r5
; VFP2-NEXT: mov.w lr, #0 ; VFP2-NEXT: mov.w r6, #-1
; VFP2-NEXT: adds r6, r2, #1 ; VFP2-NEXT: adds r2, #1
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r1, r7 ; VFP2-NEXT: movne r1, r7
; VFP2-NEXT: mov.w r7, #-1 ; VFP2-NEXT: mov.w r7, #-1
; VFP2-NEXT: cmp r12, r8 ; VFP2-NEXT: cmp r12, r8
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r7, r0 ; VFP2-NEXT: movlo r7, r0
; VFP2-NEXT: mov.w r2, #-1 ; VFP2-NEXT: mov.w lr, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r7, r0 ; VFP2-NEXT: moveq r7, r0
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it pl
; VFP2-NEXT: movmi r2, r0 ; VFP2-NEXT: movpl r0, r6
; VFP2-NEXT: cmp.w r9, #0 ; VFP2-NEXT: cmp.w r9, #0
; VFP2-NEXT: mov.w r0, #0 ; VFP2-NEXT: mov.w r3, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r7 ; VFP2-NEXT: moveq r0, r7
; VFP2-NEXT: cmp.w r4, #-2147483648 ; VFP2-NEXT: cmp.w r4, #-2147483648
; VFP2-NEXT: it hi ; VFP2-NEXT: it hi
; VFP2-NEXT: movhi r0, r2 ; VFP2-NEXT: movhi r3, r0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: moveq r3, r0
; VFP2-NEXT: cmp.w r5, #-1 ; VFP2-NEXT: cmp.w r5, #-1
; VFP2-NEXT: it le ; VFP2-NEXT: it le
; VFP2-NEXT: movle r2, lr ; VFP2-NEXT: movle r0, lr
; VFP2-NEXT: cmp r6, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r0 ; VFP2-NEXT: moveq r0, r3
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: add sp, #4 ; VFP2-NEXT: add sp, #4
; VFP2-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; VFP2-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
; ;
; FULL-LABEL: stest_f64i64_mm: ; FULL-LABEL: stest_f64i64_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; FULL-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
; FULL-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; FULL-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; FULL-NEXT: .pad #4 ; FULL-NEXT: .pad #4
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Lines
; SOFT-NEXT: b .LBB47_20 ; SOFT-NEXT: b .LBB47_20
; ;
; VFP2-LABEL: ustest_f64i64_mm: ; VFP2-LABEL: ustest_f64i64_mm:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r4, r5, r7, lr} ; VFP2-NEXT: .save {r4, r5, r7, lr}
; VFP2-NEXT: push {r4, r5, r7, lr} ; VFP2-NEXT: push {r4, r5, r7, lr}
; VFP2-NEXT: bl __fixdfti ; VFP2-NEXT: bl __fixdfti
; VFP2-NEXT: subs r4, r2, #1 ; VFP2-NEXT: subs r4, r2, #1
; VFP2-NEXT: mov r12, r1 ; VFP2-NEXT: eor r12, r2, #1
; VFP2-NEXT: eor r1, r2, #1
; VFP2-NEXT: sbcs r4, r3, #0 ; VFP2-NEXT: sbcs r4, r3, #0
; VFP2-NEXT: mov.w lr, #0 ; VFP2-NEXT: orr.w lr, r12, r3
; VFP2-NEXT: orr.w r5, r1, r3 ; VFP2-NEXT: mov.w r4, #0
; VFP2-NEXT: mov.w r5, #1
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w lr, #1 ; VFP2-NEXT: movlt r4, #1
; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r4
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp.w lr, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, lr ; VFP2-NEXT: moveq r0, lr
; VFP2-NEXT: cmp r5, #0 ; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r5 ; VFP2-NEXT: moveq r1, r4
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp.w lr, #0
; VFP2-NEXT: it ne
; VFP2-NEXT: movne lr, r12
; VFP2-NEXT: cmp r5, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq lr, r5 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: mov r12, lr ; VFP2-NEXT: mov lr, r1
; VFP2-NEXT: mov.w r4, #1 ; VFP2-NEXT: mov.w r4, #1
; VFP2-NEXT: ite ne ; VFP2-NEXT: ite ne
; VFP2-NEXT: movne r12, r0 ; VFP2-NEXT: movne lr, r0
; VFP2-NEXT: moveq r12, r0 ; VFP2-NEXT: moveq lr, r0
; VFP2-NEXT: cmp r2, #1 ; VFP2-NEXT: cmp r2, #1
; VFP2-NEXT: mov.w r5, #1
; VFP2-NEXT: mov.w r1, #0
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r5, r2 ; VFP2-NEXT: movlo r5, r2
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it mi
; VFP2-NEXT: movmi r4, r2 ; VFP2-NEXT: movmi r4, r2
; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r4, r5 ; VFP2-NEXT: moveq r4, r5
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r3, r1 ; VFP2-NEXT: movpl r3, r12
; VFP2-NEXT: rsbs r2, r4, #0 ; VFP2-NEXT: rsbs r2, r4, #0
; VFP2-NEXT: sbcs.w r2, r1, r3 ; VFP2-NEXT: sbcs.w r2, r12, r3
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r1, #1 ; VFP2-NEXT: movlt.w r12, #1
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp.w r12, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r1 ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: orrs.w r2, r4, r3 ; VFP2-NEXT: orrs.w r2, r4, r3
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r12 ; VFP2-NEXT: moveq r0, lr
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp.w r12, #0
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r1, lr ; VFP2-NEXT: movne r12, r1
; VFP2-NEXT: cmp r2, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r1, lr ; VFP2-NEXT: movne r1, r12
; VFP2-NEXT: pop {r4, r5, r7, pc} ; VFP2-NEXT: pop {r4, r5, r7, pc}
; ;
; FULL-LABEL: ustest_f64i64_mm: ; FULL-LABEL: ustest_f64i64_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, lr} ; FULL-NEXT: .save {r4, lr}
; FULL-NEXT: push {r4, lr} ; FULL-NEXT: push {r4, lr}
; FULL-NEXT: bl __fixdfti ; FULL-NEXT: bl __fixdfti
; FULL-NEXT: subs.w lr, r2, #1 ; FULL-NEXT: subs.w lr, r2, #1
▲ Show 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
; VFP2-NEXT: cmp.w r4, #-2147483648 ; VFP2-NEXT: cmp.w r4, #-2147483648
; VFP2-NEXT: mov r6, r3 ; VFP2-NEXT: mov r6, r3
; VFP2-NEXT: it hi ; VFP2-NEXT: it hi
; VFP2-NEXT: movhi r1, r4 ; VFP2-NEXT: movhi r1, r4
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: andne.w r6, r2, r6, asr #31 ; VFP2-NEXT: andne.w r6, r2, r6, asr #31
; VFP2-NEXT: and.w r2, r6, r5 ; VFP2-NEXT: and.w r2, r6, r5
; VFP2-NEXT: mov.w lr, #0 ; VFP2-NEXT: mov.w r6, #-1
; VFP2-NEXT: adds r6, r2, #1 ; VFP2-NEXT: adds r2, #1
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r1, r7 ; VFP2-NEXT: movne r1, r7
; VFP2-NEXT: mov.w r7, #-1 ; VFP2-NEXT: mov.w r7, #-1
; VFP2-NEXT: cmp r12, r8 ; VFP2-NEXT: cmp r12, r8
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r7, r0 ; VFP2-NEXT: movlo r7, r0
; VFP2-NEXT: mov.w r2, #-1 ; VFP2-NEXT: mov.w lr, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r7, r0 ; VFP2-NEXT: moveq r7, r0
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it pl
; VFP2-NEXT: movmi r2, r0 ; VFP2-NEXT: movpl r0, r6
; VFP2-NEXT: cmp.w r9, #0 ; VFP2-NEXT: cmp.w r9, #0
; VFP2-NEXT: mov.w r0, #0 ; VFP2-NEXT: mov.w r3, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r7 ; VFP2-NEXT: moveq r0, r7
; VFP2-NEXT: cmp.w r4, #-2147483648 ; VFP2-NEXT: cmp.w r4, #-2147483648
; VFP2-NEXT: it hi ; VFP2-NEXT: it hi
; VFP2-NEXT: movhi r0, r2 ; VFP2-NEXT: movhi r3, r0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: moveq r3, r0
; VFP2-NEXT: cmp.w r5, #-1 ; VFP2-NEXT: cmp.w r5, #-1
; VFP2-NEXT: it le ; VFP2-NEXT: it le
; VFP2-NEXT: movle r2, lr ; VFP2-NEXT: movle r0, lr
; VFP2-NEXT: cmp r6, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r0 ; VFP2-NEXT: moveq r0, r3
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: add sp, #4 ; VFP2-NEXT: add sp, #4
; VFP2-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; VFP2-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
; ;
; FULL-LABEL: stest_f32i64_mm: ; FULL-LABEL: stest_f32i64_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; FULL-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
; FULL-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; FULL-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; FULL-NEXT: .pad #4 ; FULL-NEXT: .pad #4
▲ Show 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
; SOFT-NEXT: b .LBB50_21 ; SOFT-NEXT: b .LBB50_21
; ;
; VFP2-LABEL: ustest_f32i64_mm: ; VFP2-LABEL: ustest_f32i64_mm:
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r4, r5, r7, lr} ; VFP2-NEXT: .save {r4, r5, r7, lr}
; VFP2-NEXT: push {r4, r5, r7, lr} ; VFP2-NEXT: push {r4, r5, r7, lr}
; VFP2-NEXT: bl __fixsfti ; VFP2-NEXT: bl __fixsfti
; VFP2-NEXT: subs r4, r2, #1 ; VFP2-NEXT: subs r4, r2, #1
; VFP2-NEXT: mov r12, r1 ; VFP2-NEXT: eor r12, r2, #1
; VFP2-NEXT: eor r1, r2, #1
; VFP2-NEXT: sbcs r4, r3, #0 ; VFP2-NEXT: sbcs r4, r3, #0
; VFP2-NEXT: mov.w lr, #0 ; VFP2-NEXT: orr.w lr, r12, r3
; VFP2-NEXT: orr.w r5, r1, r3 ; VFP2-NEXT: mov.w r4, #0
; VFP2-NEXT: mov.w r5, #1
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w lr, #1 ; VFP2-NEXT: movlt r4, #1
; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r4
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp.w lr, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, lr ; VFP2-NEXT: moveq r0, lr
; VFP2-NEXT: cmp r5, #0 ; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r5 ; VFP2-NEXT: moveq r1, r4
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp.w lr, #0
; VFP2-NEXT: it ne
; VFP2-NEXT: movne lr, r12
; VFP2-NEXT: cmp r5, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq lr, r5 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: mov r12, lr ; VFP2-NEXT: mov lr, r1
; VFP2-NEXT: mov.w r4, #1 ; VFP2-NEXT: mov.w r4, #1
; VFP2-NEXT: ite ne ; VFP2-NEXT: ite ne
; VFP2-NEXT: movne r12, r0 ; VFP2-NEXT: movne lr, r0
; VFP2-NEXT: moveq r12, r0 ; VFP2-NEXT: moveq lr, r0
; VFP2-NEXT: cmp r2, #1 ; VFP2-NEXT: cmp r2, #1
; VFP2-NEXT: mov.w r5, #1
; VFP2-NEXT: mov.w r1, #0
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r5, r2 ; VFP2-NEXT: movlo r5, r2
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it mi
; VFP2-NEXT: movmi r4, r2 ; VFP2-NEXT: movmi r4, r2
; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r4, r5 ; VFP2-NEXT: moveq r4, r5
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r3, r1 ; VFP2-NEXT: movpl r3, r12
; VFP2-NEXT: rsbs r2, r4, #0 ; VFP2-NEXT: rsbs r2, r4, #0
; VFP2-NEXT: sbcs.w r2, r1, r3 ; VFP2-NEXT: sbcs.w r2, r12, r3
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r1, #1 ; VFP2-NEXT: movlt.w r12, #1
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp.w r12, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r1 ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: orrs.w r2, r4, r3 ; VFP2-NEXT: orrs.w r2, r4, r3
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r12 ; VFP2-NEXT: moveq r0, lr
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp.w r12, #0
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r1, lr ; VFP2-NEXT: movne r12, r1
; VFP2-NEXT: cmp r2, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r1, lr ; VFP2-NEXT: movne r1, r12
; VFP2-NEXT: pop {r4, r5, r7, pc} ; VFP2-NEXT: pop {r4, r5, r7, pc}
; ;
; FULL-LABEL: ustest_f32i64_mm: ; FULL-LABEL: ustest_f32i64_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, lr} ; FULL-NEXT: .save {r4, lr}
; FULL-NEXT: push {r4, lr} ; FULL-NEXT: push {r4, lr}
; FULL-NEXT: bl __fixsfti ; FULL-NEXT: bl __fixsfti
; FULL-NEXT: subs.w lr, r2, #1 ; FULL-NEXT: subs.w lr, r2, #1
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
; VFP2-NEXT: cmp.w r4, #-2147483648 ; VFP2-NEXT: cmp.w r4, #-2147483648
; VFP2-NEXT: mov r6, r3 ; VFP2-NEXT: mov r6, r3
; VFP2-NEXT: it hi ; VFP2-NEXT: it hi
; VFP2-NEXT: movhi r1, r4 ; VFP2-NEXT: movhi r1, r4
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: andne.w r6, r2, r6, asr #31 ; VFP2-NEXT: andne.w r6, r2, r6, asr #31
; VFP2-NEXT: and.w r2, r6, r5 ; VFP2-NEXT: and.w r2, r6, r5
; VFP2-NEXT: mov.w lr, #0 ; VFP2-NEXT: mov.w r6, #-1
; VFP2-NEXT: adds r6, r2, #1 ; VFP2-NEXT: adds r2, #1
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r1, r7 ; VFP2-NEXT: movne r1, r7
; VFP2-NEXT: mov.w r7, #-1 ; VFP2-NEXT: mov.w r7, #-1
; VFP2-NEXT: cmp r12, r8 ; VFP2-NEXT: cmp r12, r8
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r7, r0 ; VFP2-NEXT: movlo r7, r0
; VFP2-NEXT: mov.w r2, #-1 ; VFP2-NEXT: mov.w lr, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r7, r0 ; VFP2-NEXT: moveq r7, r0
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it pl
; VFP2-NEXT: movmi r2, r0 ; VFP2-NEXT: movpl r0, r6
; VFP2-NEXT: cmp.w r9, #0 ; VFP2-NEXT: cmp.w r9, #0
; VFP2-NEXT: mov.w r0, #0 ; VFP2-NEXT: mov.w r3, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r7 ; VFP2-NEXT: moveq r0, r7
; VFP2-NEXT: cmp.w r4, #-2147483648 ; VFP2-NEXT: cmp.w r4, #-2147483648
; VFP2-NEXT: it hi ; VFP2-NEXT: it hi
; VFP2-NEXT: movhi r0, r2 ; VFP2-NEXT: movhi r3, r0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r2 ; VFP2-NEXT: moveq r3, r0
; VFP2-NEXT: cmp.w r5, #-1 ; VFP2-NEXT: cmp.w r5, #-1
; VFP2-NEXT: it le ; VFP2-NEXT: it le
; VFP2-NEXT: movle r2, lr ; VFP2-NEXT: movle r0, lr
; VFP2-NEXT: cmp r6, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r2, r0 ; VFP2-NEXT: moveq r0, r3
; VFP2-NEXT: mov r0, r2
; VFP2-NEXT: add sp, #4 ; VFP2-NEXT: add sp, #4
; VFP2-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; VFP2-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
; ;
; FULL-LABEL: stest_f16i64_mm: ; FULL-LABEL: stest_f16i64_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; FULL-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
; FULL-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; FULL-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; FULL-NEXT: .pad #4 ; FULL-NEXT: .pad #4
▲ Show 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
; VFP2: @ %bb.0: @ %entry ; VFP2: @ %bb.0: @ %entry
; VFP2-NEXT: .save {r4, r5, r7, lr} ; VFP2-NEXT: .save {r4, r5, r7, lr}
; VFP2-NEXT: push {r4, r5, r7, lr} ; VFP2-NEXT: push {r4, r5, r7, lr}
; VFP2-NEXT: vmov r0, s0 ; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_h2f ; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: vmov s0, r0 ; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: bl __fixsfti ; VFP2-NEXT: bl __fixsfti
; VFP2-NEXT: subs r4, r2, #1 ; VFP2-NEXT: subs r4, r2, #1
; VFP2-NEXT: mov r12, r1 ; VFP2-NEXT: eor r12, r2, #1
; VFP2-NEXT: eor r1, r2, #1
; VFP2-NEXT: sbcs r4, r3, #0 ; VFP2-NEXT: sbcs r4, r3, #0
; VFP2-NEXT: mov.w lr, #0 ; VFP2-NEXT: orr.w lr, r12, r3
; VFP2-NEXT: orr.w r5, r1, r3 ; VFP2-NEXT: mov.w r4, #0
; VFP2-NEXT: mov.w r5, #1
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w lr, #1 ; VFP2-NEXT: movlt r4, #1
; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r4
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp.w lr, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, lr ; VFP2-NEXT: moveq r0, lr
; VFP2-NEXT: cmp r5, #0 ; VFP2-NEXT: cmp r4, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r5 ; VFP2-NEXT: moveq r1, r4
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp.w lr, #0
; VFP2-NEXT: it ne
; VFP2-NEXT: movne lr, r12
; VFP2-NEXT: cmp r5, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq lr, r5 ; VFP2-NEXT: moveq r1, lr
; VFP2-NEXT: cmp.w lr, #0 ; VFP2-NEXT: cmp r1, #0
; VFP2-NEXT: mov r12, lr ; VFP2-NEXT: mov lr, r1
; VFP2-NEXT: mov.w r4, #1 ; VFP2-NEXT: mov.w r4, #1
; VFP2-NEXT: ite ne ; VFP2-NEXT: ite ne
; VFP2-NEXT: movne r12, r0 ; VFP2-NEXT: movne lr, r0
; VFP2-NEXT: moveq r12, r0 ; VFP2-NEXT: moveq lr, r0
; VFP2-NEXT: cmp r2, #1 ; VFP2-NEXT: cmp r2, #1
; VFP2-NEXT: mov.w r5, #1
; VFP2-NEXT: mov.w r1, #0
; VFP2-NEXT: it lo ; VFP2-NEXT: it lo
; VFP2-NEXT: movlo r5, r2 ; VFP2-NEXT: movlo r5, r2
; VFP2-NEXT: cmp r3, #0 ; VFP2-NEXT: cmp r3, #0
; VFP2-NEXT: it mi ; VFP2-NEXT: it mi
; VFP2-NEXT: movmi r4, r2 ; VFP2-NEXT: movmi r4, r2
; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r4, r5 ; VFP2-NEXT: moveq r4, r5
; VFP2-NEXT: it pl ; VFP2-NEXT: it pl
; VFP2-NEXT: movpl r3, r1 ; VFP2-NEXT: movpl r3, r12
; VFP2-NEXT: rsbs r2, r4, #0 ; VFP2-NEXT: rsbs r2, r4, #0
; VFP2-NEXT: sbcs.w r2, r1, r3 ; VFP2-NEXT: sbcs.w r2, r12, r3
; VFP2-NEXT: it lt ; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r1, #1 ; VFP2-NEXT: movlt.w r12, #1
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp.w r12, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r1 ; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: orrs.w r2, r4, r3 ; VFP2-NEXT: orrs.w r2, r4, r3
; VFP2-NEXT: it eq ; VFP2-NEXT: it eq
; VFP2-NEXT: moveq r0, r12 ; VFP2-NEXT: moveq r0, lr
; VFP2-NEXT: cmp r1, #0 ; VFP2-NEXT: cmp.w r12, #0
; VFP2-NEXT: it ne ; VFP2-NEXT: it ne
; VFP2-NEXT: movne r1, lr ; VFP2-NEXT: movne r12, r1
; VFP2-NEXT: cmp r2, #0 ; VFP2-NEXT: cmp r2, #0
; VFP2-NEXT: it eq ; VFP2-NEXT: it ne
; VFP2-NEXT: moveq r1, lr ; VFP2-NEXT: movne r1, r12
; VFP2-NEXT: pop {r4, r5, r7, pc} ; VFP2-NEXT: pop {r4, r5, r7, pc}
; ;
; FULL-LABEL: ustest_f16i64_mm: ; FULL-LABEL: ustest_f16i64_mm:
; FULL: @ %bb.0: @ %entry ; FULL: @ %bb.0: @ %entry
; FULL-NEXT: .save {r4, lr} ; FULL-NEXT: .save {r4, lr}
; FULL-NEXT: push {r4, lr} ; FULL-NEXT: push {r4, lr}
; FULL-NEXT: vmov.f16 r0, s0 ; FULL-NEXT: vmov.f16 r0, s0
; FULL-NEXT: vmov s0, r0 ; FULL-NEXT: vmov s0, r0
▲ Show 20 Lines • Show All 587 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

Show All 26 Lines
; ARM-NEXT: eor r0, r1, r0, lsr #7 ; ARM-NEXT: eor r0, r1, r0, lsr #7
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i8_signbit_eq: ; THUMB6-LABEL: scalar_i8_signbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: uxtb r1, r1 ; THUMB6-NEXT: uxtb r1, r1
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #128 ; THUMB6-NEXT: movs r1, #128
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i8_signbit_eq: ; THUMB78-LABEL: scalar_i8_signbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: uxtb r1, r1 ; THUMB78-NEXT: uxtb r1, r1
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: movs r1, #1 ; THUMB78-NEXT: movs r1, #1
Show All 14 Lines
; ARM-NEXT: bic r0, r2, r0, lsl r1 ; ARM-NEXT: bic r0, r2, r0, lsl r1
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i8_lowestbit_eq: ; THUMB6-LABEL: scalar_i8_lowestbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: uxtb r1, r1 ; THUMB6-NEXT: uxtb r1, r1
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i8_lowestbit_eq: ; THUMB78-LABEL: scalar_i8_lowestbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: uxtb r1, r1 ; THUMB78-NEXT: uxtb r1, r1
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: movs r1, #1 ; THUMB78-NEXT: movs r1, #1
Show All 15 Lines
; ARM-NEXT: lsr r0, r0, #5 ; ARM-NEXT: lsr r0, r0, #5
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq: ; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: uxtb r1, r1 ; THUMB6-NEXT: uxtb r1, r1
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #24 ; THUMB6-NEXT: movs r1, #24
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq: ; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: uxtb r1, r1 ; THUMB78-NEXT: uxtb r1, r1
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: and r0, r0, #24 ; THUMB78-NEXT: and r0, r0, #24
Show All 19 Lines
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i16_signbit_eq: ; THUMB6-LABEL: scalar_i16_signbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: uxth r1, r1 ; THUMB6-NEXT: uxth r1, r1
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: lsls r1, r1, #15 ; THUMB6-NEXT: lsls r1, r1, #15
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i16_signbit_eq: ; THUMB78-LABEL: scalar_i16_signbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: uxth r1, r1 ; THUMB78-NEXT: uxth r1, r1
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: movs r1, #1 ; THUMB78-NEXT: movs r1, #1
Show All 14 Lines
; ARM-NEXT: bic r0, r2, r0, lsl r1 ; ARM-NEXT: bic r0, r2, r0, lsl r1
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i16_lowestbit_eq: ; THUMB6-LABEL: scalar_i16_lowestbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: uxth r1, r1 ; THUMB6-NEXT: uxth r1, r1
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i16_lowestbit_eq: ; THUMB78-LABEL: scalar_i16_lowestbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: uxth r1, r1 ; THUMB78-NEXT: uxth r1, r1
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: movs r1, #1 ; THUMB78-NEXT: movs r1, #1
Show All 16 Lines
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq: ; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: uxth r1, r1 ; THUMB6-NEXT: uxth r1, r1
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #255 ; THUMB6-NEXT: movs r1, #255
; THUMB6-NEXT: lsls r1, r1, #4 ; THUMB6-NEXT: lsls r1, r1, #4
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq: ; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: uxth r1, r1 ; THUMB78-NEXT: uxth r1, r1
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: and r0, r0, #4080 ; THUMB78-NEXT: and r0, r0, #4080
Show All 15 Lines
; ARM-NEXT: lsr r0, r0, #31 ; ARM-NEXT: lsr r0, r0, #31
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i32_signbit_eq: ; THUMB6-LABEL: scalar_i32_signbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: lsls r1, r1, #31 ; THUMB6-NEXT: lsls r1, r1, #31
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i32_signbit_eq: ; THUMB78-LABEL: scalar_i32_signbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: mvns r0, r0 ; THUMB78-NEXT: mvns r0, r0
; THUMB78-NEXT: lsrs r0, r0, #31 ; THUMB78-NEXT: lsrs r0, r0, #31
Show All 10 Lines
; ARM-NEXT: mov r2, #1 ; ARM-NEXT: mov r2, #1
; ARM-NEXT: bic r0, r2, r0, lsl r1 ; ARM-NEXT: bic r0, r2, r0, lsl r1
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i32_lowestbit_eq: ; THUMB6-LABEL: scalar_i32_lowestbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i32_lowestbit_eq: ; THUMB78-LABEL: scalar_i32_lowestbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: lsls r0, r1 ; THUMB78-NEXT: lsls r0, r1
; THUMB78-NEXT: movs r1, #1 ; THUMB78-NEXT: movs r1, #1
; THUMB78-NEXT: bic.w r0, r1, r0 ; THUMB78-NEXT: bic.w r0, r1, r0
Show All 22 Lines
; ARM78-NEXT: clz r0, r0 ; ARM78-NEXT: clz r0, r0
; ARM78-NEXT: lsr r0, r0, #5 ; ARM78-NEXT: lsr r0, r0, #5
; ARM78-NEXT: bx lr ; ARM78-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq: ; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: lsls r0, r1 ; THUMB6-NEXT: lsls r0, r1
; THUMB6-NEXT: ldr r1, .LCPI8_0 ; THUMB6-NEXT: ldr r1, .LCPI8_0
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; THUMB6-NEXT: .p2align 2 ; THUMB6-NEXT: .p2align 2
; THUMB6-NEXT: @ %bb.1: ; THUMB6-NEXT: @ %bb.1:
; THUMB6-NEXT: .LCPI8_0: ; THUMB6-NEXT: .LCPI8_0:
; THUMB6-NEXT: .long 16776960 @ 0xffff00 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
; ;
; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq: ; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; ARM78-NEXT: bic r0, r1, r0 ; ARM78-NEXT: bic r0, r1, r0
; ARM78-NEXT: bx lr ; ARM78-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i64_lowestbit_eq: ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: push {r7, lr} ; THUMB6-NEXT: push {r7, lr}
; THUMB6-NEXT: bl __ashldi3 ; THUMB6-NEXT: bl __ashldi3
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: pop {r7, pc} ; THUMB6-NEXT: pop {r7, pc}
; ;
; THUMB78-LABEL: scalar_i64_lowestbit_eq: ; THUMB78-LABEL: scalar_i64_lowestbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: lsls r0, r2 ; THUMB78-NEXT: lsls r0, r2
; THUMB78-NEXT: subs.w r1, r2, #32 ; THUMB78-NEXT: subs.w r1, r2, #32
; THUMB78-NEXT: it pl ; THUMB78-NEXT: it pl
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
; THUMB6-NEXT: lsls r1, r0 ; THUMB6-NEXT: lsls r1, r0
; THUMB6-NEXT: movs r0, #1 ; THUMB6-NEXT: movs r0, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r1, r0
; THUMB6-NEXT: rsbs r4, r1, #0 ; THUMB6-NEXT: rsbs r4, r1, #0
; THUMB6-NEXT: adcs r1, r4 ; THUMB6-NEXT: adcs r1, r4
; THUMB6-NEXT: ldr r4, [sp, #16] ; THUMB6-NEXT: ldr r4, [sp, #16]
; THUMB6-NEXT: lsls r2, r4 ; THUMB6-NEXT: lsls r2, r4
; THUMB6-NEXT: ldr r4, .LCPI13_0 ; THUMB6-NEXT: ldr r4, .LCPI13_0
; THUMB6-NEXT: ands r4, r2 ; THUMB6-NEXT: ands r2, r4
; THUMB6-NEXT: rsbs r2, r4, #0 ; THUMB6-NEXT: rsbs r4, r2, #0
; THUMB6-NEXT: adcs r2, r4 ; THUMB6-NEXT: adcs r2, r4
; THUMB6-NEXT: ldr r4, [sp, #20] ; THUMB6-NEXT: ldr r4, [sp, #20]
; THUMB6-NEXT: lsls r3, r4 ; THUMB6-NEXT: lsls r3, r4
; THUMB6-NEXT: lsls r4, r0, #31 ; THUMB6-NEXT: lsls r4, r0, #31
; THUMB6-NEXT: ands r4, r3 ; THUMB6-NEXT: ands r3, r4
; THUMB6-NEXT: rsbs r3, r4, #0 ; THUMB6-NEXT: rsbs r4, r3, #0
; THUMB6-NEXT: adcs r3, r4 ; THUMB6-NEXT: adcs r3, r4
; THUMB6-NEXT: pop {r4, pc} ; THUMB6-NEXT: pop {r4, pc}
; THUMB6-NEXT: .p2align 2 ; THUMB6-NEXT: .p2align 2
; THUMB6-NEXT: @ %bb.1: ; THUMB6-NEXT: @ %bb.1:
; THUMB6-NEXT: .LCPI13_0: ; THUMB6-NEXT: .LCPI13_0:
; THUMB6-NEXT: .long 16776960 @ 0xffff00 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
; ;
; THUMB78-LABEL: vec_4xi32_nonsplat_eq: ; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
▲ Show 20 Lines • Show All 427 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

Show First 20 Lines • Show All 297 Lines • ▼ Show 20 Lines
; ARM-NEXT: lsr r0, r0, #31 ; ARM-NEXT: lsr r0, r0, #31
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i32_signbit_eq: ; THUMB6-LABEL: scalar_i32_signbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: lsrs r0, r1 ; THUMB6-NEXT: lsrs r0, r1
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: lsls r1, r1, #31 ; THUMB6-NEXT: lsls r1, r1, #31
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i32_signbit_eq: ; THUMB78-LABEL: scalar_i32_signbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: lsrs r0, r1 ; THUMB78-NEXT: lsrs r0, r1
; THUMB78-NEXT: mvns r0, r0 ; THUMB78-NEXT: mvns r0, r0
; THUMB78-NEXT: lsrs r0, r0, #31 ; THUMB78-NEXT: lsrs r0, r0, #31
Show All 10 Lines
; ARM-NEXT: mov r2, #1 ; ARM-NEXT: mov r2, #1
; ARM-NEXT: bic r0, r2, r0, lsr r1 ; ARM-NEXT: bic r0, r2, r0, lsr r1
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i32_lowestbit_eq: ; THUMB6-LABEL: scalar_i32_lowestbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: lsrs r0, r1 ; THUMB6-NEXT: lsrs r0, r1
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; ;
; THUMB78-LABEL: scalar_i32_lowestbit_eq: ; THUMB78-LABEL: scalar_i32_lowestbit_eq:
; THUMB78: @ %bb.0: ; THUMB78: @ %bb.0:
; THUMB78-NEXT: lsrs r0, r1 ; THUMB78-NEXT: lsrs r0, r1
; THUMB78-NEXT: movs r1, #1 ; THUMB78-NEXT: movs r1, #1
; THUMB78-NEXT: bic.w r0, r1, r0 ; THUMB78-NEXT: bic.w r0, r1, r0
Show All 22 Lines
; ARM78-NEXT: clz r0, r0 ; ARM78-NEXT: clz r0, r0
; ARM78-NEXT: lsr r0, r0, #5 ; ARM78-NEXT: lsr r0, r0, #5
; ARM78-NEXT: bx lr ; ARM78-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq: ; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: lsrs r0, r1 ; THUMB6-NEXT: lsrs r0, r1
; THUMB6-NEXT: ldr r1, .LCPI8_0 ; THUMB6-NEXT: ldr r1, .LCPI8_0
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: bx lr ; THUMB6-NEXT: bx lr
; THUMB6-NEXT: .p2align 2 ; THUMB6-NEXT: .p2align 2
; THUMB6-NEXT: @ %bb.1: ; THUMB6-NEXT: @ %bb.1:
; THUMB6-NEXT: .LCPI8_0: ; THUMB6-NEXT: .LCPI8_0:
; THUMB6-NEXT: .long 16776960 @ 0xffff00 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
; ;
; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq: ; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; ARM-NEXT: bic r0, r1, r0 ; ARM-NEXT: bic r0, r1, r0
; ARM-NEXT: bx lr ; ARM-NEXT: bx lr
; ;
; THUMB6-LABEL: scalar_i64_lowestbit_eq: ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
; THUMB6: @ %bb.0: ; THUMB6: @ %bb.0:
; THUMB6-NEXT: push {r7, lr} ; THUMB6-NEXT: push {r7, lr}
; THUMB6-NEXT: bl __lshrdi3 ; THUMB6-NEXT: bl __lshrdi3
; THUMB6-NEXT: movs r1, #1 ; THUMB6-NEXT: movs r1, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r0, r1
; THUMB6-NEXT: rsbs r0, r1, #0 ; THUMB6-NEXT: rsbs r1, r0, #0
; THUMB6-NEXT: adcs r0, r1 ; THUMB6-NEXT: adcs r0, r1
; THUMB6-NEXT: pop {r7, pc} ; THUMB6-NEXT: pop {r7, pc}
; ;
; THUMB7-LABEL: scalar_i64_lowestbit_eq: ; THUMB7-LABEL: scalar_i64_lowestbit_eq:
; THUMB7: @ %bb.0: ; THUMB7: @ %bb.0:
; THUMB7-NEXT: rsb.w r3, r2, #32 ; THUMB7-NEXT: rsb.w r3, r2, #32
; THUMB7-NEXT: lsrs r0, r2 ; THUMB7-NEXT: lsrs r0, r2
; THUMB7-NEXT: subs r2, #32 ; THUMB7-NEXT: subs r2, #32
▲ Show 20 Lines • Show All 236 Lines • ▼ Show 20 Lines
; THUMB6-NEXT: lsrs r1, r0 ; THUMB6-NEXT: lsrs r1, r0
; THUMB6-NEXT: movs r0, #1 ; THUMB6-NEXT: movs r0, #1
; THUMB6-NEXT: ands r1, r0 ; THUMB6-NEXT: ands r1, r0
; THUMB6-NEXT: rsbs r4, r1, #0 ; THUMB6-NEXT: rsbs r4, r1, #0
; THUMB6-NEXT: adcs r1, r4 ; THUMB6-NEXT: adcs r1, r4
; THUMB6-NEXT: ldr r4, [sp, #16] ; THUMB6-NEXT: ldr r4, [sp, #16]
; THUMB6-NEXT: lsrs r2, r4 ; THUMB6-NEXT: lsrs r2, r4
; THUMB6-NEXT: ldr r4, .LCPI13_0 ; THUMB6-NEXT: ldr r4, .LCPI13_0
; THUMB6-NEXT: ands r4, r2 ; THUMB6-NEXT: ands r2, r4
; THUMB6-NEXT: rsbs r2, r4, #0 ; THUMB6-NEXT: rsbs r4, r2, #0
; THUMB6-NEXT: adcs r2, r4 ; THUMB6-NEXT: adcs r2, r4
; THUMB6-NEXT: ldr r4, [sp, #20] ; THUMB6-NEXT: ldr r4, [sp, #20]
; THUMB6-NEXT: lsrs r3, r4 ; THUMB6-NEXT: lsrs r3, r4
; THUMB6-NEXT: lsls r4, r0, #31 ; THUMB6-NEXT: lsls r4, r0, #31
; THUMB6-NEXT: ands r4, r3 ; THUMB6-NEXT: ands r3, r4
; THUMB6-NEXT: rsbs r3, r4, #0 ; THUMB6-NEXT: rsbs r4, r3, #0
; THUMB6-NEXT: adcs r3, r4 ; THUMB6-NEXT: adcs r3, r4
; THUMB6-NEXT: pop {r4, pc} ; THUMB6-NEXT: pop {r4, pc}
; THUMB6-NEXT: .p2align 2 ; THUMB6-NEXT: .p2align 2
; THUMB6-NEXT: @ %bb.1: ; THUMB6-NEXT: @ %bb.1:
; THUMB6-NEXT: .LCPI13_0: ; THUMB6-NEXT: .LCPI13_0:
; THUMB6-NEXT: .long 16776960 @ 0xffff00 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
; ;
; THUMB78-LABEL: vec_4xi32_nonsplat_eq: ; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
▲ Show 20 Lines • Show All 464 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/ssat.ll

Show All 15 Lines
; x < -k ? -k : (x > k ? k : x) ; x < -k ? -k : (x > k ? k : x)
; 32-bit base test ; 32-bit base test
define i32 @sat_base_32bit(i32 %x) #0 { define i32 @sat_base_32bit(i32 %x) #0 {
; V4T-LABEL: sat_base_32bit: ; V4T-LABEL: sat_base_32bit:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: ldr r1, .LCPI0_0 ; V4T-NEXT: ldr r1, .LCPI0_0
; V4T-NEXT: cmp r0, r1 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movlt r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, #1065353216 ; V4T-NEXT: mov r1, #1065353216
; V4T-NEXT: orr r0, r0, #-1073741824 ; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r1, #8388608 ; V4T-NEXT: cmn r0, #8388608
; V4T-NEXT: movgt r0, r1 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI0_0: ; V4T-NEXT: .LCPI0_0:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: sat_base_32bit: ; V6T2-LABEL: sat_base_32bit:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
Show All 12 Lines
define i16 @sat_base_16bit(i16 %x) #0 { define i16 @sat_base_16bit(i16 %x) #0 {
; V4T-LABEL: sat_base_16bit: ; V4T-LABEL: sat_base_16bit:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: mov r2, #255 ; V4T-NEXT: mov r2, #255
; V4T-NEXT: lsl r1, r0, #16 ; V4T-NEXT: lsl r1, r0, #16
; V4T-NEXT: orr r2, r2, #1792 ; V4T-NEXT: orr r2, r2, #1792
; V4T-NEXT: asr r1, r1, #16 ; V4T-NEXT: asr r1, r1, #16
; V4T-NEXT: cmp r1, r2 ; V4T-NEXT: cmp r1, r2
; V4T-NEXT: movlt r2, r0 ; V4T-NEXT: movge r0, r2
; V4T-NEXT: lsl r0, r2, #16 ; V4T-NEXT: ldr r2, .LCPI1_0
; V4T-NEXT: asr r1, r0, #16 ; V4T-NEXT: lsl r1, r0, #16
; V4T-NEXT: ldr r0, .LCPI1_0 ; V4T-NEXT: asr r1, r1, #16
; V4T-NEXT: cmn r1, #2048 ; V4T-NEXT: cmn r1, #2048
; V4T-NEXT: movgt r0, r2 ; V4T-NEXT: movle r0, r2
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI1_0: ; V4T-NEXT: .LCPI1_0:
; V4T-NEXT: .long 4294965248 @ 0xfffff800 ; V4T-NEXT: .long 4294965248 @ 0xfffff800
; ;
; V6T2-LABEL: sat_base_16bit: ; V6T2-LABEL: sat_base_16bit:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
; V6T2-NEXT: sxth r1, r0 ; V6T2-NEXT: sxth r1, r0
; V6T2-NEXT: movw r2, #2047 ; V6T2-NEXT: movw r2, #2047
; V6T2-NEXT: cmp r1, r2 ; V6T2-NEXT: cmp r1, r2
; V6T2-NEXT: movlt r2, r0 ; V6T2-NEXT: movge r0, r2
; V6T2-NEXT: movw r0, #63488 ; V6T2-NEXT: movw r2, #63488
; V6T2-NEXT: sxth r1, r2 ; V6T2-NEXT: sxth r1, r0
; V6T2-NEXT: movt r0, #65535 ; V6T2-NEXT: movt r2, #65535
; V6T2-NEXT: cmn r1, #2048 ; V6T2-NEXT: cmn r1, #2048
; V6T2-NEXT: movgt r0, r2 ; V6T2-NEXT: movle r0, r2
; V6T2-NEXT: bx lr ; V6T2-NEXT: bx lr
entry: entry:
%0 = icmp slt i16 %x, 2047 %0 = icmp slt i16 %x, 2047
%saturateUp = select i1 %0, i16 %x, i16 2047 %saturateUp = select i1 %0, i16 %x, i16 2047
%1 = icmp sgt i16 %saturateUp, -2048 %1 = icmp sgt i16 %saturateUp, -2048
%saturateLow = select i1 %1, i16 %saturateUp, i16 -2048 %saturateLow = select i1 %1, i16 %saturateUp, i16 -2048
ret i16 %saturateLow ret i16 %saturateLow
} }
Show All 37 Lines
; ;
; x < -k ? -k : (x < k ? x : k) ; x < -k ? -k : (x < k ? x : k)
define i32 @sat_lower_upper_1(i32 %x) #0 { define i32 @sat_lower_upper_1(i32 %x) #0 {
; V4T-LABEL: sat_lower_upper_1: ; V4T-LABEL: sat_lower_upper_1:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: ldr r1, .LCPI3_0 ; V4T-NEXT: ldr r1, .LCPI3_0
; V4T-NEXT: cmp r0, r1 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movlt r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, #1065353216 ; V4T-NEXT: mov r1, #1065353216
; V4T-NEXT: orr r0, r0, #-1073741824 ; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r1, #8388608 ; V4T-NEXT: cmn r0, #8388608
; V4T-NEXT: movgt r0, r1 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI3_0: ; V4T-NEXT: .LCPI3_0:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: sat_lower_upper_1: ; V6T2-LABEL: sat_lower_upper_1:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
; V6T2-NEXT: ssat r0, #24, r0 ; V6T2-NEXT: ssat r0, #24, r0
; V6T2-NEXT: bx lr ; V6T2-NEXT: bx lr
entry: entry:
%cmpUp = icmp slt i32 %x, 8388607 %cmpUp = icmp slt i32 %x, 8388607
%saturateUp = select i1 %cmpUp, i32 %x, i32 8388607 %saturateUp = select i1 %cmpUp, i32 %x, i32 8388607
%0 = icmp sgt i32 %saturateUp, -8388608 %0 = icmp sgt i32 %saturateUp, -8388608
%saturateLow = select i1 %0, i32 %saturateUp, i32 -8388608 %saturateLow = select i1 %0, i32 %saturateUp, i32 -8388608
ret i32 %saturateLow ret i32 %saturateLow
} }
; x > -k ? (x > k ? k : x) : -k ; x > -k ? (x > k ? k : x) : -k
define i32 @sat_lower_upper_2(i32 %x) #0 { define i32 @sat_lower_upper_2(i32 %x) #0 {
; V4T-LABEL: sat_lower_upper_2: ; V4T-LABEL: sat_lower_upper_2:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: ldr r1, .LCPI4_0 ; V4T-NEXT: ldr r1, .LCPI4_0
; V4T-NEXT: cmp r0, r1 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movlt r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, #1065353216 ; V4T-NEXT: mov r1, #1065353216
; V4T-NEXT: orr r0, r0, #-1073741824 ; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r1, #8388608 ; V4T-NEXT: cmn r0, #8388608
; V4T-NEXT: movgt r0, r1 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI4_0: ; V4T-NEXT: .LCPI4_0:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: sat_lower_upper_2: ; V6T2-LABEL: sat_lower_upper_2:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
Show All 9 Lines
; x < k ? (x < -k ? -k : x) : k ; x < k ? (x < -k ? -k : x) : k
define i32 @sat_upper_lower_1(i32 %x) #0 { define i32 @sat_upper_lower_1(i32 %x) #0 {
; V4T-LABEL: sat_upper_lower_1: ; V4T-LABEL: sat_upper_lower_1:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: mov r1, #1065353216 ; V4T-NEXT: mov r1, #1065353216
; V4T-NEXT: cmn r0, #8388608 ; V4T-NEXT: cmn r0, #8388608
; V4T-NEXT: orr r1, r1, #-1073741824 ; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movgt r1, r0 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: ldr r0, .LCPI5_0 ; V4T-NEXT: ldr r1, .LCPI5_0
; V4T-NEXT: cmp r1, r0 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movge r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI5_0: ; V4T-NEXT: .LCPI5_0:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: sat_upper_lower_1: ; V6T2-LABEL: sat_upper_lower_1:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
Show All 9 Lines
; x > k ? k : (x < -k ? -k : x) ; x > k ? k : (x < -k ? -k : x)
define i32 @sat_upper_lower_2(i32 %x) #0 { define i32 @sat_upper_lower_2(i32 %x) #0 {
; V4T-LABEL: sat_upper_lower_2: ; V4T-LABEL: sat_upper_lower_2:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: mov r1, #1065353216 ; V4T-NEXT: mov r1, #1065353216
; V4T-NEXT: cmn r0, #8388608 ; V4T-NEXT: cmn r0, #8388608
; V4T-NEXT: orr r1, r1, #-1073741824 ; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movgt r1, r0 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: ldr r0, .LCPI6_0 ; V4T-NEXT: ldr r1, .LCPI6_0
; V4T-NEXT: cmp r1, r0 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movge r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI6_0: ; V4T-NEXT: .LCPI6_0:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: sat_upper_lower_2: ; V6T2-LABEL: sat_upper_lower_2:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
Show All 9 Lines
; k < x ? k : (x > -k ? x : -k) ; k < x ? k : (x > -k ? x : -k)
define i32 @sat_upper_lower_3(i32 %x) #0 { define i32 @sat_upper_lower_3(i32 %x) #0 {
; V4T-LABEL: sat_upper_lower_3: ; V4T-LABEL: sat_upper_lower_3:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: mov r1, #1065353216 ; V4T-NEXT: mov r1, #1065353216
; V4T-NEXT: cmn r0, #8388608 ; V4T-NEXT: cmn r0, #8388608
; V4T-NEXT: orr r1, r1, #-1073741824 ; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movgt r1, r0 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: ldr r0, .LCPI7_0 ; V4T-NEXT: ldr r1, .LCPI7_0
; V4T-NEXT: cmp r1, r0 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movge r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI7_0: ; V4T-NEXT: .LCPI7_0:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: sat_upper_lower_3: ; V6T2-LABEL: sat_upper_lower_3:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
Show All 14 Lines
; Check that >= and <= work the same as > and < ; Check that >= and <= work the same as > and <
; k <= x ? k : (x >= -k ? x : -k) ; k <= x ? k : (x >= -k ? x : -k)
define i32 @sat_le_ge(i32 %x) #0 { define i32 @sat_le_ge(i32 %x) #0 {
; V4T-LABEL: sat_le_ge: ; V4T-LABEL: sat_le_ge:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: mov r1, #1065353216 ; V4T-NEXT: mov r1, #1065353216
; V4T-NEXT: cmn r0, #8388608 ; V4T-NEXT: cmn r0, #8388608
; V4T-NEXT: orr r1, r1, #-1073741824 ; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movgt r1, r0 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: ldr r0, .LCPI8_0 ; V4T-NEXT: ldr r1, .LCPI8_0
; V4T-NEXT: cmp r1, r0 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movge r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI8_0: ; V4T-NEXT: .LCPI8_0:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: sat_le_ge: ; V6T2-LABEL: sat_le_ge:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
} }
; The interval is not [k, ~k] ; The interval is not [k, ~k]
define i32 @no_sat_incorrect_interval(i32 %x) #0 { define i32 @no_sat_incorrect_interval(i32 %x) #0 {
; V4T-LABEL: no_sat_incorrect_interval: ; V4T-LABEL: no_sat_incorrect_interval:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: ldr r1, .LCPI12_0 ; V4T-NEXT: ldr r1, .LCPI12_0
; V4T-NEXT: cmp r0, r1 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movgt r1, r0 ; V4T-NEXT: movle r0, r1
; V4T-NEXT: ldr r0, .LCPI12_1 ; V4T-NEXT: ldr r1, .LCPI12_1
; V4T-NEXT: cmp r1, r0 ; V4T-NEXT: cmp r0, r1
; V4T-NEXT: movge r1, r0 ; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2 ; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1: ; V4T-NEXT: @ %bb.1:
; V4T-NEXT: .LCPI12_0: ; V4T-NEXT: .LCPI12_0:
; V4T-NEXT: .long 4275878552 @ 0xfedcba98 ; V4T-NEXT: .long 4275878552 @ 0xfedcba98
; V4T-NEXT: .LCPI12_1: ; V4T-NEXT: .LCPI12_1:
; V4T-NEXT: .long 8388607 @ 0x7fffff ; V4T-NEXT: .long 8388607 @ 0x7fffff
; ;
; V6T2-LABEL: no_sat_incorrect_interval: ; V6T2-LABEL: no_sat_incorrect_interval:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
; V6T2-NEXT: movw r1, #47768 ; V6T2-NEXT: movw r1, #47768
; V6T2-NEXT: movt r1, #65244 ; V6T2-NEXT: movt r1, #65244
; V6T2-NEXT: cmp r0, r1 ; V6T2-NEXT: cmp r0, r1
; V6T2-NEXT: movgt r1, r0 ; V6T2-NEXT: movle r0, r1
; V6T2-NEXT: movw r0, #65535 ; V6T2-NEXT: movw r1, #65535
; V6T2-NEXT: movt r0, #127 ; V6T2-NEXT: movt r1, #127
; V6T2-NEXT: cmp r1, r0 ; V6T2-NEXT: cmp r0, r1
; V6T2-NEXT: movge r1, r0 ; V6T2-NEXT: movge r0, r1
; V6T2-NEXT: mov r0, r1
; V6T2-NEXT: bx lr ; V6T2-NEXT: bx lr
entry: entry:
%0 = icmp sgt i32 %x, -19088744 %0 = icmp sgt i32 %x, -19088744
%saturateLow = select i1 %0, i32 %x, i32 -19088744 %saturateLow = select i1 %0, i32 %x, i32 -19088744
%1 = icmp slt i32 %saturateLow, 8388607 %1 = icmp slt i32 %saturateLow, 8388607
%saturateUp = select i1 %1, i32 %saturateLow, i32 8388607 %saturateUp = select i1 %1, i32 %saturateLow, i32 8388607
ret i32 %saturateUp ret i32 %saturateUp
} }
▲ Show 20 Lines • Show All 188 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/usat.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesentry:
ret i32 %saturateLow ret i32 %saturateLow
} }
; x < 0 ? 0 : (x > k ? k : x) ; x < 0 ? 0 : (x > k ? k : x)
; 16-bit base test ; 16-bit base test
define i16 @unsigned_sat_base_16bit(i16 %x) #0 { define i16 @unsigned_sat_base_16bit(i16 %x) #0 {
; V4T-LABEL: unsigned_sat_base_16bit: ; V4T-LABEL: unsigned_sat_base_16bit:
; V4T: @ %bb.0: @ %entry ; V4T: @ %bb.0: @ %entry
; V4T-NEXT: mov r2, #255
; V4T-NEXT: lsl r1, r0, #16 ; V4T-NEXT: lsl r1, r0, #16
; V4T-NEXT: asr r2, r1, #16 ; V4T-NEXT: orr r2, r2, #1792
; V4T-NEXT: mov r1, #255 ; V4T-NEXT: asr r1, r1, #16
; V4T-NEXT: orr r1, r1, #1792 ; V4T-NEXT: cmp r1, r2
; V4T-NEXT: cmp r2, r1 ; V4T-NEXT: movge r0, r2
; V4T-NEXT: movlt r1, r0 ; V4T-NEXT: lsl r1, r0, #16
; V4T-NEXT: lsl r0, r1, #16 ; V4T-NEXT: asr r1, r1, #16
; V4T-NEXT: asr r0, r0, #16 ; V4T-NEXT: cmp r1, #0
; V4T-NEXT: cmp r0, #0 ; V4T-NEXT: movle r0, #0
; V4T-NEXT: movle r1, #0
; V4T-NEXT: mov r0, r1
; V4T-NEXT: bx lr ; V4T-NEXT: bx lr
; ;
; V6-LABEL: unsigned_sat_base_16bit: ; V6-LABEL: unsigned_sat_base_16bit:
; V6: @ %bb.0: @ %entry ; V6: @ %bb.0: @ %entry
; V6-NEXT: mov r1, #255 ; V6-NEXT: mov r2, #255
; V6-NEXT: sxth r2, r0 ; V6-NEXT: sxth r1, r0
; V6-NEXT: orr r1, r1, #1792 ; V6-NEXT: orr r2, r2, #1792
; V6-NEXT: cmp r2, r1 ; V6-NEXT: cmp r1, r2
; V6-NEXT: movlt r1, r0 ; V6-NEXT: movge r0, r2
; V6-NEXT: sxth r0, r1 ; V6-NEXT: sxth r1, r0
; V6-NEXT: cmp r0, #0 ; V6-NEXT: cmp r1, #0
; V6-NEXT: movle r1, #0 ; V6-NEXT: movle r0, #0
; V6-NEXT: mov r0, r1
; V6-NEXT: bx lr ; V6-NEXT: bx lr
; ;
; V6T2-LABEL: unsigned_sat_base_16bit: ; V6T2-LABEL: unsigned_sat_base_16bit:
; V6T2: @ %bb.0: @ %entry ; V6T2: @ %bb.0: @ %entry
; V6T2-NEXT: sxth r2, r0 ; V6T2-NEXT: sxth r1, r0
; V6T2-NEXT: movw r1, #2047 ; V6T2-NEXT: movw r2, #2047
; V6T2-NEXT: cmp r2, r1 ; V6T2-NEXT: cmp r1, r2
; V6T2-NEXT: movlt r1, r0 ; V6T2-NEXT: movge r0, r2
; V6T2-NEXT: sxth r0, r1 ; V6T2-NEXT: sxth r1, r0
; V6T2-NEXT: cmp r0, #0 ; V6T2-NEXT: cmp r1, #0
; V6T2-NEXT: movle r1, #0 ; V6T2-NEXT: movle r0, #0
; V6T2-NEXT: mov r0, r1
; V6T2-NEXT: bx lr ; V6T2-NEXT: bx lr
entry: entry:
%0 = icmp slt i16 %x, 2047 %0 = icmp slt i16 %x, 2047
%saturateUp = select i1 %0, i16 %x, i16 2047 %saturateUp = select i1 %0, i16 %x, i16 2047
%1 = icmp sgt i16 %saturateUp, 0 %1 = icmp sgt i16 %saturateUp, 0
%saturateLow = select i1 %1, i16 %saturateUp, i16 0 %saturateLow = select i1 %1, i16 %saturateUp, i16 0
ret i16 %saturateLow ret i16 %saturateLow
} }
▲ Show 20 Lines • Show All 515 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/int-div-01.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; Check that the sign extension of the dividend is elided when the argument ; Check that the sign extension of the dividend is elided when the argument
; is already sign-extended. ; is already sign-extended.
define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) { define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
; CHECK-LABEL: f4: ; CHECK-LABEL: f4:
; CHECK-NOT: {{%r[234]}} ; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4 ; CHECK: dsgfr %r2, %r4
; CHECK-NOT: dsgfr ; CHECK-NOT: dsgfr
; CHECK: or %r2, %r3 ; CHECK: or %r3, %r2
; CHECK: lr %r2, %r3
; CHECK: br %r14 ; CHECK: br %r14
%div = sdiv i32 %a, %b %div = sdiv i32 %a, %b
%rem = srem i32 %a, %b %rem = srem i32 %a, %b
%or = or i32 %rem, %div %or = or i32 %rem, %div
ret i32 %or ret i32 %or
} }
; Test that memory dividends are loaded using sign extension (LGF). ; Test that memory dividends are loaded using sign extension (LGF).
▲ Show 20 Lines • Show All 189 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/int-div-03.ll

Show All 30 Lines; CHECK: br %r14
ret void ret void
} }
; Test that division and remainder use a single instruction. ; Test that division and remainder use a single instruction.
define i64 @f3(i64 %dummy, i64 %a, i32 %b) { define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK-NOT: {{%r[234]}} ; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4 ; CHECK: dsgfr %r2, %r4
; CHECK: ogr %r2, %r3 ; CHECK: ogr %r3, %r2
; CHECK: lgr %r2, %r3
; CHECK: br %r14 ; CHECK: br %r14
%bext = sext i32 %b to i64 %bext = sext i32 %b to i64
%div = sdiv i64 %a, %bext %div = sdiv i64 %a, %bext
%rem = srem i64 %a, %bext %rem = srem i64 %a, %bext
%or = or i64 %rem, %div %or = or i64 %rem, %div
ret i64 %or ret i64 %or
} }
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
} }
; Test both memory division and memory remainder. ; Test both memory division and memory remainder.
define i64 @f8(i64 %dummy, i64 %a, i32 *%src) { define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
; CHECK-LABEL: f8: ; CHECK-LABEL: f8:
; CHECK-NOT: {{%r[234]}} ; CHECK-NOT: {{%r[234]}}
; CHECK: dsgf %r2, 0(%r4) ; CHECK: dsgf %r2, 0(%r4)
; CHECK-NOT: {{dsgf|dsgfr}} ; CHECK-NOT: {{dsgf|dsgfr}}
; CHECK: ogr %r2, %r3 ; CHECK: ogr %r3, %r2
; CHECK: lgr %r2, %r3
; CHECK: br %r14 ; CHECK: br %r14
%b = load i32, i32 *%src %b = load i32, i32 *%src
%bext = sext i32 %b to i64 %bext = sext i32 %b to i64
%div = sdiv i64 %a, %bext %div = sdiv i64 %a, %bext
%rem = srem i64 %a, %bext %rem = srem i64 %a, %bext
%or = or i64 %rem, %div %or = or i64 %rem, %div
ret i64 %or ret i64 %or
} }
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/int-div-04.ll

Show All 28 Lines
} }
; Testg that division and remainder use a single instruction. ; Testg that division and remainder use a single instruction.
define i64 @f3(i64 %dummy1, i64 %a, i64 %b) { define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
; CHECK-LABEL: f3: ; CHECK-LABEL: f3:
; CHECK-NOT: {{%r[234]}} ; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4 ; CHECK: dsgr %r2, %r4
; CHECK-NOT: dsgr ; CHECK-NOT: dsgr
; CHECK: ogr %r2, %r3 ; CHECK: ogr %r3, %r2
; CHECK: lgr %r2, %r3
; CHECK: br %r14 ; CHECK: br %r14
%div = sdiv i64 %a, %b %div = sdiv i64 %a, %b
%rem = srem i64 %a, %b %rem = srem i64 %a, %b
%or = or i64 %rem, %div %or = or i64 %rem, %div
ret i64 %or ret i64 %or
} }
; Testg memory division with no displacement. ; Testg memory division with no displacement.
Show All 23 Lines
} }
; Testg both memory division and memory remainder. ; Testg both memory division and memory remainder.
define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
; CHECK-LABEL: f6: ; CHECK-LABEL: f6:
; CHECK-NOT: {{%r[234]}} ; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4) ; CHECK: dsg %r2, 0(%r4)
; CHECK-NOT: {{dsg|dsgr}} ; CHECK-NOT: {{dsg|dsgr}}
; CHECK: ogr %r2, %r3 ; CHECK: ogr %r3, %r2
; CHECK: lgr %r2, %r3
; CHECK: br %r14 ; CHECK: br %r14
%b = load i64, i64 *%src %b = load i64, i64 *%src
%div = sdiv i64 %a, %b %div = sdiv i64 %a, %b
%rem = srem i64 %a, %b %rem = srem i64 %a, %b
%or = or i64 %rem, %div %or = or i64 %rem, %div
ret i64 %or ret i64 %or
} }
▲ Show 20 Lines • Show All 117 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/int-mul-08.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
} }
; Check zero-extended multiplication in which the result is split into ; Check zero-extended multiplication in which the result is split into
; high and low halves. ; high and low halves.
define i64 @f4(i64 %dummy, i64 %a, i64 %b) { define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f4: ; CHECK-LABEL: f4:
; CHECK-NOT: {{%r[234]}} ; CHECK-NOT: {{%r[234]}}
; CHECK: mlgr %r2, %r4 ; CHECK: mlgr %r2, %r4
; CHECK: ogr %r2, %r3 ; CHECK: ogr %r3, %r2
; CHECK: lgr %r2, %r3
; CHECK: br %r14 ; CHECK: br %r14
%ax = zext i64 %a to i128 %ax = zext i64 %a to i128
%bx = zext i64 %b to i128 %bx = zext i64 %b to i128
%mulx = mul i128 %ax, %bx %mulx = mul i128 %ax, %bx
%highx = lshr i128 %mulx, 64 %highx = lshr i128 %mulx, 64
%high = trunc i128 %highx to i64 %high = trunc i128 %highx to i64
%low = trunc i128 %mulx to i64 %low = trunc i128 %mulx to i64
%or = or i64 %high, %low %or = or i64 %high, %low
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ldr r0, [sp, #36] ; CHECK-NEXT: ldr r0, [sp, #36]
; CHECK-NEXT: ands r0, r5 ; CHECK-NEXT: ands r0, r5
; CHECK-NEXT: rsbs r1, r0, #0 ; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: movs r0, #8 ; CHECK-NEXT: movs r0, #8
; CHECK-NEXT: mvns r2, r0 ; CHECK-NEXT: mvns r2, r0
; CHECK-NEXT: mvns r3, r7 ; CHECK-NEXT: mvns r3, r7
; CHECK-NEXT: ldr r0, [sp, #32] ; CHECK-NEXT: ldr r0, [sp, #32]
; CHECK-NEXT: bl __aeabi_ldivmod ; CHECK-NEXT: bl __aeabi_ldivmod
; CHECK-NEXT: ands r3, r5 ; CHECK-NEXT: ands r5, r3
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: eors r2, r0 ; CHECK-NEXT: eors r2, r0
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r5
; CHECK-NEXT: subs r0, r2, #1 ; CHECK-NEXT: subs r0, r2, #1
; CHECK-NEXT: sbcs r2, r0 ; CHECK-NEXT: sbcs r2, r0
; CHECK-NEXT: movs r0, r4 ; CHECK-NEXT: movs r0, r4
; CHECK-NEXT: movs r1, r6 ; CHECK-NEXT: movs r1, r6
; CHECK-NEXT: add sp, #12 ; CHECK-NEXT: add sp, #12
; CHECK-NEXT: pop {r4, r5, r6, r7} ; CHECK-NEXT: pop {r4, r5, r6, r7}
; CHECK-NEXT: pop {r3} ; CHECK-NEXT: pop {r3}
; CHECK-NEXT: bx r3 ; CHECK-NEXT: bx r3
%srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9> %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
%cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3> %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
ret <3 x i1> %cmp ret <3 x i1> %cmp
} }

llvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines; X32-BMI2-NEXT: retl
%negshamt = sub i64 96, %shamt %negshamt = sub i64 96, %shamt
%shifted = shl i64 %val, %negshamt %shifted = shl i64 %val, %negshamt
ret i64 %shifted ret i64 %shifted
} }
define i64 @t5_cse(i64 %val, i64 %shamt, i64*%dst) nounwind { define i64 @t5_cse(i64 %val, i64 %shamt, i64*%dst) nounwind {
; X64-NOBMI2-LABEL: t5_cse: ; X64-NOBMI2-LABEL: t5_cse:
; X64-NOBMI2: # %bb.0: ; X64-NOBMI2: # %bb.0:
; X64-NOBMI2-NEXT: movq %rsi, %rcx
; X64-NOBMI2-NEXT: movq %rdi, %rax ; X64-NOBMI2-NEXT: movq %rdi, %rax
; X64-NOBMI2-NEXT: addq $32, %rcx ; X64-NOBMI2-NEXT: leaq 32(%rsi), %rcx
; X64-NOBMI2-NEXT: movq %rcx, (%rdx) ; X64-NOBMI2-NEXT: movq %rcx, (%rdx)
; X64-NOBMI2-NEXT: negq %rcx ; X64-NOBMI2-NEXT: negq %rcx
; X64-NOBMI2-NEXT: # kill: def $cl killed $cl killed $rcx ; X64-NOBMI2-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-NOBMI2-NEXT: shlq %cl, %rax ; X64-NOBMI2-NEXT: shlq %cl, %rax
; X64-NOBMI2-NEXT: retq ; X64-NOBMI2-NEXT: retq
; ;
; X64-BMI2-LABEL: t5_cse: ; X64-BMI2-LABEL: t5_cse:
; X64-BMI2: # %bb.0: ; X64-BMI2: # %bb.0:
▲ Show 20 Lines • Show All 147 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; I686-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax ; I686-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax
; I686-CMOV-NEXT: cmpb %al, %cl ; I686-CMOV-NEXT: cmpb %al, %cl
; I686-CMOV-NEXT: cmovgl %ecx, %eax ; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax ; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl ; I686-CMOV-NEXT: retl
; ;
; X86_64-LABEL: t0: ; X86_64-LABEL: t0:
; X86_64: # %bb.0: ; X86_64: # %bb.0:
; X86_64-NEXT: movl %esi, %eax ; X86_64-NEXT: # kill: def $edx killed $edx def $rdx
; X86_64-NEXT: addl %edx, %edi ; X86_64-NEXT: # kill: def $esi killed $esi def $rsi
; X86_64-NEXT: addl %edx, %eax ; X86_64-NEXT: # kill: def $edi killed $edi def $rdi
; X86_64-NEXT: cmpb %al, %dil ; X86_64-NEXT: leal (%rdi,%rdx), %ecx
; X86_64-NEXT: cmovgl %edi, %eax ; X86_64-NEXT: leal (%rsi,%rdx), %eax
; X86_64-NEXT: cmpb %al, %cl
; X86_64-NEXT: cmovgl %ecx, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax ; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq ; X86_64-NEXT: retq
%a1_wide = add i32 %a1_wide_orig, %inc %a1_wide = add i32 %a1_wide_orig, %inc
%a2_wide = add i32 %a2_wide_orig, %inc %a2_wide = add i32 %a2_wide_orig, %inc
%a1 = trunc i32 %a1_wide to i8 %a1 = trunc i32 %a1_wide to i8
%a2 = trunc i32 %a2_wide to i8 %a2 = trunc i32 %a2_wide to i8
%t1 = icmp sgt i8 %a1, %a2 %t1 = icmp sgt i8 %a1, %a2
%t2 = select i1 %t1, i8 %a1, i8 %a2 %t2 = select i1 %t1, i8 %a1, i8 %a2
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; I686-CMOV-NEXT: cmpb %al, %cl ; I686-CMOV-NEXT: cmpb %al, %cl
; I686-CMOV-NEXT: movzbl %al, %eax ; I686-CMOV-NEXT: movzbl %al, %eax
; I686-CMOV-NEXT: cmovgl %ecx, %eax ; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax ; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl ; I686-CMOV-NEXT: retl
; ;
; X86_64-LABEL: neg_only_one_truncation: ; X86_64-LABEL: neg_only_one_truncation:
; X86_64: # %bb.0: ; X86_64: # %bb.0:
; X86_64-NEXT: addl %edx, %edi ; X86_64-NEXT: # kill: def $edx killed $edx def $rdx
; X86_64-NEXT: # kill: def $edi killed $edi def $rdi
; X86_64-NEXT: leal (%rdi,%rdx), %ecx
; X86_64-NEXT: addb %sil, %dl ; X86_64-NEXT: addb %sil, %dl
; X86_64-NEXT: cmpb %dl, %dil ; X86_64-NEXT: cmpb %dl, %cl
; X86_64-NEXT: movzbl %dl, %eax ; X86_64-NEXT: movzbl %dl, %eax
; X86_64-NEXT: cmovgl %edi, %eax ; X86_64-NEXT: cmovgl %ecx, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax ; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq ; X86_64-NEXT: retq
%a1_wide = add i32 %a1_wide_orig, %inc %a1_wide = add i32 %a1_wide_orig, %inc
%inc_short = trunc i32 %inc to i8 %inc_short = trunc i32 %inc to i8
%a2 = add i8 %a2_orig, %inc_short %a2 = add i8 %a2_orig, %inc_short
%a1 = trunc i32 %a1_wide to i8 %a1 = trunc i32 %a1_wide to i8
%t1 = icmp sgt i8 %a1, %a2 %t1 = icmp sgt i8 %a1, %a2
%t2 = select i1 %t1, i8 %a1, i8 %a2 %t2 = select i1 %t1, i8 %a1, i8 %a2
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; I686-CMOV-NEXT: addw {{[0-9]+}}(%esp), %ax ; I686-CMOV-NEXT: addw {{[0-9]+}}(%esp), %ax
; I686-CMOV-NEXT: cmpb %al, %cl ; I686-CMOV-NEXT: cmpb %al, %cl
; I686-CMOV-NEXT: cmovgl %ecx, %eax ; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax ; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl ; I686-CMOV-NEXT: retl
; ;
; X86_64-LABEL: neg_type_mismatch: ; X86_64-LABEL: neg_type_mismatch:
; X86_64: # %bb.0: ; X86_64: # %bb.0:
; X86_64-NEXT: movl %esi, %eax ; X86_64-NEXT: # kill: def $edx killed $edx def $rdx
; X86_64-NEXT: addl %edx, %edi ; X86_64-NEXT: # kill: def $esi killed $esi def $rsi
; X86_64-NEXT: addl %edx, %eax ; X86_64-NEXT: # kill: def $edi killed $edi def $rdi
; X86_64-NEXT: cmpb %al, %dil ; X86_64-NEXT: leal (%rdi,%rdx), %ecx
; X86_64-NEXT: cmovgl %edi, %eax ; X86_64-NEXT: leal (%rsi,%rdx), %eax
; X86_64-NEXT: cmpb %al, %cl
; X86_64-NEXT: cmovgl %ecx, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax ; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq ; X86_64-NEXT: retq
%a1_wide = add i32 %a1_wide_orig, %inc %a1_wide = add i32 %a1_wide_orig, %inc
%inc_short = trunc i32 %inc to i16 %inc_short = trunc i32 %inc to i16
%a2_wide = add i16 %a2_wide_orig, %inc_short %a2_wide = add i16 %a2_wide_orig, %inc_short
%a1 = trunc i32 %a1_wide to i8 %a1 = trunc i32 %a1_wide to i8
%a2 = trunc i16 %a2_wide to i8 %a2 = trunc i16 %a2_wide to i8
%t1 = icmp sgt i8 %a1, %a2 %t1 = icmp sgt i8 %a1, %a2
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; I686-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax ; I686-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax
; I686-CMOV-NEXT: cmpb %al, %cl ; I686-CMOV-NEXT: cmpb %al, %cl
; I686-CMOV-NEXT: cmovgl %ecx, %eax ; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax ; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl ; I686-CMOV-NEXT: retl
; ;
; X86_64-LABEL: negative_CopyFromReg: ; X86_64-LABEL: negative_CopyFromReg:
; X86_64: # %bb.0: ; X86_64: # %bb.0:
; X86_64-NEXT: movl %esi, %eax ; X86_64-NEXT: # kill: def $edx killed $edx def $rdx
; X86_64-NEXT: addl %edx, %eax ; X86_64-NEXT: # kill: def $esi killed $esi def $rsi
; X86_64-NEXT: leal (%rsi,%rdx), %eax
; X86_64-NEXT: cmpb %al, %dil ; X86_64-NEXT: cmpb %al, %dil
; X86_64-NEXT: cmovgl %edi, %eax ; X86_64-NEXT: cmovgl %edi, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax ; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq ; X86_64-NEXT: retq
%a2_wide = add i32 %a2_wide_orig, %inc %a2_wide = add i32 %a2_wide_orig, %inc
%a1 = trunc i32 %a1_wide to i8 %a1 = trunc i32 %a1_wide to i8
%a2 = trunc i32 %a2_wide to i8 %a2 = trunc i32 %a2_wide to i8
%t1 = icmp sgt i8 %a1, %a2 %t1 = icmp sgt i8 %a1, %a2
▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/atomic-unordered.ll

Show First 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
; CHECK-O0-NEXT: retq ; CHECK-O0-NEXT: retq
; ;
; CHECK-O3-LABEL: load_fold_sdiv1: ; CHECK-O3-LABEL: load_fold_sdiv1:
; CHECK-O3: # %bb.0: ; CHECK-O3: # %bb.0:
; CHECK-O3-NEXT: movq (%rdi), %rcx ; CHECK-O3-NEXT: movq (%rdi), %rcx
; CHECK-O3-NEXT: movabsq $-8608480567731124087, %rdx # imm = 0x8888888888888889 ; CHECK-O3-NEXT: movabsq $-8608480567731124087, %rdx # imm = 0x8888888888888889
; CHECK-O3-NEXT: movq %rcx, %rax ; CHECK-O3-NEXT: movq %rcx, %rax
; CHECK-O3-NEXT: imulq %rdx ; CHECK-O3-NEXT: imulq %rdx
; CHECK-O3-NEXT: addq %rcx, %rdx ; CHECK-O3-NEXT: addq %rdx, %rcx
; CHECK-O3-NEXT: movq %rdx, %rax ; CHECK-O3-NEXT: movq %rcx, %rax
; CHECK-O3-NEXT: shrq $63, %rax ; CHECK-O3-NEXT: shrq $63, %rax
; CHECK-O3-NEXT: sarq $3, %rdx ; CHECK-O3-NEXT: sarq $3, %rcx
; CHECK-O3-NEXT: addq %rdx, %rax ; CHECK-O3-NEXT: addq %rax, %rcx
; CHECK-O3-NEXT: movq %rcx, %rax
; CHECK-O3-NEXT: retq ; CHECK-O3-NEXT: retq
%v = load atomic i64, i64* %p unordered, align 8 %v = load atomic i64, i64* %p unordered, align 8
%ret = sdiv i64 %v, 15 %ret = sdiv i64 %v, 15
ret i64 %ret ret i64 %ret
} }
; Legal to fold (TODO) ; Legal to fold (TODO)
define i64 @load_fold_sdiv2(i64* %p, i64 %v2) { define i64 @load_fold_sdiv2(i64* %p, i64 %v2) {
▲ Show 20 Lines • Show All 1,957 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll

Show First 20 Lines • Show All 387 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%shuf = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 26, i32 3, i32 4, i32 22, i32 1, i32 18, i32 29, i32 17, i32 21, i32 0, i32 20, i32 19, i32 18, i32 12, i32 11, i32 31> %shuf = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 26, i32 3, i32 4, i32 22, i32 1, i32 18, i32 29, i32 17, i32 21, i32 0, i32 20, i32 19, i32 18, i32 12, i32 11, i32 31>
%cmp = icmp eq <16 x i16> %mask, zeroinitializer %cmp = icmp eq <16 x i16> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> zeroinitializer %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> zeroinitializer
ret <16 x i16> %res ret <16 x i16> %res
} }
define <16 x i16> @test_32xi16_to_16xi16_perm_mask3(<32 x i16> %vec) { define <16 x i16> @test_32xi16_to_16xi16_perm_mask3(<32 x i16> %vec) {
; CHECK-LABEL: test_32xi16_to_16xi16_perm_mask3: ; CHECK-LABEL: test_32xi16_to_16xi16_perm_mask3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1
; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [1,0,30,5,3,6,25,29,0,13,3,8,7,20,11,5] ; CHECK-NEXT: vmovdqa {{.*#+}} ymm2 = [1,0,30,5,3,6,25,29,0,13,3,8,7,20,11,5]
; CHECK-NEXT: vpermi2w %ymm2, %ymm0, %ymm1 ; CHECK-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
; CHECK-NEXT: vmovdqa %ymm1, %ymm0 ; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 1, i32 0, i32 30, i32 5, i32 3, i32 6, i32 25, i32 29, i32 0, i32 13, i32 3, i32 8, i32 7, i32 20, i32 11, i32 5> %res = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 1, i32 0, i32 30, i32 5, i32 3, i32 6, i32 25, i32 29, i32 0, i32 13, i32 3, i32 8, i32 7, i32 20, i32 11, i32 5>
ret <16 x i16> %res ret <16 x i16> %res
} }
define <16 x i16> @test_masked_32xi16_to_16xi16_perm_mask3(<32 x i16> %vec, <16 x i16> %vec2, <16 x i16> %mask) { define <16 x i16> @test_masked_32xi16_to_16xi16_perm_mask3(<32 x i16> %vec, <16 x i16> %vec2, <16 x i16> %mask) {
; CHECK-LABEL: test_masked_32xi16_to_16xi16_perm_mask3: ; CHECK-LABEL: test_masked_32xi16_to_16xi16_perm_mask3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm3 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm3
; CHECK-NEXT: vmovdqa {{.*#+}} ymm4 = [1,0,30,5,3,6,25,29,0,13,3,8,7,20,11,5] ; CHECK-NEXT: vmovdqa {{.*#+}} ymm4 = [1,0,30,5,3,6,25,29,0,13,3,8,7,20,11,5]
; CHECK-NEXT: vpermi2w %ymm3, %ymm0, %ymm4 ; CHECK-NEXT: vpermi2w %ymm3, %ymm0, %ymm4
; CHECK-NEXT: vptestnmw %ymm2, %ymm2, %k1 ; CHECK-NEXT: vptestnmw %ymm2, %ymm2, %k1
; CHECK-NEXT: vpblendmw %ymm4, %ymm1, %ymm0 {%k1} ; CHECK-NEXT: vpblendmw %ymm4, %ymm1, %ymm0 {%k1}
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%shuf = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 1, i32 0, i32 30, i32 5, i32 3, i32 6, i32 25, i32 29, i32 0, i32 13, i32 3, i32 8, i32 7, i32 20, i32 11, i32 5> %shuf = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 1, i32 0, i32 30, i32 5, i32 3, i32 6, i32 25, i32 29, i32 0, i32 13, i32 3, i32 8, i32 7, i32 20, i32 11, i32 5>
%cmp = icmp eq <16 x i16> %mask, zeroinitializer %cmp = icmp eq <16 x i16> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> %vec2 %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> %vec2
ret <16 x i16> %res ret <16 x i16> %res
} }
define <16 x i16> @test_masked_z_32xi16_to_16xi16_perm_mask3(<32 x i16> %vec, <16 x i16> %mask) { define <16 x i16> @test_masked_z_32xi16_to_16xi16_perm_mask3(<32 x i16> %vec, <16 x i16> %mask) {
; CHECK-LABEL: test_masked_z_32xi16_to_16xi16_perm_mask3: ; CHECK-LABEL: test_masked_z_32xi16_to_16xi16_perm_mask3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm3 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2
; CHECK-NEXT: vmovdqa {{.*#+}} ymm2 = [1,0,30,5,3,6,25,29,0,13,3,8,7,20,11,5] ; CHECK-NEXT: vmovdqa {{.*#+}} ymm3 = [1,0,30,5,3,6,25,29,0,13,3,8,7,20,11,5]
; CHECK-NEXT: vptestnmw %ymm1, %ymm1, %k1 ; CHECK-NEXT: vptestnmw %ymm1, %ymm1, %k1
; CHECK-NEXT: vpermi2w %ymm3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpermt2w %ymm2, %ymm3, %ymm0 {%k1} {z}
; CHECK-NEXT: vmovdqa %ymm2, %ymm0 ; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%shuf = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 1, i32 0, i32 30, i32 5, i32 3, i32 6, i32 25, i32 29, i32 0, i32 13, i32 3, i32 8, i32 7, i32 20, i32 11, i32 5> %shuf = shufflevector <32 x i16> %vec, <32 x i16> undef, <16 x i32> <i32 1, i32 0, i32 30, i32 5, i32 3, i32 6, i32 25, i32 29, i32 0, i32 13, i32 3, i32 8, i32 7, i32 20, i32 11, i32 5>
%cmp = icmp eq <16 x i16> %mask, zeroinitializer %cmp = icmp eq <16 x i16> %mask, zeroinitializer
%res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> zeroinitializer %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> zeroinitializer
ret <16 x i16> %res ret <16 x i16> %res
} }
define <8 x i16> @test_32xi16_to_8xi16_perm_mask0(<32 x i16> %vec) { define <8 x i16> @test_32xi16_to_8xi16_perm_mask0(<32 x i16> %vec) {
; CHECK-LABEL: test_32xi16_to_8xi16_perm_mask0: ; CHECK-LABEL: test_32xi16_to_8xi16_perm_mask0:
▲ Show 20 Lines • Show All 1,808 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%cmp = icmp eq <4 x i64> %mask, zeroinitializer %cmp = icmp eq <4 x i64> %mask, zeroinitializer
%res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec2 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec2
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_masked_z_8xi64_to_4xi64_perm_mask7(<8 x i64> %vec, <4 x i64> %mask) { define <4 x i64> @test_masked_z_8xi64_to_4xi64_perm_mask7(<8 x i64> %vec, <4 x i64> %mask) {
; CHECK-LABEL: test_masked_z_8xi64_to_4xi64_perm_mask7: ; CHECK-LABEL: test_masked_z_8xi64_to_4xi64_perm_mask7:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm3 ; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; CHECK-NEXT: vmovdqa {{.*#+}} ymm2 = [2,0,3,4] ; CHECK-NEXT: vmovdqa {{.*#+}} ymm3 = [2,0,3,4]
; CHECK-NEXT: vptestnmq %ymm1, %ymm1, %k1 ; CHECK-NEXT: vptestnmq %ymm1, %ymm1, %k1
; CHECK-NEXT: vpermi2q %ymm3, %ymm0, %ymm2 {%k1} {z} ; CHECK-NEXT: vpermt2q %ymm2, %ymm3, %ymm0 {%k1} {z}
; CHECK-NEXT: vmovdqa %ymm2, %ymm0 ; CHECK-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%shuf = shufflevector <8 x i64> %vec, <8 x i64> undef, <4 x i32> <i32 2, i32 0, i32 3, i32 4> %shuf = shufflevector <8 x i64> %vec, <8 x i64> undef, <4 x i32> <i32 2, i32 0, i32 3, i32 4>
%cmp = icmp eq <4 x i64> %mask, zeroinitializer %cmp = icmp eq <4 x i64> %mask, zeroinitializer
%res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer
ret <4 x i64> %res ret <4 x i64> %res
} }
define <2 x i64> @test_8xi64_to_2xi64_perm_mask0(<8 x i64> %vec) { define <2 x i64> @test_8xi64_to_2xi64_perm_mask0(<8 x i64> %vec) {
; CHECK-LABEL: test_8xi64_to_2xi64_perm_mask0: ; CHECK-LABEL: test_8xi64_to_2xi64_perm_mask0:
▲ Show 20 Lines • Show All 1,760 Lines • ▼ Show 20 Lines; CHECK-FAST-PERLANE-NEXT: retq
%cmp = fcmp oeq <4 x double> %mask, zeroinitializer %cmp = fcmp oeq <4 x double> %mask, zeroinitializer
%res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec2 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec2
ret <4 x double> %res ret <4 x double> %res
} }
define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask4(<8 x double> %vec, <4 x double> %mask) { define <4 x double> @test_masked_z_8xdouble_to_4xdouble_perm_mask4(<8 x double> %vec, <4 x double> %mask) {
; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask4: ; CHECK-FAST-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask4:
; CHECK-FAST: # %bb.0: ; CHECK-FAST: # %bb.0:
; CHECK-FAST-NEXT: vextractf32x4 $2, %zmm0, %xmm3 ; CHECK-FAST-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm2 = [1,1,5,5] ; CHECK-FAST-NEXT: vmovapd {{.*#+}} ymm3 = [1,1,5,5]
; CHECK-FAST-NEXT: vxorpd %xmm4, %xmm4, %xmm4 ; CHECK-FAST-NEXT: vxorpd %xmm4, %xmm4, %xmm4
; CHECK-FAST-NEXT: vcmpeqpd %ymm4, %ymm1, %k1 ; CHECK-FAST-NEXT: vcmpeqpd %ymm4, %ymm1, %k1
; CHECK-FAST-NEXT: vpermi2pd %ymm3, %ymm0, %ymm2 {%k1} {z} ; CHECK-FAST-NEXT: vpermt2pd %ymm2, %ymm3, %ymm0 {%k1} {z}
; CHECK-FAST-NEXT: vmovapd %ymm2, %ymm0 ; CHECK-FAST-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; CHECK-FAST-NEXT: retq ; CHECK-FAST-NEXT: retq
; ;
; CHECK-FAST-PERLANE-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask4: ; CHECK-FAST-PERLANE-LABEL: test_masked_z_8xdouble_to_4xdouble_perm_mask4:
; CHECK-FAST-PERLANE: # %bb.0: ; CHECK-FAST-PERLANE: # %bb.0:
; CHECK-FAST-PERLANE-NEXT: vextractf32x4 $2, %zmm0, %xmm2 ; CHECK-FAST-PERLANE-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; CHECK-FAST-PERLANE-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1] ; CHECK-FAST-PERLANE-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1]
; CHECK-FAST-PERLANE-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ; CHECK-FAST-PERLANE-NEXT: vxorpd %xmm2, %xmm2, %xmm2
; CHECK-FAST-PERLANE-NEXT: vcmpeqpd %ymm2, %ymm1, %k1 ; CHECK-FAST-PERLANE-NEXT: vcmpeqpd %ymm2, %ymm1, %k1
▲ Show 20 Lines • Show All 665 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/bitreverse.ll

Show First 20 Lines • Show All 366 Lines • ▼ Show 20 Lines
; X64-LABEL: test_bitreverse_i8: ; X64-LABEL: test_bitreverse_i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rolb $4, %dil ; X64-NEXT: rolb $4, %dil
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $51, %al ; X64-NEXT: andb $51, %al
; X64-NEXT: shlb $2, %al ; X64-NEXT: shlb $2, %al
; X64-NEXT: shrb $2, %dil ; X64-NEXT: shrb $2, %dil
; X64-NEXT: andb $51, %dil ; X64-NEXT: andb $51, %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $85, %al
; X64-NEXT: addb %al, %al
; X64-NEXT: shrb %dil
; X64-NEXT: andb $85, %dil
; X64-NEXT: orb %dil, %al ; X64-NEXT: orb %dil, %al
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andb $85, %cl
; X64-NEXT: addb %cl, %cl
; X64-NEXT: shrb %al
; X64-NEXT: andb $85, %al
; X64-NEXT: orb %cl, %al
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i8: ; X86XOP-LABEL: test_bitreverse_i8:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: # kill: def $al killed $al killed $eax ; X86XOP-NEXT: # kill: def $al killed $al killed $eax
Show All 27 Lines
; X64-LABEL: test_bitreverse_i4: ; X64-LABEL: test_bitreverse_i4:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rolb $4, %dil ; X64-NEXT: rolb $4, %dil
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $51, %al ; X64-NEXT: andb $51, %al
; X64-NEXT: shlb $2, %al ; X64-NEXT: shlb $2, %al
; X64-NEXT: shrb $2, %dil ; X64-NEXT: shrb $2, %dil
; X64-NEXT: andb $51, %dil ; X64-NEXT: andb $51, %dil
; X64-NEXT: orb %al, %dil
; X64-NEXT: movl %edi, %eax
; X64-NEXT: andb $80, %al
; X64-NEXT: addb %al, %al
; X64-NEXT: shrb %dil
; X64-NEXT: andb $80, %dil
; X64-NEXT: orb %dil, %al ; X64-NEXT: orb %dil, %al
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: andb $80, %cl
; X64-NEXT: addb %cl, %cl
; X64-NEXT: shrb %al
; X64-NEXT: andb $80, %al
; X64-NEXT: orb %cl, %al
; X64-NEXT: shrb $4, %al ; X64-NEXT: shrb $4, %al
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i4: ; X86XOP-LABEL: test_bitreverse_i4:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
▲ Show 20 Lines • Show All 878 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/bmi2.ll

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Lines
; X86-NEXT: addl %edx, %edx ; X86-NEXT: addl %edx, %edx
; X86-NEXT: addl %eax, %eax ; X86-NEXT: addl %eax, %eax
; X86-NEXT: mulxl %eax, %eax, %edx ; X86-NEXT: mulxl %eax, %eax, %edx
; X86-NEXT: movl %edx, (%ecx) ; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: mulx32: ; X64-LABEL: mulx32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %esi, %eax ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: addl %edi, %edi ; X64-NEXT: addl %edi, %edi
; X64-NEXT: addl %eax, %eax ; X64-NEXT: leal (%rsi,%rsi), %eax
; X64-NEXT: imulq %rdi, %rax ; X64-NEXT: imulq %rdi, %rax
; X64-NEXT: movq %rax, %rcx ; X64-NEXT: movq %rax, %rcx
; X64-NEXT: shrq $32, %rcx ; X64-NEXT: shrq $32, %rcx
; X64-NEXT: movl %ecx, (%rdx) ; X64-NEXT: movl %ecx, (%rdx)
; X64-NEXT: # kill: def $eax killed $eax killed $rax ; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
%x1 = add i32 %x, %x %x1 = add i32 %x, %x
%y1 = add i32 %y, %y %y1 = add i32 %y, %y
Show All 15 Lines
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: addl %edx, %edx ; X86-NEXT: addl %edx, %edx
; X86-NEXT: mulxl (%eax), %eax, %edx ; X86-NEXT: mulxl (%eax), %eax, %edx
; X86-NEXT: movl %edx, (%ecx) ; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: mulx32_load: ; X64-LABEL: mulx32_load:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: addl %eax, %eax ; X64-NEXT: leal (%rdi,%rdi), %eax
; X64-NEXT: movl (%rsi), %ecx ; X64-NEXT: movl (%rsi), %ecx
; X64-NEXT: imulq %rcx, %rax ; X64-NEXT: imulq %rcx, %rax
; X64-NEXT: movq %rax, %rcx ; X64-NEXT: movq %rax, %rcx
; X64-NEXT: shrq $32, %rcx ; X64-NEXT: shrq $32, %rcx
; X64-NEXT: movl %ecx, (%rdx) ; X64-NEXT: movl %ecx, (%rdx)
; X64-NEXT: # kill: def $eax killed $eax killed $rax ; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
%x1 = add i32 %x, %x %x1 = add i32 %x, %x
Show All 10 Lines

llvm/test/CodeGen/X86/bypass-slow-division-32.ll

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1 ; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: imull %edx ; CHECK-NEXT: imull %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $3, %edx ; CHECK-NEXT: sarl $3, %edx
; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shll $5, %eax
; CHECK-NEXT: addl %edx, %eax ; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: subl %eax, %ecx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: addl %edx, %ecx ; CHECK-NEXT: shll $5, %edx
; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: subl %edx, %ecx
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%resultdiv = sdiv i32 %a, 33 %resultdiv = sdiv i32 %a, 33
%resultrem = srem i32 %a, 33 %resultrem = srem i32 %a, 33
%result = add i32 %resultdiv, %resultrem %result = add i32 %resultdiv, %resultrem
ret i32 %result ret i32 %result
} }
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/combine-bitselect.ll

Show First 20 Lines • Show All 985 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret <8 x i64> %7 ret <8 x i64> %7
} }
; Check that mask registers don't get canonicalized. ; Check that mask registers don't get canonicalized.
define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
; SSE-LABEL: bitselect_v4i1_loop: ; SSE-LABEL: bitselect_v4i1_loop:
; SSE: # %bb.0: # %bb ; SSE: # %bb.0: # %bb
; SSE-NEXT: pxor %xmm2, %xmm2 ; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE-NEXT: pcmpeqd %xmm2, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [12,12,12,12] ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [12,12,12,12]
; SSE-NEXT: pcmpeqd %xmm1, %xmm0 ; SSE-NEXT: pcmpeqd %xmm1, %xmm2
; SSE-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: pand %xmm2, %xmm1 ; SSE-NEXT: pand %xmm0, %xmm1
; SSE-NEXT: pandn %xmm0, %xmm2 ; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: por %xmm1, %xmm2 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; XOP-LABEL: bitselect_v4i1_loop: ; XOP-LABEL: bitselect_v4i1_loop:
; XOP: # %bb.0: # %bb ; XOP: # %bb.0: # %bb
; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
; XOP-NEXT: vpcomneqd %xmm2, %xmm0, %xmm0 ; XOP-NEXT: vpcomneqd %xmm2, %xmm0, %xmm0
; XOP-NEXT: vpcomeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 ; XOP-NEXT: vpcomeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2
; XOP-NEXT: vpcomeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 ; XOP-NEXT: vpcomeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/combine-sdiv.ll

Show First 20 Lines • Show All 1,607 Lines • ▼ Show 20 Lines
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrad $31, %xmm2 ; SSE2-NEXT: psrad $31, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: movdqa %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: psrlq $61, %xmm3 ; SSE2-NEXT: psrlq $61, %xmm3
; SSE2-NEXT: psrlq $60, %xmm2 ; SSE2-NEXT: psrlq $60, %xmm2
; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm3[0],xmm2[1] ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm3[0],xmm2[1]
; SSE2-NEXT: paddq %xmm1, %xmm2 ; SSE2-NEXT: paddq %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlq $3, %xmm1 ; SSE2-NEXT: psrlq $3, %xmm2
; SSE2-NEXT: psrlq $4, %xmm2 ; SSE2-NEXT: psrlq $4, %xmm1
; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1] ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; SSE2-NEXT: movapd {{.*#+}} xmm1 = [1152921504606846976,576460752303423488] ; SSE2-NEXT: movapd {{.*#+}} xmm2 = [1152921504606846976,576460752303423488]
; SSE2-NEXT: xorpd %xmm1, %xmm2 ; SSE2-NEXT: xorpd %xmm2, %xmm1
; SSE2-NEXT: psubq %xmm1, %xmm2 ; SSE2-NEXT: psubq %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: combine_vec_sdiv_by_pow2b_v4i64: ; SSE41-LABEL: combine_vec_sdiv_by_pow2b_v4i64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: psrad $31, %xmm2 ; SSE41-NEXT: psrad $31, %xmm2
; SSE41-NEXT: psrlq $62, %xmm2 ; SSE41-NEXT: psrlq $62, %xmm2
; SSE41-NEXT: paddq %xmm0, %xmm2 ; SSE41-NEXT: paddq %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrad $2, %xmm3 ; SSE41-NEXT: psrad $2, %xmm3
; SSE41-NEXT: psrlq $2, %xmm2 ; SSE41-NEXT: psrlq $2, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrad $31, %xmm2 ; SSE41-NEXT: psrad $31, %xmm2
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlq $60, %xmm3 ; SSE41-NEXT: psrlq $60, %xmm3
; SSE41-NEXT: psrlq $61, %xmm2 ; SSE41-NEXT: psrlq $61, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
; SSE41-NEXT: paddq %xmm1, %xmm2 ; SSE41-NEXT: paddq %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlq $4, %xmm1 ; SSE41-NEXT: psrlq $4, %xmm2
; SSE41-NEXT: psrlq $3, %xmm2 ; SSE41-NEXT: psrlq $3, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1152921504606846976,576460752303423488] ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [1152921504606846976,576460752303423488]
; SSE41-NEXT: pxor %xmm1, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm1
; SSE41-NEXT: psubq %xmm1, %xmm2 ; SSE41-NEXT: psubq %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm1
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: combine_vec_sdiv_by_pow2b_v4i64: ; AVX1-LABEL: combine_vec_sdiv_by_pow2b_v4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3 ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm3
; AVX1-NEXT: vpsrlq $60, %xmm3, %xmm4 ; AVX1-NEXT: vpsrlq $60, %xmm3, %xmm4
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3]
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: psrad $31, %xmm4 ; SSE2-NEXT: psrad $31, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: psrlq $61, %xmm5 ; SSE2-NEXT: psrlq $61, %xmm5
; SSE2-NEXT: psrlq $60, %xmm4 ; SSE2-NEXT: psrlq $60, %xmm4
; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm5[0],xmm4[1] ; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm5[0],xmm4[1]
; SSE2-NEXT: paddq %xmm1, %xmm4 ; SSE2-NEXT: paddq %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm4, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: psrlq $3, %xmm1 ; SSE2-NEXT: psrlq $3, %xmm4
; SSE2-NEXT: psrlq $4, %xmm4 ; SSE2-NEXT: psrlq $4, %xmm1
; SSE2-NEXT: movsd {{.*#+}} xmm4 = xmm1[0],xmm4[1] ; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm4[0],xmm1[1]
; SSE2-NEXT: movapd {{.*#+}} xmm1 = [1152921504606846976,576460752303423488] ; SSE2-NEXT: movapd {{.*#+}} xmm4 = [1152921504606846976,576460752303423488]
; SSE2-NEXT: xorpd %xmm1, %xmm4 ; SSE2-NEXT: xorpd %xmm4, %xmm1
; SSE2-NEXT: psubq %xmm1, %xmm4 ; SSE2-NEXT: psubq %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm3, %xmm5 ; SSE2-NEXT: movdqa %xmm3, %xmm5
; SSE2-NEXT: psrad $31, %xmm5 ; SSE2-NEXT: psrad $31, %xmm5
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE2-NEXT: movdqa %xmm5, %xmm6 ; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: psrlq $61, %xmm6 ; SSE2-NEXT: psrlq $61, %xmm6
; SSE2-NEXT: psrlq $60, %xmm5 ; SSE2-NEXT: psrlq $60, %xmm5
; SSE2-NEXT: movsd {{.*#+}} xmm5 = xmm6[0],xmm5[1] ; SSE2-NEXT: movsd {{.*#+}} xmm5 = xmm6[0],xmm5[1]
; SSE2-NEXT: paddq %xmm3, %xmm5 ; SSE2-NEXT: paddq %xmm5, %xmm3
; SSE2-NEXT: movdqa %xmm5, %xmm3 ; SSE2-NEXT: movdqa %xmm3, %xmm5
; SSE2-NEXT: psrlq $3, %xmm3 ; SSE2-NEXT: psrlq $3, %xmm5
; SSE2-NEXT: psrlq $4, %xmm5 ; SSE2-NEXT: psrlq $4, %xmm3
; SSE2-NEXT: movsd {{.*#+}} xmm5 = xmm3[0],xmm5[1] ; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm5[0],xmm3[1]
; SSE2-NEXT: xorpd %xmm1, %xmm5 ; SSE2-NEXT: xorpd %xmm4, %xmm3
; SSE2-NEXT: psubq %xmm1, %xmm5 ; SSE2-NEXT: psubq %xmm4, %xmm3
; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm5, %xmm3
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: combine_vec_sdiv_by_pow2b_v8i64: ; SSE41-LABEL: combine_vec_sdiv_by_pow2b_v8i64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: movdqa %xmm0, %xmm4
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: psrad $31, %xmm4
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrlq $62, %xmm4
; SSE41-NEXT: psrlq $62, %xmm1 ; SSE41-NEXT: paddq %xmm0, %xmm4
; SSE41-NEXT: paddq %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm4, %xmm5
; SSE41-NEXT: movdqa %xmm1, %xmm5
; SSE41-NEXT: psrad $2, %xmm5 ; SSE41-NEXT: psrad $2, %xmm5
; SSE41-NEXT: psrlq $2, %xmm1 ; SSE41-NEXT: psrlq $2, %xmm4
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm5[2,3],xmm1[4,5],xmm5[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1],xmm5[2,3],xmm4[4,5],xmm5[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm4[4,5,6,7]
; SSE41-NEXT: movdqa %xmm2, %xmm1 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrad $31, %xmm4
; SSE41-NEXT: psrlq $62, %xmm1 ; SSE41-NEXT: psrlq $62, %xmm4
; SSE41-NEXT: paddq %xmm2, %xmm1 ; SSE41-NEXT: paddq %xmm2, %xmm4
; SSE41-NEXT: movdqa %xmm1, %xmm5 ; SSE41-NEXT: movdqa %xmm4, %xmm5
; SSE41-NEXT: psrad $2, %xmm5 ; SSE41-NEXT: psrad $2, %xmm5
; SSE41-NEXT: psrlq $2, %xmm1 ; SSE41-NEXT: psrlq $2, %xmm4
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm5[2,3],xmm1[4,5],xmm5[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1],xmm5[2,3],xmm4[4,5],xmm5[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm4[4,5,6,7]
; SSE41-NEXT: movdqa %xmm4, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm4
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrad $31, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE41-NEXT: movdqa %xmm1, %xmm5 ; SSE41-NEXT: movdqa %xmm4, %xmm5
; SSE41-NEXT: psrlq $60, %xmm5 ; SSE41-NEXT: psrlq $60, %xmm5
; SSE41-NEXT: psrlq $61, %xmm1 ; SSE41-NEXT: psrlq $61, %xmm4
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm5[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm5[4,5,6,7]
; SSE41-NEXT: paddq %xmm4, %xmm1 ; SSE41-NEXT: paddq %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: movdqa %xmm1, %xmm4
; SSE41-NEXT: psrlq $4, %xmm4 ; SSE41-NEXT: psrlq $4, %xmm4
; SSE41-NEXT: psrlq $3, %xmm1 ; SSE41-NEXT: psrlq $3, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm4[4,5,6,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [1152921504606846976,576460752303423488] ; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [1152921504606846976,576460752303423488]
; SSE41-NEXT: pxor %xmm5, %xmm1 ; SSE41-NEXT: pxor %xmm4, %xmm1
; SSE41-NEXT: psubq %xmm5, %xmm1 ; SSE41-NEXT: psubq %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm3, %xmm4 ; SSE41-NEXT: movdqa %xmm3, %xmm5
; SSE41-NEXT: psrad $31, %xmm4 ; SSE41-NEXT: psrad $31, %xmm5
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE41-NEXT: movdqa %xmm4, %xmm6 ; SSE41-NEXT: movdqa %xmm5, %xmm6
; SSE41-NEXT: psrlq $60, %xmm6 ; SSE41-NEXT: psrlq $60, %xmm6
; SSE41-NEXT: psrlq $61, %xmm4 ; SSE41-NEXT: psrlq $61, %xmm5
; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm6[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1,2,3],xmm6[4,5,6,7]
; SSE41-NEXT: paddq %xmm3, %xmm4 ; SSE41-NEXT: paddq %xmm5, %xmm3
; SSE41-NEXT: movdqa %xmm4, %xmm3 ; SSE41-NEXT: movdqa %xmm3, %xmm5
; SSE41-NEXT: psrlq $4, %xmm3 ; SSE41-NEXT: psrlq $4, %xmm5
; SSE41-NEXT: psrlq $3, %xmm4 ; SSE41-NEXT: psrlq $3, %xmm3
; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm5[4,5,6,7]
; SSE41-NEXT: pxor %xmm5, %xmm4 ; SSE41-NEXT: pxor %xmm4, %xmm3
; SSE41-NEXT: psubq %xmm5, %xmm4 ; SSE41-NEXT: psubq %xmm4, %xmm3
; SSE41-NEXT: movdqa %xmm4, %xmm3
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: combine_vec_sdiv_by_pow2b_v8i64: ; AVX1-LABEL: combine_vec_sdiv_by_pow2b_v8i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm4 ; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm4
; AVX1-NEXT: vpsrlq $60, %xmm4, %xmm5 ; AVX1-NEXT: vpsrlq $60, %xmm4, %xmm5
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines; XOP-NEXT: retq
%1 = sdiv <8 x i64> %x, <i64 1, i64 4, i64 8, i64 16, i64 1, i64 4, i64 8, i64 16> %1 = sdiv <8 x i64> %x, <i64 1, i64 4, i64 8, i64 16, i64 1, i64 4, i64 8, i64 16>
ret <8 x i64> %1 ret <8 x i64> %1
} }
define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) { define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) {
; SSE2-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg: ; SSE2-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $31, %xmm0 ; SSE2-NEXT: psrad $31, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrld $28, %xmm2 ; SSE2-NEXT: psrld $28, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: psrld $29, %xmm3 ; SSE2-NEXT: psrld $29, %xmm3
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1] ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1]
; SSE2-NEXT: psrld $30, %xmm0 ; SSE2-NEXT: psrld $30, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0,3]
; SSE2-NEXT: paddd %xmm1, %xmm0 ; SSE2-NEXT: paddd %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrad $4, %xmm2 ; SSE2-NEXT: psrad $4, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: psrad $3, %xmm3 ; SSE2-NEXT: psrad $3, %xmm3
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1] ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1]
; SSE2-NEXT: psrad $2, %xmm0 ; SSE2-NEXT: psrad $2, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0,3]
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3,2,3]
; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: psubd %xmm2, %xmm3 ; SSE2-NEXT: psubd %xmm1, %xmm2
; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg: ; SSE41-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrad $31, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrld $28, %xmm2 ; SSE41-NEXT: psrld $28, %xmm2
▲ Show 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: non_splat_minus_one_divisor_2: ; SSE41-LABEL: non_splat_minus_one_divisor_2:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrld $31, %xmm1 ; SSE41-NEXT: psrld $31, %xmm1
; SSE41-NEXT: paddd %xmm0, %xmm1 ; SSE41-NEXT: paddd %xmm0, %xmm1
; SSE41-NEXT: psrad $1, %xmm1 ; SSE41-NEXT: psrad $1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: pxor %xmm0, %xmm0 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: psubd %xmm1, %xmm0 ; SSE41-NEXT: psubd %xmm0, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: non_splat_minus_one_divisor_2: ; AVX1-LABEL: non_splat_minus_one_divisor_2:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsrld $31, %xmm0, %xmm1 ; AVX1-NEXT: vpsrld $31, %xmm0, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vpsrad $1, %xmm1, %xmm1 ; AVX1-NEXT: vpsrad $1, %xmm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines; XOP-NEXT: retq
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <8 x i16> @combine_vec_sdiv_nonuniform3(<8 x i16> %x) { define <8 x i16> @combine_vec_sdiv_nonuniform3(<8 x i16> %x) {
; SSE2-LABEL: combine_vec_sdiv_nonuniform3: ; SSE2-LABEL: combine_vec_sdiv_nonuniform3:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [45591,45591,45591,45591,32833,32833,32833,32833] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [45591,45591,45591,45591,32833,32833,32833,32833]
; SSE2-NEXT: pmulhw %xmm0, %xmm1 ; SSE2-NEXT: pmulhw %xmm0, %xmm1
; SSE2-NEXT: paddw %xmm0, %xmm1 ; SSE2-NEXT: paddw %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psraw $4, %xmm0 ; SSE2-NEXT: psraw $4, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psraw $8, %xmm2 ; SSE2-NEXT: psraw $8, %xmm2
; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1] ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; SSE2-NEXT: psrlw $15, %xmm1 ; SSE2-NEXT: psrlw $15, %xmm0
; SSE2-NEXT: paddw %xmm2, %xmm1 ; SSE2-NEXT: paddw %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: combine_vec_sdiv_nonuniform3: ; SSE41-LABEL: combine_vec_sdiv_nonuniform3:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [45591,45591,45591,45591,32833,32833,32833,32833] ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [45591,45591,45591,45591,32833,32833,32833,32833]
; SSE41-NEXT: pmulhw %xmm0, %xmm1 ; SSE41-NEXT: pmulhw %xmm0, %xmm1
; SSE41-NEXT: paddw %xmm0, %xmm1 ; SSE41-NEXT: paddw %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psraw $8, %xmm0 ; SSE41-NEXT: psraw $8, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: psraw $4, %xmm2 ; SSE41-NEXT: psraw $4, %xmm2
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: psrlw $15, %xmm1 ; SSE41-NEXT: psrlw $15, %xmm0
; SSE41-NEXT: paddw %xmm2, %xmm1 ; SSE41-NEXT: paddw %xmm2, %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: combine_vec_sdiv_nonuniform3: ; AVX1-LABEL: combine_vec_sdiv_nonuniform3:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 ; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX1-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vpaddw %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vpsraw $8, %xmm0, %xmm1 ; AVX1-NEXT: vpsraw $8, %xmm0, %xmm1
; AVX1-NEXT: vpsraw $4, %xmm0, %xmm2 ; AVX1-NEXT: vpsraw $4, %xmm0, %xmm2
▲ Show 20 Lines • Show All 398 Lines • ▼ Show 20 Lines
; XOP-NEXT: retq ; XOP-NEXT: retq
%1 = sdiv <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 1, i16 1, i16 1, i16 1> %1 = sdiv <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @pr38658(<16 x i8> %x) { define <16 x i8> @pr38658(<16 x i8> %x) {
; SSE2-LABEL: pr38658: ; SSE2-LABEL: pr38658:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15]
; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: psrlw $8, %xmm3
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: packuswb %xmm3, %xmm1 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: psraw $8, %xmm2
; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: psrlw $8, %xmm2 ; SSE2-NEXT: psrlw $8, %xmm2
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: psrlw $7, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm3
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: paddb %xmm3, %xmm0
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; SSE2-NEXT: psraw $8, %xmm1
; SSE2-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: packuswb %xmm1, %xmm2
; SSE2-NEXT: psrlw $7, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: pr38658: ; SSE41-LABEL: pr38658:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] ; SSE41-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE41-NEXT: pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: psrlw $8, %xmm2 ; SSE41-NEXT: psrlw $8, %xmm2
; SSE41-NEXT: packuswb %xmm2, %xmm1 ; SSE41-NEXT: packuswb %xmm2, %xmm1
; SSE41-NEXT: paddb %xmm0, %xmm1 ; SSE41-NEXT: paddb %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] ; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; SSE41-NEXT: psraw $8, %xmm0 ; SSE41-NEXT: psraw $8, %xmm1
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psllw $6, %xmm2 ; SSE41-NEXT: psllw $6, %xmm2
; SSE41-NEXT: psllw $8, %xmm0 ; SSE41-NEXT: psllw $8, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7] ; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6],xmm2[7]
; SSE41-NEXT: psrlw $8, %xmm0 ; SSE41-NEXT: psrlw $8, %xmm1
; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero ; SSE41-NEXT: pmovzxbw {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; SSE41-NEXT: packuswb %xmm0, %xmm2 ; SSE41-NEXT: packuswb %xmm1, %xmm2
; SSE41-NEXT: psrlw $7, %xmm1 ; SSE41-NEXT: psrlw $7, %xmm0
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: paddb %xmm2, %xmm1 ; SSE41-NEXT: paddb %xmm2, %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: pr38658: ; AVX1-LABEL: pr38658:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 ; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
▲ Show 20 Lines • Show All 235 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/ctpop-combine.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; ;
; NO-POPCOUNT-LABEL: test4: ; NO-POPCOUNT-LABEL: test4:
; NO-POPCOUNT: # %bb.0: ; NO-POPCOUNT: # %bb.0:
; NO-POPCOUNT-NEXT: andb $127, %dil ; NO-POPCOUNT-NEXT: andb $127, %dil
; NO-POPCOUNT-NEXT: movl %edi, %eax ; NO-POPCOUNT-NEXT: movl %edi, %eax
; NO-POPCOUNT-NEXT: shrb %al ; NO-POPCOUNT-NEXT: shrb %al
; NO-POPCOUNT-NEXT: andb $21, %al ; NO-POPCOUNT-NEXT: andb $21, %al
; NO-POPCOUNT-NEXT: subb %al, %dil ; NO-POPCOUNT-NEXT: subb %al, %dil
; NO-POPCOUNT-NEXT: movl %edi, %eax ; NO-POPCOUNT-NEXT: movl %edi, %ecx
; NO-POPCOUNT-NEXT: andb $51, %al ; NO-POPCOUNT-NEXT: andb $51, %cl
; NO-POPCOUNT-NEXT: shrb $2, %dil ; NO-POPCOUNT-NEXT: shrb $2, %dil
; NO-POPCOUNT-NEXT: andb $51, %dil ; NO-POPCOUNT-NEXT: andb $51, %dil
; NO-POPCOUNT-NEXT: addb %al, %dil ; NO-POPCOUNT-NEXT: addb %dil, %cl
; NO-POPCOUNT-NEXT: movl %edi, %eax ; NO-POPCOUNT-NEXT: movl %ecx, %eax
; NO-POPCOUNT-NEXT: shrb $4, %al ; NO-POPCOUNT-NEXT: shrb $4, %al
; NO-POPCOUNT-NEXT: addb %dil, %al ; NO-POPCOUNT-NEXT: addb %cl, %al
; NO-POPCOUNT-NEXT: andb $15, %al ; NO-POPCOUNT-NEXT: andb $15, %al
; NO-POPCOUNT-NEXT: retq ; NO-POPCOUNT-NEXT: retq
%x2 = and i8 %x, 127 %x2 = and i8 %x, 127
%count = tail call i8 @llvm.ctpop.i8(i8 %x2) %count = tail call i8 @llvm.ctpop.i8(i8 %x2)
%and = and i8 %count, 7 %and = and i8 %count, 7
ret i8 %and ret i8 %and
} }
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/divide-by-constant.ll

Show First 20 Lines • Show All 436 Lines • ▼ Show 20 Lines
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: PR38622_signed: ; X64-LABEL: PR38622_signed:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movabsq $1237940039285380275, %rcx # imm = 0x112E0BE826D694B3 ; X64-NEXT: movabsq $1237940039285380275, %rcx # imm = 0x112E0BE826D694B3
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: imulq %rcx ; X64-NEXT: imulq %rcx
; X64-NEXT: movq %rdx, %rax ; X64-NEXT: movq %rdx, %rax
; X64-NEXT: movq %rdx, %rcx ; X64-NEXT: shrq $63, %rax
; X64-NEXT: shrq $63, %rcx ; X64-NEXT: sarq $28, %rdx
; X64-NEXT: sarq $28, %rax ; X64-NEXT: addq %rdx, %rax
; X64-NEXT: addq %rcx, %rax
; X64-NEXT: imull $-294967296, %eax, %ecx # imm = 0xEE6B2800 ; X64-NEXT: imull $-294967296, %eax, %ecx # imm = 0xEE6B2800
; X64-NEXT: subl %ecx, %edi ; X64-NEXT: subl %ecx, %edi
; X64-NEXT: movl %edi, %edx ; X64-NEXT: movl %edi, %edx
; X64-NEXT: retq ; X64-NEXT: retq
%2 = sdiv i64 %0, 4000000000 %2 = sdiv i64 %0, 4000000000
%3 = srem i64 %0, 4000000000 %3 = srem i64 %0, 4000000000
%4 = trunc i64 %3 to i32 %4 = trunc i64 %3 to i32
%5 = insertvalue { i64, i32 } undef, i64 %2, 0 %5 = insertvalue { i64, i32 } undef, i64 %2, 0
%6 = insertvalue { i64, i32 } %5, i32 %4, 1 %6 = insertvalue { i64, i32 } %5, i32 %4, 1
ret { i64, i32 } %6 ret { i64, i32 } %6
} }

llvm/test/CodeGen/X86/fpclamptosat.ll

Show First 20 Lines • Show All 424 Lines • ▼ Show 20 Lines
; i64 saturate ; i64 saturate
define i64 @stest_f64i64(double %x) { define i64 @stest_f64i64(double %x) {
; CHECK-LABEL: stest_f64i64: ; CHECK-LABEL: stest_f64i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixdfti@PLT ; CHECK-NEXT: callq __fixdfti@PLT
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rsi, %rax
; CHECK-NEXT: movq %rdx, %rdi ; CHECK-NEXT: movq %rdx, %rdi
; CHECK-NEXT: sbbq $0, %rdi ; CHECK-NEXT: sbbq $0, %rdi
; CHECK-NEXT: cmovlq %rdx, %rsi ; CHECK-NEXT: cmovlq %rdx, %rcx
; CHECK-NEXT: cmovlq %rax, %rcx ; CHECK-NEXT: cmovgeq %rsi, %rax
; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rax, %rdx
; CHECK-NEXT: movq $-1, %rdx ; CHECK-NEXT: movq $-1, %rsi
; CHECK-NEXT: sbbq %rsi, %rdx ; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: cmovgeq %rax, %rcx ; CHECK-NEXT: cmovgeq %rdx, %rax
; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi double %x to i128 %conv = fptosi double %x to i128
%0 = icmp slt i128 %conv, 9223372036854775807 %0 = icmp slt i128 %conv, 9223372036854775807
%spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807 %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807
%1 = icmp sgt i128 %spec.store.select, -9223372036854775808 %1 = icmp sgt i128 %spec.store.select, -9223372036854775808
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
} }
define i64 @stest_f32i64(float %x) { define i64 @stest_f32i64(float %x) {
; CHECK-LABEL: stest_f32i64: ; CHECK-LABEL: stest_f32i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixsfti@PLT ; CHECK-NEXT: callq __fixsfti@PLT
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rsi, %rax
; CHECK-NEXT: movq %rdx, %rdi ; CHECK-NEXT: movq %rdx, %rdi
; CHECK-NEXT: sbbq $0, %rdi ; CHECK-NEXT: sbbq $0, %rdi
; CHECK-NEXT: cmovlq %rdx, %rsi ; CHECK-NEXT: cmovlq %rdx, %rcx
; CHECK-NEXT: cmovlq %rax, %rcx ; CHECK-NEXT: cmovgeq %rsi, %rax
; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rax, %rdx
; CHECK-NEXT: movq $-1, %rdx ; CHECK-NEXT: movq $-1, %rsi
; CHECK-NEXT: sbbq %rsi, %rdx ; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: cmovgeq %rax, %rcx ; CHECK-NEXT: cmovgeq %rdx, %rax
; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi float %x to i128 %conv = fptosi float %x to i128
%0 = icmp slt i128 %conv, 9223372036854775807 %0 = icmp slt i128 %conv, 9223372036854775807
%spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807 %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807
%1 = icmp sgt i128 %spec.store.select, -9223372036854775808 %1 = icmp sgt i128 %spec.store.select, -9223372036854775808
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
define i64 @stest_f16i64(half %x) { define i64 @stest_f16i64(half %x) {
; CHECK-LABEL: stest_f16i64: ; CHECK-LABEL: stest_f16i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movzwl %di, %edi ; CHECK-NEXT: movzwl %di, %edi
; CHECK-NEXT: callq __gnu_h2f_ieee@PLT ; CHECK-NEXT: callq __gnu_h2f_ieee@PLT
; CHECK-NEXT: callq __fixsfti@PLT ; CHECK-NEXT: callq __fixsfti@PLT
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rsi, %rax
; CHECK-NEXT: movq %rdx, %rdi ; CHECK-NEXT: movq %rdx, %rdi
; CHECK-NEXT: sbbq $0, %rdi ; CHECK-NEXT: sbbq $0, %rdi
; CHECK-NEXT: cmovlq %rdx, %rsi ; CHECK-NEXT: cmovlq %rdx, %rcx
; CHECK-NEXT: cmovlq %rax, %rcx ; CHECK-NEXT: cmovgeq %rsi, %rax
; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rax, %rdx
; CHECK-NEXT: movq $-1, %rdx ; CHECK-NEXT: movq $-1, %rsi
; CHECK-NEXT: sbbq %rsi, %rdx ; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: cmovgeq %rax, %rcx ; CHECK-NEXT: cmovgeq %rdx, %rax
; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi half %x to i128 %conv = fptosi half %x to i128
%0 = icmp slt i128 %conv, 9223372036854775807 %0 = icmp slt i128 %conv, 9223372036854775807
%spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807 %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807
%1 = icmp sgt i128 %spec.store.select, -9223372036854775808 %1 = icmp sgt i128 %spec.store.select, -9223372036854775808
▲ Show 20 Lines • Show All 461 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixdfti@PLT ; CHECK-NEXT: callq __fixdfti@PLT
; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rcx, %rax
; CHECK-NEXT: movq %rcx, %rsi ; CHECK-NEXT: movq %rcx, %rsi
; CHECK-NEXT: cmovbq %rax, %rsi ; CHECK-NEXT: cmovbq %rax, %rsi
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: testq %rdx, %rdx ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovsq %rax, %rcx ; CHECK-NEXT: cmovnsq %rcx, %rax
; CHECK-NEXT: cmoveq %rsi, %rcx ; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: cmovsq %rdx, %rdi ; CHECK-NEXT: cmovsq %rdx, %rdi
; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: testq %rdi, %rdi
; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rcx, %rdx
; CHECK-NEXT: cmovnsq %rcx, %rdx ; CHECK-NEXT: cmovnsq %rax, %rdx
; CHECK-NEXT: cmpq %rax, %rcx ; CHECK-NEXT: cmpq %rcx, %rax
; CHECK-NEXT: cmovbeq %rax, %rcx ; CHECK-NEXT: cmovbeq %rcx, %rax
; CHECK-NEXT: cmpq $-1, %rdi ; CHECK-NEXT: cmpq $-1, %rdi
; CHECK-NEXT: cmovneq %rdx, %rcx ; CHECK-NEXT: cmovneq %rdx, %rax
; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi double %x to i128 %conv = fptosi double %x to i128
%spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807) %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)
%spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808) %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)
%conv6 = trunc i128 %spec.store.select7 to i64 %conv6 = trunc i128 %spec.store.select7 to i64
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixsfti@PLT ; CHECK-NEXT: callq __fixsfti@PLT
; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rcx, %rax
; CHECK-NEXT: movq %rcx, %rsi ; CHECK-NEXT: movq %rcx, %rsi
; CHECK-NEXT: cmovbq %rax, %rsi ; CHECK-NEXT: cmovbq %rax, %rsi
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: testq %rdx, %rdx ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovsq %rax, %rcx ; CHECK-NEXT: cmovnsq %rcx, %rax
; CHECK-NEXT: cmoveq %rsi, %rcx ; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: cmovsq %rdx, %rdi ; CHECK-NEXT: cmovsq %rdx, %rdi
; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: testq %rdi, %rdi
; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rcx, %rdx
; CHECK-NEXT: cmovnsq %rcx, %rdx ; CHECK-NEXT: cmovnsq %rax, %rdx
; CHECK-NEXT: cmpq %rax, %rcx ; CHECK-NEXT: cmpq %rcx, %rax
; CHECK-NEXT: cmovbeq %rax, %rcx ; CHECK-NEXT: cmovbeq %rcx, %rax
; CHECK-NEXT: cmpq $-1, %rdi ; CHECK-NEXT: cmpq $-1, %rdi
; CHECK-NEXT: cmovneq %rdx, %rcx ; CHECK-NEXT: cmovneq %rdx, %rax
; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi float %x to i128 %conv = fptosi float %x to i128
%spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807) %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)
%spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808) %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)
%conv6 = trunc i128 %spec.store.select7 to i64 %conv6 = trunc i128 %spec.store.select7 to i64
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-NEXT: callq __gnu_h2f_ieee@PLT ; CHECK-NEXT: callq __gnu_h2f_ieee@PLT
; CHECK-NEXT: callq __fixsfti@PLT ; CHECK-NEXT: callq __fixsfti@PLT
; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF ; CHECK-NEXT: movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
; CHECK-NEXT: cmpq %rcx, %rax ; CHECK-NEXT: cmpq %rcx, %rax
; CHECK-NEXT: movq %rcx, %rsi ; CHECK-NEXT: movq %rcx, %rsi
; CHECK-NEXT: cmovbq %rax, %rsi ; CHECK-NEXT: cmovbq %rax, %rsi
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: testq %rdx, %rdx ; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovsq %rax, %rcx ; CHECK-NEXT: cmovnsq %rcx, %rax
; CHECK-NEXT: cmoveq %rsi, %rcx ; CHECK-NEXT: cmoveq %rsi, %rax
; CHECK-NEXT: cmovsq %rdx, %rdi ; CHECK-NEXT: cmovsq %rdx, %rdi
; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: testq %rdi, %rdi
; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: movq %rcx, %rdx
; CHECK-NEXT: cmovnsq %rcx, %rdx ; CHECK-NEXT: cmovnsq %rax, %rdx
; CHECK-NEXT: cmpq %rax, %rcx ; CHECK-NEXT: cmpq %rcx, %rax
; CHECK-NEXT: cmovbeq %rax, %rcx ; CHECK-NEXT: cmovbeq %rcx, %rax
; CHECK-NEXT: cmpq $-1, %rdi ; CHECK-NEXT: cmpq $-1, %rdi
; CHECK-NEXT: cmovneq %rdx, %rcx ; CHECK-NEXT: cmovneq %rdx, %rax
; CHECK-NEXT: movq %rcx, %rax
; CHECK-NEXT: popq %rcx ; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%conv = fptosi half %x to i128 %conv = fptosi half %x to i128
%spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807) %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)
%spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808) %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)
%conv6 = trunc i128 %spec.store.select7 to i64 %conv6 = trunc i128 %spec.store.select7 to i64
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/haddsub-3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSSE3,SSSE3-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSSE3,SSSE3-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefixes=SSSE3,SSSE3-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefixes=SSSE3,SSSE3-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX1,AVX1-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX1,AVX1-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefixes=AVX1,AVX1-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefixes=AVX1,AVX1-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
define float @pr26491(<4 x float> %a0) { define float @pr26491(<4 x float> %a0) {
; SSE2-LABEL: pr26491: ; SSE2-LABEL: pr26491:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: pr26491: ; SSSE3-SLOW-LABEL: pr26491:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: pr26491: ; SSSE3-FAST-LABEL: pr26491:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-FAST-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-FAST-NEXT: addss %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addss %xmm1, %xmm0
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/haddsub-shuf.ll

Show First 20 Lines • Show All 473 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 1> %shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 1>
ret <4 x i32> %shuf ret <4 x i32> %shuf
} }
define <8 x i32> @hadd_v8i32a(<8 x i32> %a) { define <8 x i32> @hadd_v8i32a(<8 x i32> %a) {
; SSE3-LABEL: hadd_v8i32a: ; SSE3-LABEL: hadd_v8i32a:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm2 ; SSE3-NEXT: movaps %xmm0, %xmm2
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,2]
; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,3],xmm1[1,3] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
; SSE3-NEXT: paddd %xmm0, %xmm2 ; SSE3-NEXT: paddd %xmm0, %xmm2
; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,0,1] ; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,0,1]
; SSE3-NEXT: movdqa %xmm2, %xmm1 ; SSE3-NEXT: movdqa %xmm2, %xmm1
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3_SLOW-LABEL: hadd_v8i32a: ; SSSE3_SLOW-LABEL: hadd_v8i32a:
; SSSE3_SLOW: # %bb.0: ; SSSE3_SLOW: # %bb.0:
; SSSE3_SLOW-NEXT: movdqa %xmm0, %xmm2 ; SSSE3_SLOW-NEXT: movdqa %xmm0, %xmm2
▲ Show 20 Lines • Show All 954 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/haddsub.ll

Show First 20 Lines • Show All 1,771 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
ret float %10 ret float %10
} }
define float @hadd32_4(<4 x float> %x225) { define float @hadd32_4(<4 x float> %x225) {
; SSE3-SLOW-LABEL: hadd32_4: ; SSE3-SLOW-LABEL: hadd32_4:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: hadd32_4: ; SSE3-FAST-LABEL: hadd32_4:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movaps %xmm0, %xmm1
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movaps %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: hadd32_4: ; AVX-SLOW-LABEL: hadd32_4:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 13 Lines; AVX-FAST-NEXT: retq
ret float %x230 ret float %x230
} }
define float @hadd32_8(<8 x float> %x225) { define float @hadd32_8(<8 x float> %x225) {
; SSE3-SLOW-LABEL: hadd32_8: ; SSE3-SLOW-LABEL: hadd32_8:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: hadd32_8: ; SSE3-FAST-LABEL: hadd32_8:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movaps %xmm0, %xmm1
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movaps %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: hadd32_8: ; AVX-SLOW-LABEL: hadd32_8:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 15 Lines; AVX-FAST-NEXT: retq
ret float %x230 ret float %x230
} }
define float @hadd32_16(<16 x float> %x225) { define float @hadd32_16(<16 x float> %x225) {
; SSE3-SLOW-LABEL: hadd32_16: ; SSE3-SLOW-LABEL: hadd32_16:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: hadd32_16: ; SSE3-FAST-LABEL: hadd32_16:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movaps %xmm0, %xmm1
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movaps %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: hadd32_16: ; AVX-SLOW-LABEL: hadd32_16:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 15 Lines; AVX-FAST-NEXT: retq
ret float %x230 ret float %x230
} }
define float @hadd32_4_optsize(<4 x float> %x225) optsize { define float @hadd32_4_optsize(<4 x float> %x225) optsize {
; SSE3-LABEL: hadd32_4_optsize: ; SSE3-LABEL: hadd32_4_optsize:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movaps %xmm0, %xmm1
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm0, %xmm1 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm1, %xmm1 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_4_optsize: ; AVX-LABEL: hadd32_4_optsize:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%x227 = fadd <4 x float> %x225, %x226 %x227 = fadd <4 x float> %x225, %x226
%x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%x229 = fadd <4 x float> %x227, %x228 %x229 = fadd <4 x float> %x227, %x228
%x230 = extractelement <4 x float> %x229, i32 0 %x230 = extractelement <4 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_8_optsize(<8 x float> %x225) optsize { define float @hadd32_8_optsize(<8 x float> %x225) optsize {
; SSE3-LABEL: hadd32_8_optsize: ; SSE3-LABEL: hadd32_8_optsize:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movaps %xmm0, %xmm1
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm0, %xmm1 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm1, %xmm1 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_8_optsize: ; AVX-LABEL: hadd32_8_optsize:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <8 x float> %x225, %x226 %x227 = fadd <8 x float> %x225, %x226
%x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <8 x float> %x227, %x228 %x229 = fadd <8 x float> %x227, %x228
%x230 = extractelement <8 x float> %x229, i32 0 %x230 = extractelement <8 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_16_optsize(<16 x float> %x225) optsize { define float @hadd32_16_optsize(<16 x float> %x225) optsize {
; SSE3-LABEL: hadd32_16_optsize: ; SSE3-LABEL: hadd32_16_optsize:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movaps %xmm0, %xmm1
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm0, %xmm1 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm1, %xmm1 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_16_optsize: ; AVX-LABEL: hadd32_16_optsize:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <16 x float> %x225, %x226 %x227 = fadd <16 x float> %x225, %x226
%x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <16 x float> %x227, %x228 %x229 = fadd <16 x float> %x227, %x228
%x230 = extractelement <16 x float> %x229, i32 0 %x230 = extractelement <16 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_4_pgso(<4 x float> %x225) !prof !14 { define float @hadd32_4_pgso(<4 x float> %x225) !prof !14 {
; SSE3-LABEL: hadd32_4_pgso: ; SSE3-LABEL: hadd32_4_pgso:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movaps %xmm0, %xmm1
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm0, %xmm1 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm1, %xmm1 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_4_pgso: ; AVX-LABEL: hadd32_4_pgso:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %x226 = shufflevector <4 x float> %x225, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%x227 = fadd <4 x float> %x225, %x226 %x227 = fadd <4 x float> %x225, %x226
%x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <4 x float> %x227, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%x229 = fadd <4 x float> %x227, %x228 %x229 = fadd <4 x float> %x227, %x228
%x230 = extractelement <4 x float> %x229, i32 0 %x230 = extractelement <4 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_8_pgso(<8 x float> %x225) !prof !14 { define float @hadd32_8_pgso(<8 x float> %x225) !prof !14 {
; SSE3-LABEL: hadd32_8_pgso: ; SSE3-LABEL: hadd32_8_pgso:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movaps %xmm0, %xmm1
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm0, %xmm1 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm1, %xmm1 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_8_pgso: ; AVX-LABEL: hadd32_8_pgso:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <8 x float> %x225, <8 x float> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <8 x float> %x225, %x226 %x227 = fadd <8 x float> %x225, %x226
%x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <8 x float> %x227, <8 x float> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <8 x float> %x227, %x228 %x229 = fadd <8 x float> %x227, %x228
%x230 = extractelement <8 x float> %x229, i32 0 %x230 = extractelement <8 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @hadd32_16_pgso(<16 x float> %x225) !prof !14 { define float @hadd32_16_pgso(<16 x float> %x225) !prof !14 {
; SSE3-LABEL: hadd32_16_pgso: ; SSE3-LABEL: hadd32_16_pgso:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movaps %xmm0, %xmm1 ; SSE3-NEXT: movaps %xmm0, %xmm1
; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-NEXT: addps %xmm0, %xmm1 ; SSE3-NEXT: addps %xmm1, %xmm0
; SSE3-NEXT: haddps %xmm1, %xmm1 ; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; AVX-LABEL: hadd32_16_pgso: ; AVX-LABEL: hadd32_16_pgso:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x227 = fadd <16 x float> %x225, %x226 %x227 = fadd <16 x float> %x225, %x226
%x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %x228 = shufflevector <16 x float> %x227, <16 x float> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%x229 = fadd <16 x float> %x227, %x228 %x229 = fadd <16 x float> %x227, %x228
%x230 = extractelement <16 x float> %x229, i32 0 %x230 = extractelement <16 x float> %x229, i32 0
ret float %x230 ret float %x230
} }
define float @partial_reduction_fadd_v8f32(<8 x float> %x) { define float @partial_reduction_fadd_v8f32(<8 x float> %x) {
; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32: ; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32: ; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movaps %xmm0, %xmm1
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movaps %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32: ; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 17 Lines
; Negative test - only the flags on the final math op in the ; Negative test - only the flags on the final math op in the
; sequence determine whether we can transform to horizontal ops. ; sequence determine whether we can transform to horizontal ops.
define float @partial_reduction_fadd_v8f32_wrong_flags(<8 x float> %x) { define float @partial_reduction_fadd_v8f32_wrong_flags(<8 x float> %x) {
; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags: ; SSE3-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32_wrong_flags: ; SSE3-FAST-LABEL: partial_reduction_fadd_v8f32_wrong_flags:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movaps %xmm0, %xmm1
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movaps %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags: ; AVX-SLOW-LABEL: partial_reduction_fadd_v8f32_wrong_flags:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 15 Lines; AVX-FAST-NEXT: retq
ret float %r ret float %r
} }
define float @partial_reduction_fadd_v16f32(<16 x float> %x) { define float @partial_reduction_fadd_v16f32(<16 x float> %x) {
; SSE3-SLOW-LABEL: partial_reduction_fadd_v16f32: ; SSE3-SLOW-LABEL: partial_reduction_fadd_v16f32:
; SSE3-SLOW: # %bb.0: ; SSE3-SLOW: # %bb.0:
; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSE3-SLOW-NEXT: retq ; SSE3-SLOW-NEXT: retq
; ;
; SSE3-FAST-LABEL: partial_reduction_fadd_v16f32: ; SSE3-FAST-LABEL: partial_reduction_fadd_v16f32:
; SSE3-FAST: # %bb.0: ; SSE3-FAST: # %bb.0:
; SSE3-FAST-NEXT: movaps %xmm0, %xmm1 ; SSE3-FAST-NEXT: movaps %xmm0, %xmm1
; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSE3-FAST-NEXT: haddps %xmm1, %xmm1 ; SSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSE3-FAST-NEXT: movaps %xmm1, %xmm0
; SSE3-FAST-NEXT: retq ; SSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: partial_reduction_fadd_v16f32: ; AVX-SLOW-LABEL: partial_reduction_fadd_v16f32:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm0
Show All 33 Lines

llvm/test/CodeGen/X86/horizontal-reduce-fadd.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefix=SSSE3-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefix=SSSE3-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefix=AVX1-FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefix=AVX1-FAST
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
; PR37890 - subvector reduction followed by shuffle reduction ; PR37890 - subvector reduction followed by shuffle reduction
define float @PR37890_v4f32(<4 x float> %a) { define float @PR37890_v4f32(<4 x float> %a) {
; SSE2-LABEL: PR37890_v4f32: ; SSE2-LABEL: PR37890_v4f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v4f32: ; SSSE3-SLOW-LABEL: PR37890_v4f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v4f32: ; SSSE3-FAST-LABEL: PR37890_v4f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
} }
define float @PR37890_v8f32(<8 x float> %a) { define float @PR37890_v8f32(<8 x float> %a) {
; SSE2-LABEL: PR37890_v8f32: ; SSE2-LABEL: PR37890_v8f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v8f32: ; SSSE3-SLOW-LABEL: PR37890_v8f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v8f32: ; SSSE3-FAST-LABEL: PR37890_v8f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines; AVX2-NEXT: retq
ret float %e ret float %e
} }
define double @PR37890_v8f64(<8 x double> %a) { define double @PR37890_v8f64(<8 x double> %a) {
; SSE2-LABEL: PR37890_v8f64: ; SSE2-LABEL: PR37890_v8f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addpd %xmm3, %xmm1 ; SSE2-NEXT: addpd %xmm3, %xmm1
; SSE2-NEXT: addpd %xmm2, %xmm1 ; SSE2-NEXT: addpd %xmm2, %xmm1
; SSE2-NEXT: addpd %xmm0, %xmm1 ; SSE2-NEXT: addpd %xmm1, %xmm0
; SSE2-NEXT: movapd %xmm1, %xmm0 ; SSE2-NEXT: movapd %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addsd %xmm1, %xmm0 ; SSE2-NEXT: addsd %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v8f64: ; SSSE3-SLOW-LABEL: PR37890_v8f64:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: addpd %xmm3, %xmm1 ; SSSE3-SLOW-NEXT: addpd %xmm3, %xmm1
; SSSE3-SLOW-NEXT: addpd %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: addpd %xmm2, %xmm1
; SSSE3-SLOW-NEXT: addpd %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: addpd %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movapd %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: movapd %xmm0, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSSE3-SLOW-NEXT: addsd %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: addsd %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v8f64: ; SSSE3-FAST-LABEL: PR37890_v8f64:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: addpd %xmm3, %xmm1 ; SSSE3-FAST-NEXT: addpd %xmm3, %xmm1
; SSSE3-FAST-NEXT: addpd %xmm2, %xmm1 ; SSSE3-FAST-NEXT: addpd %xmm2, %xmm1
; SSSE3-FAST-NEXT: addpd %xmm0, %xmm1 ; SSSE3-FAST-NEXT: addpd %xmm1, %xmm0
; SSSE3-FAST-NEXT: haddpd %xmm1, %xmm1 ; SSSE3-FAST-NEXT: haddpd %xmm0, %xmm0
; SSSE3-FAST-NEXT: movapd %xmm1, %xmm0
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
; ;
; AVX1-SLOW-LABEL: PR37890_v8f64: ; AVX1-SLOW-LABEL: PR37890_v8f64:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 31 Lines; AVX2-NEXT: retq
ret double %e ret double %e
} }
define float @PR37890_v16f32(<16 x float> %a) { define float @PR37890_v16f32(<16 x float> %a) {
; SSE2-LABEL: PR37890_v16f32: ; SSE2-LABEL: PR37890_v16f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm3, %xmm1 ; SSE2-NEXT: addps %xmm3, %xmm1
; SSE2-NEXT: addps %xmm2, %xmm1 ; SSE2-NEXT: addps %xmm2, %xmm1
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm1, %xmm2 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm2, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-SLOW-LABEL: PR37890_v16f32: ; SSSE3-SLOW-LABEL: PR37890_v16f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: addps %xmm3, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm3, %xmm1
; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1
; SSSE3-SLOW-NEXT: addps %xmm0, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm1, %xmm2 ; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm2 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: addss %xmm2, %xmm0 ; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: PR37890_v16f32: ; SSSE3-FAST-LABEL: PR37890_v16f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: addps %xmm3, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm3, %xmm1
; SSSE3-FAST-NEXT: addps %xmm2, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm2, %xmm1
; SSSE3-FAST-NEXT: addps %xmm0, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSSE3-FAST-NEXT: movaps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: movaps %xmm0, %xmm1
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSSE3-FAST-NEXT: addps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
; ;
; AVX1-SLOW-LABEL: PR37890_v16f32: ; AVX1-SLOW-LABEL: PR37890_v16f32:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/horizontal-sum.ll

Show First 20 Lines • Show All 529 Lines • ▼ Show 20 Lines
; ;
; VTYPE sum4(VTYPE A0, VTYPE A1, VTYPE A2, VTYPE A3) { ; VTYPE sum4(VTYPE A0, VTYPE A1, VTYPE A2, VTYPE A3) {
; return (VTYPE) { sum( A0 ), sum( A1 ), sum( A2 ), sum( A3 ) }; ; return (VTYPE) { sum( A0 ), sum( A1 ), sum( A2 ), sum( A3 ) };
; } ; }
define <4 x float> @sequential_sum_v4f32_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) { define <4 x float> @sequential_sum_v4f32_v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
; SSSE3-SLOW-LABEL: sequential_sum_v4f32_v4f32: ; SSSE3-SLOW-LABEL: sequential_sum_v4f32_v4f32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm4
; SSSE3-SLOW-NEXT: haddps %xmm1, %xmm4
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm5 ; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm5
; SSSE3-SLOW-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm1[2],xmm5[3],xmm1[3] ; SSSE3-SLOW-NEXT: haddps %xmm1, %xmm5
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm4
; SSSE3-SLOW-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSSE3-SLOW-NEXT: addps %xmm2, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm2, %xmm0
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm0[0,1] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm0[0,1]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm2[2,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3]
; SSSE3-SLOW-NEXT: addps %xmm4, %xmm5 ; SSSE3-SLOW-NEXT: addps %xmm5, %xmm4
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3]
; SSSE3-SLOW-NEXT: addps %xmm5, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm4
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm3[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm3[1,1,3,3]
; SSSE3-SLOW-NEXT: addps %xmm3, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm3, %xmm0
; SSSE3-SLOW-NEXT: movaps %xmm3, %xmm2 ; SSSE3-SLOW-NEXT: movaps %xmm3, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1]
; SSSE3-SLOW-NEXT: addps %xmm0, %xmm2 ; SSSE3-SLOW-NEXT: addps %xmm0, %xmm1
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSSE3-SLOW-NEXT: addps %xmm2, %xmm3 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm3
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,3] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,0] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,0]
; SSSE3-SLOW-NEXT: movaps %xmm1, %xmm0 ; SSSE3-SLOW-NEXT: movaps %xmm4, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: sequential_sum_v4f32_v4f32: ; SSSE3-FAST-LABEL: sequential_sum_v4f32_v4f32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4
; SSSE3-FAST-NEXT: haddps %xmm1, %xmm4
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm5 ; SSSE3-FAST-NEXT: movaps %xmm0, %xmm5
; SSSE3-FAST-NEXT: unpckhps {{.*#+}} xmm5 = xmm5[2],xmm1[2],xmm5[3],xmm1[3] ; SSSE3-FAST-NEXT: haddps %xmm1, %xmm5
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4
; SSSE3-FAST-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm1[2],xmm4[3],xmm1[3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm2[2,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,3]
; SSSE3-FAST-NEXT: haddps %xmm2, %xmm2 ; SSSE3-FAST-NEXT: haddps %xmm2, %xmm2
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm2[0,1] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm2[0,1]
; SSSE3-FAST-NEXT: addps %xmm4, %xmm5 ; SSSE3-FAST-NEXT: addps %xmm5, %xmm4
; SSSE3-FAST-NEXT: addps %xmm5, %xmm1 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm4
; SSSE3-FAST-NEXT: movaps %xmm3, %xmm0 ; SSSE3-FAST-NEXT: movaps %xmm3, %xmm0
; SSSE3-FAST-NEXT: haddps %xmm3, %xmm0 ; SSSE3-FAST-NEXT: haddps %xmm3, %xmm0
; SSSE3-FAST-NEXT: movaps %xmm3, %xmm2 ; SSSE3-FAST-NEXT: movaps %xmm3, %xmm1
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1] ; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm3[1]
; SSSE3-FAST-NEXT: addps %xmm0, %xmm2 ; SSSE3-FAST-NEXT: addps %xmm0, %xmm1
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3]
; SSSE3-FAST-NEXT: addps %xmm2, %xmm3 ; SSSE3-FAST-NEXT: addps %xmm1, %xmm3
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,3] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3]
; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,0] ; SSSE3-FAST-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,0]
; SSSE3-FAST-NEXT: movaps %xmm1, %xmm0 ; SSSE3-FAST-NEXT: movaps %xmm4, %xmm0
; SSSE3-FAST-NEXT: retq ; SSSE3-FAST-NEXT: retq
; ;
; AVX-SLOW-LABEL: sequential_sum_v4f32_v4f32: ; AVX-SLOW-LABEL: sequential_sum_v4f32_v4f32:
; AVX-SLOW: # %bb.0: ; AVX-SLOW: # %bb.0:
; AVX-SLOW-NEXT: vhaddps %xmm1, %xmm0, %xmm4 ; AVX-SLOW-NEXT: vhaddps %xmm1, %xmm0, %xmm4
; AVX-SLOW-NEXT: vunpckhps {{.*#+}} xmm5 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX-SLOW-NEXT: vunpckhps {{.*#+}} xmm5 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0] ; AVX-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
; AVX-SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero ; AVX-SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
▲ Show 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
} }
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>) declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
define <4 x float> @reduction_sum_v4f32_v4f32_reassoc(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) { define <4 x float> @reduction_sum_v4f32_v4f32_reassoc(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3) {
; SSSE3-SLOW-LABEL: reduction_sum_v4f32_v4f32_reassoc: ; SSSE3-SLOW-LABEL: reduction_sum_v4f32_v4f32_reassoc:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm4 ; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm4
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; SSSE3-SLOW-NEXT: addps %xmm0, %xmm4 ; SSSE3-SLOW-NEXT: addps %xmm4, %xmm0
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; SSSE3-SLOW-NEXT: movaps %xmm1, %xmm5 ; SSSE3-SLOW-NEXT: movaps %xmm1, %xmm5
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm1[1]
; SSSE3-SLOW-NEXT: addps %xmm1, %xmm5 ; SSSE3-SLOW-NEXT: addps %xmm1, %xmm5
; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm5[1,1,3,3] ; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm5[1,1,3,3]
; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm1
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]
; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: addps %xmm2, %xmm1
; SSSE3-SLOW-NEXT: movaps %xmm3, %xmm2 ; SSSE3-SLOW-NEXT: movaps %xmm3, %xmm2
; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1] ; SSSE3-SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm3[1]
; SSSE3-SLOW-NEXT: addps %xmm3, %xmm2 ; SSSE3-SLOW-NEXT: addps %xmm3, %xmm2
; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm3 ; SSSE3-SLOW-NEXT: movaps %xmm2, %xmm3
; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm1[0] ; SSSE3-SLOW-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm1[0]
; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSSE3-SLOW-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,0] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,0]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[1,1]
; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0] ; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,0]
; SSSE3-SLOW-NEXT: addps %xmm4, %xmm0 ; SSSE3-SLOW-NEXT: addps %xmm4, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: reduction_sum_v4f32_v4f32_reassoc: ; SSSE3-FAST-LABEL: reduction_sum_v4f32_v4f32_reassoc:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4 ; SSSE3-FAST-NEXT: movaps %xmm0, %xmm4
; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; SSSE3-FAST-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; SSSE3-FAST-NEXT: addps %xmm4, %xmm0 ; SSSE3-FAST-NEXT: addps %xmm4, %xmm0
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; AVX-FAST-NEXT: retq
%12 = insertelement <4 x float> %11, float %8, i32 3 %12 = insertelement <4 x float> %11, float %8, i32 3
ret <4 x float> %12 ret <4 x float> %12
} }
define <4 x i32> @reduction_sum_v4i32_v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3) { define <4 x i32> @reduction_sum_v4i32_v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3) {
; SSSE3-SLOW-LABEL: reduction_sum_v4i32_v4i32: ; SSSE3-SLOW-LABEL: reduction_sum_v4i32_v4i32:
; SSSE3-SLOW: # %bb.0: ; SSSE3-SLOW: # %bb.0:
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
; SSSE3-SLOW-NEXT: paddd %xmm0, %xmm4 ; SSSE3-SLOW-NEXT: paddd %xmm4, %xmm0
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,1,1] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,1,1]
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm5 = xmm1[2,3,2,3] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm5 = xmm1[2,3,2,3]
; SSSE3-SLOW-NEXT: paddd %xmm1, %xmm5 ; SSSE3-SLOW-NEXT: paddd %xmm1, %xmm5
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,1,1] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,1,1]
; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3]
; SSSE3-SLOW-NEXT: paddd %xmm2, %xmm1 ; SSSE3-SLOW-NEXT: paddd %xmm2, %xmm1
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,1,1]
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm6 = xmm3[2,3,2,3] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm6 = xmm3[2,3,2,3]
; SSSE3-SLOW-NEXT: paddd %xmm3, %xmm6 ; SSSE3-SLOW-NEXT: paddd %xmm3, %xmm6
; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,1,1] ; SSSE3-SLOW-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,1,1]
; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSSE3-SLOW-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSSE3-SLOW-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0]
; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1] ; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1]
; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSSE3-SLOW-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; SSSE3-SLOW-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0] ; SSSE3-SLOW-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSSE3-SLOW-NEXT: paddd %xmm0, %xmm4 ; SSSE3-SLOW-NEXT: paddd %xmm4, %xmm0
; SSSE3-SLOW-NEXT: movdqa %xmm4, %xmm0
; SSSE3-SLOW-NEXT: retq ; SSSE3-SLOW-NEXT: retq
; ;
; SSSE3-FAST-LABEL: reduction_sum_v4i32_v4i32: ; SSSE3-FAST-LABEL: reduction_sum_v4i32_v4i32:
; SSSE3-FAST: # %bb.0: ; SSSE3-FAST: # %bb.0:
; SSSE3-FAST-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3] ; SSSE3-FAST-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
; SSSE3-FAST-NEXT: paddd %xmm4, %xmm0 ; SSSE3-FAST-NEXT: paddd %xmm4, %xmm0
; SSSE3-FAST-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3] ; SSSE3-FAST-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3]
; SSSE3-FAST-NEXT: paddd %xmm1, %xmm4 ; SSSE3-FAST-NEXT: paddd %xmm1, %xmm4
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/lzcnt-cmp.ll

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
; X86-NEXT: movl %ecx, 4(%eax) ; X86-NEXT: movl %ecx, 4(%eax)
; X86-NEXT: movl %ecx, (%eax) ; X86-NEXT: movl %ecx, (%eax)
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
; ;
; X64-LABEL: lshr_ctlz_cmpeq_zero_v2i64: ; X64-LABEL: lshr_ctlz_cmpeq_zero_v2i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pxor %xmm1, %xmm1 ; X64-NEXT: pxor %xmm1, %xmm1
; X64-NEXT: pcmpeqd %xmm0, %xmm1 ; X64-NEXT: pcmpeqd %xmm1, %xmm0
; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,3,2] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; X64-NEXT: pand %xmm1, %xmm2 ; X64-NEXT: pand %xmm1, %xmm0
; X64-NEXT: pcmpeqd %xmm0, %xmm0 ; X64-NEXT: pcmpeqd %xmm1, %xmm1
; X64-NEXT: pxor %xmm2, %xmm0 ; X64-NEXT: pxor %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%ctlz = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %in, i1 0) %ctlz = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %in, i1 0)
%lshr = lshr <2 x i64> %ctlz, <i64 6, i64 6> %lshr = lshr <2 x i64> %ctlz, <i64 6, i64 6>
%icmp = icmp eq <2 x i64> %lshr, zeroinitializer %icmp = icmp eq <2 x i64> %lshr, zeroinitializer
%sext = sext <2 x i1> %icmp to <2 x i64> %sext = sext <2 x i1> %icmp to <2 x i64>
ret <2 x i64> %sext ret <2 x i64> %sext
} }
Show All 17 Lines
; X86-NEXT: movl %ecx, 4(%eax) ; X86-NEXT: movl %ecx, 4(%eax)
; X86-NEXT: movl %ecx, (%eax) ; X86-NEXT: movl %ecx, (%eax)
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
; ;
; X64-LABEL: lshr_ctlz_cmpne_zero_v2i64: ; X64-LABEL: lshr_ctlz_cmpne_zero_v2i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pxor %xmm1, %xmm1 ; X64-NEXT: pxor %xmm1, %xmm1
; X64-NEXT: pcmpeqd %xmm0, %xmm1 ; X64-NEXT: pcmpeqd %xmm1, %xmm0
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,0,3,2] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; X64-NEXT: pand %xmm1, %xmm0 ; X64-NEXT: pand %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%ctlz = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %in, i1 0) %ctlz = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %in, i1 0)
%lshr = lshr <2 x i64> %ctlz, <i64 6, i64 6> %lshr = lshr <2 x i64> %ctlz, <i64 6, i64 6>
%icmp = icmp ne <2 x i64> %lshr, zeroinitializer %icmp = icmp ne <2 x i64> %lshr, zeroinitializer
%sext = sext <2 x i1> %icmp to <2 x i64> %sext = sext <2 x i1> %icmp to <2 x i64>
ret <2 x i64> %sext ret <2 x i64> %sext
} }
declare i64 @llvm.ctlz.i64(i64, i1) declare i64 @llvm.ctlz.i64(i64, i1)
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)

llvm/test/CodeGen/X86/nontemporal-loads.ll

Show First 20 Lines • Show All 1,758 Lines • ▼ Show 20 Lines
define <16 x i32> @test_masked_v16i32(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) { define <16 x i32> @test_masked_v16i32(i8 * %addr, <16 x i32> %old, <16 x i32> %mask1) {
; SSE2-LABEL: test_masked_v16i32: ; SSE2-LABEL: test_masked_v16i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm8, %xmm8 ; SSE2-NEXT: pxor %xmm8, %xmm8
; SSE2-NEXT: pcmpeqd %xmm8, %xmm7 ; SSE2-NEXT: pcmpeqd %xmm8, %xmm7
; SSE2-NEXT: pcmpeqd %xmm8, %xmm6 ; SSE2-NEXT: pcmpeqd %xmm8, %xmm6
; SSE2-NEXT: pcmpeqd %xmm8, %xmm5 ; SSE2-NEXT: pcmpeqd %xmm8, %xmm5
; SSE2-NEXT: pcmpeqd %xmm8, %xmm4 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm8
; SSE2-NEXT: pand %xmm4, %xmm0 ; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: pandn (%rdi), %xmm4 ; SSE2-NEXT: pandn (%rdi), %xmm8
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: por %xmm8, %xmm0
; SSE2-NEXT: pand %xmm5, %xmm1 ; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: pandn 16(%rdi), %xmm5 ; SSE2-NEXT: pandn 16(%rdi), %xmm5
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: pand %xmm6, %xmm2 ; SSE2-NEXT: pand %xmm6, %xmm2
; SSE2-NEXT: pandn 32(%rdi), %xmm6 ; SSE2-NEXT: pandn 32(%rdi), %xmm6
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: por %xmm6, %xmm2
; SSE2-NEXT: pand %xmm7, %xmm3 ; SSE2-NEXT: pand %xmm7, %xmm3
; SSE2-NEXT: pandn 48(%rdi), %xmm7 ; SSE2-NEXT: pandn 48(%rdi), %xmm7
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE4-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE4-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE4-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE4-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE4-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; SSE4-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; SSE4-NEXT: por %xmm2, %xmm1 ; SSE4-NEXT: por %xmm2, %xmm0
; SSE4-NEXT: movdqa {{.*#+}} xmm0 = [1431655765,858993459,715827882,477218588] ; SSE4-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,858993459,715827882,477218588]
; SSE4-NEXT: pminud %xmm1, %xmm0 ; SSE4-NEXT: pminud %xmm0, %xmm1
; SSE4-NEXT: pcmpeqd %xmm1, %xmm0 ; SSE4-NEXT: pcmpeqd %xmm1, %xmm0
; SSE4-NEXT: retq ; SSE4-NEXT: retq
; ;
; AVX2-LABEL: p5_vector_urem_by_const__nonsplat: ; AVX2-LABEL: p5_vector_urem_by_const__nonsplat:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 ; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
▲ Show 20 Lines • Show All 220 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/pmulh.ll

Show First 20 Lines • Show All 814 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%c = mul <4 x i32> %a1, %b1 %c = mul <4 x i32> %a1, %b1
%d = ashr <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16> %d = ashr <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %d ret <4 x i32> %d
} }
define <8 x i32> @zext_mulhuw_v8i16_lshr(<8 x i16> %a, <8 x i16> %b) { define <8 x i32> @zext_mulhuw_v8i16_lshr(<8 x i16> %a, <8 x i16> %b) {
; SSE2-LABEL: zext_mulhuw_v8i16_lshr: ; SSE2-LABEL: zext_mulhuw_v8i16_lshr:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: pmulhuw %xmm0, %xmm1
; SSE2-NEXT: pmulhuw %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: zext_mulhuw_v8i16_lshr: ; SSE41-LABEL: zext_mulhuw_v8i16_lshr:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pmulhuw %xmm1, %xmm2 ; SSE41-NEXT: pmulhuw %xmm1, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
Show All 11 Lines; AVX-NEXT: retq
%c = mul <8 x i32> %a1, %b1 %c = mul <8 x i32> %a1, %b1
%d = lshr <8 x i32> %c, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> %d = lshr <8 x i32> %c, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <8 x i32> %d ret <8 x i32> %d
} }
define <8 x i32> @mulhsw_v8i16_lshr(<8 x i16> %a, <8 x i16> %b) { define <8 x i32> @mulhsw_v8i16_lshr(<8 x i16> %a, <8 x i16> %b) {
; SSE2-LABEL: mulhsw_v8i16_lshr: ; SSE2-LABEL: mulhsw_v8i16_lshr:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: pmulhw %xmm0, %xmm1
; SSE2-NEXT: pmulhw %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: mulhsw_v8i16_lshr: ; SSE41-LABEL: mulhsw_v8i16_lshr:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pmulhw %xmm1, %xmm2 ; SSE41-NEXT: pmulhw %xmm1, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%c = mul <8 x i32> %a1, %b1 %c = mul <8 x i32> %a1, %b1
%d = ashr <8 x i32> %c, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> %d = ashr <8 x i32> %c, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <8 x i32> %d ret <8 x i32> %d
} }
define <16 x i32> @zext_mulhuw_v16i16_lshr(<16 x i16> %a, <16 x i16> %b) { define <16 x i32> @zext_mulhuw_v16i16_lshr(<16 x i16> %a, <16 x i16> %b) {
; SSE2-LABEL: zext_mulhuw_v16i16_lshr: ; SSE2-LABEL: zext_mulhuw_v16i16_lshr:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: pmulhuw %xmm2, %xmm4
; SSE2-NEXT: pmulhuw %xmm2, %xmm1
; SSE2-NEXT: pxor %xmm5, %xmm5 ; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm4, %xmm0
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm5[4],xmm1[5],xmm5[5],xmm1[6],xmm5[6],xmm1[7],xmm5[7]
; SSE2-NEXT: pmulhuw %xmm3, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm2
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7]
; SSE2-NEXT: movdqa %xmm4, %xmm3 ; SSE2-NEXT: pmulhuw %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm2
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm5[4],xmm3[5],xmm5[5],xmm3[6],xmm5[6],xmm3[7],xmm5[7]
; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: zext_mulhuw_v16i16_lshr: ; SSE41-LABEL: zext_mulhuw_v16i16_lshr:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: movdqa %xmm1, %xmm4
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: pmulhuw %xmm2, %xmm1 ; SSE41-NEXT: pmulhuw %xmm2, %xmm1
; SSE41-NEXT: pxor %xmm5, %xmm5 ; SSE41-NEXT: pxor %xmm5, %xmm5
Show All 23 Lines; AVX512-NEXT: retq
%c = mul <16 x i32> %a1, %b1 %c = mul <16 x i32> %a1, %b1
%d = lshr <16 x i32> %c, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> %d = lshr <16 x i32> %c, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i32> %d ret <16 x i32> %d
} }
define <16 x i32> @mulhsw_v16i16_lshr(<16 x i16> %a, <16 x i16> %b) { define <16 x i32> @mulhsw_v16i16_lshr(<16 x i16> %a, <16 x i16> %b) {
; SSE2-LABEL: mulhsw_v16i16_lshr: ; SSE2-LABEL: mulhsw_v16i16_lshr:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: pmulhw %xmm2, %xmm4
; SSE2-NEXT: pmulhw %xmm2, %xmm1
; SSE2-NEXT: pxor %xmm5, %xmm5 ; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm4, %xmm0
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm5[4],xmm1[5],xmm5[5],xmm1[6],xmm5[6],xmm1[7],xmm5[7]
; SSE2-NEXT: pmulhw %xmm3, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm2
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm5[4],xmm4[5],xmm5[5],xmm4[6],xmm5[6],xmm4[7],xmm5[7]
; SSE2-NEXT: movdqa %xmm4, %xmm3 ; SSE2-NEXT: pmulhw %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm2
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm5[4],xmm3[5],xmm5[5],xmm3[6],xmm5[6],xmm3[7],xmm5[7]
; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: mulhsw_v16i16_lshr: ; SSE41-LABEL: mulhsw_v16i16_lshr:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: movdqa %xmm1, %xmm4
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: pmulhw %xmm2, %xmm1 ; SSE41-NEXT: pmulhw %xmm2, %xmm1
; SSE41-NEXT: pxor %xmm5, %xmm5 ; SSE41-NEXT: pxor %xmm5, %xmm5
▲ Show 20 Lines • Show All 1,097 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/popcnt.ll

Show All 25 Lines
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: cnt8: ; X64-LABEL: cnt8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edi, %eax
; X64-NEXT: shrb %al ; X64-NEXT: shrb %al
; X64-NEXT: andb $85, %al ; X64-NEXT: andb $85, %al
; X64-NEXT: subb %al, %dil ; X64-NEXT: subb %al, %dil
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edi, %ecx
; X64-NEXT: andb $51, %al ; X64-NEXT: andb $51, %cl
; X64-NEXT: shrb $2, %dil ; X64-NEXT: shrb $2, %dil
; X64-NEXT: andb $51, %dil ; X64-NEXT: andb $51, %dil
; X64-NEXT: addb %al, %dil ; X64-NEXT: addb %dil, %cl
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %ecx, %eax
; X64-NEXT: shrb $4, %al ; X64-NEXT: shrb $4, %al
; X64-NEXT: addb %dil, %al ; X64-NEXT: addb %cl, %al
; X64-NEXT: andb $15, %al ; X64-NEXT: andb $15, %al
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt8: ; X86-POPCNT-LABEL: cnt8:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: popcntl %eax, %eax ; X86-POPCNT-NEXT: popcntl %eax, %eax
; X86-POPCNT-NEXT: # kill: def $al killed $al killed $eax ; X86-POPCNT-NEXT: # kill: def $al killed $al killed $eax
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
; X64-NEXT: shrq %rax ; X64-NEXT: shrq %rax
; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 ; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: subq %rcx, %rdi ; X64-NEXT: subq %rcx, %rdi
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 ; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: shrq $2, %rdi ; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rax, %rdi ; X64-NEXT: andq %rdi, %rax
; X64-NEXT: addq %rcx, %rdi ; X64-NEXT: addq %rcx, %rax
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rax, %rcx
; X64-NEXT: shrq $4, %rax ; X64-NEXT: shrq $4, %rcx
; X64-NEXT: addq %rdi, %rax ; X64-NEXT: addq %rax, %rcx
; X64-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F ; X64-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rcx, %rdx
; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101 ; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101
; X64-NEXT: imulq %rcx, %rax ; X64-NEXT: imulq %rdx, %rax
; X64-NEXT: shrq $56, %rax ; X64-NEXT: shrq $56, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt64: ; X86-POPCNT-LABEL: cnt64:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: addl %ecx, %eax ; X86-POPCNT-NEXT: addl %ecx, %eax
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
; ;
; X64-LABEL: cnt128: ; X64-LABEL: cnt128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rsi, %rax ; X64-NEXT: movq %rsi, %rax
; X64-NEXT: shrq %rax ; X64-NEXT: shrq %rax
; X64-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555 ; X64-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555
; X64-NEXT: andq %r8, %rax ; X64-NEXT: andq %r8, %rax
; X64-NEXT: subq %rax, %rsi ; X64-NEXT: subq %rax, %rsi
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 ; X64-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
; X64-NEXT: movq %rsi, %rcx ; X64-NEXT: movq %rsi, %rax
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rcx, %rax
; X64-NEXT: shrq $2, %rsi ; X64-NEXT: shrq $2, %rsi
; X64-NEXT: andq %rax, %rsi ; X64-NEXT: andq %rcx, %rsi
; X64-NEXT: addq %rcx, %rsi ; X64-NEXT: addq %rsi, %rax
; X64-NEXT: movq %rsi, %rcx ; X64-NEXT: movq %rax, %rdx
; X64-NEXT: shrq $4, %rcx ; X64-NEXT: shrq $4, %rdx
; X64-NEXT: addq %rsi, %rcx ; X64-NEXT: addq %rax, %rdx
; X64-NEXT: movabsq $1085102592571150095, %r9 # imm = 0xF0F0F0F0F0F0F0F ; X64-NEXT: movabsq $1085102592571150095, %r9 # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %r9, %rcx ; X64-NEXT: andq %r9, %rdx
; X64-NEXT: movabsq $72340172838076673, %rdx # imm = 0x101010101010101 ; X64-NEXT: movabsq $72340172838076673, %rsi # imm = 0x101010101010101
; X64-NEXT: imulq %rdx, %rcx ; X64-NEXT: imulq %rsi, %rdx
; X64-NEXT: shrq $56, %rcx ; X64-NEXT: shrq $56, %rdx
; X64-NEXT: movq %rdi, %rsi ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shrq %rsi ; X64-NEXT: shrq %rax
; X64-NEXT: andq %r8, %rsi ; X64-NEXT: andq %r8, %rax
; X64-NEXT: subq %rsi, %rdi ; X64-NEXT: subq %rax, %rdi
; X64-NEXT: movq %rdi, %rsi
; X64-NEXT: andq %rax, %rsi
; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rax, %rdi
; X64-NEXT: addq %rsi, %rdi
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: andq %rcx, %rax
; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rdi, %rcx
; X64-NEXT: addq %rax, %rcx
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: shrq $4, %rax ; X64-NEXT: shrq $4, %rax
; X64-NEXT: addq %rdi, %rax ; X64-NEXT: addq %rcx, %rax
; X64-NEXT: andq %r9, %rax ; X64-NEXT: andq %r9, %rax
; X64-NEXT: imulq %rdx, %rax ; X64-NEXT: imulq %rsi, %rax
; X64-NEXT: shrq $56, %rax ; X64-NEXT: shrq $56, %rax
; X64-NEXT: addq %rcx, %rax ; X64-NEXT: addq %rdx, %rax
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt128: ; X86-POPCNT-LABEL: cnt128:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: pushl %esi ; X86-POPCNT-NEXT: pushl %esi
; X86-POPCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx
▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
; X64-NEXT: shrq %rax ; X64-NEXT: shrq %rax
; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 ; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: subq %rcx, %rdi ; X64-NEXT: subq %rcx, %rdi
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 ; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: shrq $2, %rdi ; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rax, %rdi ; X64-NEXT: andq %rdi, %rax
; X64-NEXT: addq %rcx, %rdi ; X64-NEXT: addq %rcx, %rax
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rax, %rcx
; X64-NEXT: shrq $4, %rax ; X64-NEXT: shrq $4, %rcx
; X64-NEXT: addq %rdi, %rax ; X64-NEXT: addq %rax, %rcx
; X64-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F ; X64-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rcx, %rdx
; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101 ; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101
; X64-NEXT: imulq %rcx, %rax ; X64-NEXT: imulq %rdx, %rax
; X64-NEXT: shrq $56, %rax ; X64-NEXT: shrq $56, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt64_noimplicitfloat: ; X86-POPCNT-LABEL: cnt64_noimplicitfloat:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: addl %ecx, %eax ; X86-POPCNT-NEXT: addl %ecx, %eax
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; X64-NEXT: shrq %rax ; X64-NEXT: shrq %rax
; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 ; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: subq %rcx, %rdi ; X64-NEXT: subq %rcx, %rdi
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 ; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: shrq $2, %rdi ; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rax, %rdi ; X64-NEXT: andq %rdi, %rax
; X64-NEXT: addq %rcx, %rdi ; X64-NEXT: addq %rcx, %rax
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rax, %rcx
; X64-NEXT: shrq $4, %rax ; X64-NEXT: shrq $4, %rcx
; X64-NEXT: addq %rdi, %rax ; X64-NEXT: addq %rax, %rcx
; X64-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F ; X64-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rcx, %rdx
; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101 ; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101
; X64-NEXT: imulq %rcx, %rax ; X64-NEXT: imulq %rdx, %rax
; X64-NEXT: shrq $56, %rax ; X64-NEXT: shrq $56, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt64_optsize: ; X86-POPCNT-LABEL: cnt64_optsize:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: addl %ecx, %eax ; X86-POPCNT-NEXT: addl %ecx, %eax
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; ;
; X64-LABEL: cnt128_optsize: ; X64-LABEL: cnt128_optsize:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rsi, %rax ; X64-NEXT: movq %rsi, %rax
; X64-NEXT: shrq %rax ; X64-NEXT: shrq %rax
; X64-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555 ; X64-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555
; X64-NEXT: andq %r8, %rax ; X64-NEXT: andq %r8, %rax
; X64-NEXT: subq %rax, %rsi ; X64-NEXT: subq %rax, %rsi
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 ; X64-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
; X64-NEXT: movq %rsi, %rcx ; X64-NEXT: movq %rsi, %rax
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rcx, %rax
; X64-NEXT: shrq $2, %rsi ; X64-NEXT: shrq $2, %rsi
; X64-NEXT: andq %rax, %rsi ; X64-NEXT: andq %rcx, %rsi
; X64-NEXT: addq %rcx, %rsi ; X64-NEXT: addq %rsi, %rax
; X64-NEXT: movq %rsi, %rcx ; X64-NEXT: movq %rax, %rdx
; X64-NEXT: shrq $4, %rcx ; X64-NEXT: shrq $4, %rdx
; X64-NEXT: addq %rsi, %rcx ; X64-NEXT: addq %rax, %rdx
; X64-NEXT: movabsq $1085102592571150095, %r9 # imm = 0xF0F0F0F0F0F0F0F ; X64-NEXT: movabsq $1085102592571150095, %r9 # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %r9, %rcx ; X64-NEXT: andq %r9, %rdx
; X64-NEXT: movabsq $72340172838076673, %rdx # imm = 0x101010101010101 ; X64-NEXT: movabsq $72340172838076673, %rsi # imm = 0x101010101010101
; X64-NEXT: imulq %rdx, %rcx ; X64-NEXT: imulq %rsi, %rdx
; X64-NEXT: shrq $56, %rcx ; X64-NEXT: shrq $56, %rdx
; X64-NEXT: movq %rdi, %rsi ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shrq %rsi ; X64-NEXT: shrq %rax
; X64-NEXT: andq %r8, %rsi ; X64-NEXT: andq %r8, %rax
; X64-NEXT: subq %rsi, %rdi ; X64-NEXT: subq %rax, %rdi
; X64-NEXT: movq %rdi, %rsi
; X64-NEXT: andq %rax, %rsi
; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rax, %rdi
; X64-NEXT: addq %rsi, %rdi
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: andq %rcx, %rax
; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rdi, %rcx
; X64-NEXT: addq %rax, %rcx
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: shrq $4, %rax ; X64-NEXT: shrq $4, %rax
; X64-NEXT: addq %rdi, %rax ; X64-NEXT: addq %rcx, %rax
; X64-NEXT: andq %r9, %rax ; X64-NEXT: andq %r9, %rax
; X64-NEXT: imulq %rdx, %rax ; X64-NEXT: imulq %rsi, %rax
; X64-NEXT: shrq $56, %rax ; X64-NEXT: shrq $56, %rax
; X64-NEXT: addq %rcx, %rax ; X64-NEXT: addq %rdx, %rax
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt128_optsize: ; X86-POPCNT-LABEL: cnt128_optsize:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: pushl %esi ; X86-POPCNT-NEXT: pushl %esi
; X86-POPCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx
▲ Show 20 Lines • Show All 215 Lines • ▼ Show 20 Lines
; X64-NEXT: shrq %rax ; X64-NEXT: shrq %rax
; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 ; X64-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: subq %rcx, %rdi ; X64-NEXT: subq %rcx, %rdi
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 ; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rax, %rcx
; X64-NEXT: shrq $2, %rdi ; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rax, %rdi ; X64-NEXT: andq %rdi, %rax
; X64-NEXT: addq %rcx, %rdi ; X64-NEXT: addq %rcx, %rax
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rax, %rcx
; X64-NEXT: shrq $4, %rax ; X64-NEXT: shrq $4, %rcx
; X64-NEXT: addq %rdi, %rax ; X64-NEXT: addq %rax, %rcx
; X64-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F ; X64-NEXT: movabsq $1085102592571150095, %rdx # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rcx, %rdx
; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101 ; X64-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101
; X64-NEXT: imulq %rcx, %rax ; X64-NEXT: imulq %rdx, %rax
; X64-NEXT: shrq $56, %rax ; X64-NEXT: shrq $56, %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt64_pgso: ; X86-POPCNT-LABEL: cnt64_pgso:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: addl %ecx, %eax ; X86-POPCNT-NEXT: addl %ecx, %eax
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; ;
; X64-LABEL: cnt128_pgso: ; X64-LABEL: cnt128_pgso:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rsi, %rax ; X64-NEXT: movq %rsi, %rax
; X64-NEXT: shrq %rax ; X64-NEXT: shrq %rax
; X64-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555 ; X64-NEXT: movabsq $6148914691236517205, %r8 # imm = 0x5555555555555555
; X64-NEXT: andq %r8, %rax ; X64-NEXT: andq %r8, %rax
; X64-NEXT: subq %rax, %rsi ; X64-NEXT: subq %rax, %rsi
; X64-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 ; X64-NEXT: movabsq $3689348814741910323, %rcx # imm = 0x3333333333333333
; X64-NEXT: movq %rsi, %rcx ; X64-NEXT: movq %rsi, %rax
; X64-NEXT: andq %rax, %rcx ; X64-NEXT: andq %rcx, %rax
; X64-NEXT: shrq $2, %rsi ; X64-NEXT: shrq $2, %rsi
; X64-NEXT: andq %rax, %rsi ; X64-NEXT: andq %rcx, %rsi
; X64-NEXT: addq %rcx, %rsi ; X64-NEXT: addq %rsi, %rax
; X64-NEXT: movq %rsi, %rcx ; X64-NEXT: movq %rax, %rdx
; X64-NEXT: shrq $4, %rcx ; X64-NEXT: shrq $4, %rdx
; X64-NEXT: addq %rsi, %rcx ; X64-NEXT: addq %rax, %rdx
; X64-NEXT: movabsq $1085102592571150095, %r9 # imm = 0xF0F0F0F0F0F0F0F ; X64-NEXT: movabsq $1085102592571150095, %r9 # imm = 0xF0F0F0F0F0F0F0F
; X64-NEXT: andq %r9, %rcx ; X64-NEXT: andq %r9, %rdx
; X64-NEXT: movabsq $72340172838076673, %rdx # imm = 0x101010101010101 ; X64-NEXT: movabsq $72340172838076673, %rsi # imm = 0x101010101010101
; X64-NEXT: imulq %rdx, %rcx ; X64-NEXT: imulq %rsi, %rdx
; X64-NEXT: shrq $56, %rcx ; X64-NEXT: shrq $56, %rdx
; X64-NEXT: movq %rdi, %rsi
; X64-NEXT: shrq %rsi
; X64-NEXT: andq %r8, %rsi
; X64-NEXT: subq %rsi, %rdi
; X64-NEXT: movq %rdi, %rsi
; X64-NEXT: andq %rax, %rsi
; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rax, %rdi
; X64-NEXT: addq %rsi, %rdi
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: shrq %rax
; X64-NEXT: andq %r8, %rax
; X64-NEXT: subq %rax, %rdi
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: andq %rcx, %rax
; X64-NEXT: shrq $2, %rdi
; X64-NEXT: andq %rdi, %rcx
; X64-NEXT: addq %rax, %rcx
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: shrq $4, %rax ; X64-NEXT: shrq $4, %rax
; X64-NEXT: addq %rdi, %rax ; X64-NEXT: addq %rcx, %rax
; X64-NEXT: andq %r9, %rax ; X64-NEXT: andq %r9, %rax
; X64-NEXT: imulq %rdx, %rax ; X64-NEXT: imulq %rsi, %rax
; X64-NEXT: shrq $56, %rax ; X64-NEXT: shrq $56, %rax
; X64-NEXT: addq %rcx, %rax ; X64-NEXT: addq %rdx, %rax
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-POPCNT-LABEL: cnt128_pgso: ; X86-POPCNT-LABEL: cnt128_pgso:
; X86-POPCNT: # %bb.0: ; X86-POPCNT: # %bb.0:
; X86-POPCNT-NEXT: pushl %esi ; X86-POPCNT-NEXT: pushl %esi
; X86-POPCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-POPCNT-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx ; X86-POPCNT-NEXT: popcntl {{[0-9]+}}(%esp), %ecx
▲ Show 20 Lines • Show All 245 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/pull-binop-through-shift.ll

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines; X32-NEXT: retl
%r = shl i32 %t0, 8 %r = shl i32 %t0, 8
store i32 %r, i32* %dst store i32 %r, i32* %dst
ret i32 %r ret i32 %r
} }
define i32 @add_signbit_shl(i32 %x, i32* %dst) { define i32 @add_signbit_shl(i32 %x, i32* %dst) {
; X64-LABEL: add_signbit_shl: ; X64-LABEL: add_signbit_shl:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: shll $8, %eax ; X64-NEXT: shll $8, %edi
; X64-NEXT: addl $-16777216, %eax # imm = 0xFF000000 ; X64-NEXT: leal -16777216(%rdi), %eax
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %eax, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_signbit_shl: ; X32-LABEL: add_signbit_shl:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $8, %eax ; X32-NEXT: shll $8, %eax
; X32-NEXT: addl $-16777216, %eax # imm = 0xFF000000 ; X32-NEXT: addl $-16777216, %eax # imm = 0xFF000000
; X32-NEXT: movl %eax, (%ecx) ; X32-NEXT: movl %eax, (%ecx)
; X32-NEXT: retl ; X32-NEXT: retl
%t0 = add i32 %x, 4294901760 ; 0xFFFF0000 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
%r = shl i32 %t0, 8 %r = shl i32 %t0, 8
store i32 %r, i32* %dst store i32 %r, i32* %dst
ret i32 %r ret i32 %r
} }
define i32 @add_nosignbit_shl(i32 %x, i32* %dst) { define i32 @add_nosignbit_shl(i32 %x, i32* %dst) {
; X64-LABEL: add_nosignbit_shl: ; X64-LABEL: add_nosignbit_shl:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: shll $8, %eax ; X64-NEXT: shll $8, %edi
; X64-NEXT: addl $-16777216, %eax # imm = 0xFF000000 ; X64-NEXT: leal -16777216(%rdi), %eax
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %eax, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_nosignbit_shl: ; X32-LABEL: add_nosignbit_shl:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shll $8, %eax ; X32-NEXT: shll $8, %eax
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines; X32-NEXT: retl
%r = lshr i32 %t0, 8 %r = lshr i32 %t0, 8
store i32 %r, i32* %dst store i32 %r, i32* %dst
ret i32 %r ret i32 %r
} }
define i32 @add_signbit_lshr(i32 %x, i32* %dst) { define i32 @add_signbit_lshr(i32 %x, i32* %dst) {
; X64-LABEL: add_signbit_lshr: ; X64-LABEL: add_signbit_lshr:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: addl $-65536, %eax # imm = 0xFFFF0000 ; X64-NEXT: leal -65536(%rdi), %eax
; X64-NEXT: shrl $8, %eax ; X64-NEXT: shrl $8, %eax
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %eax, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_signbit_lshr: ; X32-LABEL: add_signbit_lshr:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
; X32-NEXT: addl {{[0-9]+}}(%esp), %eax ; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
; X32-NEXT: shrl $8, %eax ; X32-NEXT: shrl $8, %eax
; X32-NEXT: movl %eax, (%ecx) ; X32-NEXT: movl %eax, (%ecx)
; X32-NEXT: retl ; X32-NEXT: retl
%t0 = add i32 %x, 4294901760 ; 0xFFFF0000 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
%r = lshr i32 %t0, 8 %r = lshr i32 %t0, 8
store i32 %r, i32* %dst store i32 %r, i32* %dst
ret i32 %r ret i32 %r
} }
define i32 @add_nosignbit_lshr(i32 %x, i32* %dst) { define i32 @add_nosignbit_lshr(i32 %x, i32* %dst) {
; X64-LABEL: add_nosignbit_lshr: ; X64-LABEL: add_nosignbit_lshr:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: addl $2147418112, %eax # imm = 0x7FFF0000 ; X64-NEXT: leal 2147418112(%rdi), %eax
; X64-NEXT: shrl $8, %eax ; X64-NEXT: shrl $8, %eax
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %eax, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_nosignbit_lshr: ; X32-LABEL: add_nosignbit_lshr:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines; X32-NEXT: retl
%r = ashr i32 %t0, 8 %r = ashr i32 %t0, 8
store i32 %r, i32* %dst store i32 %r, i32* %dst
ret i32 %r ret i32 %r
} }
define i32 @add_signbit_ashr(i32 %x, i32* %dst) { define i32 @add_signbit_ashr(i32 %x, i32* %dst) {
; X64-LABEL: add_signbit_ashr: ; X64-LABEL: add_signbit_ashr:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: addl $-65536, %eax # imm = 0xFFFF0000 ; X64-NEXT: leal -65536(%rdi), %eax
; X64-NEXT: sarl $8, %eax ; X64-NEXT: sarl $8, %eax
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %eax, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_signbit_ashr: ; X32-LABEL: add_signbit_ashr:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
; X32-NEXT: addl {{[0-9]+}}(%esp), %eax ; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
; X32-NEXT: sarl $8, %eax ; X32-NEXT: sarl $8, %eax
; X32-NEXT: movl %eax, (%ecx) ; X32-NEXT: movl %eax, (%ecx)
; X32-NEXT: retl ; X32-NEXT: retl
%t0 = add i32 %x, 4294901760 ; 0xFFFF0000 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
%r = ashr i32 %t0, 8 %r = ashr i32 %t0, 8
store i32 %r, i32* %dst store i32 %r, i32* %dst
ret i32 %r ret i32 %r
} }
define i32 @add_nosignbit_ashr(i32 %x, i32* %dst) { define i32 @add_nosignbit_ashr(i32 %x, i32* %dst) {
; X64-LABEL: add_nosignbit_ashr: ; X64-LABEL: add_nosignbit_ashr:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: addl $2147418112, %eax # imm = 0x7FFF0000 ; X64-NEXT: leal 2147418112(%rdi), %eax
; X64-NEXT: sarl $8, %eax ; X64-NEXT: sarl $8, %eax
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %eax, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: add_nosignbit_ashr: ; X32-LABEL: add_nosignbit_ashr:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
Show All 9 Lines

llvm/test/CodeGen/X86/rem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+cmov | FileCheck %s ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+cmov | FileCheck %s
define i32 @test1(i32 %X) { define i32 @test1(i32 %X) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081 ; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: imull %edx ; CHECK-NEXT: imull %edx
; CHECK-NEXT: addl %ecx, %edx ; CHECK-NEXT: leal (%edx,%ecx), %eax
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: sarl $7, %edx ; CHECK-NEXT: sarl $7, %eax
; CHECK-NEXT: addl %eax, %edx ; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: shll $8, %eax ; CHECK-NEXT: shll $8, %edx
; CHECK-NEXT: subl %eax, %edx ; CHECK-NEXT: subl %edx, %eax
; CHECK-NEXT: addl %edx, %ecx ; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%tmp1 = srem i32 %X, 255 %tmp1 = srem i32 %X, 255
ret i32 %tmp1 ret i32 %tmp1
} }
define i32 @test2(i32 %X) { define i32 @test2(i32 %X) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sat-add.ll

Show First 20 Lines • Show All 1,259 Lines • ▼ Show 20 Lines
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
; SSE41-NEXT: por %xmm1, %xmm0 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: por %xmm2, %xmm0 ; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; SSE42-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: ; SSE42-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; SSE42-NEXT: paddq %xmm0, %xmm1 ; SSE42-NEXT: movdqa %xmm0, %xmm3
; SSE42-NEXT: pxor %xmm2, %xmm0 ; SSE42-NEXT: pxor %xmm2, %xmm3
; SSE42-NEXT: pxor %xmm1, %xmm2 ; SSE42-NEXT: paddq %xmm1, %xmm0
; SSE42-NEXT: pcmpgtq %xmm2, %xmm0 ; SSE42-NEXT: pxor %xmm0, %xmm2
; SSE42-NEXT: por %xmm1, %xmm0 ; SSE42-NEXT: pcmpgtq %xmm2, %xmm3
; SSE42-NEXT: por %xmm3, %xmm0
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX2-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: ; AVX2-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3 ; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm1 ; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm1
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sdiv_fix_sat.ll

Show All 23 Lines
; X64-NEXT: testl %esi, %esi ; X64-NEXT: testl %esi, %esi
; X64-NEXT: sets %sil ; X64-NEXT: sets %sil
; X64-NEXT: testl %ecx, %ecx ; X64-NEXT: testl %ecx, %ecx
; X64-NEXT: sets %cl ; X64-NEXT: sets %cl
; X64-NEXT: xorb %sil, %cl ; X64-NEXT: xorb %sil, %cl
; X64-NEXT: testl %edx, %edx ; X64-NEXT: testl %edx, %edx
; X64-NEXT: setne %dl ; X64-NEXT: setne %dl
; X64-NEXT: testb %cl, %dl ; X64-NEXT: testb %cl, %dl
; X64-NEXT: cmovel %eax, %edi ; X64-NEXT: cmovnel %edi, %eax
; X64-NEXT: cmpl $65535, %edi # imm = 0xFFFF ; X64-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X64-NEXT: movl $65535, %ecx # imm = 0xFFFF ; X64-NEXT: movl $65535, %ecx # imm = 0xFFFF
; X64-NEXT: cmovll %edi, %ecx
; X64-NEXT: cmpl $-65535, %ecx # imm = 0xFFFF0001
; X64-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
; X64-NEXT: cmovgel %ecx, %eax ; X64-NEXT: cmovgel %ecx, %eax
; X64-NEXT: cmpl $-65535, %eax # imm = 0xFFFF0001
; X64-NEXT: movl $-65536, %ecx # imm = 0xFFFF0000
; X64-NEXT: cmovll %ecx, %eax
; X64-NEXT: shrl %eax ; X64-NEXT: shrl %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: func: ; X86-LABEL: func:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movswl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movswl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: shll $8, %ecx ; X86-NEXT: shll $8, %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: cltd ; X86-NEXT: cltd
; X86-NEXT: idivl %edi ; X86-NEXT: idivl %esi
; X86-NEXT: leal -1(%eax), %esi ; X86-NEXT: leal -1(%eax), %edi
; X86-NEXT: testl %edi, %edi ; X86-NEXT: testl %esi, %esi
; X86-NEXT: sets %bl ; X86-NEXT: sets %bl
; X86-NEXT: testl %ecx, %ecx ; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: sets %cl ; X86-NEXT: sets %cl
; X86-NEXT: xorb %bl, %cl ; X86-NEXT: xorb %bl, %cl
; X86-NEXT: testl %edx, %edx ; X86-NEXT: testl %edx, %edx
; X86-NEXT: setne %dl ; X86-NEXT: setne %dl
; X86-NEXT: testb %cl, %dl ; X86-NEXT: testb %cl, %dl
; X86-NEXT: cmovel %eax, %esi ; X86-NEXT: cmovnel %edi, %eax
; X86-NEXT: cmpl $65535, %esi # imm = 0xFFFF ; X86-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-NEXT: movl $65535, %ecx # imm = 0xFFFF ; X86-NEXT: movl $65535, %ecx # imm = 0xFFFF
; X86-NEXT: cmovll %esi, %ecx
; X86-NEXT: cmpl $-65535, %ecx # imm = 0xFFFF0001
; X86-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
; X86-NEXT: cmovgel %ecx, %eax ; X86-NEXT: cmovgel %ecx, %eax
; X86-NEXT: cmpl $-65535, %eax # imm = 0xFFFF0001
; X86-NEXT: movl $-65536, %ecx # imm = 0xFFFF0000
; X86-NEXT: cmovll %ecx, %eax
; X86-NEXT: shrl %eax ; X86-NEXT: shrl %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl ; X86-NEXT: retl
%tmp = call i16 @llvm.sdiv.fix.sat.i16(i16 %x, i16 %y, i32 7) %tmp = call i16 @llvm.sdiv.fix.sat.i16(i16 %x, i16 %y, i32 7)
ret i16 %tmp ret i16 %tmp
Show All 16 Lines
; X64-NEXT: testl %esi, %esi ; X64-NEXT: testl %esi, %esi
; X64-NEXT: sets %sil ; X64-NEXT: sets %sil
; X64-NEXT: testl %ecx, %ecx ; X64-NEXT: testl %ecx, %ecx
; X64-NEXT: sets %cl ; X64-NEXT: sets %cl
; X64-NEXT: xorb %sil, %cl ; X64-NEXT: xorb %sil, %cl
; X64-NEXT: testl %edx, %edx ; X64-NEXT: testl %edx, %edx
; X64-NEXT: setne %dl ; X64-NEXT: setne %dl
; X64-NEXT: testb %cl, %dl ; X64-NEXT: testb %cl, %dl
; X64-NEXT: cmovel %eax, %edi ; X64-NEXT: cmovnel %edi, %eax
; X64-NEXT: cmpl $16383, %edi # imm = 0x3FFF ; X64-NEXT: cmpl $16383, %eax # imm = 0x3FFF
; X64-NEXT: movl $16383, %ecx # imm = 0x3FFF ; X64-NEXT: movl $16383, %ecx # imm = 0x3FFF
; X64-NEXT: cmovll %edi, %ecx
; X64-NEXT: cmpl $-16383, %ecx # imm = 0xC001
; X64-NEXT: movl $-16384, %eax # imm = 0xC000
; X64-NEXT: cmovgel %ecx, %eax ; X64-NEXT: cmovgel %ecx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: cmpl $-16383, %eax # imm = 0xC001
; X64-NEXT: movl $-16384, %ecx # imm = 0xC000
; X64-NEXT: cmovll %ecx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: func2: ; X86-LABEL: func2:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movsbl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movsbl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movsbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movsbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: shll $14, %ecx ; X86-NEXT: shll $14, %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: cltd ; X86-NEXT: cltd
; X86-NEXT: idivl %edi ; X86-NEXT: idivl %esi
; X86-NEXT: leal -1(%eax), %esi ; X86-NEXT: leal -1(%eax), %edi
; X86-NEXT: testl %edi, %edi ; X86-NEXT: testl %esi, %esi
; X86-NEXT: sets %bl ; X86-NEXT: sets %bl
; X86-NEXT: testl %ecx, %ecx ; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: sets %cl ; X86-NEXT: sets %cl
; X86-NEXT: xorb %bl, %cl ; X86-NEXT: xorb %bl, %cl
; X86-NEXT: testl %edx, %edx ; X86-NEXT: testl %edx, %edx
; X86-NEXT: setne %dl ; X86-NEXT: setne %dl
; X86-NEXT: testb %cl, %dl ; X86-NEXT: testb %cl, %dl
; X86-NEXT: cmovel %eax, %esi ; X86-NEXT: cmovnel %edi, %eax
; X86-NEXT: cmpl $16383, %esi # imm = 0x3FFF ; X86-NEXT: cmpl $16383, %eax # imm = 0x3FFF
; X86-NEXT: movl $16383, %ecx # imm = 0x3FFF ; X86-NEXT: movl $16383, %ecx # imm = 0x3FFF
; X86-NEXT: cmovll %esi, %ecx
; X86-NEXT: cmpl $-16383, %ecx # imm = 0xC001
; X86-NEXT: movl $-16384, %eax # imm = 0xC000
; X86-NEXT: cmovgel %ecx, %eax ; X86-NEXT: cmovgel %ecx, %eax
; X86-NEXT: cmpl $-16383, %eax # imm = 0xC001
; X86-NEXT: movl $-16384, %ecx # imm = 0xC000
; X86-NEXT: cmovll %ecx, %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl ; X86-NEXT: retl
%x2 = sext i8 %x to i15 %x2 = sext i8 %x to i15
%y2 = sext i8 %y to i15 %y2 = sext i8 %y to i15
%tmp = call i15 @llvm.sdiv.fix.sat.i15(i15 %x2, i15 %y2, i32 14) %tmp = call i15 @llvm.sdiv.fix.sat.i15(i15 %x2, i15 %y2, i32 14)
Show All 17 Lines
; X64-NEXT: testw %di, %di ; X64-NEXT: testw %di, %di
; X64-NEXT: sets %dil ; X64-NEXT: sets %dil
; X64-NEXT: testw %cx, %cx ; X64-NEXT: testw %cx, %cx
; X64-NEXT: sets %cl ; X64-NEXT: sets %cl
; X64-NEXT: xorb %dil, %cl ; X64-NEXT: xorb %dil, %cl
; X64-NEXT: testw %dx, %dx ; X64-NEXT: testw %dx, %dx
; X64-NEXT: setne %dl ; X64-NEXT: setne %dl
; X64-NEXT: testb %cl, %dl ; X64-NEXT: testb %cl, %dl
; X64-NEXT: cmovel %eax, %esi ; X64-NEXT: cmovnel %esi, %eax
; X64-NEXT: movswl %si, %eax ; X64-NEXT: movswl %ax, %ecx
; X64-NEXT: cmpl $16383, %eax # imm = 0x3FFF ; X64-NEXT: cmpl $16383, %ecx # imm = 0x3FFF
; X64-NEXT: movl $16383, %ecx # imm = 0x3FFF ; X64-NEXT: movl $16383, %ecx # imm = 0x3FFF
; X64-NEXT: cmovll %esi, %ecx
; X64-NEXT: movswl %cx, %eax
; X64-NEXT: cmpl $-16383, %eax # imm = 0xC001
; X64-NEXT: movl $49152, %eax # imm = 0xC000
; X64-NEXT: cmovgel %ecx, %eax ; X64-NEXT: cmovgel %ecx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: movswl %ax, %ecx
; X64-NEXT: cmpl $-16383, %ecx # imm = 0xC001
; X64-NEXT: movl $49152, %ecx # imm = 0xC000
; X64-NEXT: cmovll %ecx, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: func3: ; X86-LABEL: func3:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shll $8, %eax ; X86-NEXT: shll $8, %eax
; X86-NEXT: movswl %ax, %edi ; X86-NEXT: movswl %ax, %esi
; X86-NEXT: addl %ecx, %ecx ; X86-NEXT: addl %ecx, %ecx
; X86-NEXT: shrl $4, %edi ; X86-NEXT: shrl $4, %esi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: cwtd ; X86-NEXT: cwtd
; X86-NEXT: idivw %di ; X86-NEXT: idivw %si
; X86-NEXT: # kill: def $ax killed $ax def $eax ; X86-NEXT: # kill: def $ax killed $ax def $eax
; X86-NEXT: leal -1(%eax), %esi ; X86-NEXT: leal -1(%eax), %edi
; X86-NEXT: testw %cx, %cx ; X86-NEXT: testw %cx, %cx
; X86-NEXT: sets %cl ; X86-NEXT: sets %cl
; X86-NEXT: testw %di, %di ; X86-NEXT: testw %si, %si
; X86-NEXT: sets %ch ; X86-NEXT: sets %ch
; X86-NEXT: xorb %cl, %ch ; X86-NEXT: xorb %cl, %ch
; X86-NEXT: testw %dx, %dx ; X86-NEXT: testw %dx, %dx
; X86-NEXT: setne %cl ; X86-NEXT: setne %cl
; X86-NEXT: testb %ch, %cl ; X86-NEXT: testb %ch, %cl
; X86-NEXT: cmovel %eax, %esi ; X86-NEXT: cmovnel %edi, %eax
; X86-NEXT: movswl %si, %eax ; X86-NEXT: movswl %ax, %ecx
; X86-NEXT: cmpl $16383, %eax # imm = 0x3FFF ; X86-NEXT: cmpl $16383, %ecx # imm = 0x3FFF
; X86-NEXT: movl $16383, %ecx # imm = 0x3FFF ; X86-NEXT: movl $16383, %ecx # imm = 0x3FFF
; X86-NEXT: cmovll %esi, %ecx
; X86-NEXT: movswl %cx, %eax
; X86-NEXT: cmpl $-16383, %eax # imm = 0xC001
; X86-NEXT: movl $49152, %eax # imm = 0xC000
; X86-NEXT: cmovgel %ecx, %eax ; X86-NEXT: cmovgel %ecx, %eax
; X86-NEXT: movswl %ax, %ecx
; X86-NEXT: cmpl $-16383, %ecx # imm = 0xC001
; X86-NEXT: movl $49152, %ecx # imm = 0xC000
; X86-NEXT: cmovll %ecx, %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl ; X86-NEXT: retl
%y2 = sext i8 %y to i15 %y2 = sext i8 %y to i15
%y3 = shl i15 %y2, 7 %y3 = shl i15 %y2, 7
%tmp = call i15 @llvm.sdiv.fix.sat.i15(i15 %x, i15 %y3, i32 4) %tmp = call i15 @llvm.sdiv.fix.sat.i15(i15 %x, i15 %y3, i32 4)
%tmp2 = sext i15 %tmp to i16 %tmp2 = sext i15 %tmp to i16
▲ Show 20 Lines • Show All 292 Lines • ▼ Show 20 Lines
; X64-NEXT: testl %esi, %esi ; X64-NEXT: testl %esi, %esi
; X64-NEXT: sets %sil ; X64-NEXT: sets %sil
; X64-NEXT: testl %ecx, %ecx ; X64-NEXT: testl %ecx, %ecx
; X64-NEXT: sets %cl ; X64-NEXT: sets %cl
; X64-NEXT: xorb %sil, %cl ; X64-NEXT: xorb %sil, %cl
; X64-NEXT: testl %edx, %edx ; X64-NEXT: testl %edx, %edx
; X64-NEXT: setne %dl ; X64-NEXT: setne %dl
; X64-NEXT: testb %cl, %dl ; X64-NEXT: testb %cl, %dl
; X64-NEXT: cmovel %eax, %edi ; X64-NEXT: cmovnel %edi, %eax
; X64-NEXT: cmpl $131071, %edi # imm = 0x1FFFF ; X64-NEXT: cmpl $131071, %eax # imm = 0x1FFFF
; X64-NEXT: movl $131071, %ecx # imm = 0x1FFFF ; X64-NEXT: movl $131071, %ecx # imm = 0x1FFFF
; X64-NEXT: cmovll %edi, %ecx
; X64-NEXT: cmpl $-131071, %ecx # imm = 0xFFFE0001
; X64-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X64-NEXT: cmovgel %ecx, %eax ; X64-NEXT: cmovgel %ecx, %eax
; X64-NEXT: cmpl $-131071, %eax # imm = 0xFFFE0001
; X64-NEXT: movl $-131072, %ecx # imm = 0xFFFE0000
; X64-NEXT: cmovll %ecx, %eax
; X64-NEXT: # kill: def $eax killed $eax killed $rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: func6: ; X86-LABEL: func6:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movswl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movswl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: shll $7, %ecx ; X86-NEXT: shll $7, %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: cltd ; X86-NEXT: cltd
; X86-NEXT: idivl %edi ; X86-NEXT: idivl %esi
; X86-NEXT: leal -1(%eax), %esi ; X86-NEXT: leal -1(%eax), %edi
; X86-NEXT: testl %edi, %edi ; X86-NEXT: testl %esi, %esi
; X86-NEXT: sets %bl ; X86-NEXT: sets %bl
; X86-NEXT: testl %ecx, %ecx ; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: sets %cl ; X86-NEXT: sets %cl
; X86-NEXT: xorb %bl, %cl ; X86-NEXT: xorb %bl, %cl
; X86-NEXT: testl %edx, %edx ; X86-NEXT: testl %edx, %edx
; X86-NEXT: setne %dl ; X86-NEXT: setne %dl
; X86-NEXT: testb %cl, %dl ; X86-NEXT: testb %cl, %dl
; X86-NEXT: cmovel %eax, %esi ; X86-NEXT: cmovnel %edi, %eax
; X86-NEXT: cmpl $131071, %esi # imm = 0x1FFFF ; X86-NEXT: cmpl $131071, %eax # imm = 0x1FFFF
; X86-NEXT: movl $131071, %ecx # imm = 0x1FFFF ; X86-NEXT: movl $131071, %ecx # imm = 0x1FFFF
; X86-NEXT: cmovll %esi, %ecx
; X86-NEXT: cmpl $-131071, %ecx # imm = 0xFFFE0001
; X86-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-NEXT: cmovgel %ecx, %eax ; X86-NEXT: cmovgel %ecx, %eax
; X86-NEXT: cmpl $-131071, %eax # imm = 0xFFFE0001
; X86-NEXT: movl $-131072, %ecx # imm = 0xFFFE0000
; X86-NEXT: cmovll %ecx, %eax
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl ; X86-NEXT: retl
%x2 = sext i16 %x to i18 %x2 = sext i16 %x to i18
%y2 = sext i16 %y to i18 %y2 = sext i16 %y to i18
%tmp = call i18 @llvm.sdiv.fix.sat.i18(i18 %x2, i18 %y2, i32 7) %tmp = call i18 @llvm.sdiv.fix.sat.i18(i18 %x2, i18 %y2, i32 7)
ret i18 %tmp ret i18 %tmp
▲ Show 20 Lines • Show All 770 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/setcc-combine.ll

Show First 20 Lines • Show All 320 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%r = select i1 %cmp, i64 %s1, i64 %s2 %r = select i1 %cmp, i64 %s1, i64 %s2
ret i64 %r ret i64 %r
} }
define <4 x float> @sub_to_shift_to_add_vec(<4 x i32> %x, <4 x i32> %y, <4 x float> %s1, <4 x float> %s2) { define <4 x float> @sub_to_shift_to_add_vec(<4 x i32> %x, <4 x i32> %y, <4 x float> %s1, <4 x float> %s2) {
; SSE2-LABEL: sub_to_shift_to_add_vec: ; SSE2-LABEL: sub_to_shift_to_add_vec:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: paddd %xmm1, %xmm1 ; SSE2-NEXT: paddd %xmm1, %xmm1
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: pandn %xmm3, %xmm1 ; SSE2-NEXT: pandn %xmm3, %xmm0
; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: sub_to_shift_to_add_vec: ; SSE41-LABEL: sub_to_shift_to_add_vec:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: paddd %xmm1, %xmm1 ; SSE41-NEXT: paddd %xmm1, %xmm1
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3 ; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
; SSE41-NEXT: movaps %xmm3, %xmm0 ; SSE41-NEXT: movaps %xmm3, %xmm0
Show All 21 Lines

llvm/test/CodeGen/X86/shift-combine.ll

Show First 20 Lines • Show All 311 Lines • ▼ Show 20 Lines
; X32-NEXT: shll $24, %eax ; X32-NEXT: shll $24, %eax
; X32-NEXT: addl $33554432, %eax # imm = 0x2000000 ; X32-NEXT: addl $33554432, %eax # imm = 0x2000000
; X32-NEXT: movl %eax, (%ecx) ; X32-NEXT: movl %eax, (%ecx)
; X32-NEXT: sarl $24, %eax ; X32-NEXT: sarl $24, %eax
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: ashr_add_shl_i32_i8_extra_use1: ; X64-LABEL: ashr_add_shl_i32_i8_extra_use1:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: shll $24, %eax ; X64-NEXT: shll $24, %edi
; X64-NEXT: addl $33554432, %eax # imm = 0x2000000 ; X64-NEXT: leal 33554432(%rdi), %eax
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %eax, (%rsi)
; X64-NEXT: sarl $24, %eax ; X64-NEXT: sarl $24, %eax
; X64-NEXT: retq ; X64-NEXT: retq
%conv = shl i32 %r, 24 %conv = shl i32 %r, 24
%sext = add i32 %conv, 33554432 %sext = add i32 %conv, 33554432
store i32 %sext, i32* %p store i32 %sext, i32* %p
%conv1 = ashr i32 %sext, 24 %conv1 = ashr i32 %sext, 24
ret i32 %conv1 ret i32 %conv1
Show All 35 Lines
; X32-NEXT: movl %eax, (%edx) ; X32-NEXT: movl %eax, (%edx)
; X32-NEXT: addl $33554432, %eax # imm = 0x2000000 ; X32-NEXT: addl $33554432, %eax # imm = 0x2000000
; X32-NEXT: movl %eax, (%ecx) ; X32-NEXT: movl %eax, (%ecx)
; X32-NEXT: sarl $24, %eax ; X32-NEXT: sarl $24, %eax
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: ashr_add_shl_i32_i8_extra_use3: ; X64-LABEL: ashr_add_shl_i32_i8_extra_use3:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: shll $24, %eax ; X64-NEXT: shll $24, %edi
; X64-NEXT: movl %eax, (%rsi) ; X64-NEXT: movl %edi, (%rsi)
; X64-NEXT: addl $33554432, %eax # imm = 0x2000000 ; X64-NEXT: leal 33554432(%rdi), %eax
; X64-NEXT: movl %eax, (%rdx) ; X64-NEXT: movl %eax, (%rdx)
; X64-NEXT: sarl $24, %eax ; X64-NEXT: sarl $24, %eax
; X64-NEXT: retq ; X64-NEXT: retq
%conv = shl i32 %r, 24 %conv = shl i32 %r, 24
store i32 %conv, i32* %p1 store i32 %conv, i32* %p1
%sext = add i32 %conv, 33554432 %sext = add i32 %conv, 33554432
store i32 %sext, i32* %p2 store i32 %sext, i32* %p2
%conv1 = ashr i32 %sext, 24 %conv1 = ashr i32 %sext, 24
Show All 35 Lines

llvm/test/CodeGen/X86/shl-crash-on-legalize.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s | FileCheck %s ;RUN: llc < %s | FileCheck %s
; This test case failed on legalization of "shl" node. PR29058. ; This test case failed on legalization of "shl" node. PR29058.
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@structMember = external dso_local local_unnamed_addr global i64, align 8 @structMember = external dso_local local_unnamed_addr global i64, align 8
define i32 @PR29058(i8 %x, i32 %y) { define i32 @PR29058(i8 %x, i32 %y) {
; CHECK-LABEL: PR29058: ; CHECK-LABEL: PR29058:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %esi, %ecx
; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: movl $2147483646, %eax # imm = 0x7FFFFFFE ; CHECK-NEXT: movl $2147483646, %eax # imm = 0x7FFFFFFE
; CHECK-NEXT: cmovnel %esi, %eax ; CHECK-NEXT: cmovnel %esi, %eax
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpb $1, %dil ; CHECK-NEXT: cmpb $1, %dil
; CHECK-NEXT: sbbl %edx, %edx ; CHECK-NEXT: sbbl %ecx, %ecx
; CHECK-NEXT: orb %dl, %cl ; CHECK-NEXT: orb %sil, %cl
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx ; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: shll %cl, %eax ; CHECK-NEXT: shll %cl, %eax
; CHECK-NEXT: movq %rax, structMember(%rip) ; CHECK-NEXT: movq %rax, structMember(%rip)
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%bool_1 = icmp ne i8 %x, 0 %bool_1 = icmp ne i8 %x, 0
%bool_2 = icmp eq i8 %x, 0 %bool_2 = icmp eq i8 %x, 0
Show All 12 Lines

llvm/test/CodeGen/X86/slow-pmulld.ll

Show First 20 Lines • Show All 458 Lines • ▼ Show 20 Lines; AVX-64-NEXT: retq
%z = zext <4 x i16> %A to <4 x i32> %z = zext <4 x i16> %A to <4 x i32>
%m = mul nuw nsw <4 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778> %m = mul nuw nsw <4 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778>
ret <4 x i32> %m ret <4 x i32> %m
} }
define <8 x i32> @test_mul_v8i32_v8i16(<8 x i16> %A) { define <8 x i32> @test_mul_v8i32_v8i16(<8 x i16> %A) {
; SLM32-LABEL: test_mul_v8i32_v8i16: ; SLM32-LABEL: test_mul_v8i32_v8i16:
; SLM32: # %bb.0: ; SLM32: # %bb.0:
; SLM32-NEXT: movdqa %xmm0, %xmm1 ; SLM32-NEXT: movdqa {{.*#+}} xmm1 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLM32-NEXT: movdqa {{.*#+}} xmm0 = [18778,18778,18778,18778,18778,18778,18778,18778] ; SLM32-NEXT: movdqa %xmm0, %xmm2
; SLM32-NEXT: movdqa %xmm1, %xmm2 ; SLM32-NEXT: pmulhuw %xmm1, %xmm2
; SLM32-NEXT: pmullw %xmm0, %xmm1 ; SLM32-NEXT: pmullw %xmm0, %xmm1
; SLM32-NEXT: pmulhuw %xmm0, %xmm2
; SLM32-NEXT: movdqa %xmm1, %xmm0 ; SLM32-NEXT: movdqa %xmm1, %xmm0
; SLM32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SLM32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SLM32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SLM32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLM32-NEXT: retl ; SLM32-NEXT: retl
; ;
; SLM64-LABEL: test_mul_v8i32_v8i16: ; SLM64-LABEL: test_mul_v8i32_v8i16:
; SLM64: # %bb.0: ; SLM64: # %bb.0:
; SLM64-NEXT: movdqa %xmm0, %xmm1 ; SLM64-NEXT: movdqa {{.*#+}} xmm1 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLM64-NEXT: movdqa {{.*#+}} xmm0 = [18778,18778,18778,18778,18778,18778,18778,18778] ; SLM64-NEXT: movdqa %xmm0, %xmm2
; SLM64-NEXT: movdqa %xmm1, %xmm2 ; SLM64-NEXT: pmulhuw %xmm1, %xmm2
; SLM64-NEXT: pmullw %xmm0, %xmm1 ; SLM64-NEXT: pmullw %xmm0, %xmm1
; SLM64-NEXT: pmulhuw %xmm0, %xmm2
; SLM64-NEXT: movdqa %xmm1, %xmm0 ; SLM64-NEXT: movdqa %xmm1, %xmm0
; SLM64-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SLM64-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SLM64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SLM64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLM64-NEXT: retq ; SLM64-NEXT: retq
; ;
; SLOW32-LABEL: test_mul_v8i32_v8i16: ; SLOW32-LABEL: test_mul_v8i32_v8i16:
; SLOW32: # %bb.0: ; SLOW32: # %bb.0:
; SLOW32-NEXT: movdqa %xmm0, %xmm1 ; SLOW32-NEXT: movdqa {{.*#+}} xmm1 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLOW32-NEXT: movdqa {{.*#+}} xmm0 = [18778,18778,18778,18778,18778,18778,18778,18778] ; SLOW32-NEXT: movdqa %xmm0, %xmm2
; SLOW32-NEXT: movdqa %xmm1, %xmm2 ; SLOW32-NEXT: pmulhuw %xmm1, %xmm2
; SLOW32-NEXT: pmulhuw %xmm0, %xmm2
; SLOW32-NEXT: pmullw %xmm0, %xmm1 ; SLOW32-NEXT: pmullw %xmm0, %xmm1
; SLOW32-NEXT: movdqa %xmm1, %xmm0 ; SLOW32-NEXT: movdqa %xmm1, %xmm0
; SLOW32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SLOW32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLOW32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SLOW32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SLOW32-NEXT: retl ; SLOW32-NEXT: retl
; ;
; SLOW64-LABEL: test_mul_v8i32_v8i16: ; SLOW64-LABEL: test_mul_v8i32_v8i16:
; SLOW64: # %bb.0: ; SLOW64: # %bb.0:
; SLOW64-NEXT: movdqa %xmm0, %xmm1 ; SLOW64-NEXT: movdqa {{.*#+}} xmm1 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLOW64-NEXT: movdqa {{.*#+}} xmm0 = [18778,18778,18778,18778,18778,18778,18778,18778] ; SLOW64-NEXT: movdqa %xmm0, %xmm2
; SLOW64-NEXT: movdqa %xmm1, %xmm2 ; SLOW64-NEXT: pmulhuw %xmm1, %xmm2
; SLOW64-NEXT: pmulhuw %xmm0, %xmm2
; SLOW64-NEXT: pmullw %xmm0, %xmm1 ; SLOW64-NEXT: pmullw %xmm0, %xmm1
; SLOW64-NEXT: movdqa %xmm1, %xmm0 ; SLOW64-NEXT: movdqa %xmm1, %xmm0
; SLOW64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SLOW64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLOW64-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SLOW64-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SLOW64-NEXT: retq ; SLOW64-NEXT: retq
; ;
; SSE4-32-LABEL: test_mul_v8i32_v8i16: ; SSE4-32-LABEL: test_mul_v8i32_v8i16:
; SSE4-32: # %bb.0: ; SSE4-32: # %bb.0:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines; AVX-64-NEXT: retq
%z = zext <8 x i16> %A to <8 x i32> %z = zext <8 x i16> %A to <8 x i32>
%m = mul nuw nsw <8 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778> %m = mul nuw nsw <8 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778>
ret <8 x i32> %m ret <8 x i32> %m
} }
define <16 x i32> @test_mul_v16i32_v16i16(<16 x i16> %A) { define <16 x i32> @test_mul_v16i32_v16i16(<16 x i16> %A) {
; SLM32-LABEL: test_mul_v16i32_v16i16: ; SLM32-LABEL: test_mul_v16i32_v16i16:
; SLM32: # %bb.0: ; SLM32: # %bb.0:
; SLM32-NEXT: movdqa %xmm1, %xmm3 ; SLM32-NEXT: movdqa {{.*#+}} xmm3 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLM32-NEXT: movdqa %xmm0, %xmm1 ; SLM32-NEXT: movdqa %xmm0, %xmm4
; SLM32-NEXT: movdqa {{.*#+}} xmm0 = [18778,18778,18778,18778,18778,18778,18778,18778] ; SLM32-NEXT: movdqa %xmm0, %xmm2
; SLM32-NEXT: movdqa %xmm1, %xmm2 ; SLM32-NEXT: movdqa %xmm1, %xmm5
; SLM32-NEXT: movdqa %xmm3, %xmm4 ; SLM32-NEXT: pmullw %xmm3, %xmm4
; SLM32-NEXT: pmullw %xmm0, %xmm1 ; SLM32-NEXT: pmulhuw %xmm3, %xmm2
; SLM32-NEXT: pmulhuw %xmm0, %xmm2 ; SLM32-NEXT: pmulhuw %xmm3, %xmm5
; SLM32-NEXT: pmullw %xmm0, %xmm3 ; SLM32-NEXT: pmullw %xmm1, %xmm3
; SLM32-NEXT: pmulhuw %xmm0, %xmm4 ; SLM32-NEXT: movdqa %xmm4, %xmm0
; SLM32-NEXT: movdqa %xmm1, %xmm0 ; SLM32-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
; SLM32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SLM32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SLM32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLM32-NEXT: movdqa %xmm3, %xmm2 ; SLM32-NEXT: movdqa %xmm3, %xmm2
; SLM32-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] ; SLM32-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm5[4],xmm3[5],xmm5[5],xmm3[6],xmm5[6],xmm3[7],xmm5[7]
; SLM32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] ; SLM32-NEXT: movdqa %xmm4, %xmm1
; SLM32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SLM32-NEXT: retl ; SLM32-NEXT: retl
; ;
; SLM64-LABEL: test_mul_v16i32_v16i16: ; SLM64-LABEL: test_mul_v16i32_v16i16:
; SLM64: # %bb.0: ; SLM64: # %bb.0:
; SLM64-NEXT: movdqa %xmm1, %xmm3 ; SLM64-NEXT: movdqa {{.*#+}} xmm3 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLM64-NEXT: movdqa %xmm0, %xmm1 ; SLM64-NEXT: movdqa %xmm0, %xmm4
; SLM64-NEXT: movdqa {{.*#+}} xmm0 = [18778,18778,18778,18778,18778,18778,18778,18778] ; SLM64-NEXT: movdqa %xmm0, %xmm2
; SLM64-NEXT: movdqa %xmm1, %xmm2 ; SLM64-NEXT: movdqa %xmm1, %xmm5
; SLM64-NEXT: movdqa %xmm3, %xmm4 ; SLM64-NEXT: pmullw %xmm3, %xmm4
; SLM64-NEXT: pmullw %xmm0, %xmm1 ; SLM64-NEXT: pmulhuw %xmm3, %xmm2
; SLM64-NEXT: pmulhuw %xmm0, %xmm2 ; SLM64-NEXT: pmulhuw %xmm3, %xmm5
; SLM64-NEXT: pmullw %xmm0, %xmm3 ; SLM64-NEXT: pmullw %xmm1, %xmm3
; SLM64-NEXT: pmulhuw %xmm0, %xmm4 ; SLM64-NEXT: movdqa %xmm4, %xmm0
; SLM64-NEXT: movdqa %xmm1, %xmm0 ; SLM64-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
; SLM64-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SLM64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SLM64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLM64-NEXT: movdqa %xmm3, %xmm2 ; SLM64-NEXT: movdqa %xmm3, %xmm2
; SLM64-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] ; SLM64-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm5[4],xmm3[5],xmm5[5],xmm3[6],xmm5[6],xmm3[7],xmm5[7]
; SLM64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] ; SLM64-NEXT: movdqa %xmm4, %xmm1
; SLM64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SLM64-NEXT: retq ; SLM64-NEXT: retq
; ;
; SLOW32-LABEL: test_mul_v16i32_v16i16: ; SLOW32-LABEL: test_mul_v16i32_v16i16:
; SLOW32: # %bb.0: ; SLOW32: # %bb.0:
; SLOW32-NEXT: movdqa %xmm1, %xmm3
; SLOW32-NEXT: movdqa %xmm0, %xmm1
; SLOW32-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLOW32-NEXT: movdqa %xmm0, %xmm4 ; SLOW32-NEXT: movdqa %xmm0, %xmm4
; SLOW32-NEXT: pmulhuw %xmm2, %xmm4 ; SLOW32-NEXT: movdqa {{.*#+}} xmm3 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLOW32-NEXT: pmullw %xmm2, %xmm1 ; SLOW32-NEXT: movdqa %xmm0, %xmm2
; SLOW32-NEXT: movdqa %xmm1, %xmm0 ; SLOW32-NEXT: pmulhuw %xmm3, %xmm2
; SLOW32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] ; SLOW32-NEXT: pmullw %xmm3, %xmm4
; SLOW32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] ; SLOW32-NEXT: movdqa %xmm4, %xmm0
; SLOW32-NEXT: movdqa %xmm3, %xmm4 ; SLOW32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLOW32-NEXT: pmulhuw %xmm2, %xmm4 ; SLOW32-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
; SLOW32-NEXT: pmullw %xmm2, %xmm3 ; SLOW32-NEXT: movdqa %xmm1, %xmm5
; SLOW32-NEXT: pmulhuw %xmm3, %xmm5
; SLOW32-NEXT: pmullw %xmm1, %xmm3
; SLOW32-NEXT: movdqa %xmm3, %xmm2 ; SLOW32-NEXT: movdqa %xmm3, %xmm2
; SLOW32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] ; SLOW32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SLOW32-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] ; SLOW32-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm5[4],xmm3[5],xmm5[5],xmm3[6],xmm5[6],xmm3[7],xmm5[7]
; SLOW32-NEXT: movdqa %xmm4, %xmm1
; SLOW32-NEXT: retl ; SLOW32-NEXT: retl
; ;
; SLOW64-LABEL: test_mul_v16i32_v16i16: ; SLOW64-LABEL: test_mul_v16i32_v16i16:
; SLOW64: # %bb.0: ; SLOW64: # %bb.0:
; SLOW64-NEXT: movdqa %xmm1, %xmm3
; SLOW64-NEXT: movdqa %xmm0, %xmm1
; SLOW64-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLOW64-NEXT: movdqa %xmm0, %xmm4 ; SLOW64-NEXT: movdqa %xmm0, %xmm4
; SLOW64-NEXT: pmulhuw %xmm2, %xmm4 ; SLOW64-NEXT: movdqa {{.*#+}} xmm3 = [18778,18778,18778,18778,18778,18778,18778,18778]
; SLOW64-NEXT: pmullw %xmm2, %xmm1 ; SLOW64-NEXT: movdqa %xmm0, %xmm2
; SLOW64-NEXT: movdqa %xmm1, %xmm0 ; SLOW64-NEXT: pmulhuw %xmm3, %xmm2
; SLOW64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] ; SLOW64-NEXT: pmullw %xmm3, %xmm4
; SLOW64-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] ; SLOW64-NEXT: movdqa %xmm4, %xmm0
; SLOW64-NEXT: movdqa %xmm3, %xmm4 ; SLOW64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SLOW64-NEXT: pmulhuw %xmm2, %xmm4 ; SLOW64-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
; SLOW64-NEXT: pmullw %xmm2, %xmm3 ; SLOW64-NEXT: movdqa %xmm1, %xmm5
; SLOW64-NEXT: pmulhuw %xmm3, %xmm5
; SLOW64-NEXT: pmullw %xmm1, %xmm3
; SLOW64-NEXT: movdqa %xmm3, %xmm2 ; SLOW64-NEXT: movdqa %xmm3, %xmm2
; SLOW64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3] ; SLOW64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3]
; SLOW64-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] ; SLOW64-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm5[4],xmm3[5],xmm5[5],xmm3[6],xmm5[6],xmm3[7],xmm5[7]
; SLOW64-NEXT: movdqa %xmm4, %xmm1
; SLOW64-NEXT: retq ; SLOW64-NEXT: retq
; ;
; SSE4-32-LABEL: test_mul_v16i32_v16i16: ; SSE4-32-LABEL: test_mul_v16i32_v16i16:
; SSE4-32: # %bb.0: ; SSE4-32: # %bb.0:
; SSE4-32-NEXT: movdqa %xmm0, %xmm4 ; SSE4-32-NEXT: movdqa %xmm0, %xmm4
; SSE4-32-NEXT: pxor %xmm3, %xmm3 ; SSE4-32-NEXT: pxor %xmm3, %xmm3
; SSE4-32-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero ; SSE4-32-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
; SSE4-32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7] ; SSE4-32-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]
▲ Show 20 Lines • Show All 728 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/smul_fix.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; X86-NEXT: .cfi_offset %edi, -16 ; X86-NEXT: .cfi_offset %edi, -16
; X86-NEXT: .cfi_offset %ebx, -12 ; X86-NEXT: .cfi_offset %ebx, -12
; X86-NEXT: .cfi_offset %ebp, -8 ; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: movl %edx, %edi ; X86-NEXT: movl %edx, %edi
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebp
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull %ecx ; X86-NEXT: mull %ecx
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %esi
; X86-NEXT: movl %edx, %ebp ; X86-NEXT: addl %edx, %ebp
; X86-NEXT: addl %ebx, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %edi
; X86-NEXT: movl %ebx, %eax ; X86-NEXT: movl %ebx, %eax
; X86-NEXT: mull %ecx ; X86-NEXT: mull %ecx
; X86-NEXT: addl %ebp, %eax ; X86-NEXT: addl %ebp, %eax
; X86-NEXT: adcl %edi, %edx ; X86-NEXT: adcl %edi, %edx
; X86-NEXT: movl %ebx, %edi ; X86-NEXT: movl %ebx, %edi
; X86-NEXT: imull {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: addl %edx, %edi ; X86-NEXT: imull %ebp, %edi
; X86-NEXT: movl %edi, %ebp ; X86-NEXT: addl %edi, %edx
; X86-NEXT: subl %ecx, %ebp ; X86-NEXT: movl %edx, %edi
; X86-NEXT: subl %ecx, %edi
; X86-NEXT: testl %ebx, %ebx ; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: cmovnsl %edi, %ebp ; X86-NEXT: cmovsl %edi, %edx
; X86-NEXT: movl %ebp, %edx ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: subl {{[0-9]+}}(%esp), %edx ; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: testl %ebp, %ebp
; X86-NEXT: cmovnsl %ebp, %edx ; X86-NEXT: cmovsl %ecx, %edx
; X86-NEXT: shldl $30, %eax, %edx ; X86-NEXT: shldl $30, %eax, %edx
; X86-NEXT: shldl $30, %esi, %eax ; X86-NEXT: shldl $30, %esi, %eax
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: .cfi_def_cfa_offset 16
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
▲ Show 20 Lines • Show All 238 Lines • ▼ Show 20 Lines
; X86-NEXT: mull %esi ; X86-NEXT: mull %esi
; X86-NEXT: addl %edx, %ebx ; X86-NEXT: addl %edx, %ebx
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %edi
; X86-NEXT: movl %ebp, %eax ; X86-NEXT: movl %ebp, %eax
; X86-NEXT: mull %esi ; X86-NEXT: mull %esi
; X86-NEXT: addl %ebx, %eax ; X86-NEXT: addl %ebx, %eax
; X86-NEXT: adcl %edi, %edx ; X86-NEXT: adcl %edi, %edx
; X86-NEXT: movl %ebp, %edi ; X86-NEXT: movl %ebp, %edi
; X86-NEXT: imull {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: addl %edx, %edi ; X86-NEXT: imull %ebx, %edi
; X86-NEXT: movl %edi, %ebx ; X86-NEXT: addl %edi, %edx
; X86-NEXT: subl %esi, %ebx ; X86-NEXT: movl %edx, %edi
; X86-NEXT: subl %esi, %edi
; X86-NEXT: testl %ebp, %ebp ; X86-NEXT: testl %ebp, %ebp
; X86-NEXT: cmovnsl %edi, %ebx ; X86-NEXT: cmovsl %edi, %edx
; X86-NEXT: movl %ebx, %edx ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: subl %ecx, %edx ; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: testl %ebx, %ebx
; X86-NEXT: cmovnsl %ebx, %edx ; X86-NEXT: cmovsl %ecx, %edx
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 32) %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 32)
ret i64 %tmp ret i64 %tmp
} }
Show All 9 Lines
; X86-LABEL: func8: ; X86-LABEL: func8:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull %edi ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: movl %edx, %ebx ; X86-NEXT: movl %edx, %edi
; X86-NEXT: movl %eax, %ebp ; X86-NEXT: movl %eax, %ebp
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull %esi ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: addl %edx, %ebp ; X86-NEXT: addl %edx, %ebp
; X86-NEXT: adcl $0, %ebx ; X86-NEXT: adcl $0, %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: imull %edi ; X86-NEXT: imull {{[0-9]+}}(%esp)
; X86-NEXT: movl %edx, %edi ; X86-NEXT: movl %edx, %ebx
; X86-NEXT: movl %eax, %ecx ; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull %esi ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: addl %ebp, %eax ; X86-NEXT: addl %ebp, %eax
; X86-NEXT: adcl %ebx, %edx ; X86-NEXT: adcl %edx, %edi
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %ebx
; X86-NEXT: addl %ecx, %edx ; X86-NEXT: addl %ecx, %edi
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %ebx
; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %edi, %ecx
; X86-NEXT: subl %esi, %ecx ; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %edi, %esi ; X86-NEXT: movl %ebx, %esi
; X86-NEXT: sbbl $0, %esi ; X86-NEXT: sbbl $0, %esi
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnsl %edi, %esi ; X86-NEXT: cmovnsl %ebx, %esi
; X86-NEXT: cmovnsl %edx, %ecx ; X86-NEXT: cmovnsl %edi, %ecx
; X86-NEXT: movl %ecx, %edi ; X86-NEXT: movl %ecx, %edi
; X86-NEXT: subl {{[0-9]+}}(%esp), %edi ; X86-NEXT: subl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %esi, %edx ; X86-NEXT: movl %esi, %edx
; X86-NEXT: sbbl $0, %edx ; X86-NEXT: sbbl $0, %edx
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnsl %esi, %edx ; X86-NEXT: cmovnsl %esi, %edx
; X86-NEXT: cmovnsl %ecx, %edi ; X86-NEXT: cmovnsl %ecx, %edi
; X86-NEXT: shldl $1, %edi, %edx ; X86-NEXT: shldl $1, %edi, %edx
Show All 9 Lines

llvm/test/CodeGen/X86/smul_fix_sat.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; ;
; X86-LABEL: func2: ; X86-LABEL: func2:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: mull %esi ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull %ecx
; X86-NEXT: movl %ecx, %ebx
; X86-NEXT: movl %edx, %ebp ; X86-NEXT: movl %edx, %ebp
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, (%esp) # 4-byte Spill ; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
; X86-NEXT: movl %edx, %ecx ; X86-NEXT: addl %edx, %ecx
; X86-NEXT: addl %edi, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: adcl $0, %ebp ; X86-NEXT: adcl $0, %ebp
; X86-NEXT: movl %edi, %eax ; X86-NEXT: movl %edi, %eax
; X86-NEXT: imull %esi ; X86-NEXT: imull %ebx
; X86-NEXT: movl %edx, %ebx ; X86-NEXT: movl %edx, %ebx
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %esi
; X86-NEXT: movl %edi, %eax ; X86-NEXT: movl %edi, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: addl %ecx, %eax ; X86-NEXT: movl %eax, %edi
; X86-NEXT: addl %ecx, %edi
; X86-NEXT: adcl %ebp, %edx ; X86-NEXT: adcl %ebp, %edx
; X86-NEXT: adcl $0, %ebx ; X86-NEXT: adcl $0, %ebx
; X86-NEXT: addl %esi, %edx ; X86-NEXT: addl %esi, %edx
; X86-NEXT: adcl $0, %ebx ; X86-NEXT: adcl $0, %ebx
; X86-NEXT: movl %edx, %esi ; X86-NEXT: movl %edx, %esi
; X86-NEXT: subl {{[0-9]+}}(%esp), %esi ; X86-NEXT: subl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %ebx, %ebp ; X86-NEXT: movl %ebx, %ebp
; X86-NEXT: sbbl $0, %ebp ; X86-NEXT: sbbl $0, %ebp
; X86-NEXT: testl %edi, %edi ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnsl %ebx, %ebp ; X86-NEXT: cmovnsl %ebx, %ebp
; X86-NEXT: cmovnsl %edx, %esi ; X86-NEXT: cmovnsl %edx, %esi
; X86-NEXT: movl %esi, %ecx ; X86-NEXT: movl %esi, %ecx
; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ebp, %edi ; X86-NEXT: movl %ebp, %edx
; X86-NEXT: sbbl $0, %edi ; X86-NEXT: sbbl $0, %edx
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnsl %ebp, %edi ; X86-NEXT: cmovnsl %ebp, %edx
; X86-NEXT: cmovnsl %esi, %ecx ; X86-NEXT: cmovnsl %esi, %ecx
; X86-NEXT: testl %edi, %edi ; X86-NEXT: testl %edx, %edx
; X86-NEXT: setg %bl ; X86-NEXT: setg %bl
; X86-NEXT: sete %bh ; X86-NEXT: sete %bh
; X86-NEXT: cmpl $2, %ecx ; X86-NEXT: cmpl $2, %ecx
; X86-NEXT: setae %dl ; X86-NEXT: setae %al
; X86-NEXT: andb %bh, %dl ; X86-NEXT: andb %bh, %al
; X86-NEXT: orb %bl, %dl ; X86-NEXT: orb %bl, %al
; X86-NEXT: movl (%esp), %ebx ; X86-NEXT: movl (%esp), %ebx # 4-byte Reload
; X86-NEXT: shrdl $2, %eax, %ebx ; X86-NEXT: shrdl $2, %edi, %ebx
; X86-NEXT: shrdl $2, %ecx, %eax ; X86-NEXT: shrdl $2, %ecx, %edi
; X86-NEXT: testb %dl, %dl ; X86-NEXT: testb %al, %al
; X86-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF
; X86-NEXT: cmovel %eax, %esi ; X86-NEXT: cmovel %edi, %esi
; X86-NEXT: movl $-1, %edx ; X86-NEXT: movl $-1, %edi
; X86-NEXT: cmovel %ebx, %edx ; X86-NEXT: cmovel %ebx, %edi
; X86-NEXT: cmpl $-1, %edi ; X86-NEXT: cmpl $-1, %edx
; X86-NEXT: setl %bl ; X86-NEXT: setl %dl
; X86-NEXT: sete %al ; X86-NEXT: sete %al
; X86-NEXT: cmpl $-2, %ecx ; X86-NEXT: cmpl $-2, %ecx
; X86-NEXT: setb %cl ; X86-NEXT: setb %cl
; X86-NEXT: andb %al, %cl ; X86-NEXT: andb %al, %cl
; X86-NEXT: xorl %eax, %eax ; X86-NEXT: xorl %eax, %eax
; X86-NEXT: orb %bl, %cl ; X86-NEXT: orb %dl, %cl
; X86-NEXT: cmovel %edx, %eax ; X86-NEXT: cmovel %edi, %eax
; X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000 ; X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000
; X86-NEXT: cmovel %esi, %edx ; X86-NEXT: cmovel %esi, %edx
; X86-NEXT: addl $4, %esp ; X86-NEXT: addl $4, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: .cfi_def_cfa_offset 16
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: .cfi_def_cfa_offset 20 ; X86-NEXT: .cfi_def_cfa_offset 20
; X86-NEXT: subl $12, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: .cfi_def_cfa_offset 28
; X86-NEXT: .cfi_offset %esi, -20 ; X86-NEXT: .cfi_offset %esi, -20
; X86-NEXT: .cfi_offset %edi, -16 ; X86-NEXT: .cfi_offset %edi, -16
; X86-NEXT: .cfi_offset %ebx, -12 ; X86-NEXT: .cfi_offset %ebx, -12
; X86-NEXT: .cfi_offset %ebp, -8 ; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, %edi ; X86-NEXT: movl %ecx, %ebx
; X86-NEXT: sarl $31, %edi ; X86-NEXT: sarl $31, %ebx
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: imull %edi, %esi
; X86-NEXT: mull %edi
; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
; X86-NEXT: addl %esi, %edx
; X86-NEXT: movl %ebx, %esi
; X86-NEXT: imull %ebx, %edi ; X86-NEXT: imull %ebx, %edi
; X86-NEXT: mull %ebx
; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
; X86-NEXT: addl %edi, %edx
; X86-NEXT: movl %ebp, %edi
; X86-NEXT: imull %ebp, %ebx
; X86-NEXT: addl %edx, %ebx
; X86-NEXT: sarl $31, %edi
; X86-NEXT: movl %edi, %ebp
; X86-NEXT: imull %ecx, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %edi, %eax
; X86-NEXT: mull %esi
; X86-NEXT: addl %ebp, %edx
; X86-NEXT: imull %esi, %edi
; X86-NEXT: addl %edx, %edi ; X86-NEXT: addl %edx, %edi
; X86-NEXT: sarl $31, %esi
; X86-NEXT: movl %esi, %ebx
; X86-NEXT: imull %ecx, %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull %ebp
; X86-NEXT: addl %ebx, %edx
; X86-NEXT: imull %ebp, %esi
; X86-NEXT: addl %edx, %esi
; X86-NEXT: addl (%esp), %eax # 4-byte Folded Reload ; X86-NEXT: addl (%esp), %eax # 4-byte Folded Reload
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl %edi, %esi ; X86-NEXT: adcl %ebx, %edi
; X86-NEXT: movl %ebp, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: mull %edi ; X86-NEXT: mull %esi
; X86-NEXT: movl %edx, %ebp ; X86-NEXT: movl %edx, %ebp
; X86-NEXT: movl %eax, (%esp) # 4-byte Spill ; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull %edi ; X86-NEXT: mull %esi
; X86-NEXT: movl %edx, %ebx ; X86-NEXT: movl %edx, %ebx
; X86-NEXT: movl %eax, %edi ; X86-NEXT: addl %eax, %ebp
; X86-NEXT: addl %ebp, %edi
; X86-NEXT: adcl $0, %ebx ; X86-NEXT: adcl $0, %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: movl %edx, %ebp
; X86-NEXT: addl %edi, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: adcl %ebx, %ebp
; X86-NEXT: setb %bl
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: mull %edx ; X86-NEXT: mull %edx
; X86-NEXT: addl %ebp, %eax ; X86-NEXT: movl %edx, %esi
; X86-NEXT: movzbl %bl, %edi ; X86-NEXT: addl %eax, %ebp
; X86-NEXT: adcl %edi, %edx ; X86-NEXT: adcl %ebx, %esi
; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: setb %bl
; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: addl %esi, %eax
; X86-NEXT: movzbl %bl, %esi
; X86-NEXT: adcl %esi, %edx ; X86-NEXT: adcl %esi, %edx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
; X86-NEXT: movl %ebx, %edi ; X86-NEXT: adcl %edi, %edx
; X86-NEXT: movl %ebp, %edi
; X86-NEXT: sarl $31, %edi ; X86-NEXT: sarl $31, %edi
; X86-NEXT: xorl %edi, %edx ; X86-NEXT: xorl %edi, %edx
; X86-NEXT: xorl %eax, %edi ; X86-NEXT: xorl %eax, %edi
; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sarl $31, %ecx ; X86-NEXT: sarl $31, %ecx
; X86-NEXT: movl %ecx, %esi ; X86-NEXT: movl %ecx, %esi
; X86-NEXT: xorl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-NEXT: xorl $2147483647, %esi # imm = 0x7FFFFFFF
; X86-NEXT: orl %edx, %edi ; X86-NEXT: orl %edx, %edi
; X86-NEXT: notl %ecx ; X86-NEXT: notl %ecx
; X86-NEXT: cmovel (%esp), %ecx # 4-byte Folded Reload ; X86-NEXT: cmovel (%esp), %ecx # 4-byte Folded Reload
; X86-NEXT: cmovel %ebx, %esi ; X86-NEXT: cmovel %ebp, %esi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: movl %esi, %edx ; X86-NEXT: movl %esi, %edx
; X86-NEXT: addl $12, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: .cfi_def_cfa_offset 20 ; X86-NEXT: .cfi_def_cfa_offset 20
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: .cfi_def_cfa_offset 16
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
; X86-NEXT: movl %eax, %ecx ; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull %esi ; X86-NEXT: mull %esi
; X86-NEXT: addl %ebp, %eax ; X86-NEXT: addl %ebp, %eax
; X86-NEXT: adcl %ebx, %edx ; X86-NEXT: adcl %ebx, %edx
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %edi
; X86-NEXT: addl %ecx, %edx ; X86-NEXT: addl %ecx, %edx
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %edi
; X86-NEXT: movl %edx, %ebx ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: subl %esi, %ebx ; X86-NEXT: subl %esi, %ecx
; X86-NEXT: movl %edi, %esi ; X86-NEXT: movl %edi, %esi
; X86-NEXT: sbbl $0, %esi ; X86-NEXT: sbbl $0, %esi
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnsl %edi, %esi ; X86-NEXT: cmovnsl %edi, %esi
; X86-NEXT: cmovnsl %edx, %ebx ; X86-NEXT: cmovsl %ecx, %edx
; X86-NEXT: movl %ebx, %edx ; X86-NEXT: movl %edx, %edi
; X86-NEXT: subl {{[0-9]+}}(%esp), %edx ; X86-NEXT: subl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %esi, %ecx ; X86-NEXT: movl %esi, %ecx
; X86-NEXT: sbbl $0, %ecx ; X86-NEXT: sbbl $0, %ecx
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnsl %esi, %ecx ; X86-NEXT: cmovnsl %esi, %ecx
; X86-NEXT: cmovnsl %ebx, %edx ; X86-NEXT: cmovsl %edi, %edx
; X86-NEXT: testl %edx, %edx ; X86-NEXT: testl %edx, %edx
; X86-NEXT: setns {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; X86-NEXT: setns {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: sets %bh ; X86-NEXT: sets %bh
; X86-NEXT: testl %ecx, %ecx ; X86-NEXT: testl %ecx, %ecx
; X86-NEXT: setg {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; X86-NEXT: setg {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: sete %bl ; X86-NEXT: sete %bl
; X86-NEXT: andb %bh, %bl ; X86-NEXT: andb %bh, %bl
; X86-NEXT: orb {{[-0-9]+}}(%e{{[sb]}}p), %bl # 1-byte Folded Reload ; X86-NEXT: orb {{[-0-9]+}}(%e{{[sb]}}p), %bl # 1-byte Folded Reload
; X86-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF
; X86-NEXT: cmovel %edx, %esi ; X86-NEXT: cmovnel %esi, %edx
; X86-NEXT: movl $-1, %edx ; X86-NEXT: movl $-1, %esi
; X86-NEXT: cmovnel %edx, %eax ; X86-NEXT: cmovnel %esi, %eax
; X86-NEXT: cmpl $-1, %ecx ; X86-NEXT: cmpl $-1, %ecx
; X86-NEXT: setl %cl ; X86-NEXT: setl %cl
; X86-NEXT: sete %dl ; X86-NEXT: sete %ch
; X86-NEXT: andb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Folded Reload ; X86-NEXT: andb {{[-0-9]+}}(%e{{[sb]}}p), %ch # 1-byte Folded Reload
; X86-NEXT: xorl %edi, %edi ; X86-NEXT: xorl %esi, %esi
; X86-NEXT: orb %cl, %dl ; X86-NEXT: orb %cl, %ch
; X86-NEXT: cmovnel %edi, %eax ; X86-NEXT: cmovnel %esi, %eax
; X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000 ; X86-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-NEXT: cmovel %esi, %edx ; X86-NEXT: cmovnel %ecx, %edx
; X86-NEXT: addl $4, %esp ; X86-NEXT: addl $4, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
%tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 32) %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 32)
ret i64 %tmp ret i64 %tmp
Show All 18 Lines
; X86-LABEL: func8: ; X86-LABEL: func8:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull %edi ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: movl %edx, %ebx ; X86-NEXT: movl %edx, %edi
; X86-NEXT: movl %eax, %ebp ; X86-NEXT: movl %eax, %ebp
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull %esi ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: addl %edx, %ebp ; X86-NEXT: addl %edx, %ebp
; X86-NEXT: adcl $0, %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: imull %edi
; X86-NEXT: movl %edx, %edi
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull %esi
; X86-NEXT: addl %ebp, %eax
; X86-NEXT: adcl %ebx, %edx
; X86-NEXT: adcl $0, %edi
; X86-NEXT: addl %ecx, %edx
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %edi
; X86-NEXT: movl %esi, %eax
; X86-NEXT: imull {{[0-9]+}}(%esp)
; X86-NEXT: movl %edx, %ebx ; X86-NEXT: movl %edx, %ebx
; X86-NEXT: subl %esi, %ebx ; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movl %edi, %esi ; X86-NEXT: movl %esi, %eax
; X86-NEXT: sbbl $0, %esi ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: addl %ebp, %eax
; X86-NEXT: cmovnsl %edi, %esi ; X86-NEXT: adcl %edx, %edi
; X86-NEXT: cmovnsl %edx, %ebx ; X86-NEXT: adcl $0, %ebx
; X86-NEXT: movl %ebx, %edx ; X86-NEXT: addl %ecx, %edi
; X86-NEXT: adcl $0, %ebx
; X86-NEXT: movl %edi, %edx
; X86-NEXT: subl {{[0-9]+}}(%esp), %edx ; X86-NEXT: subl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl %esi, %ecx ; X86-NEXT: movl %ebx, %ebp
; X86-NEXT: sbbl $0, %ebp
; X86-NEXT: testl %esi, %esi
; X86-NEXT: cmovnsl %ebx, %ebp
; X86-NEXT: cmovnsl %edi, %edx
; X86-NEXT: movl %edx, %esi
; X86-NEXT: subl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %ebp, %ecx
; X86-NEXT: sbbl $0, %ecx ; X86-NEXT: sbbl $0, %ecx
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnsl %esi, %ecx ; X86-NEXT: cmovnsl %ebp, %ecx
; X86-NEXT: cmovnsl %ebx, %edx ; X86-NEXT: cmovnsl %edx, %esi
; X86-NEXT: shrdl $31, %edx, %eax ; X86-NEXT: shrdl $31, %esi, %eax
; X86-NEXT: shrdl $31, %ecx, %edx ; X86-NEXT: shrdl $31, %ecx, %esi
; X86-NEXT: cmpl $1073741824, %ecx # imm = 0x40000000 ; X86-NEXT: cmpl $1073741824, %ecx # imm = 0x40000000
; X86-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-NEXT: movl $2147483647, %edi # imm = 0x7FFFFFFF
; X86-NEXT: cmovll %edx, %esi ; X86-NEXT: cmovll %esi, %edi
; X86-NEXT: movl $-1, %edx ; X86-NEXT: movl $-1, %edx
; X86-NEXT: cmovgel %edx, %eax ; X86-NEXT: cmovgel %edx, %eax
; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edx, %edx
; X86-NEXT: cmpl $-1073741824, %ecx # imm = 0xC0000000 ; X86-NEXT: cmpl $-1073741824, %ecx # imm = 0xC0000000
; X86-NEXT: cmovll %edx, %eax ; X86-NEXT: cmovll %edx, %eax
; X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000 ; X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000
; X86-NEXT: cmovgel %esi, %edx ; X86-NEXT: cmovgel %edi, %edx
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
%tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 63) %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 63)
ret i64 %tmp ret i64 %tmp
} }

llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll

Show All 36 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,306783378,171798690,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,306783378,171798690,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even: ; CHECK-AVX1-LABEL: test_srem_odd_even:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 343 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,306783378,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,306783378,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even_allones_eq: ; CHECK-AVX1-LABEL: test_srem_odd_even_allones_eq:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,306783378,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,306783378,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even_allones_ne: ; CHECK-AVX1-LABEL: test_srem_odd_even_allones_ne:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,858993458,268435454,858993458] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,858993458,268435454,858993458]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_poweroftwo: ; CHECK-AVX1-LABEL: test_srem_odd_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,306783378,268435454,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,306783378,268435454,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_even_poweroftwo: ; CHECK-AVX1-LABEL: test_srem_even_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,306783378,268435454,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,306783378,268435454,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even_poweroftwo: ; CHECK-AVX1-LABEL: test_srem_odd_even_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 208 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,306783378,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,306783378,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even_one: ; CHECK-AVX1-LABEL: test_srem_odd_even_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 394 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,4294967295,268435454,858993458] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,4294967295,268435454,858993458]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_srem_odd_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,4294967295,268435454,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,4294967295,268435454,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_even_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_srem_even_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,4294967295,268435454,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,4294967295,268435454,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_srem_odd_even_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 208 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,4294967295,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,4294967295,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even_allones_and_one: ; CHECK-AVX1-LABEL: test_srem_odd_even_allones_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,268435454,4294967295,858993458] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,268435454,4294967295,858993458]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_srem_odd_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,268435454,4294967295,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,268435454,4294967295,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_even_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_srem_even_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993458,268435454,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993458,268435454,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_srem_odd_even_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_srem_odd_even_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 525 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sse3-avx-addsub-2.ll

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret <4 x float> %vecinsert1 ret <4 x float> %vecinsert1
} }
define <4 x float> @test13(<4 x float> %A, <4 x float> %B) { define <4 x float> @test13(<4 x float> %A, <4 x float> %B) {
; SSE-LABEL: test13: ; SSE-LABEL: test13:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; SSE-NEXT: addss %xmm0, %xmm1 ; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: test13: ; AVX1-LABEL: test13:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,3,3,3]
; AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0] ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
▲ Show 20 Lines • Show All 368 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/uadd_sat.ll

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
; ;
; X64-LABEL: vec: ; X64-LABEL: vec:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; X64-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; X64-NEXT: paddd %xmm0, %xmm1 ; X64-NEXT: movdqa %xmm0, %xmm3
; X64-NEXT: pxor %xmm2, %xmm0 ; X64-NEXT: pxor %xmm2, %xmm3
; X64-NEXT: pxor %xmm1, %xmm2 ; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: pcmpgtd %xmm2, %xmm0 ; X64-NEXT: pxor %xmm0, %xmm2
; X64-NEXT: por %xmm1, %xmm0 ; X64-NEXT: pcmpgtd %xmm2, %xmm3
; X64-NEXT: por %xmm3, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%tmp = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %tmp = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %tmp ret <4 x i32> %tmp
} }

llvm/test/CodeGen/X86/uadd_sat_vec.ll

Show First 20 Lines • Show All 516 Lines • ▼ Show 20 Lines
} }
; Expanded ; Expanded
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind { define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; SSE2-LABEL: v2i32: ; SSE2-LABEL: v2i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm2, %xmm3
; SSE2-NEXT: pxor %xmm1, %xmm2 ; SSE2-NEXT: paddd %xmm1, %xmm0
; SSE2-NEXT: pcmpgtd %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm0, %xmm2
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm3
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: v2i32: ; SSSE3-LABEL: v2i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; SSSE3-NEXT: paddd %xmm0, %xmm1 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm2, %xmm3
; SSSE3-NEXT: pxor %xmm1, %xmm2 ; SSSE3-NEXT: paddd %xmm1, %xmm0
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm0, %xmm2
; SSSE3-NEXT: por %xmm1, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm3
; SSSE3-NEXT: por %xmm3, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: v2i32: ; SSE41-LABEL: v2i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm2 ; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: pminud %xmm2, %xmm0 ; SSE41-NEXT: pminud %xmm2, %xmm0
; SSE41-NEXT: paddd %xmm1, %xmm0 ; SSE41-NEXT: paddd %xmm1, %xmm0
Show All 35 Lines; AVX512BW-NEXT: retq
%z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y) %z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
ret <2 x i32> %z ret <2 x i32> %z
} }
define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-LABEL: v4i32: ; SSE2-LABEL: v4i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm2, %xmm3
; SSE2-NEXT: pxor %xmm1, %xmm2 ; SSE2-NEXT: paddd %xmm1, %xmm0
; SSE2-NEXT: pcmpgtd %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm0, %xmm2
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm3
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: v4i32: ; SSSE3-LABEL: v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; SSSE3-NEXT: paddd %xmm0, %xmm1 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm2, %xmm3
; SSSE3-NEXT: pxor %xmm1, %xmm2 ; SSSE3-NEXT: paddd %xmm1, %xmm0
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm0, %xmm2
; SSSE3-NEXT: por %xmm1, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm3
; SSSE3-NEXT: por %xmm3, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: v4i32: ; SSE41-LABEL: v4i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
; SSE41-NEXT: pxor %xmm1, %xmm2 ; SSE41-NEXT: pxor %xmm1, %xmm2
; SSE41-NEXT: pminud %xmm2, %xmm0 ; SSE41-NEXT: pminud %xmm2, %xmm0
; SSE41-NEXT: paddd %xmm1, %xmm0 ; SSE41-NEXT: paddd %xmm1, %xmm0
Show All 35 Lines; AVX512BW-NEXT: retq
%z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %z ret <4 x i32> %z
} }
define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; SSE2-LABEL: v8i32: ; SSE2-LABEL: v8i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
; SSE2-NEXT: paddd %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: pxor %xmm4, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm5
; SSE2-NEXT: pxor %xmm4, %xmm5 ; SSE2-NEXT: pxor %xmm4, %xmm5
; SSE2-NEXT: pcmpgtd %xmm5, %xmm0 ; SSE2-NEXT: paddd %xmm2, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: paddd %xmm1, %xmm3 ; SSE2-NEXT: pxor %xmm4, %xmm2
; SSE2-NEXT: pxor %xmm4, %xmm1 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm5
; SSE2-NEXT: pxor %xmm3, %xmm4 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: pcmpgtd %xmm4, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: pxor %xmm4, %xmm2
; SSE2-NEXT: paddd %xmm3, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm4
; SSE2-NEXT: pcmpgtd %xmm4, %xmm2
; SSE2-NEXT: por %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: v8i32: ; SSSE3-LABEL: v8i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
; SSSE3-NEXT: paddd %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm5
; SSSE3-NEXT: pxor %xmm4, %xmm0
; SSSE3-NEXT: movdqa %xmm2, %xmm5
; SSSE3-NEXT: pxor %xmm4, %xmm5 ; SSSE3-NEXT: pxor %xmm4, %xmm5
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm0 ; SSSE3-NEXT: paddd %xmm2, %xmm0
; SSSE3-NEXT: por %xmm2, %xmm0 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: paddd %xmm1, %xmm3 ; SSSE3-NEXT: pxor %xmm4, %xmm2
; SSSE3-NEXT: pxor %xmm4, %xmm1 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm5
; SSSE3-NEXT: pxor %xmm3, %xmm4 ; SSSE3-NEXT: por %xmm5, %xmm0
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm1 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: por %xmm3, %xmm1 ; SSSE3-NEXT: pxor %xmm4, %xmm2
; SSSE3-NEXT: paddd %xmm3, %xmm1
; SSSE3-NEXT: pxor %xmm1, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm2
; SSSE3-NEXT: por %xmm2, %xmm1
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: v8i32: ; SSE41-LABEL: v8i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm4, %xmm4 ; SSE41-NEXT: pcmpeqd %xmm4, %xmm4
; SSE41-NEXT: movdqa %xmm2, %xmm5 ; SSE41-NEXT: movdqa %xmm2, %xmm5
; SSE41-NEXT: pxor %xmm4, %xmm5 ; SSE41-NEXT: pxor %xmm4, %xmm5
; SSE41-NEXT: pminud %xmm5, %xmm0 ; SSE41-NEXT: pminud %xmm5, %xmm0
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines; AVX512BW-NEXT: retq
%z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y) %z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
ret <8 x i32> %z ret <8 x i32> %z
} }
define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
; SSE2-LABEL: v16i32: ; SSE2-LABEL: v16i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648,2147483648,2147483648]
; SSE2-NEXT: paddd %xmm0, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm9
; SSE2-NEXT: pxor %xmm8, %xmm0
; SSE2-NEXT: movdqa %xmm4, %xmm9
; SSE2-NEXT: pxor %xmm8, %xmm9 ; SSE2-NEXT: pxor %xmm8, %xmm9
; SSE2-NEXT: pcmpgtd %xmm9, %xmm0 ; SSE2-NEXT: paddd %xmm4, %xmm0
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: paddd %xmm1, %xmm5
; SSE2-NEXT: pxor %xmm8, %xmm1
; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: pxor %xmm8, %xmm4 ; SSE2-NEXT: pxor %xmm8, %xmm4
; SSE2-NEXT: pcmpgtd %xmm4, %xmm1 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm9
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm9, %xmm0
; SSE2-NEXT: paddd %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pxor %xmm8, %xmm2
; SSE2-NEXT: movdqa %xmm6, %xmm4
; SSE2-NEXT: pxor %xmm8, %xmm4 ; SSE2-NEXT: pxor %xmm8, %xmm4
; SSE2-NEXT: pcmpgtd %xmm4, %xmm2 ; SSE2-NEXT: paddd %xmm5, %xmm1
; SSE2-NEXT: por %xmm6, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: paddd %xmm3, %xmm7 ; SSE2-NEXT: pxor %xmm8, %xmm5
; SSE2-NEXT: pxor %xmm8, %xmm3 ; SSE2-NEXT: pcmpgtd %xmm5, %xmm4
; SSE2-NEXT: pxor %xmm7, %xmm8 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: pcmpgtd %xmm8, %xmm3 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: por %xmm7, %xmm3 ; SSE2-NEXT: pxor %xmm8, %xmm4
; SSE2-NEXT: paddd %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm5
; SSE2-NEXT: pxor %xmm8, %xmm5
; SSE2-NEXT: pcmpgtd %xmm5, %xmm4
; SSE2-NEXT: por %xmm4, %xmm2
; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pxor %xmm8, %xmm4
; SSE2-NEXT: paddd %xmm7, %xmm3
; SSE2-NEXT: pxor %xmm3, %xmm8
; SSE2-NEXT: pcmpgtd %xmm8, %xmm4
; SSE2-NEXT: por %xmm4, %xmm3
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: v16i32: ; SSSE3-LABEL: v16i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648,2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648,2147483648,2147483648]
; SSSE3-NEXT: paddd %xmm0, %xmm4 ; SSSE3-NEXT: movdqa %xmm0, %xmm9
; SSSE3-NEXT: pxor %xmm8, %xmm0
; SSSE3-NEXT: movdqa %xmm4, %xmm9
; SSSE3-NEXT: pxor %xmm8, %xmm9 ; SSSE3-NEXT: pxor %xmm8, %xmm9
; SSSE3-NEXT: pcmpgtd %xmm9, %xmm0 ; SSSE3-NEXT: paddd %xmm4, %xmm0
; SSSE3-NEXT: por %xmm4, %xmm0 ; SSSE3-NEXT: movdqa %xmm0, %xmm4
; SSSE3-NEXT: paddd %xmm1, %xmm5
; SSSE3-NEXT: pxor %xmm8, %xmm1
; SSSE3-NEXT: movdqa %xmm5, %xmm4
; SSSE3-NEXT: pxor %xmm8, %xmm4 ; SSSE3-NEXT: pxor %xmm8, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm1 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm9
; SSSE3-NEXT: por %xmm5, %xmm1 ; SSSE3-NEXT: por %xmm9, %xmm0
; SSSE3-NEXT: paddd %xmm2, %xmm6 ; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pxor %xmm8, %xmm2
; SSSE3-NEXT: movdqa %xmm6, %xmm4
; SSSE3-NEXT: pxor %xmm8, %xmm4 ; SSSE3-NEXT: pxor %xmm8, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm2 ; SSSE3-NEXT: paddd %xmm5, %xmm1
; SSSE3-NEXT: por %xmm6, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm5
; SSSE3-NEXT: paddd %xmm3, %xmm7 ; SSSE3-NEXT: pxor %xmm8, %xmm5
; SSSE3-NEXT: pxor %xmm8, %xmm3 ; SSSE3-NEXT: pcmpgtd %xmm5, %xmm4
; SSSE3-NEXT: pxor %xmm7, %xmm8 ; SSSE3-NEXT: por %xmm4, %xmm1
; SSSE3-NEXT: pcmpgtd %xmm8, %xmm3 ; SSSE3-NEXT: movdqa %xmm2, %xmm4
; SSSE3-NEXT: por %xmm7, %xmm3 ; SSSE3-NEXT: pxor %xmm8, %xmm4
; SSSE3-NEXT: paddd %xmm6, %xmm2
; SSSE3-NEXT: movdqa %xmm2, %xmm5
; SSSE3-NEXT: pxor %xmm8, %xmm5
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm4
; SSSE3-NEXT: por %xmm4, %xmm2
; SSSE3-NEXT: movdqa %xmm3, %xmm4
; SSSE3-NEXT: pxor %xmm8, %xmm4
; SSSE3-NEXT: paddd %xmm7, %xmm3
; SSSE3-NEXT: pxor %xmm3, %xmm8
; SSSE3-NEXT: pcmpgtd %xmm8, %xmm4
; SSSE3-NEXT: por %xmm4, %xmm3
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: v16i32: ; SSE41-LABEL: v16i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm8, %xmm8 ; SSE41-NEXT: pcmpeqd %xmm8, %xmm8
; SSE41-NEXT: movdqa %xmm4, %xmm9 ; SSE41-NEXT: movdqa %xmm4, %xmm9
; SSE41-NEXT: pxor %xmm8, %xmm9 ; SSE41-NEXT: pxor %xmm8, %xmm9
; SSE41-NEXT: pminud %xmm9, %xmm0 ; SSE41-NEXT: pminud %xmm9, %xmm0
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
%z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y) %z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
ret <16 x i32> %z ret <16 x i32> %z
} }
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE-LABEL: v2i64: ; SSE-LABEL: v2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: paddq %xmm0, %xmm1
; SSE-NEXT: pxor %xmm2, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pcmpgtd %xmm2, %xmm3 ; SSE-NEXT: pxor %xmm2, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] ; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE-NEXT: pxor %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm1
; SSE-NEXT: pcmpgtd %xmm2, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm3, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm2 ; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: por %xmm2, %xmm0 ; SSE-NEXT: por %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v2i64: ; AVX1-LABEL: v2i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3 ; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3
Show All 34 Lines; AVX512BW-NEXT: retq
%z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %z ret <2 x i64> %z
} }
define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; SSE-LABEL: v4i64: ; SSE-LABEL: v4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: paddq %xmm0, %xmm2 ; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm0, %xmm6 ; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm2, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm5 ; SSE-NEXT: pcmpeqd %xmm5, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm5 ; SSE-NEXT: pand %xmm7, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm2, %xmm0
; SSE-NEXT: por %xmm5, %xmm0 ; SSE-NEXT: por %xmm5, %xmm0
; SSE-NEXT: paddq %xmm1, %xmm3 ; SSE-NEXT: por %xmm2, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtd %xmm4, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2] ; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: pcmpeqd %xmm1, %xmm4 ; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE-NEXT: movdqa %xmm2, %xmm3
; SSE-NEXT: pand %xmm5, %xmm4 ; SSE-NEXT: pcmpgtd %xmm4, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm2, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: por %xmm3, %xmm1
; SSE-NEXT: por %xmm4, %xmm1 ; SSE-NEXT: por %xmm2, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v4i64: ; AVX1-LABEL: v4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm4 ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm4
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
Show All 39 Lines; AVX512BW-NEXT: retq
%z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y) %z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
ret <4 x i64> %z ret <4 x i64> %z
} }
define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; SSE-LABEL: v8i64: ; SSE-LABEL: v8i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: paddq %xmm0, %xmm4 ; SSE-NEXT: movdqa %xmm0, %xmm9
; SSE-NEXT: pxor %xmm8, %xmm0
; SSE-NEXT: movdqa %xmm4, %xmm9
; SSE-NEXT: pxor %xmm8, %xmm9 ; SSE-NEXT: pxor %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm0, %xmm10 ; SSE-NEXT: paddq %xmm4, %xmm0
; SSE-NEXT: pcmpgtd %xmm9, %xmm10 ; SSE-NEXT: movdqa %xmm0, %xmm4
; SSE-NEXT: pxor %xmm8, %xmm4
; SSE-NEXT: movdqa %xmm9, %xmm10
; SSE-NEXT: pcmpgtd %xmm4, %xmm10
; SSE-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm9 ; SSE-NEXT: pcmpeqd %xmm9, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm11, %xmm9 ; SSE-NEXT: pand %xmm11, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm10[1,1,3,3]
; SSE-NEXT: por %xmm4, %xmm0 ; SSE-NEXT: por %xmm4, %xmm0
; SSE-NEXT: por %xmm9, %xmm0 ; SSE-NEXT: por %xmm9, %xmm0
; SSE-NEXT: paddq %xmm1, %xmm5
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm5, %xmm4
; SSE-NEXT: pxor %xmm8, %xmm4
; SSE-NEXT: movdqa %xmm1, %xmm9 ; SSE-NEXT: movdqa %xmm1, %xmm9
; SSE-NEXT: pcmpgtd %xmm4, %xmm9 ; SSE-NEXT: pxor %xmm8, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2] ; SSE-NEXT: paddq %xmm5, %xmm1
; SSE-NEXT: pcmpeqd %xmm1, %xmm4 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pxor %xmm8, %xmm5
; SSE-NEXT: movdqa %xmm9, %xmm4
; SSE-NEXT: pcmpgtd %xmm5, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm4[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm9, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm9[1,1,3,3]
; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: por %xmm4, %xmm1 ; SSE-NEXT: por %xmm4, %xmm1
; SSE-NEXT: paddq %xmm2, %xmm6 ; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: movdqa %xmm6, %xmm4
; SSE-NEXT: pxor %xmm8, %xmm4 ; SSE-NEXT: pxor %xmm8, %xmm4
; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm5 ; SSE-NEXT: movdqa %xmm2, %xmm5
; SSE-NEXT: pcmpgtd %xmm4, %xmm5 ; SSE-NEXT: pxor %xmm8, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2] ; SSE-NEXT: movdqa %xmm4, %xmm6
; SSE-NEXT: pcmpeqd %xmm2, %xmm4 ; SSE-NEXT: pcmpgtd %xmm5, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm6[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm4, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm4 ; SSE-NEXT: pand %xmm9, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm2 ; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: por %xmm4, %xmm2 ; SSE-NEXT: por %xmm4, %xmm2
; SSE-NEXT: paddq %xmm3, %xmm7
; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: pxor %xmm7, %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm4 ; SSE-NEXT: movdqa %xmm3, %xmm4
; SSE-NEXT: pcmpgtd %xmm8, %xmm4 ; SSE-NEXT: pxor %xmm8, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE-NEXT: paddq %xmm7, %xmm3
; SSE-NEXT: pcmpeqd %xmm3, %xmm8 ; SSE-NEXT: pxor %xmm3, %xmm8
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3] ; SSE-NEXT: movdqa %xmm4, %xmm5
; SSE-NEXT: pand %xmm5, %xmm6 ; SSE-NEXT: pcmpgtd %xmm8, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
; SSE-NEXT: por %xmm7, %xmm3 ; SSE-NEXT: pcmpeqd %xmm4, %xmm8
; SSE-NEXT: por %xmm6, %xmm3 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm8[1,1,3,3]
; SSE-NEXT: pand %xmm6, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: por %xmm4, %xmm3
pengfeiUnsubmitted
Not Done
ReplyInline Actions

The tests in this file seem all become bad. Do you have any idea to optimizate for them?

pengfei: The tests in this file seem all become bad. Do you have any idea to optimizate for them?
CarrotAuthorUnsubmitted
Done
ReplyInline Actions

Let's take function v4i32 as an example

With this patch

liveins: $xmm0, $xmm1
%1:vr128 = COPY killed $xmm1
%0:vr128 = COPY killed $xmm0
%2:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
%3:vr128 = COPY %0:vr128
%3:vr128 = PXORrr %3:vr128(tied-def 0), %2:vr128
%4:vr128 = COPY killed %0:vr128
%4:vr128 = PADDDrr %4:vr128(tied-def 0), killed %1:vr128
%5:vr128 = COPY killed %2:vr128
%5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
%6:vr128 = COPY killed %3:vr128
%6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), killed %5:vr128
%7:vr128 = COPY killed %4:vr128
%7:vr128 = PORrr %7:vr128(tied-def 0), killed %6:vr128
$xmm0 = COPY killed %7:vr128
RET 0, killed $xmm0

The final extra movdqa comes from

3:vr128 = COPY %0:vr128

It can't be deleted because %0 is not kill at this point. All other COPY instructions can be coalesced and deleted.

Without this patch

liveins: $xmm0, $xmm1
%1:vr128 = COPY killed $xmm1
%0:vr128 = COPY killed $xmm0
%2:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
%3:vr128 = COPY %0:vr128
%3:vr128 = PXORrr %3:vr128(tied-def 0), %2:vr128
%4:vr128 = COPY killed %1:vr128
%4:vr128 = PADDDrr %4:vr128(tied-def 0), killed %0:vr128
%5:vr128 = COPY killed %2:vr128
%5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
%6:vr128 = COPY killed %3:vr128
%6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), killed %5:vr128
%7:vr128 = COPY killed %6:vr128
%7:vr128 = PORrr %7:vr128(tied-def 0), killed %4:vr128
$xmm0 = COPY killed %7:vr128
RET 0, killed $xmm0

It also contains

3:vr128 = COPY %0:vr128

and %0 is not killed, so %3 is not xmm0 and this COPY is a real MOV at this point. The SrcRegMap contains %7 -> %6 -> %3, so %7 can't be coalesced with xmm0, and the last COPY is also a real MOV.

It can seen clearly after coalescing

0B      bb.0 (%ir-block.0):
          liveins: $xmm0, $xmm1
16B       %4:vr128 = COPY $xmm1
32B       %0:vr128 = COPY $xmm0
48B       %5:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
64B       %6:vr128 = COPY %0:vr128
80B       %6:vr128 = PXORrr %6:vr128(tied-def 0), %5:vr128
112B      %4:vr128 = PADDDrr %4:vr128(tied-def 0), %0:vr128
144B      %5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
176B      %6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), %5:vr128
208B      %6:vr128 = PORrr %6:vr128(tied-def 0), %4:vr128
224B      $xmm0 = COPY %6:vr128
240B      RET 0, $xmm0

So the two address conversion result is actually better with my new patch.

But after scheduling, the %0 in the COPY instruction becomes killed operand, so now %6 and %0 and xmm0 can be coalesced, and both COPY instructions can be deleted.

0B      bb.0 (%ir-block.0):
          liveins: $xmm0, $xmm1
16B       %4:vr128 = COPY $xmm1
32B       %0:vr128 = COPY $xmm0
48B       %5:vr128 = MOVAPSrm $rip, 1, $noreg, %const.0, $noreg :: (load (s128) from constant-pool)
112B      %4:vr128 = PADDDrr %4:vr128(tied-def 0), %0:vr128
116B      %6:vr128 = COPY %0:vr128
120B      %6:vr128 = PXORrr %6:vr128(tied-def 0), %5:vr128
144B      %5:vr128 = PXORrr %5:vr128(tied-def 0), %4:vr128
176B      %6:vr128 = PCMPGTDrr %6:vr128(tied-def 0), %5:vr128
208B      %6:vr128 = PORrr %6:vr128(tied-def 0), %4:vr128
224B      $xmm0 = COPY %6:vr128
240B      RET 0, $xmm0

So this is another pass order problem between scheduling/TwoAddressInstructionPass.

Carrot: Let's take function v4i32 as an example With this patch ``` liveins: $xmm0, $xmm1 %1:vr128…
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v8i64: ; AVX1-LABEL: v8i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808]
; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm6 ; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm6
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm7 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/umul-with-overflow.ll

Show All 28 Lines
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addl {{[0-9]+}}(%esp), %eax ; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
; X86-NEXT: addl %eax, %eax ; X86-NEXT: addl %eax, %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test2: ; X64-LABEL: test2:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: # kill: def $edi killed $edi def $rdi ; X64-NEXT: # kill: def $edi killed $edi def $rdi
; X64-NEXT: addl %esi, %edi ; X64-NEXT: leal (%rdi,%rsi), %eax
; X64-NEXT: leal (%rdi,%rdi), %eax ; X64-NEXT: addl %eax, %eax
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%tmp0 = add i32 %b, %a %tmp0 = add i32 %b, %a
%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2) %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2)
%tmp2 = extractvalue { i32, i1 } %tmp1, 0 %tmp2 = extractvalue { i32, i1 } %tmp1, 0
ret i32 %tmp2 ret i32 %tmp2
} }
▲ Show 20 Lines • Show All 582 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/umul_fix.ll

Show All 39 Lines
; X86-LABEL: func2: ; X86-LABEL: func2:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: movl %edx, %edi ; X86-NEXT: movl %edx, %edi
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull %ebp
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %esi
; X86-NEXT: movl %edx, %ebp ; X86-NEXT: addl %edx, %ebx
; X86-NEXT: addl %ebx, %ebp
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %edi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull %ebp
; X86-NEXT: addl %ebp, %eax ; X86-NEXT: addl %ebx, %eax
; X86-NEXT: adcl %edi, %edx ; X86-NEXT: adcl %edi, %edx
; X86-NEXT: imull {{[0-9]+}}(%esp), %ecx ; X86-NEXT: imull {{[0-9]+}}(%esp), %ecx
; X86-NEXT: addl %ecx, %edx ; X86-NEXT: addl %ecx, %edx
; X86-NEXT: shldl $30, %eax, %edx ; X86-NEXT: shldl $30, %eax, %edx
; X86-NEXT: shldl $30, %esi, %eax ; X86-NEXT: shldl $30, %esi, %eax
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: func8: ; X86-LABEL: func8:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull %ebp ; X86-NEXT: mull %ebp
; X86-NEXT: movl %edx, %esi ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: movl %eax, %edi ; X86-NEXT: movl %eax, %edi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: mull %ebx ; X86-NEXT: mull %ebx
; X86-NEXT: addl %edx, %edi ; X86-NEXT: addl %edx, %edi
; X86-NEXT: adcl $0, %esi ; X86-NEXT: adcl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull %ebp ; X86-NEXT: mull %ebp
; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %edx, %esi
; X86-NEXT: movl %eax, %ebp ; X86-NEXT: movl %eax, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull %ebx ; X86-NEXT: mull %ebx
; X86-NEXT: addl %edi, %eax ; X86-NEXT: addl %edi, %eax
; X86-NEXT: adcl %esi, %edx ; X86-NEXT: adcl %edx, %ecx
; X86-NEXT: adcl $0, %ecx ; X86-NEXT: adcl $0, %esi
; X86-NEXT: addl %ebp, %edx ; X86-NEXT: addl %ebp, %ecx
; X86-NEXT: adcl $0, %ecx ; X86-NEXT: adcl $0, %esi
; X86-NEXT: shldl $1, %edx, %ecx ; X86-NEXT: shldl $1, %ecx, %esi
; X86-NEXT: shrdl $31, %edx, %eax ; X86-NEXT: shrdl $31, %ecx, %eax
; X86-NEXT: movl %ecx, %edx ; X86-NEXT: movl %esi, %edx
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 63) %tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 63)
ret i64 %tmp ret i64 %tmp
} }
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/umul_fix_sat.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; ;
; X86-LABEL: func2: ; X86-LABEL: func2:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull %ebx ; X86-NEXT: mull %esi
; X86-NEXT: movl %edx, %edi ; X86-NEXT: movl %edx, %edi
; X86-NEXT: movl %eax, %esi ; X86-NEXT: movl %eax, %ebx
; X86-NEXT: movl %ecx, %eax ; X86-NEXT: movl %ecx, %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, %ecx ; X86-NEXT: movl %eax, %ecx
; X86-NEXT: movl %edx, %ebp ; X86-NEXT: addl %edx, %ebx
; X86-NEXT: addl %esi, %ebp
; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull %ebx ; X86-NEXT: mull %esi
; X86-NEXT: movl %edx, %esi ; X86-NEXT: movl %edx, %esi
; X86-NEXT: movl %eax, %ebx ; X86-NEXT: movl %eax, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: mull {{[0-9]+}}(%esp) ; X86-NEXT: mull {{[0-9]+}}(%esp)
; X86-NEXT: addl %ebp, %eax ; X86-NEXT: addl %ebx, %eax
; X86-NEXT: adcl %edi, %edx ; X86-NEXT: adcl %edi, %edx
; X86-NEXT: adcl $0, %esi ; X86-NEXT: adcl $0, %esi
; X86-NEXT: addl %ebx, %edx ; X86-NEXT: addl %ebp, %edx
; X86-NEXT: adcl $0, %esi ; X86-NEXT: adcl $0, %esi
; X86-NEXT: shrdl $2, %eax, %ecx ; X86-NEXT: shrdl $2, %eax, %ecx
; X86-NEXT: shrdl $2, %edx, %eax ; X86-NEXT: shrdl $2, %edx, %eax
; X86-NEXT: shrl $2, %edx ; X86-NEXT: shrl $2, %edx
; X86-NEXT: orl %esi, %edx ; X86-NEXT: orl %esi, %edx
; X86-NEXT: movl $-1, %edx ; X86-NEXT: movl $-1, %edx
; X86-NEXT: cmovnel %edx, %ecx ; X86-NEXT: cmovnel %edx, %ecx
; X86-NEXT: cmovel %eax, %edx ; X86-NEXT: cmovel %eax, %edx
▲ Show 20 Lines • Show All 458 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll

Show All 29 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,306783378,171798691,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,306783378,171798691,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even: ; CHECK-AVX1-LABEL: test_urem_odd_even:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,306783378,1,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,306783378,1,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_allones_eq: ; CHECK-AVX1-LABEL: test_urem_even_allones_eq:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783379,306783379,2,306783379] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783379,306783379,2,306783379]
; CHECK-SSE41-NEXT: pmaxud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pmaxud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_allones_ne: ; CHECK-AVX1-LABEL: test_urem_even_allones_ne:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,306783378,1,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,306783378,1,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_allones_eq: ; CHECK-AVX1-LABEL: test_urem_odd_even_allones_eq:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993460,306783379,2,42949673] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993460,306783379,2,42949673]
; CHECK-SSE41-NEXT: pmaxud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pmaxud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_allones_ne: ; CHECK-AVX1-LABEL: test_urem_odd_even_allones_ne:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,858993459,268435455,858993459] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,858993459,268435455,858993459]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_odd_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,306783378,268435455,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,306783378,268435455,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_even_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,306783378,268435455,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,306783378,268435455,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,306783378,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,306783378,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_one: ; CHECK-AVX1-LABEL: test_urem_odd_even_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,858993459,1,858993459] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,858993459,1,858993459]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_INT_MIN: ; CHECK-AVX1-LABEL: test_urem_odd_INT_MIN:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,306783378,1,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,306783378,1,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_INT_MIN: ; CHECK-AVX1-LABEL: test_urem_even_INT_MIN:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,306783378,1,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,306783378,1,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_INT_MIN: ; CHECK-AVX1-LABEL: test_urem_odd_even_INT_MIN:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,1,268435455,858993459] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,1,268435455,858993459]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,1,268435455,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,1,268435455,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,1,268435455,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,1,268435455,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_odd_even_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,1,4294967295,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,1,4294967295,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_allones_and_one: ; CHECK-AVX1-LABEL: test_urem_even_allones_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,1,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,1,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_allones_and_one: ; CHECK-AVX1-LABEL: test_urem_odd_even_allones_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,268435455,4294967295,858993459] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,268435455,4294967295,858993459]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_odd_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,268435455,4294967295,306783378] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,268435455,4294967295,306783378]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_even_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,268435455,4294967295,42949672] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,268435455,4294967295,42949672]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [858993459,1,268435455,4294967295] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,1,268435455,4294967295]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: por %xmm2, %xmm1 ; CHECK-SSE41-NEXT: por %xmm2, %xmm0
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm0 = [306783378,1,268435455,4294967295] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [306783378,1,268435455,4294967295]
; CHECK-SSE41-NEXT: pminud %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 36 Lines

llvm/test/CodeGen/X86/vec-strict-cmp-128.ll

Show First 20 Lines • Show All 717 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpneqps %xmm3, %xmm4 ; SSE-32-NEXT: cmpneqps %xmm3, %xmm4
; SSE-32-NEXT: cmpordps %xmm3, %xmm2 ; SSE-32-NEXT: cmpordps %xmm2, %xmm3
; SSE-32-NEXT: andps %xmm4, %xmm2 ; SSE-32-NEXT: andps %xmm4, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_one_q: ; SSE-64-LABEL: test_v4f32_one_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpneqps %xmm3, %xmm4 ; SSE-64-NEXT: cmpneqps %xmm3, %xmm4
; SSE-64-NEXT: cmpordps %xmm3, %xmm2 ; SSE-64-NEXT: cmpordps %xmm3, %xmm2
; SSE-64-NEXT: andps %xmm4, %xmm2 ; SSE-64-NEXT: andps %xmm2, %xmm4
; SSE-64-NEXT: andps %xmm2, %xmm0 ; SSE-64-NEXT: andps %xmm4, %xmm0
; SSE-64-NEXT: andnps %xmm1, %xmm2 ; SSE-64-NEXT: andnps %xmm1, %xmm4
; SSE-64-NEXT: orps %xmm2, %xmm0 ; SSE-64-NEXT: orps %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_one_q: ; AVX-32-LABEL: test_v4f32_one_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpeqps %xmm3, %xmm4 ; SSE-32-NEXT: cmpeqps %xmm3, %xmm4
; SSE-32-NEXT: cmpunordps %xmm3, %xmm2 ; SSE-32-NEXT: cmpunordps %xmm2, %xmm3
; SSE-32-NEXT: orps %xmm4, %xmm2 ; SSE-32-NEXT: orps %xmm4, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ueq_q: ; SSE-64-LABEL: test_v4f32_ueq_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpeqps %xmm3, %xmm4 ; SSE-64-NEXT: cmpeqps %xmm3, %xmm4
; SSE-64-NEXT: cmpunordps %xmm3, %xmm2 ; SSE-64-NEXT: cmpunordps %xmm3, %xmm2
; SSE-64-NEXT: orps %xmm4, %xmm2 ; SSE-64-NEXT: orps %xmm2, %xmm4
; SSE-64-NEXT: andps %xmm2, %xmm0 ; SSE-64-NEXT: andps %xmm4, %xmm0
; SSE-64-NEXT: andnps %xmm1, %xmm2 ; SSE-64-NEXT: andnps %xmm1, %xmm4
; SSE-64-NEXT: orps %xmm2, %xmm0 ; SSE-64-NEXT: orps %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_ueq_q: ; AVX-32-LABEL: test_v4f32_ueq_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 1,433 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpneqpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpneqpd %xmm3, %xmm4
; SSE-32-NEXT: cmpordpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpordpd %xmm2, %xmm3
; SSE-32-NEXT: andpd %xmm4, %xmm2 ; SSE-32-NEXT: andpd %xmm4, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_one_q: ; SSE-64-LABEL: test_v2f64_one_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpneqpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpneqpd %xmm3, %xmm4
; SSE-64-NEXT: cmpordpd %xmm3, %xmm2 ; SSE-64-NEXT: cmpordpd %xmm3, %xmm2
; SSE-64-NEXT: andpd %xmm4, %xmm2 ; SSE-64-NEXT: andpd %xmm2, %xmm4
; SSE-64-NEXT: andpd %xmm2, %xmm0 ; SSE-64-NEXT: andpd %xmm4, %xmm0
; SSE-64-NEXT: andnpd %xmm1, %xmm2 ; SSE-64-NEXT: andnpd %xmm1, %xmm4
; SSE-64-NEXT: orpd %xmm2, %xmm0 ; SSE-64-NEXT: orpd %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_one_q: ; AVX-32-LABEL: test_v2f64_one_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpeqpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpeqpd %xmm3, %xmm4
; SSE-32-NEXT: cmpunordpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpunordpd %xmm2, %xmm3
; SSE-32-NEXT: orpd %xmm4, %xmm2 ; SSE-32-NEXT: orpd %xmm4, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ueq_q: ; SSE-64-LABEL: test_v2f64_ueq_q:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpeqpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpeqpd %xmm3, %xmm4
; SSE-64-NEXT: cmpunordpd %xmm3, %xmm2 ; SSE-64-NEXT: cmpunordpd %xmm3, %xmm2
; SSE-64-NEXT: orpd %xmm4, %xmm2 ; SSE-64-NEXT: orpd %xmm2, %xmm4
; SSE-64-NEXT: andpd %xmm2, %xmm0 ; SSE-64-NEXT: andpd %xmm4, %xmm0
; SSE-64-NEXT: andnpd %xmm1, %xmm2 ; SSE-64-NEXT: andnpd %xmm1, %xmm4
; SSE-64-NEXT: orpd %xmm2, %xmm0 ; SSE-64-NEXT: orpd %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_ueq_q: ; AVX-32-LABEL: test_v2f64_ueq_q:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpltps %xmm3, %xmm4 ; SSE-32-NEXT: cmpltps %xmm3, %xmm4
; SSE-32-NEXT: cmpeqps %xmm3, %xmm2 ; SSE-32-NEXT: cmpeqps %xmm2, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_oeq_s: ; SSE-64-LABEL: test_v4f32_oeq_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpltps %xmm3, %xmm4 ; SSE-64-NEXT: cmpltps %xmm3, %xmm4
▲ Show 20 Lines • Show All 458 Lines • ▼ Show 20 Lines
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpltps %xmm3, %xmm4 ; SSE-32-NEXT: cmpltps %xmm3, %xmm4
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpneqps %xmm3, %xmm4 ; SSE-32-NEXT: cmpneqps %xmm3, %xmm4
; SSE-32-NEXT: cmpordps %xmm3, %xmm2 ; SSE-32-NEXT: cmpordps %xmm2, %xmm3
; SSE-32-NEXT: andps %xmm4, %xmm2 ; SSE-32-NEXT: andps %xmm4, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_one_s: ; SSE-64-LABEL: test_v4f32_one_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpltps %xmm3, %xmm4 ; SSE-64-NEXT: cmpltps %xmm3, %xmm4
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpneqps %xmm3, %xmm4 ; SSE-64-NEXT: cmpneqps %xmm3, %xmm4
; SSE-64-NEXT: cmpordps %xmm3, %xmm2 ; SSE-64-NEXT: cmpordps %xmm3, %xmm2
; SSE-64-NEXT: andps %xmm4, %xmm2 ; SSE-64-NEXT: andps %xmm2, %xmm4
; SSE-64-NEXT: andps %xmm2, %xmm0 ; SSE-64-NEXT: andps %xmm4, %xmm0
; SSE-64-NEXT: andnps %xmm1, %xmm2 ; SSE-64-NEXT: andnps %xmm1, %xmm4
; SSE-64-NEXT: orps %xmm2, %xmm0 ; SSE-64-NEXT: orps %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_one_s: ; AVX-32-LABEL: test_v4f32_one_s:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpltps %xmm3, %xmm4 ; SSE-32-NEXT: cmpltps %xmm3, %xmm4
; SSE-32-NEXT: cmpordps %xmm3, %xmm2 ; SSE-32-NEXT: cmpordps %xmm2, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ord_s: ; SSE-64-LABEL: test_v4f32_ord_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpltps %xmm3, %xmm4 ; SSE-64-NEXT: cmpltps %xmm3, %xmm4
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpltps %xmm3, %xmm4 ; SSE-32-NEXT: cmpltps %xmm3, %xmm4
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpeqps %xmm3, %xmm4 ; SSE-32-NEXT: cmpeqps %xmm3, %xmm4
; SSE-32-NEXT: cmpunordps %xmm3, %xmm2 ; SSE-32-NEXT: cmpunordps %xmm2, %xmm3
; SSE-32-NEXT: orps %xmm4, %xmm2 ; SSE-32-NEXT: orps %xmm4, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_ueq_s: ; SSE-64-LABEL: test_v4f32_ueq_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpltps %xmm3, %xmm4 ; SSE-64-NEXT: cmpltps %xmm3, %xmm4
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpeqps %xmm3, %xmm4 ; SSE-64-NEXT: cmpeqps %xmm3, %xmm4
; SSE-64-NEXT: cmpunordps %xmm3, %xmm2 ; SSE-64-NEXT: cmpunordps %xmm3, %xmm2
; SSE-64-NEXT: orps %xmm4, %xmm2 ; SSE-64-NEXT: orps %xmm2, %xmm4
; SSE-64-NEXT: andps %xmm2, %xmm0 ; SSE-64-NEXT: andps %xmm4, %xmm0
; SSE-64-NEXT: andnps %xmm1, %xmm2 ; SSE-64-NEXT: andnps %xmm1, %xmm4
; SSE-64-NEXT: orps %xmm2, %xmm0 ; SSE-64-NEXT: orps %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v4f32_ueq_s: ; AVX-32-LABEL: test_v4f32_ueq_s:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 444 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpltps %xmm3, %xmm4 ; SSE-32-NEXT: cmpltps %xmm3, %xmm4
; SSE-32-NEXT: cmpneqps %xmm3, %xmm2 ; SSE-32-NEXT: cmpneqps %xmm2, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_une_s: ; SSE-64-LABEL: test_v4f32_une_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpltps %xmm3, %xmm4 ; SSE-64-NEXT: cmpltps %xmm3, %xmm4
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movaps 8(%ebp), %xmm3 ; SSE-32-NEXT: movaps 8(%ebp), %xmm3
; SSE-32-NEXT: movaps %xmm2, %xmm4 ; SSE-32-NEXT: movaps %xmm2, %xmm4
; SSE-32-NEXT: cmpltps %xmm3, %xmm4 ; SSE-32-NEXT: cmpltps %xmm3, %xmm4
; SSE-32-NEXT: cmpunordps %xmm3, %xmm2 ; SSE-32-NEXT: cmpunordps %xmm2, %xmm3
; SSE-32-NEXT: andps %xmm2, %xmm0 ; SSE-32-NEXT: andps %xmm3, %xmm0
; SSE-32-NEXT: andnps %xmm1, %xmm2 ; SSE-32-NEXT: andnps %xmm1, %xmm3
; SSE-32-NEXT: orps %xmm2, %xmm0 ; SSE-32-NEXT: orps %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v4f32_uno_s: ; SSE-64-LABEL: test_v4f32_uno_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movaps %xmm2, %xmm4 ; SSE-64-NEXT: movaps %xmm2, %xmm4
; SSE-64-NEXT: cmpltps %xmm3, %xmm4 ; SSE-64-NEXT: cmpltps %xmm3, %xmm4
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpltpd %xmm3, %xmm4
; SSE-32-NEXT: cmpeqpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpeqpd %xmm2, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_oeq_s: ; SSE-64-LABEL: test_v2f64_oeq_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpltpd %xmm3, %xmm4
▲ Show 20 Lines • Show All 458 Lines • ▼ Show 20 Lines
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpltpd %xmm3, %xmm4
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpneqpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpneqpd %xmm3, %xmm4
; SSE-32-NEXT: cmpordpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpordpd %xmm2, %xmm3
; SSE-32-NEXT: andpd %xmm4, %xmm2 ; SSE-32-NEXT: andpd %xmm4, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_one_s: ; SSE-64-LABEL: test_v2f64_one_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpltpd %xmm3, %xmm4
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpneqpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpneqpd %xmm3, %xmm4
; SSE-64-NEXT: cmpordpd %xmm3, %xmm2 ; SSE-64-NEXT: cmpordpd %xmm3, %xmm2
; SSE-64-NEXT: andpd %xmm4, %xmm2 ; SSE-64-NEXT: andpd %xmm2, %xmm4
; SSE-64-NEXT: andpd %xmm2, %xmm0 ; SSE-64-NEXT: andpd %xmm4, %xmm0
; SSE-64-NEXT: andnpd %xmm1, %xmm2 ; SSE-64-NEXT: andnpd %xmm1, %xmm4
; SSE-64-NEXT: orpd %xmm2, %xmm0 ; SSE-64-NEXT: orpd %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_one_s: ; AVX-32-LABEL: test_v2f64_one_s:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpltpd %xmm3, %xmm4
; SSE-32-NEXT: cmpordpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpordpd %xmm2, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ord_s: ; SSE-64-LABEL: test_v2f64_ord_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpltpd %xmm3, %xmm4
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpltpd %xmm3, %xmm4
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpeqpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpeqpd %xmm3, %xmm4
; SSE-32-NEXT: cmpunordpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpunordpd %xmm2, %xmm3
; SSE-32-NEXT: orpd %xmm4, %xmm2 ; SSE-32-NEXT: orpd %xmm4, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_ueq_s: ; SSE-64-LABEL: test_v2f64_ueq_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpltpd %xmm3, %xmm4
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpeqpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpeqpd %xmm3, %xmm4
; SSE-64-NEXT: cmpunordpd %xmm3, %xmm2 ; SSE-64-NEXT: cmpunordpd %xmm3, %xmm2
; SSE-64-NEXT: orpd %xmm4, %xmm2 ; SSE-64-NEXT: orpd %xmm2, %xmm4
; SSE-64-NEXT: andpd %xmm2, %xmm0 ; SSE-64-NEXT: andpd %xmm4, %xmm0
; SSE-64-NEXT: andnpd %xmm1, %xmm2 ; SSE-64-NEXT: andnpd %xmm1, %xmm4
; SSE-64-NEXT: orpd %xmm2, %xmm0 ; SSE-64-NEXT: orpd %xmm4, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; AVX-32-LABEL: test_v2f64_ueq_s: ; AVX-32-LABEL: test_v2f64_ueq_s:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX-32-NEXT: pushl %ebp
; AVX-32-NEXT: movl %esp, %ebp ; AVX-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: andl $-16, %esp ; AVX-32-NEXT: andl $-16, %esp
; AVX-32-NEXT: subl $16, %esp ; AVX-32-NEXT: subl $16, %esp
▲ Show 20 Lines • Show All 444 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpltpd %xmm3, %xmm4
; SSE-32-NEXT: cmpneqpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpneqpd %xmm2, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_une_s: ; SSE-64-LABEL: test_v2f64_une_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpltpd %xmm3, %xmm4
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pushl %ebp ; SSE-32-NEXT: pushl %ebp
; SSE-32-NEXT: movl %esp, %ebp ; SSE-32-NEXT: movl %esp, %ebp
; SSE-32-NEXT: andl $-16, %esp ; SSE-32-NEXT: andl $-16, %esp
; SSE-32-NEXT: subl $16, %esp ; SSE-32-NEXT: subl $16, %esp
; SSE-32-NEXT: movapd 8(%ebp), %xmm3 ; SSE-32-NEXT: movapd 8(%ebp), %xmm3
; SSE-32-NEXT: movapd %xmm2, %xmm4 ; SSE-32-NEXT: movapd %xmm2, %xmm4
; SSE-32-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-32-NEXT: cmpltpd %xmm3, %xmm4
; SSE-32-NEXT: cmpunordpd %xmm3, %xmm2 ; SSE-32-NEXT: cmpunordpd %xmm2, %xmm3
; SSE-32-NEXT: andpd %xmm2, %xmm0 ; SSE-32-NEXT: andpd %xmm3, %xmm0
; SSE-32-NEXT: andnpd %xmm1, %xmm2 ; SSE-32-NEXT: andnpd %xmm1, %xmm3
; SSE-32-NEXT: orpd %xmm2, %xmm0 ; SSE-32-NEXT: orpd %xmm3, %xmm0
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: test_v2f64_uno_s: ; SSE-64-LABEL: test_v2f64_uno_s:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movapd %xmm2, %xmm4 ; SSE-64-NEXT: movapd %xmm2, %xmm4
; SSE-64-NEXT: cmpltpd %xmm3, %xmm4 ; SSE-64-NEXT: cmpltpd %xmm3, %xmm4
▲ Show 20 Lines • Show All 82 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec_ctbits.ll

Show All 31 Lines; CHECK-NEXT: retq
ret <2 x i64> %c ret <2 x i64> %c
} }
define <2 x i64> @foolz(<2 x i64> %a) nounwind { define <2 x i64> @foolz(<2 x i64> %a) nounwind {
; CHECK-LABEL: foolz: ; CHECK-LABEL: foolz:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlq $1, %xmm1 ; CHECK-NEXT: psrlq $1, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlq $2, %xmm0 ; CHECK-NEXT: psrlq $2, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlq $4, %xmm1 ; CHECK-NEXT: psrlq $4, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlq $8, %xmm0 ; CHECK-NEXT: psrlq $8, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlq $16, %xmm1 ; CHECK-NEXT: psrlq $16, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlq $32, %xmm0 ; CHECK-NEXT: psrlq $32, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm1 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm0 ; CHECK-NEXT: psrlw $1, %xmm1
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm0, %xmm1 ; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pand %xmm0, %xmm2 ; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: psrlw $2, %xmm1 ; CHECK-NEXT: psrlw $2, %xmm0
; CHECK-NEXT: pand %xmm0, %xmm1 ; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm1 ; CHECK-NEXT: paddb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm2 ; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm1, %xmm2 ; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm0, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: psadbw %xmm2, %xmm0 ; CHECK-NEXT: psadbw %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 true) %c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 true)
ret <2 x i64> %c ret <2 x i64> %c
} }
define <2 x i64> @foopop(<2 x i64> %a) nounwind { define <2 x i64> @foopop(<2 x i64> %a) nounwind {
; CHECK-LABEL: foopop: ; CHECK-LABEL: foopop:
Show All 36 Lines
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pand %xmm1, %xmm2 ; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: psrlw $2, %xmm0 ; CHECK-NEXT: psrlw $2, %xmm0
; CHECK-NEXT: pand %xmm1, %xmm0 ; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm0 ; CHECK-NEXT: paddb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1 ; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1 ; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm0, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; CHECK-NEXT: psadbw %xmm0, %xmm2 ; CHECK-NEXT: psadbw %xmm1, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: psadbw %xmm0, %xmm1 ; CHECK-NEXT: psadbw %xmm1, %xmm0
; CHECK-NEXT: packuswb %xmm2, %xmm1 ; CHECK-NEXT: packuswb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%c = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 false) %c = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 false)
ret <2 x i32> %c ret <2 x i32> %c
} }
define <2 x i32> @promlz(<2 x i32> %a) nounwind { define <2 x i32> @promlz(<2 x i32> %a) nounwind {
; CHECK-LABEL: promlz: ; CHECK-LABEL: promlz:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $1, %xmm1 ; CHECK-NEXT: psrld $1, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $2, %xmm0 ; CHECK-NEXT: psrld $2, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $4, %xmm1 ; CHECK-NEXT: psrld $4, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $8, %xmm0 ; CHECK-NEXT: psrld $8, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $16, %xmm1 ; CHECK-NEXT: psrld $16, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm1, %xmm2 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm2, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm0 ; CHECK-NEXT: psrlw $1, %xmm1
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm0, %xmm2 ; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm2, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pand %xmm0, %xmm1 ; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: psrlw $2, %xmm2 ; CHECK-NEXT: psrlw $2, %xmm0
; CHECK-NEXT: pand %xmm0, %xmm2 ; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: paddb %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: psrlw $4, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm0 ; CHECK-NEXT: paddb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; CHECK-NEXT: psadbw %xmm1, %xmm2 ; CHECK-NEXT: psadbw %xmm1, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: psadbw %xmm1, %xmm0 ; CHECK-NEXT: psadbw %xmm1, %xmm0
; CHECK-NEXT: packuswb %xmm2, %xmm0 ; CHECK-NEXT: packuswb %xmm2, %xmm0
Show All 13 Lines
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pand %xmm1, %xmm2 ; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: psrlw $2, %xmm0 ; CHECK-NEXT: psrlw $2, %xmm0
; CHECK-NEXT: pand %xmm1, %xmm0 ; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm0 ; CHECK-NEXT: paddb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1 ; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1 ; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm0, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; CHECK-NEXT: psadbw %xmm0, %xmm2 ; CHECK-NEXT: psadbw %xmm1, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: psadbw %xmm0, %xmm1 ; CHECK-NEXT: psadbw %xmm1, %xmm0
; CHECK-NEXT: packuswb %xmm2, %xmm1 ; CHECK-NEXT: packuswb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%c = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a) %c = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a)
ret <2 x i32> %c ret <2 x i32> %c
} }

llvm/test/CodeGen/X86/vec_umulo.ll

Show First 20 Lines • Show All 1,088 Lines • ▼ Show 20 Lines
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
; SSE2-NEXT: pmullw %xmm1, %xmm0 ; SSE2-NEXT: pmullw %xmm1, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm4 ; SSE2-NEXT: pand %xmm0, %xmm4
; SSE2-NEXT: packuswb %xmm3, %xmm4 ; SSE2-NEXT: packuswb %xmm3, %xmm4
; SSE2-NEXT: psrlw $8, %xmm5 ; SSE2-NEXT: psrlw $8, %xmm5
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: packuswb %xmm5, %xmm0 ; SSE2-NEXT: packuswb %xmm5, %xmm0
; SSE2-NEXT: pcmpeqb %xmm2, %xmm0 ; SSE2-NEXT: pcmpeqb %xmm0, %xmm2
; SSE2-NEXT: pcmpeqd %xmm3, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm0, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm3
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE2-NEXT: psrad $24, %xmm0 ; SSE2-NEXT: psrad $24, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm1 ; SSE2-NEXT: movdqa %xmm3, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
; SSE2-NEXT: pslld $31, %xmm1 ; SSE2-NEXT: pslld $31, %xmm1
; SSE2-NEXT: psrad $31, %xmm1 ; SSE2-NEXT: psrad $31, %xmm1
Show All 22 Lines
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
; SSSE3-NEXT: pmullw %xmm1, %xmm0 ; SSSE3-NEXT: pmullw %xmm1, %xmm0
; SSSE3-NEXT: pand %xmm0, %xmm4 ; SSSE3-NEXT: pand %xmm0, %xmm4
; SSSE3-NEXT: packuswb %xmm3, %xmm4 ; SSSE3-NEXT: packuswb %xmm3, %xmm4
; SSSE3-NEXT: psrlw $8, %xmm5 ; SSSE3-NEXT: psrlw $8, %xmm5
; SSSE3-NEXT: psrlw $8, %xmm0 ; SSSE3-NEXT: psrlw $8, %xmm0
; SSSE3-NEXT: packuswb %xmm5, %xmm0 ; SSSE3-NEXT: packuswb %xmm5, %xmm0
; SSSE3-NEXT: pcmpeqb %xmm2, %xmm0 ; SSSE3-NEXT: pcmpeqb %xmm0, %xmm2
; SSSE3-NEXT: pcmpeqd %xmm3, %xmm3 ; SSSE3-NEXT: pcmpeqd %xmm3, %xmm3
; SSSE3-NEXT: pxor %xmm0, %xmm3 ; SSSE3-NEXT: pxor %xmm2, %xmm3
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSSE3-NEXT: psrad $24, %xmm0 ; SSSE3-NEXT: psrad $24, %xmm0
; SSSE3-NEXT: movdqa %xmm3, %xmm1 ; SSSE3-NEXT: movdqa %xmm3, %xmm1
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
; SSSE3-NEXT: pslld $31, %xmm1 ; SSSE3-NEXT: pslld $31, %xmm1
; SSSE3-NEXT: psrad $31, %xmm1 ; SSSE3-NEXT: psrad $31, %xmm1
▲ Show 20 Lines • Show All 1,231 Lines • ▼ Show 20 Lines; AVX512BW-NEXT: retq
ret <64 x i32> %res ret <64 x i32> %res
} }
define <8 x i32> @umulo_v8i16(<8 x i16> %a0, <8 x i16> %a1, <8 x i16>* %p2) nounwind { define <8 x i32> @umulo_v8i16(<8 x i16> %a0, <8 x i16> %a1, <8 x i16>* %p2) nounwind {
; SSE2-LABEL: umulo_v8i16: ; SSE2-LABEL: umulo_v8i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pmullw %xmm1, %xmm2 ; SSE2-NEXT: pmullw %xmm1, %xmm2
; SSE2-NEXT: pmulhuw %xmm1, %xmm0 ; SSE2-NEXT: pmulhuw %xmm0, %xmm1
; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: pcmpeqw %xmm0, %xmm3 ; SSE2-NEXT: pcmpeqw %xmm0, %xmm1
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm1 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE2-NEXT: psrad $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0
; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
; SSE2-NEXT: pslld $31, %xmm1 ; SSE2-NEXT: pslld $31, %xmm1
; SSE2-NEXT: psrad $31, %xmm1 ; SSE2-NEXT: psrad $31, %xmm1
; SSE2-NEXT: movdqa %xmm2, (%rdi) ; SSE2-NEXT: movdqa %xmm2, (%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: umulo_v8i16: ; SSSE3-LABEL: umulo_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pmullw %xmm1, %xmm2 ; SSSE3-NEXT: pmullw %xmm1, %xmm2
; SSSE3-NEXT: pmulhuw %xmm1, %xmm0 ; SSSE3-NEXT: pmulhuw %xmm0, %xmm1
; SSSE3-NEXT: pxor %xmm3, %xmm3 ; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: pcmpeqw %xmm0, %xmm3 ; SSSE3-NEXT: pcmpeqw %xmm0, %xmm1
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm0, %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm1 ; SSSE3-NEXT: pxor %xmm0, %xmm1
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSSE3-NEXT: psrad $16, %xmm0 ; SSSE3-NEXT: psrad $16, %xmm0
; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
; SSSE3-NEXT: pslld $31, %xmm1 ; SSSE3-NEXT: pslld $31, %xmm1
; SSSE3-NEXT: psrad $31, %xmm1 ; SSSE3-NEXT: psrad $31, %xmm1
; SSSE3-NEXT: movdqa %xmm2, (%rdi) ; SSSE3-NEXT: movdqa %xmm2, (%rdi)
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: umulo_v8i16: ; SSE41-LABEL: umulo_v8i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pmullw %xmm1, %xmm2 ; SSE41-NEXT: pmullw %xmm1, %xmm2
; SSE41-NEXT: pmulhuw %xmm1, %xmm0 ; SSE41-NEXT: pmulhuw %xmm0, %xmm1
; SSE41-NEXT: pxor %xmm3, %xmm3 ; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: pcmpeqw %xmm0, %xmm3 ; SSE41-NEXT: pcmpeqw %xmm0, %xmm1
; SSE41-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE41-NEXT: pcmpeqd %xmm0, %xmm0
; SSE41-NEXT: pxor %xmm3, %xmm1 ; SSE41-NEXT: pxor %xmm0, %xmm1
; SSE41-NEXT: pmovsxwd %xmm1, %xmm0 ; SSE41-NEXT: pmovsxwd %xmm1, %xmm0
; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
; SSE41-NEXT: pslld $31, %xmm1 ; SSE41-NEXT: pslld $31, %xmm1
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrad $31, %xmm1
; SSE41-NEXT: movdqa %xmm2, (%rdi) ; SSE41-NEXT: movdqa %xmm2, (%rdi)
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: umulo_v8i16: ; AVX1-LABEL: umulo_v8i16:
▲ Show 20 Lines • Show All 972 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-bitreverse.ll

Show All 19 Lines
; SSE-LABEL: test_bitreverse_i8: ; SSE-LABEL: test_bitreverse_i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rolb $4, %dil ; SSE-NEXT: rolb $4, %dil
; SSE-NEXT: movl %edi, %eax ; SSE-NEXT: movl %edi, %eax
; SSE-NEXT: andb $51, %al ; SSE-NEXT: andb $51, %al
; SSE-NEXT: shlb $2, %al ; SSE-NEXT: shlb $2, %al
; SSE-NEXT: shrb $2, %dil ; SSE-NEXT: shrb $2, %dil
; SSE-NEXT: andb $51, %dil ; SSE-NEXT: andb $51, %dil
; SSE-NEXT: orb %al, %dil
; SSE-NEXT: movl %edi, %eax
; SSE-NEXT: andb $85, %al
; SSE-NEXT: addb %al, %al
; SSE-NEXT: shrb %dil
; SSE-NEXT: andb $85, %dil
; SSE-NEXT: orb %dil, %al ; SSE-NEXT: orb %dil, %al
; SSE-NEXT: movl %eax, %ecx
; SSE-NEXT: andb $85, %cl
; SSE-NEXT: addb %cl, %cl
; SSE-NEXT: shrb %al
; SSE-NEXT: andb $85, %al
; SSE-NEXT: orb %cl, %al
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_bitreverse_i8: ; AVX-LABEL: test_bitreverse_i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: rolb $4, %dil ; AVX-NEXT: rolb $4, %dil
; AVX-NEXT: movl %edi, %eax ; AVX-NEXT: movl %edi, %eax
; AVX-NEXT: andb $51, %al ; AVX-NEXT: andb $51, %al
; AVX-NEXT: shlb $2, %al ; AVX-NEXT: shlb $2, %al
; AVX-NEXT: shrb $2, %dil ; AVX-NEXT: shrb $2, %dil
; AVX-NEXT: andb $51, %dil ; AVX-NEXT: andb $51, %dil
; AVX-NEXT: orb %al, %dil
; AVX-NEXT: movl %edi, %eax
; AVX-NEXT: andb $85, %al
; AVX-NEXT: addb %al, %al
; AVX-NEXT: shrb %dil
; AVX-NEXT: andb $85, %dil
; AVX-NEXT: orb %dil, %al ; AVX-NEXT: orb %dil, %al
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: andb $85, %cl
; AVX-NEXT: addb %cl, %cl
; AVX-NEXT: shrb %al
; AVX-NEXT: andb $85, %al
; AVX-NEXT: orb %cl, %al
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; XOP-LABEL: test_bitreverse_i8: ; XOP-LABEL: test_bitreverse_i8:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovd %edi, %xmm0 ; XOP-NEXT: vmovd %edi, %xmm0
; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0 ; XOP-NEXT: vpperm {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0, %xmm0
; XOP-NEXT: vmovd %xmm0, %eax ; XOP-NEXT: vmovd %xmm0, %eax
; XOP-NEXT: # kill: def $al killed $al killed $eax ; XOP-NEXT: # kill: def $al killed $al killed $eax
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; GFNISSE-LABEL: test_bitreverse_i8: ; GFNISSE-LABEL: test_bitreverse_i8:
; GFNISSE: # %bb.0: ; GFNISSE: # %bb.0:
; GFNISSE-NEXT: rolb $4, %dil ; GFNISSE-NEXT: rolb $4, %dil
; GFNISSE-NEXT: movl %edi, %eax ; GFNISSE-NEXT: movl %edi, %eax
; GFNISSE-NEXT: andb $51, %al ; GFNISSE-NEXT: andb $51, %al
; GFNISSE-NEXT: shlb $2, %al ; GFNISSE-NEXT: shlb $2, %al
; GFNISSE-NEXT: shrb $2, %dil ; GFNISSE-NEXT: shrb $2, %dil
; GFNISSE-NEXT: andb $51, %dil ; GFNISSE-NEXT: andb $51, %dil
; GFNISSE-NEXT: orb %al, %dil
; GFNISSE-NEXT: movl %edi, %eax
; GFNISSE-NEXT: andb $85, %al
; GFNISSE-NEXT: addb %al, %al
; GFNISSE-NEXT: shrb %dil
; GFNISSE-NEXT: andb $85, %dil
; GFNISSE-NEXT: orb %dil, %al ; GFNISSE-NEXT: orb %dil, %al
; GFNISSE-NEXT: movl %eax, %ecx
; GFNISSE-NEXT: andb $85, %cl
; GFNISSE-NEXT: addb %cl, %cl
; GFNISSE-NEXT: shrb %al
; GFNISSE-NEXT: andb $85, %al
; GFNISSE-NEXT: orb %cl, %al
; GFNISSE-NEXT: retq ; GFNISSE-NEXT: retq
; ;
; GFNIAVX-LABEL: test_bitreverse_i8: ; GFNIAVX-LABEL: test_bitreverse_i8:
; GFNIAVX: # %bb.0: ; GFNIAVX: # %bb.0:
; GFNIAVX-NEXT: rolb $4, %dil ; GFNIAVX-NEXT: rolb $4, %dil
; GFNIAVX-NEXT: movl %edi, %eax ; GFNIAVX-NEXT: movl %edi, %eax
; GFNIAVX-NEXT: andb $51, %al ; GFNIAVX-NEXT: andb $51, %al
; GFNIAVX-NEXT: shlb $2, %al ; GFNIAVX-NEXT: shlb $2, %al
; GFNIAVX-NEXT: shrb $2, %dil ; GFNIAVX-NEXT: shrb $2, %dil
; GFNIAVX-NEXT: andb $51, %dil ; GFNIAVX-NEXT: andb $51, %dil
; GFNIAVX-NEXT: orb %al, %dil
; GFNIAVX-NEXT: movl %edi, %eax
; GFNIAVX-NEXT: andb $85, %al
; GFNIAVX-NEXT: addb %al, %al
; GFNIAVX-NEXT: shrb %dil
; GFNIAVX-NEXT: andb $85, %dil
; GFNIAVX-NEXT: orb %dil, %al ; GFNIAVX-NEXT: orb %dil, %al
; GFNIAVX-NEXT: movl %eax, %ecx
; GFNIAVX-NEXT: andb $85, %cl
; GFNIAVX-NEXT: addb %cl, %cl
; GFNIAVX-NEXT: shrb %al
; GFNIAVX-NEXT: andb $85, %al
; GFNIAVX-NEXT: orb %cl, %al
; GFNIAVX-NEXT: retq ; GFNIAVX-NEXT: retq
; ;
; GFNIAVX2-LABEL: test_bitreverse_i8: ; GFNIAVX2-LABEL: test_bitreverse_i8:
; GFNIAVX2: # %bb.0: ; GFNIAVX2: # %bb.0:
; GFNIAVX2-NEXT: rolb $4, %dil ; GFNIAVX2-NEXT: rolb $4, %dil
; GFNIAVX2-NEXT: movl %edi, %eax ; GFNIAVX2-NEXT: movl %edi, %eax
; GFNIAVX2-NEXT: andb $51, %al ; GFNIAVX2-NEXT: andb $51, %al
; GFNIAVX2-NEXT: shlb $2, %al ; GFNIAVX2-NEXT: shlb $2, %al
; GFNIAVX2-NEXT: shrb $2, %dil ; GFNIAVX2-NEXT: shrb $2, %dil
; GFNIAVX2-NEXT: andb $51, %dil ; GFNIAVX2-NEXT: andb $51, %dil
; GFNIAVX2-NEXT: orb %al, %dil
; GFNIAVX2-NEXT: movl %edi, %eax
; GFNIAVX2-NEXT: andb $85, %al
; GFNIAVX2-NEXT: addb %al, %al
; GFNIAVX2-NEXT: shrb %dil
; GFNIAVX2-NEXT: andb $85, %dil
; GFNIAVX2-NEXT: orb %dil, %al ; GFNIAVX2-NEXT: orb %dil, %al
; GFNIAVX2-NEXT: movl %eax, %ecx
; GFNIAVX2-NEXT: andb $85, %cl
; GFNIAVX2-NEXT: addb %cl, %cl
; GFNIAVX2-NEXT: shrb %al
; GFNIAVX2-NEXT: andb $85, %al
; GFNIAVX2-NEXT: orb %cl, %al
; GFNIAVX2-NEXT: retq ; GFNIAVX2-NEXT: retq
; ;
; GFNIAVX512F-LABEL: test_bitreverse_i8: ; GFNIAVX512F-LABEL: test_bitreverse_i8:
; GFNIAVX512F: # %bb.0: ; GFNIAVX512F: # %bb.0:
; GFNIAVX512F-NEXT: rolb $4, %dil ; GFNIAVX512F-NEXT: rolb $4, %dil
; GFNIAVX512F-NEXT: movl %edi, %eax ; GFNIAVX512F-NEXT: movl %edi, %eax
; GFNIAVX512F-NEXT: andb $51, %al ; GFNIAVX512F-NEXT: andb $51, %al
; GFNIAVX512F-NEXT: shlb $2, %al ; GFNIAVX512F-NEXT: shlb $2, %al
; GFNIAVX512F-NEXT: shrb $2, %dil ; GFNIAVX512F-NEXT: shrb $2, %dil
; GFNIAVX512F-NEXT: andb $51, %dil ; GFNIAVX512F-NEXT: andb $51, %dil
; GFNIAVX512F-NEXT: orb %al, %dil
; GFNIAVX512F-NEXT: movl %edi, %eax
; GFNIAVX512F-NEXT: andb $85, %al
; GFNIAVX512F-NEXT: addb %al, %al
; GFNIAVX512F-NEXT: shrb %dil
; GFNIAVX512F-NEXT: andb $85, %dil
; GFNIAVX512F-NEXT: orb %dil, %al ; GFNIAVX512F-NEXT: orb %dil, %al
; GFNIAVX512F-NEXT: movl %eax, %ecx
; GFNIAVX512F-NEXT: andb $85, %cl
; GFNIAVX512F-NEXT: addb %cl, %cl
; GFNIAVX512F-NEXT: shrb %al
; GFNIAVX512F-NEXT: andb $85, %al
; GFNIAVX512F-NEXT: orb %cl, %al
; GFNIAVX512F-NEXT: retq ; GFNIAVX512F-NEXT: retq
; ;
; GFNIAVX512BW-LABEL: test_bitreverse_i8: ; GFNIAVX512BW-LABEL: test_bitreverse_i8:
; GFNIAVX512BW: # %bb.0: ; GFNIAVX512BW: # %bb.0:
; GFNIAVX512BW-NEXT: rolb $4, %dil ; GFNIAVX512BW-NEXT: rolb $4, %dil
; GFNIAVX512BW-NEXT: movl %edi, %eax ; GFNIAVX512BW-NEXT: movl %edi, %eax
; GFNIAVX512BW-NEXT: andb $51, %al ; GFNIAVX512BW-NEXT: andb $51, %al
; GFNIAVX512BW-NEXT: shlb $2, %al ; GFNIAVX512BW-NEXT: shlb $2, %al
; GFNIAVX512BW-NEXT: shrb $2, %dil ; GFNIAVX512BW-NEXT: shrb $2, %dil
; GFNIAVX512BW-NEXT: andb $51, %dil ; GFNIAVX512BW-NEXT: andb $51, %dil
; GFNIAVX512BW-NEXT: orb %al, %dil
; GFNIAVX512BW-NEXT: movl %edi, %eax
; GFNIAVX512BW-NEXT: andb $85, %al
; GFNIAVX512BW-NEXT: addb %al, %al
; GFNIAVX512BW-NEXT: shrb %dil
; GFNIAVX512BW-NEXT: andb $85, %dil
; GFNIAVX512BW-NEXT: orb %dil, %al ; GFNIAVX512BW-NEXT: orb %dil, %al
; GFNIAVX512BW-NEXT: movl %eax, %ecx
; GFNIAVX512BW-NEXT: andb $85, %cl
; GFNIAVX512BW-NEXT: addb %cl, %cl
; GFNIAVX512BW-NEXT: shrb %al
; GFNIAVX512BW-NEXT: andb $85, %al
; GFNIAVX512BW-NEXT: orb %cl, %al
; GFNIAVX512BW-NEXT: retq ; GFNIAVX512BW-NEXT: retq
%b = call i8 @llvm.bitreverse.i8(i8 %a) %b = call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %b ret i8 %b
} }
define i16 @test_bitreverse_i16(i16 %a) nounwind { define i16 @test_bitreverse_i16(i16 %a) nounwind {
; SSE-LABEL: test_bitreverse_i16: ; SSE-LABEL: test_bitreverse_i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
▲ Show 20 Lines • Show All 3,206 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-ext-logic.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
define <8 x i32> @zext_and_v8i32(<8 x i16> %x, <8 x i16> %y) { define <8 x i32> @zext_and_v8i32(<8 x i16> %x, <8 x i16> %y) {
; SSE2-LABEL: zext_and_v8i32: ; SSE2-LABEL: zext_and_v8i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: zext_and_v8i32: ; AVX2-LABEL: zext_and_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%xz = zext <8 x i16> %x to <8 x i32> %xz = zext <8 x i16> %x to <8 x i32>
%yz = zext <8 x i16> %y to <8 x i32> %yz = zext <8 x i16> %y to <8 x i32>
%r = and <8 x i32> %xz, %yz %r = and <8 x i32> %xz, %yz
ret <8 x i32> %r ret <8 x i32> %r
} }
define <8 x i32> @zext_or_v8i32(<8 x i16> %x, <8 x i16> %y) { define <8 x i32> @zext_or_v8i32(<8 x i16> %x, <8 x i16> %y) {
; SSE2-LABEL: zext_or_v8i32: ; SSE2-LABEL: zext_or_v8i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: por %xmm0, %xmm1
; SSE2-NEXT: por %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: zext_or_v8i32: ; AVX2-LABEL: zext_or_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%xz = zext <8 x i16> %x to <8 x i32> %xz = zext <8 x i16> %x to <8 x i32>
%yz = zext <8 x i16> %y to <8 x i32> %yz = zext <8 x i16> %y to <8 x i32>
%r = or <8 x i32> %xz, %yz %r = or <8 x i32> %xz, %yz
ret <8 x i32> %r ret <8 x i32> %r
} }
define <8 x i32> @zext_xor_v8i32(<8 x i16> %x, <8 x i16> %y) { define <8 x i32> @zext_xor_v8i32(<8 x i16> %x, <8 x i16> %y) {
; SSE2-LABEL: zext_xor_v8i32: ; SSE2-LABEL: zext_xor_v8i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: zext_xor_v8i32: ; AVX2-LABEL: zext_xor_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%xz = zext <8 x i16> %x to <8 x i32> %xz = zext <8 x i16> %x to <8 x i32>
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Lines; AVX2-NEXT: retq
%yz = zext <8 x i1> %y to <8 x i32> %yz = zext <8 x i1> %y to <8 x i32>
%r = and <8 x i32> %xz, %yz %r = and <8 x i32> %xz, %yz
ret <8 x i32> %r ret <8 x i32> %r
} }
define <8 x i32> @bool_zext_or(<8 x i1> %x, <8 x i1> %y) { define <8 x i32> @bool_zext_or(<8 x i1> %x, <8 x i1> %y) {
; SSE2-LABEL: bool_zext_or: ; SSE2-LABEL: bool_zext_or:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: por %xmm0, %xmm1
; SSE2-NEXT: por %xmm1, %xmm2 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: bool_zext_or: ; AVX2-LABEL: bool_zext_or:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%xz = zext <8 x i1> %x to <8 x i32> %xz = zext <8 x i1> %x to <8 x i32>
%yz = zext <8 x i1> %y to <8 x i32> %yz = zext <8 x i1> %y to <8 x i32>
%r = or <8 x i32> %xz, %yz %r = or <8 x i32> %xz, %yz
ret <8 x i32> %r ret <8 x i32> %r
} }
define <8 x i32> @bool_zext_xor(<8 x i1> %x, <8 x i1> %y) { define <8 x i32> @bool_zext_xor(<8 x i1> %x, <8 x i1> %y) {
; SSE2-LABEL: bool_zext_xor: ; SSE2-LABEL: bool_zext_xor:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm2 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: bool_zext_xor: ; AVX2-LABEL: bool_zext_xor:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: retq ; AVX2-NEXT: retq
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-fshl-128.ll

Show First 20 Lines • Show All 721 Lines • ▼ Show 20 Lines; X86-SSE2-NEXT: retl
%res = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt) %res = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt)
ret <8 x i16> %res ret <8 x i16> %res
} }
define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) nounwind { define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) nounwind {
; SSE2-LABEL: var_funnnel_v16i8: ; SSE2-LABEL: var_funnnel_v16i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: psrlw $1, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE2-NEXT: pand %xmm6, %xmm1 ; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; SSE2-NEXT: movdqa %xmm2, %xmm7 ; SSE2-NEXT: movdqa %xmm2, %xmm7
; SSE2-NEXT: pandn %xmm8, %xmm7 ; SSE2-NEXT: pandn %xmm8, %xmm7
; SSE2-NEXT: psllw $5, %xmm7 ; SSE2-NEXT: psllw $5, %xmm7
; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm6, %xmm6
; SSE2-NEXT: pcmpgtb %xmm7, %xmm4 ; SSE2-NEXT: pcmpgtb %xmm7, %xmm6
; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: movdqa %xmm6, %xmm4
; SSE2-NEXT: pandn %xmm1, %xmm5 ; SSE2-NEXT: pandn %xmm1, %xmm4
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm6
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: paddb %xmm7, %xmm7 ; SSE2-NEXT: paddb %xmm7, %xmm7
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm7, %xmm4 ; SSE2-NEXT: pcmpgtb %xmm7, %xmm1
; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pandn %xmm1, %xmm5 ; SSE2-NEXT: pandn %xmm6, %xmm4
; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm6
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm6
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: paddb %xmm7, %xmm7 ; SSE2-NEXT: paddb %xmm7, %xmm7
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm7, %xmm4 ; SSE2-NEXT: pcmpgtb %xmm7, %xmm1
; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pandn %xmm1, %xmm5 ; SSE2-NEXT: pandn %xmm6, %xmm4
; SSE2-NEXT: psrlw $1, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm6
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm1
; SSE2-NEXT: por %xmm5, %xmm4 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: pand %xmm8, %xmm2 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: psllw $5, %xmm2 ; SSE2-NEXT: psllw $5, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5 ; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psllw $4, %xmm0 ; SSE2-NEXT: psllw $4, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm4
; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm0, %xmm5 ; SSE2-NEXT: pandn %xmm0, %xmm5
; SSE2-NEXT: psllw $2, %xmm0 ; SSE2-NEXT: psllw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: por %xmm5, %xmm0 ; SSE2-NEXT: por %xmm5, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: paddb %xmm2, %xmm2
; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm1 ; SSE2-NEXT: movdqa %xmm3, %xmm2
; SSE2-NEXT: pandn %xmm0, %xmm1 ; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: paddb %xmm0, %xmm0 ; SSE2-NEXT: paddb %xmm0, %xmm0
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_funnnel_v16i8: ; SSE41-LABEL: var_funnnel_v16i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm0, %xmm4
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: movdqa %xmm3, %xmm0 ; SSE41-NEXT: pandn %xmm3, %xmm0
; SSE41-NEXT: pandn %xmm4, %xmm0
; SSE41-NEXT: psllw $5, %xmm0 ; SSE41-NEXT: psllw $5, %xmm0
; SSE41-NEXT: psrlw $1, %xmm1 ; SSE41-NEXT: psrlw $1, %xmm1
; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; SSE41-NEXT: pand %xmm5, %xmm1 ; SSE41-NEXT: pand %xmm5, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm6 ; SSE41-NEXT: movdqa %xmm1, %xmm6
; SSE41-NEXT: psrlw $4, %xmm6 ; SSE41-NEXT: psrlw $4, %xmm6
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
; SSE41-NEXT: pblendvb %xmm0, %xmm6, %xmm1 ; SSE41-NEXT: pblendvb %xmm0, %xmm6, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm6 ; SSE41-NEXT: movdqa %xmm1, %xmm6
; SSE41-NEXT: psrlw $2, %xmm6 ; SSE41-NEXT: psrlw $2, %xmm6
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
; SSE41-NEXT: paddb %xmm0, %xmm0 ; SSE41-NEXT: paddb %xmm0, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm6, %xmm1 ; SSE41-NEXT: pblendvb %xmm0, %xmm6, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm6 ; SSE41-NEXT: movdqa %xmm1, %xmm6
; SSE41-NEXT: psrlw $1, %xmm6 ; SSE41-NEXT: psrlw $1, %xmm6
; SSE41-NEXT: pand %xmm5, %xmm6 ; SSE41-NEXT: pand %xmm5, %xmm6
; SSE41-NEXT: paddb %xmm0, %xmm0 ; SSE41-NEXT: paddb %xmm0, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm6, %xmm1 ; SSE41-NEXT: pblendvb %xmm0, %xmm6, %xmm1
; SSE41-NEXT: pand %xmm4, %xmm3 ; SSE41-NEXT: pand %xmm2, %xmm3
; SSE41-NEXT: psllw $5, %xmm3 ; SSE41-NEXT: psllw $5, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm4 ; SSE41-NEXT: movdqa %xmm3, %xmm2
; SSE41-NEXT: paddb %xmm3, %xmm4 ; SSE41-NEXT: paddb %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm5 ; SSE41-NEXT: movdqa %xmm4, %xmm5
; SSE41-NEXT: psllw $4, %xmm5 ; SSE41-NEXT: psllw $4, %xmm5
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
; SSE41-NEXT: movdqa %xmm3, %xmm0 ; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm5, %xmm2 ; SSE41-NEXT: pblendvb %xmm0, %xmm5, %xmm4
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm4, %xmm3
; SSE41-NEXT: psllw $2, %xmm3 ; SSE41-NEXT: psllw $2, %xmm3
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE41-NEXT: movdqa %xmm4, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: paddb %xmm2, %xmm3
; SSE41-NEXT: paddb %xmm4, %xmm4
; SSE41-NEXT: movdqa %xmm4, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: por %xmm1, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm4
; SSE41-NEXT: movdqa %xmm4, %xmm3
; SSE41-NEXT: paddb %xmm4, %xmm3
; SSE41-NEXT: paddb %xmm2, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm4
; SSE41-NEXT: por %xmm1, %xmm4
; SSE41-NEXT: movdqa %xmm4, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: var_funnnel_v16i8: ; AVX-LABEL: var_funnnel_v16i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; AVX-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; AVX-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX-NEXT: vpsllw $5, %xmm4, %xmm4 ; AVX-NEXT: vpsllw $5, %xmm4, %xmm4
; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 ; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
; XOP-NEXT: vpand %xmm3, %xmm2, %xmm2 ; XOP-NEXT: vpand %xmm3, %xmm2, %xmm2
; XOP-NEXT: vpshlb %xmm2, %xmm0, %xmm0 ; XOP-NEXT: vpshlb %xmm2, %xmm0, %xmm0
; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v16i8: ; X86-SSE2-LABEL: var_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]
; X86-SSE2-NEXT: pand %xmm5, %xmm1 ; X86-SSE2-NEXT: pand %xmm4, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; X86-SSE2-NEXT: movdqa %xmm2, %xmm6 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm6
; X86-SSE2-NEXT: pandn %xmm4, %xmm6 ; X86-SSE2-NEXT: pandn %xmm3, %xmm6
; X86-SSE2-NEXT: psllw $5, %xmm6 ; X86-SSE2-NEXT: psllw $5, %xmm6
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm5, %xmm5
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm5
; X86-SSE2-NEXT: movdqa %xmm3, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm5, %xmm7
; X86-SSE2-NEXT: pandn %xmm1, %xmm7 ; X86-SSE2-NEXT: pandn %xmm1, %xmm7
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand %xmm3, %xmm1 ; X86-SSE2-NEXT: pand %xmm1, %xmm5
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm5
; X86-SSE2-NEXT: por %xmm7, %xmm1 ; X86-SSE2-NEXT: por %xmm7, %xmm5
; X86-SSE2-NEXT: paddb %xmm6, %xmm6 ; X86-SSE2-NEXT: paddb %xmm6, %xmm6
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
; X86-SSE2-NEXT: movdqa %xmm3, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm7
; X86-SSE2-NEXT: pandn %xmm1, %xmm7 ; X86-SSE2-NEXT: pandn %xmm5, %xmm7
; X86-SSE2-NEXT: psrlw $2, %xmm1 ; X86-SSE2-NEXT: psrlw $2, %xmm5
; X86-SSE2-NEXT: pand %xmm3, %xmm1 ; X86-SSE2-NEXT: pand %xmm1, %xmm5
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm5
; X86-SSE2-NEXT: por %xmm7, %xmm1 ; X86-SSE2-NEXT: por %xmm7, %xmm5
; X86-SSE2-NEXT: paddb %xmm6, %xmm6 ; X86-SSE2-NEXT: paddb %xmm6, %xmm6
; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm6
; X86-SSE2-NEXT: pand %xmm5, %xmm3
; X86-SSE2-NEXT: pandn %xmm1, %xmm6
; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand %xmm1, %xmm3
; X86-SSE2-NEXT: por %xmm6, %xmm3
; X86-SSE2-NEXT: pand %xmm4, %xmm2
; X86-SSE2-NEXT: psllw $5, %xmm2
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm6
; X86-SSE2-NEXT: pand %xmm4, %xmm1
; X86-SSE2-NEXT: pandn %xmm5, %xmm6
; X86-SSE2-NEXT: psrlw $1, %xmm5
; X86-SSE2-NEXT: pand %xmm5, %xmm1
; X86-SSE2-NEXT: por %xmm6, %xmm1
; X86-SSE2-NEXT: pand %xmm3, %xmm2
; X86-SSE2-NEXT: psllw $5, %xmm2
; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: pandn %xmm0, %xmm4 ; X86-SSE2-NEXT: pandn %xmm0, %xmm4
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm3, %xmm0
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: paddb %xmm2, %xmm2 ; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm1, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: pandn %xmm0, %xmm4 ; X86-SSE2-NEXT: pandn %xmm0, %xmm4
; X86-SSE2-NEXT: psllw $2, %xmm0 ; X86-SSE2-NEXT: psllw $2, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm3, %xmm0
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: paddb %xmm2, %xmm2 ; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm1, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm2
; X86-SSE2-NEXT: pandn %xmm0, %xmm2 ; X86-SSE2-NEXT: pandn %xmm0, %xmm2
; X86-SSE2-NEXT: por %xmm3, %xmm2 ; X86-SSE2-NEXT: por %xmm1, %xmm2
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm3, %xmm0
; X86-SSE2-NEXT: por %xmm2, %xmm0 ; X86-SSE2-NEXT: por %xmm2, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) %res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt)
ret <16 x i8> %res ret <16 x i8> %res
} }
; ;
; Uniform Variable Shifts ; Uniform Variable Shifts
▲ Show 20 Lines • Show All 1,785 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-fshr-128.ll

Show First 20 Lines • Show All 420 Lines • ▼ Show 20 Lines
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %amt) %res = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %amt)
ret <4 x i32> %res ret <4 x i32> %res
} }
define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt) nounwind { define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt) nounwind {
; SSE2-LABEL: var_funnnel_v8i16: ; SSE2-LABEL: var_funnnel_v8i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: psllw $12, %xmm3 ; SSE2-NEXT: psllw $12, %xmm4
; SSE2-NEXT: movdqa %xmm3, %xmm4 ; SSE2-NEXT: movdqa %xmm4, %xmm3
; SSE2-NEXT: psraw $15, %xmm4 ; SSE2-NEXT: psraw $15, %xmm3
; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: movdqa %xmm3, %xmm5
; SSE2-NEXT: pandn %xmm1, %xmm5 ; SSE2-NEXT: pandn %xmm1, %xmm5
; SSE2-NEXT: psrlw $8, %xmm1 ; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: paddw %xmm3, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: psraw $15, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm1, %xmm5
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: paddw %xmm3, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: psraw $15, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm1, %xmm5
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: por %xmm5, %xmm1
; SSE2-NEXT: paddw %xmm3, %xmm3
; SSE2-NEXT: psraw $15, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pandn %xmm1, %xmm4
; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: por %xmm5, %xmm3
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: psraw $15, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: psrlw $4, %xmm3
; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: por %xmm5, %xmm3
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: psraw $15, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: psrlw $2, %xmm3
; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: por %xmm5, %xmm3
; SSE2-NEXT: paddw %xmm4, %xmm4
; SSE2-NEXT: psraw $15, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: pandn %xmm3, %xmm1
; SSE2-NEXT: psrlw $1, %xmm3
; SSE2-NEXT: pand %xmm4, %xmm3
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm1 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4,4,5,5,6,6,7,7]
; SSE2-NEXT: pslld $23, %xmm1 ; SSE2-NEXT: pslld $23, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1065353216,1065353216,1065353216,1065353216] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1065353216,1065353216,1065353216,1065353216]
; SSE2-NEXT: paddd %xmm5, %xmm1 ; SSE2-NEXT: paddd %xmm5, %xmm4
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; SSE2-NEXT: cvttps2dq %xmm4, %xmm4
; SSE2-NEXT: pslld $16, %xmm1 ; SSE2-NEXT: pslld $16, %xmm4
; SSE2-NEXT: psrad $16, %xmm1 ; SSE2-NEXT: psrad $16, %xmm4
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
; SSE2-NEXT: pslld $23, %xmm2 ; SSE2-NEXT: pslld $23, %xmm2
; SSE2-NEXT: paddd %xmm5, %xmm2 ; SSE2-NEXT: paddd %xmm5, %xmm2
; SSE2-NEXT: cvttps2dq %xmm2, %xmm2 ; SSE2-NEXT: cvttps2dq %xmm2, %xmm2
; SSE2-NEXT: pslld $16, %xmm2 ; SSE2-NEXT: pslld $16, %xmm2
; SSE2-NEXT: psrad $16, %xmm2 ; SSE2-NEXT: psrad $16, %xmm2
; SSE2-NEXT: packssdw %xmm1, %xmm2 ; SSE2-NEXT: packssdw %xmm4, %xmm2
; SSE2-NEXT: psllw $1, %xmm0 ; SSE2-NEXT: psllw $1, %xmm0
; SSE2-NEXT: pmullw %xmm2, %xmm0 ; SSE2-NEXT: pmullw %xmm2, %xmm0
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_funnnel_v8i16: ; SSE41-LABEL: var_funnnel_v8i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm3 ; SSE41-NEXT: movdqa %xmm0, %xmm3
; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [15,15,15,15,15,15,15,15] ; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [15,15,15,15,15,15,15,15]
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: movdqa %xmm2, %xmm0
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
; XOP-NEXT: vpsubw %xmm2, %xmm3, %xmm2 ; XOP-NEXT: vpsubw %xmm2, %xmm3, %xmm2
; XOP-NEXT: vpshlw %xmm2, %xmm1, %xmm1 ; XOP-NEXT: vpshlw %xmm2, %xmm1, %xmm1
; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v8i16: ; X86-SSE2-LABEL: var_funnnel_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm2, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: psllw $12, %xmm3 ; X86-SSE2-NEXT: psllw $12, %xmm4
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm4, %xmm3
; X86-SSE2-NEXT: psraw $15, %xmm4 ; X86-SSE2-NEXT: psraw $15, %xmm3
; X86-SSE2-NEXT: movdqa %xmm4, %xmm5 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm5
; X86-SSE2-NEXT: pandn %xmm1, %xmm5 ; X86-SSE2-NEXT: pandn %xmm1, %xmm5
; X86-SSE2-NEXT: psrlw $8, %xmm1 ; X86-SSE2-NEXT: psrlw $8, %xmm1
; X86-SSE2-NEXT: pand %xmm4, %xmm1
; X86-SSE2-NEXT: por %xmm5, %xmm1
; X86-SSE2-NEXT: paddw %xmm3, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: psraw $15, %xmm4
; X86-SSE2-NEXT: movdqa %xmm4, %xmm5
; X86-SSE2-NEXT: pandn %xmm1, %xmm5
; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand %xmm4, %xmm1
; X86-SSE2-NEXT: por %xmm5, %xmm1
; X86-SSE2-NEXT: paddw %xmm3, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: psraw $15, %xmm4
; X86-SSE2-NEXT: movdqa %xmm4, %xmm5
; X86-SSE2-NEXT: pandn %xmm1, %xmm5
; X86-SSE2-NEXT: psrlw $2, %xmm1
; X86-SSE2-NEXT: pand %xmm4, %xmm1
; X86-SSE2-NEXT: por %xmm5, %xmm1
; X86-SSE2-NEXT: paddw %xmm3, %xmm3
; X86-SSE2-NEXT: psraw $15, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: pandn %xmm1, %xmm4
; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand %xmm1, %xmm3 ; X86-SSE2-NEXT: pand %xmm1, %xmm3
; X86-SSE2-NEXT: por %xmm5, %xmm3
; X86-SSE2-NEXT: paddw %xmm4, %xmm4
; X86-SSE2-NEXT: movdqa %xmm4, %xmm1
; X86-SSE2-NEXT: psraw $15, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm5
; X86-SSE2-NEXT: pandn %xmm3, %xmm5
; X86-SSE2-NEXT: psrlw $4, %xmm3
; X86-SSE2-NEXT: pand %xmm1, %xmm3
; X86-SSE2-NEXT: por %xmm5, %xmm3
; X86-SSE2-NEXT: paddw %xmm4, %xmm4
; X86-SSE2-NEXT: movdqa %xmm4, %xmm1
; X86-SSE2-NEXT: psraw $15, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm5
; X86-SSE2-NEXT: pandn %xmm3, %xmm5
; X86-SSE2-NEXT: psrlw $2, %xmm3
; X86-SSE2-NEXT: pand %xmm1, %xmm3
; X86-SSE2-NEXT: por %xmm5, %xmm3
; X86-SSE2-NEXT: paddw %xmm4, %xmm4
; X86-SSE2-NEXT: psraw $15, %xmm4
; X86-SSE2-NEXT: movdqa %xmm4, %xmm1
; X86-SSE2-NEXT: pandn %xmm3, %xmm1
; X86-SSE2-NEXT: psrlw $1, %xmm3
; X86-SSE2-NEXT: pand %xmm4, %xmm3
; X86-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2 ; X86-SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm4
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1065353216,1065353216,1065353216,1065353216] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1065353216,1065353216,1065353216,1065353216]
; X86-SSE2-NEXT: paddd %xmm5, %xmm1 ; X86-SSE2-NEXT: paddd %xmm5, %xmm4
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm4, %xmm4
; X86-SSE2-NEXT: pslld $16, %xmm1 ; X86-SSE2-NEXT: pslld $16, %xmm4
; X86-SSE2-NEXT: psrad $16, %xmm1 ; X86-SSE2-NEXT: psrad $16, %xmm4
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3] ; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: paddd %xmm5, %xmm2 ; X86-SSE2-NEXT: paddd %xmm5, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm2 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm2
; X86-SSE2-NEXT: pslld $16, %xmm2 ; X86-SSE2-NEXT: pslld $16, %xmm2
; X86-SSE2-NEXT: psrad $16, %xmm2 ; X86-SSE2-NEXT: psrad $16, %xmm2
; X86-SSE2-NEXT: packssdw %xmm1, %xmm2 ; X86-SSE2-NEXT: packssdw %xmm4, %xmm2
; X86-SSE2-NEXT: psllw $1, %xmm0 ; X86-SSE2-NEXT: psllw $1, %xmm0
; X86-SSE2-NEXT: pmullw %xmm2, %xmm0 ; X86-SSE2-NEXT: pmullw %xmm2, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: por %xmm3, %xmm0 ; X86-SSE2-NEXT: por %xmm3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt) %res = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt)
ret <8 x i16> %res ret <8 x i16> %res
} }
define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) nounwind { define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) nounwind {
; SSE2-LABEL: var_funnnel_v16i8: ; SSE2-LABEL: var_funnnel_v16i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
; SSE2-NEXT: movdqa %xmm2, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm6
; SSE2-NEXT: psllw $5, %xmm6 ; SSE2-NEXT: psllw $5, %xmm6
; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm4, %xmm4
; SSE2-NEXT: pcmpgtb %xmm6, %xmm4 ; SSE2-NEXT: pcmpgtb %xmm6, %xmm4
; SSE2-NEXT: movdqa %xmm4, %xmm7 ; SSE2-NEXT: movdqa %xmm4, %xmm7
; SSE2-NEXT: pandn %xmm1, %xmm7 ; SSE2-NEXT: pandn %xmm1, %xmm7
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm7, %xmm1 ; SSE2-NEXT: por %xmm7, %xmm4
; SSE2-NEXT: paddb %xmm6, %xmm6 ; SSE2-NEXT: paddb %xmm6, %xmm6
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm6, %xmm4 ; SSE2-NEXT: pcmpgtb %xmm6, %xmm1
; SSE2-NEXT: movdqa %xmm4, %xmm7 ; SSE2-NEXT: movdqa %xmm1, %xmm7
; SSE2-NEXT: pandn %xmm1, %xmm7 ; SSE2-NEXT: pandn %xmm4, %xmm7
; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm7, %xmm1 ; SSE2-NEXT: por %xmm7, %xmm4
; SSE2-NEXT: paddb %xmm6, %xmm6 ; SSE2-NEXT: paddb %xmm6, %xmm6
; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm6, %xmm4 ; SSE2-NEXT: pcmpgtb %xmm6, %xmm1
; SSE2-NEXT: movdqa %xmm4, %xmm6 ; SSE2-NEXT: movdqa %xmm1, %xmm6
; SSE2-NEXT: pandn %xmm1, %xmm6 ; SSE2-NEXT: pandn %xmm4, %xmm6
; SSE2-NEXT: psrlw $1, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm4
; SSE2-NEXT: pand %xmm1, %xmm4 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
; SSE2-NEXT: por %xmm6, %xmm4 ; SSE2-NEXT: por %xmm6, %xmm4
; SSE2-NEXT: pandn %xmm5, %xmm2 ; SSE2-NEXT: pandn %xmm5, %xmm2
; SSE2-NEXT: psllw $5, %xmm2 ; SSE2-NEXT: psllw $5, %xmm2
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm0 ; SSE2-NEXT: paddb %xmm0, %xmm0
▲ Show 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
; X86-SSE2-NEXT: pand %xmm5, %xmm6 ; X86-SSE2-NEXT: pand %xmm5, %xmm6
; X86-SSE2-NEXT: psllw $5, %xmm6 ; X86-SSE2-NEXT: psllw $5, %xmm6
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pxor %xmm4, %xmm4 ; X86-SSE2-NEXT: pxor %xmm4, %xmm4
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm4 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm4
; X86-SSE2-NEXT: movdqa %xmm4, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm4, %xmm7
; X86-SSE2-NEXT: pandn %xmm1, %xmm7 ; X86-SSE2-NEXT: pandn %xmm1, %xmm7
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand %xmm4, %xmm1 ; X86-SSE2-NEXT: pand %xmm1, %xmm4
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm7, %xmm1 ; X86-SSE2-NEXT: por %xmm7, %xmm4
; X86-SSE2-NEXT: paddb %xmm6, %xmm6 ; X86-SSE2-NEXT: paddb %xmm6, %xmm6
; X86-SSE2-NEXT: pxor %xmm4, %xmm4 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm4 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
; X86-SSE2-NEXT: movdqa %xmm4, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm7
; X86-SSE2-NEXT: pandn %xmm1, %xmm7 ; X86-SSE2-NEXT: pandn %xmm4, %xmm7
; X86-SSE2-NEXT: psrlw $2, %xmm1 ; X86-SSE2-NEXT: psrlw $2, %xmm4
; X86-SSE2-NEXT: pand %xmm4, %xmm1 ; X86-SSE2-NEXT: pand %xmm1, %xmm4
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm7, %xmm1 ; X86-SSE2-NEXT: por %xmm7, %xmm4
; X86-SSE2-NEXT: paddb %xmm6, %xmm6 ; X86-SSE2-NEXT: paddb %xmm6, %xmm6
; X86-SSE2-NEXT: pxor %xmm4, %xmm4 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm4 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm1
; X86-SSE2-NEXT: movdqa %xmm4, %xmm6 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm6
; X86-SSE2-NEXT: pandn %xmm1, %xmm6 ; X86-SSE2-NEXT: pandn %xmm4, %xmm6
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm4
; X86-SSE2-NEXT: pand %xmm1, %xmm4 ; X86-SSE2-NEXT: pand %xmm1, %xmm4
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm6, %xmm4 ; X86-SSE2-NEXT: por %xmm6, %xmm4
; X86-SSE2-NEXT: pandn %xmm5, %xmm2 ; X86-SSE2-NEXT: pandn %xmm5, %xmm2
; X86-SSE2-NEXT: psllw $5, %xmm2 ; X86-SSE2-NEXT: psllw $5, %xmm2
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
▲ Show 20 Lines • Show All 1,544 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = sdiv <2 x i64> %a, <i64 7, i64 7> %res = sdiv <2 x i64> %a, <i64 7, i64 7>
ret <2 x i64> %res ret <2 x i64> %res
} }
define <4 x i32> @test_div7_4i32(<4 x i32> %a) nounwind { define <4 x i32> @test_div7_4i32(<4 x i32> %a) nounwind {
; SSE2-LABEL: test_div7_4i32: ; SSE2-LABEL: test_div7_4i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2454267027,2454267027,2454267027,2454267027]
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pmuludq %xmm2, %xmm1 ; SSE2-NEXT: pmuludq %xmm1, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm2, %xmm3 ; SSE2-NEXT: pmuludq %xmm1, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: pcmpgtd %xmm0, %xmm3 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm3
; SSE2-NEXT: pand %xmm2, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: paddd %xmm0, %xmm3 ; SSE2-NEXT: paddd %xmm0, %xmm3
; SSE2-NEXT: psubd %xmm3, %xmm1 ; SSE2-NEXT: psubd %xmm3, %xmm2
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: paddd %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $31, %xmm0 ; SSE2-NEXT: psrld $31, %xmm1
; SSE2-NEXT: psrad $2, %xmm1 ; SSE2-NEXT: psrad $2, %xmm0
; SSE2-NEXT: paddd %xmm0, %xmm1 ; SSE2-NEXT: paddd %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_div7_4i32: ; SSE41-LABEL: test_div7_4i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2454267027,2454267027,2454267027,2454267027] ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
; SSE41-NEXT: pmuldq %xmm1, %xmm2 ; SSE41-NEXT: pmuldq %xmm2, %xmm1
; SSE41-NEXT: pmuldq %xmm0, %xmm1 ; SSE41-NEXT: pmuldq %xmm0, %xmm2
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; SSE41-NEXT: paddd %xmm0, %xmm1 ; SSE41-NEXT: paddd %xmm2, %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrld $31, %xmm0 ; SSE41-NEXT: psrld $31, %xmm1
; SSE41-NEXT: psrad $2, %xmm1 ; SSE41-NEXT: psrad $2, %xmm0
; SSE41-NEXT: paddd %xmm0, %xmm1 ; SSE41-NEXT: paddd %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: test_div7_4i32: ; AVX1-LABEL: test_div7_4i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027]
; AVX1-NEXT: vpmuldq %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpmuldq %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpmuldq %xmm2, %xmm0, %xmm2 ; AVX1-NEXT: vpmuldq %xmm2, %xmm0, %xmm2
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> %res = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %res ret <8 x i16> %res
} }
define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind { define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
; SSE-LABEL: test_div7_16i8: ; SSE-LABEL: test_div7_16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: pxor %xmm1, %xmm1
; SSE-NEXT: pxor %xmm0, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm2 ; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [37632,37632,37632,37632,37632,37632,37632,37632] ; SSE-NEXT: movdqa {{.*#+}} xmm3 = [37632,37632,37632,37632,37632,37632,37632,37632]
; SSE-NEXT: pmulhw %xmm3, %xmm2 ; SSE-NEXT: pmulhw %xmm3, %xmm2
; SSE-NEXT: psrlw $8, %xmm2 ; SSE-NEXT: psrlw $8, %xmm2
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; SSE-NEXT: pmulhw %xmm3, %xmm0 ; SSE-NEXT: pmulhw %xmm3, %xmm1
; SSE-NEXT: psrlw $8, %xmm0 ; SSE-NEXT: psrlw $8, %xmm1
; SSE-NEXT: packuswb %xmm2, %xmm0 ; SSE-NEXT: packuswb %xmm2, %xmm1
; SSE-NEXT: paddb %xmm1, %xmm0 ; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: psrlw $2, %xmm1 ; SSE-NEXT: psrlw $2, %xmm1
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32] ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
; SSE-NEXT: pxor %xmm2, %xmm1 ; SSE-NEXT: pxor %xmm2, %xmm1
; SSE-NEXT: psrlw $7, %xmm0 ; SSE-NEXT: psrlw $7, %xmm0
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
▲ Show 20 Lines • Show All 931 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-lzcnt-128.ll

Show All 12 Lines
; Just one 32-bit run to make sure we do reasonable things for i64 lzcnt. ; Just one 32-bit run to make sure we do reasonable things for i64 lzcnt.
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32-SSE ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32-SSE
define <2 x i64> @testv2i64(<2 x i64> %in) nounwind { define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; SSE2-LABEL: testv2i64: ; SSE2-LABEL: testv2i64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $1, %xmm1 ; SSE2-NEXT: psrlq $1, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $2, %xmm0 ; SSE2-NEXT: psrlq $2, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $4, %xmm1 ; SSE2-NEXT: psrlq $4, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $8, %xmm0 ; SSE2-NEXT: psrlq $8, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $16, %xmm1 ; SSE2-NEXT: psrlq $16, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $32, %xmm0 ; SSE2-NEXT: psrlq $32, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: paddb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv2i64: ; SSE3-LABEL: testv2i64:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $1, %xmm1 ; SSE3-NEXT: psrlq $1, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $2, %xmm0 ; SSE3-NEXT: psrlq $2, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $4, %xmm1 ; SSE3-NEXT: psrlq $4, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $8, %xmm0 ; SSE3-NEXT: psrlq $8, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $16, %xmm1 ; SSE3-NEXT: psrlq $16, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $32, %xmm0 ; SSE3-NEXT: psrlq $32, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pand %xmm0, %xmm2
; SSE3-NEXT: psrlw $2, %xmm1
; SSE3-NEXT: pand %xmm0, %xmm1
; SSE3-NEXT: paddb %xmm2, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm2, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv2i64: ; SSSE3-LABEL: testv2i64:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSSE3-NEXT: movdqa %xmm2, %xmm3 ; SSSE3-NEXT: movdqa %xmm2, %xmm3
; SSSE3-NEXT: pshufb %xmm0, %xmm3 ; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1 ; SSSE3-NEXT: movdqa %xmm0, %xmm1
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines; X32-SSE-NEXT: retl
ret <2 x i64> %out ret <2 x i64> %out
} }
define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind { define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; SSE2-LABEL: testv2i64u: ; SSE2-LABEL: testv2i64u:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $1, %xmm1 ; SSE2-NEXT: psrlq $1, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $2, %xmm0 ; SSE2-NEXT: psrlq $2, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $4, %xmm1 ; SSE2-NEXT: psrlq $4, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $8, %xmm0 ; SSE2-NEXT: psrlq $8, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $16, %xmm1 ; SSE2-NEXT: psrlq $16, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlq $32, %xmm0 ; SSE2-NEXT: psrlq $32, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psubb %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: paddb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: psadbw %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv2i64u: ; SSE3-LABEL: testv2i64u:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $1, %xmm1 ; SSE3-NEXT: psrlq $1, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $2, %xmm0 ; SSE3-NEXT: psrlq $2, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $4, %xmm1 ; SSE3-NEXT: psrlq $4, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $8, %xmm0 ; SSE3-NEXT: psrlq $8, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $16, %xmm1 ; SSE3-NEXT: psrlq $16, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlq $32, %xmm0 ; SSE3-NEXT: psrlq $32, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: psubb %xmm0, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: pand %xmm0, %xmm2
; SSE3-NEXT: psrlw $2, %xmm1
; SSE3-NEXT: pand %xmm0, %xmm1
; SSE3-NEXT: paddb %xmm2, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: psadbw %xmm2, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv2i64u: ; SSSE3-LABEL: testv2i64u:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSSE3-NEXT: movdqa %xmm2, %xmm3 ; SSSE3-NEXT: movdqa %xmm2, %xmm3
; SSSE3-NEXT: pshufb %xmm0, %xmm3 ; SSSE3-NEXT: pshufb %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1 ; SSSE3-NEXT: movdqa %xmm0, %xmm1
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines; X32-SSE-NEXT: retl
ret <2 x i64> %out ret <2 x i64> %out
} }
define <4 x i32> @testv4i32(<4 x i32> %in) nounwind { define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
; SSE2-LABEL: testv4i32: ; SSE2-LABEL: testv4i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $1, %xmm1 ; SSE2-NEXT: psrld $1, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $2, %xmm0 ; SSE2-NEXT: psrld $2, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $4, %xmm1 ; SSE2-NEXT: psrld $4, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $8, %xmm0 ; SSE2-NEXT: psrld $8, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $16, %xmm1 ; SSE2-NEXT: psrld $16, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm0, %xmm2 ; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm2, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm2 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm1, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm1, %xmm0 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv4i32: ; SSE3-LABEL: testv4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $1, %xmm1 ; SSE3-NEXT: psrld $1, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $2, %xmm0 ; SSE3-NEXT: psrld $2, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $4, %xmm1 ; SSE3-NEXT: psrld $4, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $8, %xmm0 ; SSE3-NEXT: psrld $8, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $16, %xmm1 ; SSE3-NEXT: psrld $16, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm1, %xmm2 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm2, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm0, %xmm2 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm2, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm0, %xmm1 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm2 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm0, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psrlw $4, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm1, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm1, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm1, %xmm0 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm0 ; SSE3-NEXT: packuswb %xmm2, %xmm0
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines; X32-SSE-NEXT: retl
ret <4 x i32> %out ret <4 x i32> %out
} }
define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind { define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
; SSE2-LABEL: testv4i32u: ; SSE2-LABEL: testv4i32u:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $1, %xmm1 ; SSE2-NEXT: psrld $1, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $2, %xmm0 ; SSE2-NEXT: psrld $2, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $4, %xmm1 ; SSE2-NEXT: psrld $4, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $8, %xmm0 ; SSE2-NEXT: psrld $8, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $16, %xmm1 ; SSE2-NEXT: psrld $16, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm0, %xmm2 ; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm2, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm2 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm1, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm1, %xmm0 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv4i32u: ; SSE3-LABEL: testv4i32u:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $1, %xmm1 ; SSE3-NEXT: psrld $1, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $2, %xmm0 ; SSE3-NEXT: psrld $2, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $4, %xmm1 ; SSE3-NEXT: psrld $4, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $8, %xmm0 ; SSE3-NEXT: psrld $8, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrld $16, %xmm1 ; SSE3-NEXT: psrld $16, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm1, %xmm2 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm2, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm0, %xmm2 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm2, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm0, %xmm1 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm2 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm0, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psrlw $4, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm1, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm1, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm1, %xmm0 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm0 ; SSE3-NEXT: packuswb %xmm2, %xmm0
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines; X32-SSE-NEXT: retl
ret <4 x i32> %out ret <4 x i32> %out
} }
define <8 x i16> @testv8i16(<8 x i16> %in) nounwind { define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
; SSE2-LABEL: testv8i16: ; SSE2-LABEL: testv8i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm0, %xmm1 ; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv8i16: ; SSE3-LABEL: testv8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm0, %xmm1 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm0, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm1 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm0, %xmm1 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv8i16: ; SSSE3-LABEL: testv8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pshufb %xmm0, %xmm2 ; SSSE3-NEXT: pshufb %xmm0, %xmm2
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines; X32-SSE-NEXT: retl
ret <8 x i16> %out ret <8 x i16> %out
} }
define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind { define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
; SSE2-LABEL: testv8i16u: ; SSE2-LABEL: testv8i16u:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm0, %xmm1 ; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrlw $4, %xmm2
; SSE2-NEXT: paddb %xmm1, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0
; SSE2-NEXT: psllw $8, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv8i16u: ; SSE3-LABEL: testv8i16u:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm0, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm0, %xmm1 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm0, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm1 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm0, %xmm1 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2
; SSE3-NEXT: psrlw $4, %xmm2
; SSE3-NEXT: paddb %xmm1, %xmm2
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE3-NEXT: movdqa %xmm2, %xmm0
; SSE3-NEXT: psllw $8, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv8i16u: ; SSSE3-LABEL: testv8i16u:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pshufb %xmm0, %xmm2 ; SSSE3-NEXT: pshufb %xmm0, %xmm2
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
} }
define <16 x i8> @testv16i8(<16 x i8> %in) nounwind { define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
; SSE2-LABEL: testv16i8: ; SSE2-LABEL: testv16i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm3, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm3 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm0, %xmm3 ; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm3, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psrlw $2, %xmm3 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: paddb %xmm3, %xmm0 ; SSE2-NEXT: paddb %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv16i8: ; SSE3-LABEL: testv16i8:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE3-NEXT: pand %xmm2, %xmm1 ; SSE3-NEXT: pand %xmm2, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm3, %xmm3 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm1, %xmm3 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm3, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm0, %xmm3 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm3, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm3
; SSE3-NEXT: pand %xmm0, %xmm1 ; SSE3-NEXT: pand %xmm1, %xmm3
; SSE3-NEXT: psrlw $2, %xmm3 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm0, %xmm3 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm3
; SSE3-NEXT: movdqa %xmm3, %xmm0
; SSE3-NEXT: psrlw $4, %xmm0
; SSE3-NEXT: paddb %xmm3, %xmm0 ; SSE3-NEXT: paddb %xmm3, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand %xmm2, %xmm0 ; SSE3-NEXT: pand %xmm2, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv16i8: ; SSSE3-LABEL: testv16i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pshufb %xmm0, %xmm2 ; SSSE3-NEXT: pshufb %xmm0, %xmm2
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
} }
define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind { define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
; SSE2-LABEL: testv16i8u: ; SSE2-LABEL: testv16i8u:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pand %xmm2, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm3, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: pxor %xmm1, %xmm3 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubb %xmm0, %xmm3 ; SSE2-NEXT: psubb %xmm1, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm3, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm3
; SSE2-NEXT: psrlw $2, %xmm3 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm3, %xmm0
; SSE2-NEXT: psrlw $4, %xmm0
; SSE2-NEXT: paddb %xmm3, %xmm0 ; SSE2-NEXT: paddb %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv16i8u: ; SSE3-LABEL: testv16i8u:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: por %xmm1, %xmm0 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSE3-NEXT: pand %xmm2, %xmm1 ; SSE3-NEXT: pand %xmm2, %xmm1
; SSE3-NEXT: por %xmm0, %xmm1 ; SSE3-NEXT: por %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm3, %xmm3 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: pxor %xmm1, %xmm3 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm3, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm0 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm0, %xmm3 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm3, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm3
; SSE3-NEXT: pand %xmm0, %xmm1 ; SSE3-NEXT: pand %xmm1, %xmm3
; SSE3-NEXT: psrlw $2, %xmm3 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm0, %xmm3 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm1, %xmm3
; SSE3-NEXT: movdqa %xmm3, %xmm0
; SSE3-NEXT: psrlw $4, %xmm0
; SSE3-NEXT: paddb %xmm3, %xmm0 ; SSE3-NEXT: paddb %xmm3, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand %xmm2, %xmm0 ; SSE3-NEXT: pand %xmm2, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv16i8u: ; SSSE3-LABEL: testv16i8u:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pshufb %xmm0, %xmm2 ; SSSE3-NEXT: pshufb %xmm0, %xmm2
▲ Show 20 Lines • Show All 274 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-lzcnt-sub128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1 immarg) declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1 immarg)
define <2 x i32> @illegal_ctlz(<2 x i32> %v1) { define <2 x i32> @illegal_ctlz(<2 x i32> %v1) {
; CHECK-LABEL: illegal_ctlz: ; CHECK-LABEL: illegal_ctlz:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $1, %xmm1 ; CHECK-NEXT: psrld $1, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $2, %xmm0 ; CHECK-NEXT: psrld $2, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $4, %xmm1 ; CHECK-NEXT: psrld $4, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $8, %xmm0 ; CHECK-NEXT: psrld $8, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrld $16, %xmm1 ; CHECK-NEXT: psrld $16, %xmm1
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm1, %xmm2 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: movdqa %xmm2, %xmm0 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $1, %xmm0 ; CHECK-NEXT: psrlw $1, %xmm1
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; CHECK-NEXT: psubb %xmm0, %xmm2 ; CHECK-NEXT: psubb %xmm1, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm2, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pand %xmm0, %xmm1 ; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: psrlw $2, %xmm2 ; CHECK-NEXT: psrlw $2, %xmm0
; CHECK-NEXT: pand %xmm0, %xmm2 ; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: paddb %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: psrlw $4, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm0 ; CHECK-NEXT: paddb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm1 ; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; CHECK-NEXT: psadbw %xmm1, %xmm2 ; CHECK-NEXT: psadbw %xmm1, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: psadbw %xmm1, %xmm0 ; CHECK-NEXT: psadbw %xmm1, %xmm0
; CHECK-NEXT: packuswb %xmm2, %xmm0 ; CHECK-NEXT: packuswb %xmm2, %xmm0
Show All 17 Lines
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pand %xmm1, %xmm2 ; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: psrlw $2, %xmm0 ; CHECK-NEXT: psrlw $2, %xmm0
; CHECK-NEXT: pand %xmm1, %xmm0 ; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: paddb %xmm2, %xmm0 ; CHECK-NEXT: paddb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm0, %xmm1
; CHECK-NEXT: psrlw $4, %xmm1 ; CHECK-NEXT: psrlw $4, %xmm1
; CHECK-NEXT: paddb %xmm0, %xmm1 ; CHECK-NEXT: paddb %xmm1, %xmm0
; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT: pxor %xmm0, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; CHECK-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; CHECK-NEXT: psadbw %xmm0, %xmm2 ; CHECK-NEXT: psadbw %xmm1, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: psadbw %xmm0, %xmm1 ; CHECK-NEXT: psadbw %xmm1, %xmm0
; CHECK-NEXT: packuswb %xmm2, %xmm1 ; CHECK-NEXT: packuswb %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v2 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %v1, i1 true) %v2 = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %v1, i1 true)
ret <2 x i32> %v2 ret <2 x i32> %v2
} }

llvm/test/CodeGen/X86/vector-narrow-binop.ll

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
define <4 x double> @fmul_v2f64(<2 x double> %x, <2 x double> %y) { define <4 x double> @fmul_v2f64(<2 x double> %x, <2 x double> %y) {
; SSE-LABEL: fmul_v2f64: ; SSE-LABEL: fmul_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm1, %xmm2 ; SSE-NEXT: movapd %xmm1, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE-NEXT: mulpd %xmm2, %xmm2 ; SSE-NEXT: mulpd %xmm2, %xmm2
; SSE-NEXT: mulpd %xmm1, %xmm1 ; SSE-NEXT: mulpd %xmm1, %xmm1
; SSE-NEXT: addpd %xmm2, %xmm1 ; SSE-NEXT: addpd %xmm1, %xmm2
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: fmul_v2f64: ; AVX1-LABEL: fmul_v2f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0] ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0]
; AVX1-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; AVX1-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; AVX1-NEXT: vmulpd %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vmulpd %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmulpd %xmm2, %xmm2, %xmm1 ; AVX1-NEXT: vmulpd %xmm2, %xmm2, %xmm1
Show All 29 Lines

llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,663 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_2_v8i16: ; SSE3-LABEL: ugt_2_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_2_v8i16: ; SSSE3-LABEL: ugt_2_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_3_v8i16: ; SSE3-LABEL: ugt_3_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_3_v8i16: ; SSSE3-LABEL: ugt_3_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_4_v8i16: ; SSE3-LABEL: ugt_4_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_4_v8i16: ; SSSE3-LABEL: ugt_4_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_5_v8i16: ; SSE3-LABEL: ugt_5_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_5_v8i16: ; SSSE3-LABEL: ugt_5_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_6_v8i16: ; SSE3-LABEL: ugt_6_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_6_v8i16: ; SSSE3-LABEL: ugt_6_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_7_v8i16: ; SSE3-LABEL: ugt_7_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_7_v8i16: ; SSSE3-LABEL: ugt_7_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_8_v8i16: ; SSE3-LABEL: ugt_8_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_8_v8i16: ; SSSE3-LABEL: ugt_8_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_9_v8i16: ; SSE3-LABEL: ugt_9_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_9_v8i16: ; SSSE3-LABEL: ugt_9_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_10_v8i16: ; SSE3-LABEL: ugt_10_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_10_v8i16: ; SSSE3-LABEL: ugt_10_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_11_v8i16: ; SSE3-LABEL: ugt_11_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_11_v8i16: ; SSSE3-LABEL: ugt_11_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_12_v8i16: ; SSE3-LABEL: ugt_12_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_12_v8i16: ; SSSE3-LABEL: ugt_12_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_13_v8i16: ; SSE3-LABEL: ugt_13_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_13_v8i16: ; SSSE3-LABEL: ugt_13_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_14_v8i16: ; SSE3-LABEL: ugt_14_v8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE3-NEXT: pcmpgtw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_14_v8i16: ; SSSE3-LABEL: ugt_14_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 420 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_2_v4i32: ; SSE3-LABEL: ugt_2_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_2_v4i32: ; SSSE3-LABEL: ugt_2_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_3_v4i32: ; SSE3-LABEL: ugt_3_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_3_v4i32: ; SSSE3-LABEL: ugt_3_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_4_v4i32: ; SSE3-LABEL: ugt_4_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_4_v4i32: ; SSSE3-LABEL: ugt_4_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_5_v4i32: ; SSE3-LABEL: ugt_5_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_5_v4i32: ; SSSE3-LABEL: ugt_5_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_6_v4i32: ; SSE3-LABEL: ugt_6_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_6_v4i32: ; SSSE3-LABEL: ugt_6_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_7_v4i32: ; SSE3-LABEL: ugt_7_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_7_v4i32: ; SSSE3-LABEL: ugt_7_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_8_v4i32: ; SSE3-LABEL: ugt_8_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_8_v4i32: ; SSSE3-LABEL: ugt_8_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_9_v4i32: ; SSE3-LABEL: ugt_9_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_9_v4i32: ; SSSE3-LABEL: ugt_9_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_10_v4i32: ; SSE3-LABEL: ugt_10_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_10_v4i32: ; SSSE3-LABEL: ugt_10_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_11_v4i32: ; SSE3-LABEL: ugt_11_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_11_v4i32: ; SSSE3-LABEL: ugt_11_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_12_v4i32: ; SSE3-LABEL: ugt_12_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_12_v4i32: ; SSSE3-LABEL: ugt_12_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_13_v4i32: ; SSE3-LABEL: ugt_13_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_13_v4i32: ; SSSE3-LABEL: ugt_13_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_14_v4i32: ; SSE3-LABEL: ugt_14_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_14_v4i32: ; SSSE3-LABEL: ugt_14_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_15_v4i32: ; SSE3-LABEL: ugt_15_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_15_v4i32: ; SSSE3-LABEL: ugt_15_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_16_v4i32: ; SSE3-LABEL: ugt_16_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_16_v4i32: ; SSSE3-LABEL: ugt_16_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_17_v4i32: ; SSE3-LABEL: ugt_17_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_17_v4i32: ; SSSE3-LABEL: ugt_17_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_18_v4i32: ; SSE3-LABEL: ugt_18_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_18_v4i32: ; SSSE3-LABEL: ugt_18_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_19_v4i32: ; SSE3-LABEL: ugt_19_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_19_v4i32: ; SSSE3-LABEL: ugt_19_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_20_v4i32: ; SSE3-LABEL: ugt_20_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_20_v4i32: ; SSSE3-LABEL: ugt_20_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_21_v4i32: ; SSE3-LABEL: ugt_21_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_21_v4i32: ; SSSE3-LABEL: ugt_21_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_22_v4i32: ; SSE3-LABEL: ugt_22_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_22_v4i32: ; SSSE3-LABEL: ugt_22_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_23_v4i32: ; SSE3-LABEL: ugt_23_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_23_v4i32: ; SSSE3-LABEL: ugt_23_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_24_v4i32: ; SSE3-LABEL: ugt_24_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_24_v4i32: ; SSSE3-LABEL: ugt_24_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_25_v4i32: ; SSE3-LABEL: ugt_25_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_25_v4i32: ; SSSE3-LABEL: ugt_25_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_26_v4i32: ; SSE3-LABEL: ugt_26_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_26_v4i32: ; SSSE3-LABEL: ugt_26_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_27_v4i32: ; SSE3-LABEL: ugt_27_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_27_v4i32: ; SSSE3-LABEL: ugt_27_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_28_v4i32: ; SSE3-LABEL: ugt_28_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_28_v4i32: ; SSSE3-LABEL: ugt_28_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_29_v4i32: ; SSE3-LABEL: ugt_29_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_29_v4i32: ; SSSE3-LABEL: ugt_29_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_30_v4i32: ; SSE3-LABEL: ugt_30_v4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_30_v4i32: ; SSSE3-LABEL: ugt_30_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 317 Lines • ▼ Show 20 Lines
} }
define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) {
; SSE2-LABEL: ugt_1_v2i64: ; SSE2-LABEL: ugt_1_v2i64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: paddq %xmm1, %xmm2 ; SSE2-NEXT: paddq %xmm1, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpeqd %xmm2, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,3,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,0,3,2]
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ugt_1_v2i64: ; SSE3-LABEL: ugt_1_v2i64:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: paddq %xmm1, %xmm2 ; SSE3-NEXT: paddq %xmm1, %xmm2
; SSE3-NEXT: pand %xmm0, %xmm2 ; SSE3-NEXT: pand %xmm2, %xmm0
; SSE3-NEXT: pxor %xmm3, %xmm3 ; SSE3-NEXT: pxor %xmm2, %xmm2
; SSE3-NEXT: pcmpeqd %xmm2, %xmm3 ; SSE3-NEXT: pcmpeqd %xmm2, %xmm0
; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,3,2] ; SSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,0,3,2]
; SSE3-NEXT: pand %xmm3, %xmm0 ; SSE3-NEXT: pand %xmm2, %xmm0
; SSE3-NEXT: pxor %xmm1, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ugt_1_v2i64: ; SSSE3-LABEL: ugt_1_v2i64:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSSE3-NEXT: movdqa %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: paddq %xmm1, %xmm2 ; SSSE3-NEXT: paddq %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm0, %xmm2 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm3 ; SSSE3-NEXT: pxor %xmm2, %xmm2
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm3 ; SSSE3-NEXT: pcmpeqd %xmm2, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,3,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,0,3,2]
; SSSE3-NEXT: pand %xmm3, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pxor %xmm1, %xmm0 ; SSSE3-NEXT: pxor %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: ugt_1_v2i64: ; SSE41-LABEL: ugt_1_v2i64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: paddq %xmm1, %xmm2 ; SSE41-NEXT: paddq %xmm1, %xmm2
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines; BITALG-NEXT: retq
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ult_2_v2i64(<2 x i64> %0) { define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
; SSE2-LABEL: ult_2_v2i64: ; SSE2-LABEL: ult_2_v2i64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
; SSE2-NEXT: paddq %xmm0, %xmm1 ; SSE2-NEXT: paddq %xmm0, %xmm1
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,0,3,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ult_2_v2i64: ; SSE3-LABEL: ult_2_v2i64:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: paddq %xmm0, %xmm1 ; SSE3-NEXT: paddq %xmm0, %xmm1
; SSE3-NEXT: pand %xmm0, %xmm1 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: pxor %xmm2, %xmm2 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm0
; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,0,3,2] ; SSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; SSE3-NEXT: pand %xmm2, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ult_2_v2i64: ; SSSE3-LABEL: ult_2_v2i64:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSSE3-NEXT: paddq %xmm0, %xmm1 ; SSSE3-NEXT: paddq %xmm0, %xmm1
; SSSE3-NEXT: pand %xmm0, %xmm1 ; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: pxor %xmm2, %xmm2 ; SSSE3-NEXT: pxor %xmm1, %xmm1
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm2 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,0,3,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; SSSE3-NEXT: pand %xmm2, %xmm0 ; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: ult_2_v2i64: ; SSE41-LABEL: ult_2_v2i64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
; SSE41-NEXT: paddq %xmm0, %xmm1 ; SSE41-NEXT: paddq %xmm0, %xmm1
; SSE41-NEXT: pand %xmm1, %xmm0 ; SSE41-NEXT: pand %xmm1, %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
▲ Show 20 Lines • Show All 22,757 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-popcnt-128.ll

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv4i32: ; SSE3-LABEL: testv4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv4i32: ; SSSE3-LABEL: testv4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm3
; SSSE3-NEXT: pand %xmm2, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv8i16: ; SSE3-LABEL: testv8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv8i16: ; SSSE3-LABEL: testv8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; SSSE3-NEXT: movdqa %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
▲ Show 20 Lines • Show All 433 Lines • ▼ Show 20 Lines; BITALG-NEXT: retq
%4 = sext <2 x i1> %3 to <2 x i64> %4 = sext <2 x i1> %3 to <2 x i64>
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <2 x i64> @ne_1_v2i64(<2 x i64> %0) { define <2 x i64> @ne_1_v2i64(<2 x i64> %0) {
; SSE2-LABEL: ne_1_v2i64: ; SSE2-LABEL: ne_1_v2i64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,0,3,2]
; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: paddq %xmm2, %xmm3 ; SSE2-NEXT: paddq %xmm2, %xmm4
; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,0,3,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; SSE2-NEXT: pand %xmm0, %xmm4 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: pcmpeqd %xmm1, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,3,2]
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: ne_1_v2i64: ; SSE3-LABEL: ne_1_v2i64:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: pxor %xmm1, %xmm1 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pcmpeqd %xmm1, %xmm2
; SSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,0,3,2]
; SSE3-NEXT: pand %xmm2, %xmm3
; SSE3-NEXT: pcmpeqd %xmm2, %xmm2 ; SSE3-NEXT: pcmpeqd %xmm2, %xmm2
; SSE3-NEXT: movdqa %xmm0, %xmm3 ; SSE3-NEXT: movdqa %xmm0, %xmm4
; SSE3-NEXT: paddq %xmm2, %xmm3 ; SSE3-NEXT: paddq %xmm2, %xmm4
; SSE3-NEXT: pand %xmm0, %xmm3 ; SSE3-NEXT: pand %xmm4, %xmm0
; SSE3-NEXT: pcmpeqd %xmm1, %xmm0 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm0
; SSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,0,3,2] ; SSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; SSE3-NEXT: pand %xmm0, %xmm4 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: pcmpeqd %xmm1, %xmm3
; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,3,2]
; SSE3-NEXT: pand %xmm3, %xmm0
; SSE3-NEXT: pxor %xmm2, %xmm0 ; SSE3-NEXT: pxor %xmm2, %xmm0
; SSE3-NEXT: por %xmm4, %xmm0 ; SSE3-NEXT: por %xmm3, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: ne_1_v2i64: ; SSSE3-LABEL: ne_1_v2i64:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pxor %xmm1, %xmm1 ; SSSE3-NEXT: pxor %xmm1, %xmm1
; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,0,3,2]
; SSSE3-NEXT: pand %xmm2, %xmm3
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm2 ; SSSE3-NEXT: pcmpeqd %xmm2, %xmm2
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm4
; SSSE3-NEXT: paddq %xmm2, %xmm3 ; SSSE3-NEXT: paddq %xmm2, %xmm4
; SSSE3-NEXT: pand %xmm0, %xmm3 ; SSSE3-NEXT: pand %xmm4, %xmm0
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm0 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,0,3,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; SSSE3-NEXT: pand %xmm0, %xmm4 ; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,3,2]
; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm2, %xmm0
; SSSE3-NEXT: por %xmm4, %xmm0 ; SSSE3-NEXT: por %xmm3, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: ne_1_v2i64: ; SSE41-LABEL: ne_1_v2i64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: pcmpeqq %xmm1, %xmm2 ; SSE41-NEXT: pcmpeqq %xmm1, %xmm2
; SSE41-NEXT: pcmpeqd %xmm3, %xmm3 ; SSE41-NEXT: pcmpeqd %xmm3, %xmm3
▲ Show 20 Lines • Show All 500 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret float %1 ret float %1
} }
define float @test_v4f32_zero(<4 x float> %a0) { define float @test_v4f32_zero(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_zero: ; SSE2-LABEL: test_v4f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_zero: ; SSE41-LABEL: test_v4f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm0, %xmm1 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f32_zero: ; AVX1-SLOW-LABEL: test_v4f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 26 Lines
} }
define float @test_v8f32_zero(<8 x float> %a0) { define float @test_v8f32_zero(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_zero: ; SSE2-LABEL: test_v8f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_zero: ; SSE41-LABEL: test_v8f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm0, %xmm1 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f32_zero: ; AVX1-SLOW-LABEL: test_v8f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 40 Lines
define float @test_v16f32_zero(<16 x float> %a0) { define float @test_v16f32_zero(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_zero: ; SSE2-LABEL: test_v16f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm3, %xmm1 ; SSE2-NEXT: addps %xmm3, %xmm1
; SSE2-NEXT: addps %xmm2, %xmm0 ; SSE2-NEXT: addps %xmm2, %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_zero: ; SSE41-LABEL: test_v16f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm3, %xmm1 ; SSE41-NEXT: addps %xmm3, %xmm1
; SSE41-NEXT: addps %xmm2, %xmm0 ; SSE41-NEXT: addps %xmm2, %xmm0
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm0, %xmm1 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f32_zero: ; AVX1-SLOW-LABEL: test_v16f32_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret float %1 ret float %1
} }
define float @test_v4f32_undef(<4 x float> %a0) { define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_undef: ; SSE2-LABEL: test_v4f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_undef: ; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm0, %xmm1 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v4f32_undef: ; AVX1-SLOW-LABEL: test_v4f32_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX1-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 26 Lines
} }
define float @test_v8f32_undef(<8 x float> %a0) { define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_undef: ; SSE2-LABEL: test_v8f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_undef: ; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm0, %xmm1 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v8f32_undef: ; AVX1-SLOW-LABEL: test_v8f32_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX1-SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 40 Lines
define float @test_v16f32_undef(<16 x float> %a0) { define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_undef: ; SSE2-LABEL: test_v16f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: addps %xmm3, %xmm1 ; SSE2-NEXT: addps %xmm3, %xmm1
; SSE2-NEXT: addps %xmm2, %xmm0 ; SSE2-NEXT: addps %xmm2, %xmm0
; SSE2-NEXT: addps %xmm1, %xmm0 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: addps %xmm0, %xmm1 ; SSE2-NEXT: addps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: addss %xmm1, %xmm0 ; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_undef: ; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: addps %xmm3, %xmm1 ; SSE41-NEXT: addps %xmm3, %xmm1
; SSE41-NEXT: addps %xmm2, %xmm0 ; SSE41-NEXT: addps %xmm2, %xmm0
; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: addps %xmm0, %xmm1 ; SSE41-NEXT: addps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: addss %xmm1, %xmm0 ; SSE41-NEXT: addss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f32_undef: ; AVX1-SLOW-LABEL: test_v16f32_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX1-SLOW-NEXT: vaddps %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 410 Lines • ▼ Show 20 Lines
; SSE-LABEL: test_v16f64_zero: ; SSE-LABEL: test_v16f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm0, %xmm1 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64_zero: ; AVX1-SLOW-LABEL: test_v16f64_zero:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
; SSE-LABEL: test_v16f64_undef: ; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm0, %xmm1 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64_undef: ; AVX1-SLOW-LABEL: test_v16f64_undef:
; AVX1-SLOW: # %bb.0: ; AVX1-SLOW: # %bb.0:
; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-SLOW-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-SLOW-NEXT: vaddpd %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret float %1 ret float %1
} }
define float @test_v4f32_zero(<4 x float> %a0) { define float @test_v4f32_zero(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_zero: ; SSE2-LABEL: test_v4f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_zero: ; SSE41-LABEL: test_v4f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32_zero: ; AVX-LABEL: test_v4f32_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 12 Lines
} }
define float @test_v8f32_zero(<8 x float> %a0) { define float @test_v8f32_zero(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_zero: ; SSE2-LABEL: test_v8f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_zero: ; SSE41-LABEL: test_v8f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32_zero: ; AVX-LABEL: test_v8f32_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 20 Lines
define float @test_v16f32_zero(<16 x float> %a0) { define float @test_v16f32_zero(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_zero: ; SSE2-LABEL: test_v16f32_zero:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm3, %xmm1 ; SSE2-NEXT: mulps %xmm3, %xmm1
; SSE2-NEXT: mulps %xmm2, %xmm0 ; SSE2-NEXT: mulps %xmm2, %xmm0
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_zero: ; SSE41-LABEL: test_v16f32_zero:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm3, %xmm1 ; SSE41-NEXT: mulps %xmm3, %xmm1
; SSE41-NEXT: mulps %xmm2, %xmm0 ; SSE41-NEXT: mulps %xmm2, %xmm0
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32_zero: ; AVX-LABEL: test_v16f32_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret float %1 ret float %1
} }
define float @test_v4f32_undef(<4 x float> %a0) { define float @test_v4f32_undef(<4 x float> %a0) {
; SSE2-LABEL: test_v4f32_undef: ; SSE2-LABEL: test_v4f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v4f32_undef: ; SSE41-LABEL: test_v4f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v4f32_undef: ; AVX-LABEL: test_v4f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
Show All 12 Lines
} }
define float @test_v8f32_undef(<8 x float> %a0) { define float @test_v8f32_undef(<8 x float> %a0) {
; SSE2-LABEL: test_v8f32_undef: ; SSE2-LABEL: test_v8f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v8f32_undef: ; SSE41-LABEL: test_v8f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v8f32_undef: ; AVX-LABEL: test_v8f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
Show All 20 Lines
define float @test_v16f32_undef(<16 x float> %a0) { define float @test_v16f32_undef(<16 x float> %a0) {
; SSE2-LABEL: test_v16f32_undef: ; SSE2-LABEL: test_v16f32_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: mulps %xmm3, %xmm1 ; SSE2-NEXT: mulps %xmm3, %xmm1
; SSE2-NEXT: mulps %xmm2, %xmm0 ; SSE2-NEXT: mulps %xmm2, %xmm0
; SSE2-NEXT: mulps %xmm1, %xmm0 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: mulps %xmm0, %xmm1 ; SSE2-NEXT: mulps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE2-NEXT: mulss %xmm1, %xmm0 ; SSE2-NEXT: mulss %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_v16f32_undef: ; SSE41-LABEL: test_v16f32_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: mulps %xmm3, %xmm1 ; SSE41-NEXT: mulps %xmm3, %xmm1
; SSE41-NEXT: mulps %xmm2, %xmm0 ; SSE41-NEXT: mulps %xmm2, %xmm0
; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movaps %xmm0, %xmm1 ; SSE41-NEXT: movaps %xmm0, %xmm1
; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE41-NEXT: mulps %xmm0, %xmm1 ; SSE41-NEXT: mulps %xmm1, %xmm0
; SSE41-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: mulss %xmm1, %xmm0 ; SSE41-NEXT: mulss %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: test_v16f32_undef: ; AVX-LABEL: test_v16f32_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 262 Lines • ▼ Show 20 Lines
; SSE-LABEL: test_v16f64_zero: ; SSE-LABEL: test_v16f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm4, %xmm0 ; SSE-NEXT: mulpd %xmm4, %xmm0
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm0, %xmm1 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_zero: ; AVX-LABEL: test_v16f64_zero:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1
; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; SSE-LABEL: test_v16f64_undef: ; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm4, %xmm0 ; SSE-NEXT: mulpd %xmm4, %xmm0
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm0, %xmm1 ; SSE-NEXT: mulpd %xmm1, %xmm0
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_undef: ; AVX-LABEL: test_v16f64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1 ; AVX-NEXT: vmulpd %ymm3, %ymm1, %ymm1
; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
Show All 31 Lines

llvm/test/CodeGen/X86/vector-shift-ashr-128.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pandn %xmm0, %xmm2 ; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psraw $1, %xmm0 ; SSE2-NEXT: psraw $1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_shift_v8i16: ; SSE41-LABEL: var_shift_v8i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: psllw $12, %xmm0 ; SSE41-NEXT: psllw $12, %xmm0
; SSE41-NEXT: psllw $4, %xmm2 ; SSE41-NEXT: psllw $4, %xmm1
; SSE41-NEXT: por %xmm0, %xmm2 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: paddw %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: paddw %xmm2, %xmm3 ; SSE41-NEXT: psraw $8, %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: psraw $8, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: psraw $4, %xmm3
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $4, %xmm2
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $2, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $1, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psraw $2, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psraw $1, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: var_shift_v8i16: ; AVX1-LABEL: var_shift_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 ; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
▲ Show 20 Lines • Show All 1,486 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pandn %xmm0, %xmm2 ; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psraw $1, %xmm0 ; SSE2-NEXT: psraw $1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_shift_v4i16: ; SSE41-LABEL: var_shift_v4i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: psllw $12, %xmm0 ; SSE41-NEXT: psllw $12, %xmm0
; SSE41-NEXT: psllw $4, %xmm2 ; SSE41-NEXT: psllw $4, %xmm1
; SSE41-NEXT: por %xmm0, %xmm2 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: paddw %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: paddw %xmm2, %xmm3 ; SSE41-NEXT: psraw $8, %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: psraw $8, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: psraw $4, %xmm3
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $4, %xmm2
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $2, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $1, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psraw $2, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psraw $1, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: var_shift_v4i16: ; AVX1-LABEL: var_shift_v4i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 ; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pandn %xmm0, %xmm2 ; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psraw $1, %xmm0 ; SSE2-NEXT: psraw $1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_shift_v2i16: ; SSE41-LABEL: var_shift_v2i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: psllw $12, %xmm0 ; SSE41-NEXT: psllw $12, %xmm0
; SSE41-NEXT: psllw $4, %xmm2 ; SSE41-NEXT: psllw $4, %xmm1
; SSE41-NEXT: por %xmm0, %xmm2 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: paddw %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: paddw %xmm2, %xmm3 ; SSE41-NEXT: psraw $8, %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: psraw $8, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: psraw $4, %xmm3
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $4, %xmm2
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $2, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psraw $1, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psraw $2, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psraw $1, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: var_shift_v2i16: ; AVX1-LABEL: var_shift_v2i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 ; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
▲ Show 20 Lines • Show All 2,095 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shift-lshr-128.ll

Show First 20 Lines • Show All 221 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pandn %xmm0, %xmm2 ; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_shift_v8i16: ; SSE41-LABEL: var_shift_v8i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: psllw $12, %xmm0 ; SSE41-NEXT: psllw $12, %xmm0
; SSE41-NEXT: psllw $4, %xmm2 ; SSE41-NEXT: psllw $4, %xmm1
; SSE41-NEXT: por %xmm0, %xmm2 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: paddw %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: paddw %xmm2, %xmm3 ; SSE41-NEXT: psrlw $8, %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: psrlw $8, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: psrlw $4, %xmm3
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $4, %xmm2
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $2, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $1, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlw $2, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlw $1, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: var_shift_v8i16: ; AVX1-LABEL: var_shift_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 ; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
▲ Show 20 Lines • Show All 1,379 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pandn %xmm0, %xmm2 ; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_shift_v4i16: ; SSE41-LABEL: var_shift_v4i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: psllw $12, %xmm0 ; SSE41-NEXT: psllw $12, %xmm0
; SSE41-NEXT: psllw $4, %xmm2 ; SSE41-NEXT: psllw $4, %xmm1
; SSE41-NEXT: por %xmm0, %xmm2 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: paddw %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: paddw %xmm2, %xmm3 ; SSE41-NEXT: psrlw $8, %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: psrlw $8, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: psrlw $4, %xmm3
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $4, %xmm2
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $2, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $1, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlw $2, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlw $1, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: var_shift_v4i16: ; AVX1-LABEL: var_shift_v4i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 ; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pandn %xmm0, %xmm2 ; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: psrlw $1, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: var_shift_v2i16: ; SSE41-LABEL: var_shift_v2i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: psllw $12, %xmm0 ; SSE41-NEXT: psllw $12, %xmm0
; SSE41-NEXT: psllw $4, %xmm2 ; SSE41-NEXT: psllw $4, %xmm1
; SSE41-NEXT: por %xmm0, %xmm2 ; SSE41-NEXT: por %xmm1, %xmm0
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: paddw %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm2, %xmm3 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: paddw %xmm2, %xmm3 ; SSE41-NEXT: psrlw $8, %xmm3
; SSE41-NEXT: movdqa %xmm1, %xmm4 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: psrlw $8, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: psrlw $4, %xmm3
; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $4, %xmm2
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $2, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrlw $1, %xmm2
; SSE41-NEXT: paddw %xmm3, %xmm3
; SSE41-NEXT: movdqa %xmm3, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlw $2, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm3
; SSE41-NEXT: psrlw $1, %xmm3
; SSE41-NEXT: paddw %xmm1, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: var_shift_v2i16: ; AVX1-LABEL: var_shift_v2i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2 ; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
▲ Show 20 Lines • Show All 1,766 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll

Show All 17 Lines; CHECK-NEXT: ret{{[l|q]}}
%res1 = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> <i16 63, i16 30, i16 61, i16 28, i16 59, i16 26, i16 57, i16 24, i16 55, i16 22, i16 53, i16 20, i16 51, i16 18, i16 49, i16 16, i16 47, i16 46, i16 13, i16 44, i16 11, i16 42, i16 9, i16 40, i16 7, i16 38, i16 5, i16 36, i16 3, i16 34, i16 1, i16 32>, <32 x i16> %res0, <32 x i16> %res0, i32 -1) %res1 = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> <i16 63, i16 30, i16 61, i16 28, i16 59, i16 26, i16 57, i16 24, i16 55, i16 22, i16 53, i16 20, i16 51, i16 18, i16 49, i16 16, i16 47, i16 46, i16 13, i16 44, i16 11, i16 42, i16 9, i16 40, i16 7, i16 38, i16 5, i16 36, i16 3, i16 34, i16 1, i16 32>, <32 x i16> %res0, <32 x i16> %res0, i32 -1)
ret <32 x i16> %res1 ret <32 x i16> %res1
} }
define <32 x i16> @combine_vpermt2var_32i16_identity_mask(<32 x i16> %x0, <32 x i16> %x1, i32 %m) { define <32 x i16> @combine_vpermt2var_32i16_identity_mask(<32 x i16> %x0, <32 x i16> %x1, i32 %m) {
; X86-LABEL: combine_vpermt2var_32i16_identity_mask: ; X86-LABEL: combine_vpermt2var_32i16_identity_mask:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 ; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1
; X86-NEXT: vpermi2w %zmm0, %zmm0, %zmm1 {%k1} {z} ; X86-NEXT: vpermt2w %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [63,30,61,28,59,26,57,24,55,22,53,20,51,18,49,16,47,46,13,44,11,42,9,40,7,38,5,36,3,34,1,32] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [63,30,61,28,59,26,57,24,55,22,53,20,51,18,49,16,47,46,13,44,11,42,9,40,7,38,5,36,3,34,1,32]
; X86-NEXT: vpermi2w %zmm1, %zmm1, %zmm0 {%k1} {z} ; X86-NEXT: vpermt2w %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_vpermt2var_32i16_identity_mask: ; X64-LABEL: combine_vpermt2var_32i16_identity_mask:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: kmovd %edi, %k1
; X64-NEXT: vpermi2w %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-NEXT: vpermt2w %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [63,30,61,28,59,26,57,24,55,22,53,20,51,18,49,16,47,46,13,44,11,42,9,40,7,38,5,36,3,34,1,32] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [63,30,61,28,59,26,57,24,55,22,53,20,51,18,49,16,47,46,13,44,11,42,9,40,7,38,5,36,3,34,1,32]
; X64-NEXT: vpermi2w %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-NEXT: vpermt2w %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> <i16 31, i16 30, i16 29, i16 28, i16 27, i16 26, i16 25, i16 24, i16 23, i16 22, i16 21, i16 20, i16 19, i16 18, i16 17, i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, <32 x i16> %x0, <32 x i16> %x1, i32 %m) %res0 = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> <i16 31, i16 30, i16 29, i16 28, i16 27, i16 26, i16 25, i16 24, i16 23, i16 22, i16 21, i16 20, i16 19, i16 18, i16 17, i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, <32 x i16> %x0, <32 x i16> %x1, i32 %m)
%res1 = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> <i16 63, i16 30, i16 61, i16 28, i16 59, i16 26, i16 57, i16 24, i16 55, i16 22, i16 53, i16 20, i16 51, i16 18, i16 49, i16 16, i16 47, i16 46, i16 13, i16 44, i16 11, i16 42, i16 9, i16 40, i16 7, i16 38, i16 5, i16 36, i16 3, i16 34, i16 1, i16 32>, <32 x i16> %res0, <32 x i16> %res0, i32 %m) %res1 = call <32 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.512(<32 x i16> <i16 63, i16 30, i16 61, i16 28, i16 59, i16 26, i16 57, i16 24, i16 55, i16 22, i16 53, i16 20, i16 51, i16 18, i16 49, i16 16, i16 47, i16 46, i16 13, i16 44, i16 11, i16 42, i16 9, i16 40, i16 7, i16 38, i16 5, i16 36, i16 3, i16 34, i16 1, i16 32>, <32 x i16> %res0, <32 x i16> %res0, i32 %m)
ret <32 x i16> %res1 ret <32 x i16> %res1
} }
define <64 x i8> @combine_pshufb_identity(<64 x i8> %x0) { define <64 x i8> @combine_pshufb_identity(<64 x i8> %x0) {
; CHECK-LABEL: combine_pshufb_identity: ; CHECK-LABEL: combine_pshufb_identity:
▲ Show 20 Lines • Show All 265 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

Show All 12 Lines; CHECK-NEXT: ret{{[l|q]}}
%res1 = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 30, i16 13, i16 28, i16 11, i16 26, i16 9, i16 24, i16 7, i16 22, i16 5, i16 20, i16 3, i16 18, i16 1, i16 16>, <16 x i16> %res0, <16 x i16> %res0, i16 -1) %res1 = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 30, i16 13, i16 28, i16 11, i16 26, i16 9, i16 24, i16 7, i16 22, i16 5, i16 20, i16 3, i16 18, i16 1, i16 16>, <16 x i16> %res0, <16 x i16> %res0, i16 -1)
ret <16 x i16> %res1 ret <16 x i16> %res1
} }
define <16 x i16> @combine_vpermt2var_16i16_identity_mask(<16 x i16> %x0, <16 x i16> %x1, i16 %m) { define <16 x i16> @combine_vpermt2var_16i16_identity_mask(<16 x i16> %x0, <16 x i16> %x1, i16 %m) {
; X86-LABEL: combine_vpermt2var_16i16_identity_mask: ; X86-LABEL: combine_vpermt2var_16i16_identity_mask:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{.*#+}} ymm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X86-NEXT: vmovdqa {{.*#+}} ymm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
; X86-NEXT: vpermi2w %ymm0, %ymm0, %ymm1 {%k1} {z} ; X86-NEXT: vpermt2w %ymm0, %ymm1, %ymm0 {%k1} {z}
; X86-NEXT: vmovdqa {{.*#+}} ymm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X86-NEXT: vmovdqa {{.*#+}} ymm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X86-NEXT: vpermi2w %ymm1, %ymm1, %ymm0 {%k1} {z} ; X86-NEXT: vpermt2w %ymm0, %ymm1, %ymm0 {%k1} {z}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_vpermt2var_16i16_identity_mask: ; X64-LABEL: combine_vpermt2var_16i16_identity_mask:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*#+}} ymm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X64-NEXT: vmovdqa {{.*#+}} ymm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: kmovd %edi, %k1
; X64-NEXT: vpermi2w %ymm0, %ymm0, %ymm1 {%k1} {z} ; X64-NEXT: vpermt2w %ymm0, %ymm1, %ymm0 {%k1} {z}
; X64-NEXT: vmovdqa {{.*#+}} ymm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X64-NEXT: vmovdqa {{.*#+}} ymm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X64-NEXT: vpermi2w %ymm1, %ymm1, %ymm0 {%k1} {z} ; X64-NEXT: vpermt2w %ymm0, %ymm1, %ymm0 {%k1} {z}
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, <16 x i16> %x0, <16 x i16> %x1, i16 %m) %res0 = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, <16 x i16> %x0, <16 x i16> %x1, i16 %m)
%res1 = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 30, i16 13, i16 28, i16 11, i16 26, i16 9, i16 24, i16 7, i16 22, i16 5, i16 20, i16 3, i16 18, i16 1, i16 16>, <16 x i16> %res0, <16 x i16> %res0, i16 %m) %res1 = call <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 30, i16 13, i16 28, i16 11, i16 26, i16 9, i16 24, i16 7, i16 22, i16 5, i16 20, i16 3, i16 18, i16 1, i16 16>, <16 x i16> %res0, <16 x i16> %res0, i16 %m)
ret <16 x i16> %res1 ret <16 x i16> %res1
} }
define <16 x i16> @combine_vpermi2var_16i16_as_permw(<16 x i16> %x0, <16 x i16> %x1) { define <16 x i16> @combine_vpermi2var_16i16_as_permw(<16 x i16> %x0, <16 x i16> %x1) {
; CHECK-LABEL: combine_vpermi2var_16i16_as_permw: ; CHECK-LABEL: combine_vpermi2var_16i16_as_permw:
▲ Show 20 Lines • Show All 136 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret{{[l|q]}}
ret <8 x double> %res1 ret <8 x double> %res1
} }
define <8 x double> @combine_vpermt2var_8f64_identity_mask(<8 x double> %x0, <8 x double> %x1, i8 %m) { define <8 x double> @combine_vpermt2var_8f64_identity_mask(<8 x double> %x0, <8 x double> %x1, i8 %m) {
; X86-AVX512F-LABEL: combine_vpermt2var_8f64_identity_mask: ; X86-AVX512F-LABEL: combine_vpermt2var_8f64_identity_mask:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0] ; X86-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k1 ; X86-AVX512F-NEXT: kmovw %eax, %k1
; X86-AVX512F-NEXT: vpermi2pd %zmm0, %zmm0, %zmm1 {%k1} {z} ; X86-AVX512F-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512F-NEXT: vmovapd {{.*#+}} zmm0 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0] ; X86-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0]
; X86-AVX512F-NEXT: vpermi2pd %zmm1, %zmm1, %zmm0 {%k1} {z} ; X86-AVX512F-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X86-AVX512BW-LABEL: combine_vpermt2var_8f64_identity_mask: ; X86-AVX512BW-LABEL: combine_vpermt2var_8f64_identity_mask:
; X86-AVX512BW: # %bb.0: ; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0] ; X86-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k1 ; X86-AVX512BW-NEXT: kmovd %eax, %k1
; X86-AVX512BW-NEXT: vpermi2pd %zmm0, %zmm0, %zmm1 {%k1} {z} ; X86-AVX512BW-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512BW-NEXT: vmovapd {{.*#+}} zmm0 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0] ; X86-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0]
; X86-AVX512BW-NEXT: vpermi2pd %zmm1, %zmm1, %zmm0 {%k1} {z} ; X86-AVX512BW-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512BW-NEXT: retl ; X86-AVX512BW-NEXT: retl
; ;
; X64-AVX512F-LABEL: combine_vpermt2var_8f64_identity_mask: ; X64-AVX512F-LABEL: combine_vpermt2var_8f64_identity_mask:
; X64-AVX512F: # %bb.0: ; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0] ; X64-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X64-AVX512F-NEXT: kmovw %edi, %k1 ; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vpermi2pd %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: vmovapd {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8] ; X64-AVX512F-NEXT: vmovapd {{.*#+}} zmm1 = [7,14,5,12,3,10,1,8]
; X64-AVX512F-NEXT: vpermi2pd %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: retq ; X64-AVX512F-NEXT: retq
; ;
; X64-AVX512BW-LABEL: combine_vpermt2var_8f64_identity_mask: ; X64-AVX512BW-LABEL: combine_vpermt2var_8f64_identity_mask:
; X64-AVX512BW: # %bb.0: ; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0] ; X64-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X64-AVX512BW-NEXT: kmovd %edi, %k1 ; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vpermi2pd %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: vmovapd {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8] ; X64-AVX512BW-NEXT: vmovapd {{.*#+}} zmm1 = [7,14,5,12,3,10,1,8]
; X64-AVX512BW-NEXT: vpermi2pd %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2pd %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: retq ; X64-AVX512BW-NEXT: retq
%res0 = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>, <8 x double> %x0, <8 x double> %x1, i8 %m) %res0 = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>, <8 x double> %x0, <8 x double> %x1, i8 %m)
%res1 = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> <i64 7, i64 14, i64 5, i64 12, i64 3, i64 10, i64 1, i64 8>, <8 x double> %res0, <8 x double> %res0, i8 %m) %res1 = call <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64> <i64 7, i64 14, i64 5, i64 12, i64 3, i64 10, i64 1, i64 8>, <8 x double> %res0, <8 x double> %res0, i8 %m)
ret <8 x double> %res1 ret <8 x double> %res1
} }
define <8 x double> @combine_vpermt2var_8f64_movddup(<8 x double> %x0, <8 x double> %x1) { define <8 x double> @combine_vpermt2var_8f64_movddup(<8 x double> %x0, <8 x double> %x1) {
; CHECK-LABEL: combine_vpermt2var_8f64_movddup: ; CHECK-LABEL: combine_vpermt2var_8f64_movddup:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret{{[l|q]}}
ret <8 x i64> %res1 ret <8 x i64> %res1
} }
define <8 x i64> @combine_vpermt2var_8i64_identity_mask(<8 x i64> %x0, <8 x i64> %x1, i8 %m) { define <8 x i64> @combine_vpermt2var_8i64_identity_mask(<8 x i64> %x0, <8 x i64> %x1, i8 %m) {
; X86-AVX512F-LABEL: combine_vpermt2var_8i64_identity_mask: ; X86-AVX512F-LABEL: combine_vpermt2var_8i64_identity_mask:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0] ; X86-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k1 ; X86-AVX512F-NEXT: kmovw %eax, %k1
; X86-AVX512F-NEXT: vpermi2q %zmm0, %zmm0, %zmm1 {%k1} {z} ; X86-AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0] ; X86-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0]
; X86-AVX512F-NEXT: vpermi2q %zmm1, %zmm1, %zmm0 {%k1} {z} ; X86-AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X86-AVX512BW-LABEL: combine_vpermt2var_8i64_identity_mask: ; X86-AVX512BW-LABEL: combine_vpermt2var_8i64_identity_mask:
; X86-AVX512BW: # %bb.0: ; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0] ; X86-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,0,6,0,5,0,4,0,3,0,2,0,1,0,0,0]
; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k1 ; X86-AVX512BW-NEXT: kmovd %eax, %k1
; X86-AVX512BW-NEXT: vpermi2q %zmm0, %zmm0, %zmm1 {%k1} {z} ; X86-AVX512BW-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0] ; X86-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,0,14,0,5,0,12,0,3,0,10,0,1,0,8,0]
; X86-AVX512BW-NEXT: vpermi2q %zmm1, %zmm1, %zmm0 {%k1} {z} ; X86-AVX512BW-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-AVX512BW-NEXT: retl ; X86-AVX512BW-NEXT: retl
; ;
; X64-AVX512F-LABEL: combine_vpermt2var_8i64_identity_mask: ; X64-AVX512F-LABEL: combine_vpermt2var_8i64_identity_mask:
; X64-AVX512F: # %bb.0: ; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0] ; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X64-AVX512F-NEXT: kmovw %edi, %k1 ; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vpermi2q %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8] ; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,14,5,12,3,10,1,8]
; X64-AVX512F-NEXT: vpermi2q %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: retq ; X64-AVX512F-NEXT: retq
; ;
; X64-AVX512BW-LABEL: combine_vpermt2var_8i64_identity_mask: ; X64-AVX512BW-LABEL: combine_vpermt2var_8i64_identity_mask:
; X64-AVX512BW: # %bb.0: ; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0] ; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,6,5,4,3,2,1,0]
; X64-AVX512BW-NEXT: kmovd %edi, %k1 ; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vpermi2q %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [7,14,5,12,3,10,1,8] ; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [7,14,5,12,3,10,1,8]
; X64-AVX512BW-NEXT: vpermi2q %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2q %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: retq ; X64-AVX512BW-NEXT: retq
%res0 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>, <8 x i64> %x0, <8 x i64> %x1, i8 %m) %res0 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>, <8 x i64> %x0, <8 x i64> %x1, i8 %m)
%res1 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 7, i64 14, i64 5, i64 12, i64 3, i64 10, i64 1, i64 8>, <8 x i64> %res0, <8 x i64> %res0, i8 %m) %res1 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 7, i64 14, i64 5, i64 12, i64 3, i64 10, i64 1, i64 8>, <8 x i64> %res0, <8 x i64> %res0, i8 %m)
ret <8 x i64> %res1 ret <8 x i64> %res1
} }
define <16 x float> @combine_vpermt2var_16f32_identity(<16 x float> %x0, <16 x float> %x1) { define <16 x float> @combine_vpermt2var_16f32_identity(<16 x float> %x0, <16 x float> %x1) {
; CHECK-LABEL: combine_vpermt2var_16f32_identity: ; CHECK-LABEL: combine_vpermt2var_16f32_identity:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
%res0 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>, <16 x float> %x0, <16 x float> %x1, i16 -1) %res0 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>, <16 x float> %x0, <16 x float> %x1, i16 -1)
%res1 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 11, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x float> %res0, <16 x float> %res0, i16 -1) %res1 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 11, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x float> %res0, <16 x float> %res0, i16 -1)
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @combine_vpermt2var_16f32_identity_mask(<16 x float> %x0, <16 x float> %x1, i16 %m) { define <16 x float> @combine_vpermt2var_16f32_identity_mask(<16 x float> %x0, <16 x float> %x1, i16 %m) {
; X86-LABEL: combine_vpermt2var_16f32_identity_mask: ; X86-LABEL: combine_vpermt2var_16f32_identity_mask:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X86-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
; X86-NEXT: vpermi2ps %zmm0, %zmm0, %zmm1 {%k1} {z} ; X86-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-NEXT: vmovaps {{.*#+}} zmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X86-NEXT: vmovaps {{.*#+}} zmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X86-NEXT: vpermi2ps %zmm1, %zmm1, %zmm0 {%k1} {z} ; X86-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-AVX512F-LABEL: combine_vpermt2var_16f32_identity_mask: ; X64-AVX512F-LABEL: combine_vpermt2var_16f32_identity_mask:
; X64-AVX512F: # %bb.0: ; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X64-AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-AVX512F-NEXT: kmovw %edi, %k1 ; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vpermi2ps %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: vmovaps {{.*#+}} zmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X64-AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X64-AVX512F-NEXT: vpermi2ps %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: retq ; X64-AVX512F-NEXT: retq
; ;
; X64-AVX512BW-LABEL: combine_vpermt2var_16f32_identity_mask: ; X64-AVX512BW-LABEL: combine_vpermt2var_16f32_identity_mask:
; X64-AVX512BW: # %bb.0: ; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X64-AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-AVX512BW-NEXT: kmovd %edi, %k1 ; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vpermi2ps %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: vmovaps {{.*#+}} zmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X64-AVX512BW-NEXT: vmovaps {{.*#+}} zmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X64-AVX512BW-NEXT: vpermi2ps %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2ps %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: retq ; X64-AVX512BW-NEXT: retq
%res0 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>, <16 x float> %x0, <16 x float> %x1, i16 %m) %res0 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>, <16 x float> %x0, <16 x float> %x1, i16 %m)
%res1 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 11, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x float> %res0, <16 x float> %res0, i16 %m) %res1 = call <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 11, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x float> %res0, <16 x float> %res0, i16 %m)
ret <16 x float> %res1 ret <16 x float> %res1
} }
define <16 x float> @combine_vpermt2var_16f32_vmovddup(<16 x float> %x0, <16 x float> %x1) { define <16 x float> @combine_vpermt2var_16f32_vmovddup(<16 x float> %x0, <16 x float> %x1) {
; CHECK-LABEL: combine_vpermt2var_16f32_vmovddup: ; CHECK-LABEL: combine_vpermt2var_16f32_vmovddup:
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret{{[l|q]}}
%res1 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 undef, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x i32> %res0, <16 x i32> %res0, i16 -1) %res1 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 undef, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x i32> %res0, <16 x i32> %res0, i16 -1)
ret <16 x i32> %res1 ret <16 x i32> %res1
} }
define <16 x i32> @combine_vpermt2var_16i32_identity_mask(<16 x i32> %x0, <16 x i32> %x1, i16 %m) { define <16 x i32> @combine_vpermt2var_16i32_identity_mask(<16 x i32> %x0, <16 x i32> %x1, i16 %m) {
; X86-LABEL: combine_vpermt2var_16i32_identity_mask: ; X86-LABEL: combine_vpermt2var_16i32_identity_mask:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
; X86-NEXT: vpermi2d %zmm0, %zmm0, %zmm1 {%k1} {z} ; X86-NEXT: vpermt2d %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X86-NEXT: vpermi2d %zmm1, %zmm1, %zmm0 {%k1} {z} ; X86-NEXT: vpermt2d %zmm0, %zmm1, %zmm0 {%k1} {z}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-AVX512F-LABEL: combine_vpermt2var_16i32_identity_mask: ; X64-AVX512F-LABEL: combine_vpermt2var_16i32_identity_mask:
; X64-AVX512F: # %bb.0: ; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-AVX512F-NEXT: kmovw %edi, %k1 ; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vpermi2d %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2d %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X64-AVX512F-NEXT: vpermi2d %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512F-NEXT: vpermt2d %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: retq ; X64-AVX512F-NEXT: retq
; ;
; X64-AVX512BW-LABEL: combine_vpermt2var_16i32_identity_mask: ; X64-AVX512BW-LABEL: combine_vpermt2var_16i32_identity_mask:
; X64-AVX512BW: # %bb.0: ; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-AVX512BW-NEXT: kmovd %edi, %k1 ; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vpermi2d %zmm0, %zmm0, %zmm1 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2d %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X64-AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X64-AVX512BW-NEXT: vpermi2d %zmm1, %zmm1, %zmm0 {%k1} {z} ; X64-AVX512BW-NEXT: vpermt2d %zmm0, %zmm1, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: retq ; X64-AVX512BW-NEXT: retq
%res0 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>, <16 x i32> %x0, <16 x i32> %x1, i16 %m) %res0 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>, <16 x i32> %x0, <16 x i32> %x1, i16 %m)
%res1 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 11, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x i32> %res0, <16 x i32> %res0, i16 %m) %res1 = call <16 x i32> @llvm.x86.avx512.maskz.vpermt2var.d.512(<16 x i32> <i32 15, i32 30, i32 13, i32 28, i32 11, i32 26, i32 9, i32 24, i32 7, i32 22, i32 5, i32 20, i32 3, i32 18, i32 1, i32 16>, <16 x i32> %res0, <16 x i32> %res0, i16 %m)
ret <16 x i32> %res1 ret <16 x i32> %res1
} }
define <16 x i32> @combine_permvar_as_vpbroadcastd512(<16 x i32> %x0) { define <16 x i32> @combine_permvar_as_vpbroadcastd512(<16 x i32> %x0) {
; CHECK-LABEL: combine_permvar_as_vpbroadcastd512: ; CHECK-LABEL: combine_permvar_as_vpbroadcastd512:
▲ Show 20 Lines • Show All 347 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll

Show All 25 Lines; CHECK-NEXT: ret{{[l|q]}}
%res1 = call <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8> <i8 15, i8 30, i8 13, i8 28, i8 11, i8 26, i8 9, i8 24, i8 7, i8 22, i8 5, i8 20, i8 3, i8 18, i8 1, i8 16>, <16 x i8> %res0, <16 x i8> %res0, i16 -1) %res1 = call <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8> <i8 15, i8 30, i8 13, i8 28, i8 11, i8 26, i8 9, i8 24, i8 7, i8 22, i8 5, i8 20, i8 3, i8 18, i8 1, i8 16>, <16 x i8> %res0, <16 x i8> %res0, i16 -1)
ret <16 x i8> %res1 ret <16 x i8> %res1
} }
define <16 x i8> @combine_vpermt2var_16i8_identity_mask(<16 x i8> %x0, <16 x i8> %x1, i16 %m) { define <16 x i8> @combine_vpermt2var_16i8_identity_mask(<16 x i8> %x0, <16 x i8> %x1, i16 %m) {
; X86-LABEL: combine_vpermt2var_16i8_identity_mask: ; X86-LABEL: combine_vpermt2var_16i8_identity_mask:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{.*#+}} xmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X86-NEXT: vmovdqa {{.*#+}} xmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
; X86-NEXT: vpermi2b %xmm0, %xmm0, %xmm1 {%k1} {z} ; X86-NEXT: vpermt2b %xmm0, %xmm1, %xmm0 {%k1} {z}
; X86-NEXT: vmovdqa {{.*#+}} xmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X86-NEXT: vmovdqa {{.*#+}} xmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X86-NEXT: vpermi2b %xmm1, %xmm1, %xmm0 {%k1} {z} ; X86-NEXT: vpermt2b %xmm0, %xmm1, %xmm0 {%k1} {z}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_vpermt2var_16i8_identity_mask: ; X64-LABEL: combine_vpermt2var_16i8_identity_mask:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0] ; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0]
; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: kmovd %edi, %k1
; X64-NEXT: vpermi2b %xmm0, %xmm0, %xmm1 {%k1} {z} ; X64-NEXT: vpermt2b %xmm0, %xmm1, %xmm0 {%k1} {z}
; X64-NEXT: vmovdqa {{.*#+}} xmm0 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16] ; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [15,30,13,28,11,26,9,24,7,22,5,20,3,18,1,16]
; X64-NEXT: vpermi2b %xmm1, %xmm1, %xmm0 {%k1} {z} ; X64-NEXT: vpermt2b %xmm0, %xmm1, %xmm0 {%k1} {z}
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = call <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8> %x0, <16 x i8> %x1, i16 %m) %res0 = call <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8> %x0, <16 x i8> %x1, i16 %m)
%res1 = call <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8> <i8 15, i8 30, i8 13, i8 28, i8 11, i8 26, i8 9, i8 24, i8 7, i8 22, i8 5, i8 20, i8 3, i8 18, i8 1, i8 16>, <16 x i8> %res0, <16 x i8> %res0, i16 %m) %res1 = call <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8> <i8 15, i8 30, i8 13, i8 28, i8 11, i8 26, i8 9, i8 24, i8 7, i8 22, i8 5, i8 20, i8 3, i8 18, i8 1, i8 16>, <16 x i8> %res0, <16 x i8> %res0, i16 %m)
ret <16 x i8> %res1 ret <16 x i8> %res1
} }
define <16 x i8> @combine_vpermi2var_16i8_as_vpshufb(<16 x i8> %x0, <16 x i8> %x1) { define <16 x i8> @combine_vpermi2var_16i8_as_vpshufb(<16 x i8> %x0, <16 x i8> %x1) {
; CHECK-LABEL: combine_vpermi2var_16i8_as_vpshufb: ; CHECK-LABEL: combine_vpermi2var_16i8_as_vpshufb:
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-trunc-packus.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%5 = trunc <2 x i64> %4 to <2 x i32> %5 = trunc <2 x i64> %4 to <2 x i32>
store <2 x i32> %5, <2 x i32>* %p1 store <2 x i32> %5, <2 x i32>* %p1
ret void ret void
} }
define <4 x i32> @trunc_packus_v4i64_v4i32(<4 x i64> %a0) { define <4 x i32> @trunc_packus_v4i64_v4i32(<4 x i64> %a0) {
; SSE2-LABEL: trunc_packus_v4i64_v4i32: ; SSE2-LABEL: trunc_packus_v4i64_v4i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [4294967295,4294967295] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: pxor %xmm2, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [2147483647,2147483647] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [2147483647,2147483647]
; SSE2-NEXT: movdqa %xmm5, %xmm6 ; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pcmpgtd %xmm3, %xmm6 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: pand %xmm7, %xmm4 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm4, %xmm3 ; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm8, %xmm3
; SSE2-NEXT: por %xmm0, %xmm3
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: pcmpgtd %xmm0, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: pandn %xmm3, %xmm6
; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pxor %xmm2, %xmm4
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm4 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE2-NEXT: pandn %xmm8, %xmm4 ; SSE2-NEXT: por %xmm4, %xmm5
; SSE2-NEXT: por %xmm1, %xmm4 ; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: movdqa %xmm4, %xmm0 ; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm5
; SSE2-NEXT: movdqa %xmm5, %xmm1
; SSE2-NEXT: pxor %xmm2, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: pcmpgtd %xmm2, %xmm3
; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pand %xmm3, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE2-NEXT: por %xmm1, %xmm3
; SSE2-NEXT: pand %xmm5, %xmm3
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pcmpgtd %xmm2, %xmm1 ; SSE2-NEXT: pxor %xmm2, %xmm1
; SSE2-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE2-NEXT: pcmpgtd %xmm2, %xmm4
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm1
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm3, %xmm0 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm4 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pcmpgtd %xmm2, %xmm4 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
; SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE2-NEXT: pand %xmm4, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_packus_v4i64_v4i32: ; SSSE3-LABEL: trunc_packus_v4i64_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [4294967295,4294967295] ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm4
; SSSE3-NEXT: pxor %xmm2, %xmm3 ; SSSE3-NEXT: pxor %xmm2, %xmm4
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2147483647,2147483647] ; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2147483647,2147483647]
; SSSE3-NEXT: movdqa %xmm5, %xmm6 ; SSSE3-NEXT: movdqa %xmm5, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm6 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm3 ; SSSE3-NEXT: pcmpeqd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: pand %xmm7, %xmm4 ; SSSE3-NEXT: pand %xmm7, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSSE3-NEXT: por %xmm4, %xmm3 ; SSSE3-NEXT: por %xmm4, %xmm6
; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pandn %xmm8, %xmm3
; SSSE3-NEXT: por %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: pxor %xmm2, %xmm0
; SSSE3-NEXT: movdqa %xmm5, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSSE3-NEXT: pand %xmm6, %xmm0 ; SSSE3-NEXT: pand %xmm6, %xmm0
; SSSE3-NEXT: pandn %xmm3, %xmm6
; SSSE3-NEXT: por %xmm6, %xmm0
; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pxor %xmm2, %xmm4
; SSSE3-NEXT: movdqa %xmm5, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm0, %xmm4 ; SSSE3-NEXT: pand %xmm7, %xmm4
; SSSE3-NEXT: pand %xmm4, %xmm1 ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSSE3-NEXT: pandn %xmm8, %xmm4 ; SSSE3-NEXT: por %xmm4, %xmm5
; SSSE3-NEXT: por %xmm1, %xmm4 ; SSSE3-NEXT: pand %xmm5, %xmm1
; SSSE3-NEXT: movdqa %xmm4, %xmm0 ; SSSE3-NEXT: pandn %xmm3, %xmm5
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: por %xmm1, %xmm5
; SSSE3-NEXT: movdqa %xmm5, %xmm1
; SSSE3-NEXT: pxor %xmm2, %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm3
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm3
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSSE3-NEXT: pand %xmm3, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSSE3-NEXT: por %xmm1, %xmm3
; SSSE3-NEXT: pand %xmm5, %xmm3
; SSSE3-NEXT: movdqa %xmm0, %xmm1 ; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm1 ; SSSE3-NEXT: pxor %xmm2, %xmm1
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm0 ; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4
; SSSE3-NEXT: pand %xmm1, %xmm0 ; SSSE3-NEXT: pcmpeqd %xmm2, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSSE3-NEXT: por %xmm0, %xmm1
; SSSE3-NEXT: pand %xmm4, %xmm1 ; SSSE3-NEXT: pand %xmm4, %xmm1
; SSSE3-NEXT: movdqa %xmm3, %xmm0 ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: por %xmm1, %xmm2
; SSSE3-NEXT: movdqa %xmm0, %xmm4 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSSE3-NEXT: pand %xmm4, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm2, %xmm0
; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_packus_v4i64_v4i32: ; SSE41-LABEL: trunc_packus_v4i64_v4i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movapd {{.*#+}} xmm4 = [4294967295,4294967295] ; SSE41-NEXT: movapd {{.*#+}} xmm4 = [4294967295,4294967295]
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
; SSE41-NEXT: pxor %xmm3, %xmm0 ; SSE41-NEXT: pxor %xmm3, %xmm0
▲ Show 20 Lines • Show All 1,871 Lines • ▼ Show 20 Lines
; ;
; SSSE3-LABEL: trunc_packus_v4i32_v4i16: ; SSSE3-LABEL: trunc_packus_v4i32_v4i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2 ; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
; SSSE3-NEXT: pand %xmm2, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pandn %xmm1, %xmm2 ; SSSE3-NEXT: pandn %xmm1, %xmm2
; SSSE3-NEXT: por %xmm0, %xmm2 ; SSSE3-NEXT: por %xmm2, %xmm0
; SSSE3-NEXT: pxor %xmm1, %xmm1 ; SSSE3-NEXT: pxor %xmm1, %xmm1
; SSSE3-NEXT: movdqa %xmm2, %xmm0 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm2, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_packus_v4i32_v4i16: ; SSE41-LABEL: trunc_packus_v4i32_v4i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: packusdw %xmm0, %xmm0 ; SSE41-NEXT: packusdw %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pcmpgtd %xmm1, %xmm3 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm1 ; SSE2-NEXT: pand %xmm3, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm3 ; SSE2-NEXT: pandn %xmm2, %xmm3
; SSE2-NEXT: por %xmm1, %xmm3 ; SSE2-NEXT: por %xmm1, %xmm3
; SSE2-NEXT: movdqa %xmm2, %xmm1 ; SSE2-NEXT: movdqa %xmm2, %xmm1
; SSE2-NEXT: pcmpgtd %xmm0, %xmm1 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: pandn %xmm2, %xmm1 ; SSE2-NEXT: pandn %xmm2, %xmm1
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm2, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm1 ; SSE2-NEXT: movdqa %xmm3, %xmm2
; SSE2-NEXT: pcmpgtd %xmm2, %xmm1 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: pand %xmm3, %xmm1 ; SSE2-NEXT: pand %xmm3, %xmm2
; SSE2-NEXT: pslld $16, %xmm1 ; SSE2-NEXT: pslld $16, %xmm2
; SSE2-NEXT: psrad $16, %xmm1 ; SSE2-NEXT: psrad $16, %xmm2
; SSE2-NEXT: pslld $16, %xmm0 ; SSE2-NEXT: pslld $16, %xmm0
; SSE2-NEXT: psrad $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0
; SSE2-NEXT: packssdw %xmm1, %xmm0 ; SSE2-NEXT: packssdw %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_packus_v8i32_v8i16: ; SSSE3-LABEL: trunc_packus_v8i32_v8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535]
; SSSE3-NEXT: movdqa %xmm2, %xmm3 ; SSSE3-NEXT: movdqa %xmm2, %xmm3
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm3 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm3
; SSSE3-NEXT: pand %xmm3, %xmm1 ; SSSE3-NEXT: pand %xmm3, %xmm1
; SSSE3-NEXT: pandn %xmm2, %xmm3 ; SSSE3-NEXT: pandn %xmm2, %xmm3
; SSSE3-NEXT: por %xmm1, %xmm3 ; SSSE3-NEXT: por %xmm1, %xmm3
; SSSE3-NEXT: movdqa %xmm2, %xmm1 ; SSSE3-NEXT: movdqa %xmm2, %xmm1
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm1 ; SSSE3-NEXT: pcmpgtd %xmm0, %xmm1
; SSSE3-NEXT: pand %xmm1, %xmm0 ; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: pandn %xmm2, %xmm1 ; SSSE3-NEXT: pandn %xmm2, %xmm1
; SSSE3-NEXT: por %xmm0, %xmm1 ; SSSE3-NEXT: por %xmm1, %xmm0
; SSSE3-NEXT: pxor %xmm2, %xmm2 ; SSSE3-NEXT: pxor %xmm1, %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm0 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm1, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: movdqa %xmm3, %xmm1 ; SSSE3-NEXT: movdqa %xmm3, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm1 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm3, %xmm1 ; SSSE3-NEXT: pand %xmm3, %xmm2
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; SSSE3-NEXT: pshufb %xmm2, %xmm1 ; SSSE3-NEXT: pshufb %xmm1, %xmm2
; SSSE3-NEXT: pshufb %xmm2, %xmm0 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_packus_v8i32_v8i16: ; SSE41-LABEL: trunc_packus_v8i32_v8i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: packusdw %xmm1, %xmm0 ; SSE41-NEXT: packusdw %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: trunc_packus_v8i32_v8i16: ; AVX1-LABEL: trunc_packus_v8i32_v8i16:
▲ Show 20 Lines • Show All 222 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: pand %xmm5, %xmm2 ; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm3 ; SSE2-NEXT: por %xmm2, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm1, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] ; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_packus_v2i64_v2i8: ; SSSE3-LABEL: trunc_packus_v2i64_v2i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; SSSE3-NEXT: movdqa %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pxor %xmm1, %xmm2 ; SSSE3-NEXT: pxor %xmm1, %xmm2
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2147483903,2147483903] ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2147483903,2147483903]
; SSSE3-NEXT: movdqa %xmm3, %xmm4 ; SSSE3-NEXT: movdqa %xmm3, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm3, %xmm2 ; SSSE3-NEXT: pcmpeqd %xmm3, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSSE3-NEXT: pand %xmm5, %xmm2 ; SSSE3-NEXT: pand %xmm5, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm2, %xmm3 ; SSSE3-NEXT: por %xmm2, %xmm3
; SSSE3-NEXT: pand %xmm3, %xmm0 ; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSSE3-NEXT: por %xmm0, %xmm3 ; SSSE3-NEXT: por %xmm3, %xmm0
; SSSE3-NEXT: movdqa %xmm3, %xmm0
; SSSE3-NEXT: pxor %xmm1, %xmm0
; SSSE3-NEXT: movdqa %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2 ; SSSE3-NEXT: pxor %xmm1, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] ; SSSE3-NEXT: movdqa %xmm2, %xmm3
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSSE3-NEXT: pand %xmm4, %xmm1 ; SSSE3-NEXT: pand %xmm4, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; SSSE3-NEXT: por %xmm1, %xmm0 ; SSSE3-NEXT: por %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm3, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_packus_v2i64_v2i8: ; SSE41-LABEL: trunc_packus_v2i64_v2i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: movapd {{.*#+}} xmm2 = [255,255] ; SSE41-NEXT: movapd {{.*#+}} xmm2 = [255,255]
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pandn %xmm8, %xmm4 ; SSE2-NEXT: pandn %xmm8, %xmm4
; SSE2-NEXT: por %xmm1, %xmm4 ; SSE2-NEXT: por %xmm1, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pxor %xmm3, %xmm1 ; SSE2-NEXT: pxor %xmm3, %xmm1
; SSE2-NEXT: movdqa %xmm5, %xmm2 ; SSE2-NEXT: movdqa %xmm5, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm2 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm2[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm2[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pand %xmm6, %xmm5 ; SSE2-NEXT: pand %xmm6, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: por %xmm5, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn %xmm8, %xmm1 ; SSE2-NEXT: pandn %xmm8, %xmm2
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: pxor %xmm3, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm3, %xmm2 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pand %xmm5, %xmm6 ; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: por %xmm6, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: movdqa %xmm4, %xmm2 ; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: pxor %xmm3, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm5 ; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: pcmpgtd %xmm3, %xmm5 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm5
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pand %xmm6, %xmm2 ; SSE2-NEXT: pand %xmm6, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm3 ; SSE2-NEXT: por %xmm1, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm3 ; SSE2-NEXT: pand %xmm8, %xmm3
; SSE2-NEXT: pand %xmm4, %xmm3 ; SSE2-NEXT: pand %xmm4, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm0 ; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: packuswb %xmm3, %xmm0 ; SSE2-NEXT: packuswb %xmm3, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_packus_v4i64_v4i8: ; SSSE3-LABEL: trunc_packus_v4i64_v4i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [255,255] ; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [255,255]
Show All 19 Lines
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm5, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSSE3-NEXT: pand %xmm6, %xmm1 ; SSSE3-NEXT: pand %xmm6, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm1, %xmm4 ; SSSE3-NEXT: por %xmm1, %xmm4
; SSSE3-NEXT: pand %xmm4, %xmm0 ; SSSE3-NEXT: pand %xmm4, %xmm0
; SSSE3-NEXT: pandn %xmm8, %xmm4 ; SSSE3-NEXT: pandn %xmm8, %xmm4
; SSSE3-NEXT: por %xmm0, %xmm4 ; SSSE3-NEXT: por %xmm4, %xmm0
; SSSE3-NEXT: movdqa %xmm4, %xmm0
; SSSE3-NEXT: pxor %xmm2, %xmm0
; SSSE3-NEXT: movdqa %xmm0, %xmm1 ; SSSE3-NEXT: movdqa %xmm0, %xmm1
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm1 ; SSSE3-NEXT: pxor %xmm2, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm1[0,0,2,2] ; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSSE3-NEXT: pand %xmm5, %xmm6 ; SSSE3-NEXT: pcmpeqd %xmm2, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSSE3-NEXT: por %xmm6, %xmm0 ; SSSE3-NEXT: pand %xmm5, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm1, %xmm4
; SSSE3-NEXT: pand %xmm4, %xmm0 ; SSSE3-NEXT: pand %xmm4, %xmm0
; SSSE3-NEXT: movdqa %xmm3, %xmm1 ; SSSE3-NEXT: movdqa %xmm3, %xmm1
; SSSE3-NEXT: pxor %xmm2, %xmm1 ; SSSE3-NEXT: pxor %xmm2, %xmm1
; SSSE3-NEXT: movdqa %xmm1, %xmm4 ; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm2, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
▲ Show 20 Lines • Show All 1,961 Lines • ▼ Show 20 Lines
define <4 x i8> @trunc_packus_v4i32_v4i8(<4 x i32> %a0) "min-legal-vector-width"="256" { define <4 x i8> @trunc_packus_v4i32_v4i8(<4 x i32> %a0) "min-legal-vector-width"="256" {
; SSE2-LABEL: trunc_packus_v4i32_v4i8: ; SSE2-LABEL: trunc_packus_v4i32_v4i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm2 ; SSE2-NEXT: pandn %xmm1, %xmm2
; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_packus_v4i32_v4i8: ; SSSE3-LABEL: trunc_packus_v4i32_v4i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2 ; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
; SSSE3-NEXT: pand %xmm2, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pandn %xmm1, %xmm2 ; SSSE3-NEXT: pandn %xmm1, %xmm2
; SSSE3-NEXT: por %xmm0, %xmm2 ; SSSE3-NEXT: por %xmm2, %xmm0
; SSSE3-NEXT: pxor %xmm1, %xmm1 ; SSSE3-NEXT: pxor %xmm1, %xmm1
; SSSE3-NEXT: movdqa %xmm2, %xmm0 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm2, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_packus_v4i32_v4i8: ; SSE41-LABEL: trunc_packus_v4i32_v4i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE41-NEXT: pminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pmaxsd %xmm0, %xmm1 ; SSE41-NEXT: pmaxsd %xmm1, %xmm0
; SSE41-NEXT: packusdw %xmm1, %xmm1 ; SSE41-NEXT: packusdw %xmm0, %xmm0
; SSE41-NEXT: packuswb %xmm1, %xmm1 ; SSE41-NEXT: packuswb %xmm0, %xmm0
; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: trunc_packus_v4i32_v4i8: ; AVX1-LABEL: trunc_packus_v4i32_v4i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpackusdw %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vpackusdw %xmm0, %xmm0, %xmm0
▲ Show 20 Lines • Show All 712 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-trunc-ssat.ll

Show First 20 Lines • Show All 307 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%5 = trunc <2 x i64> %4 to <2 x i32> %5 = trunc <2 x i64> %4 to <2 x i32>
store <2 x i32> %5, <2 x i32>* %p1 store <2 x i32> %5, <2 x i32>* %p1
ret void ret void
} }
define <4 x i32> @trunc_ssat_v4i64_v4i32(<4 x i64> %a0) { define <4 x i32> @trunc_ssat_v4i64_v4i32(<4 x i64> %a0) {
; SSE2-LABEL: trunc_ssat_v4i64_v4i32: ; SSE2-LABEL: trunc_ssat_v4i64_v4i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483647,2147483647] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: pxor %xmm2, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295]
; SSE2-NEXT: movdqa %xmm5, %xmm6 ; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pcmpgtd %xmm3, %xmm6 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: pand %xmm7, %xmm4 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm4, %xmm3 ; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm8, %xmm3
; SSE2-NEXT: por %xmm0, %xmm3
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: pcmpgtd %xmm0, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: pandn %xmm3, %xmm6
; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pxor %xmm2, %xmm4
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm4 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE2-NEXT: pandn %xmm8, %xmm4 ; SSE2-NEXT: por %xmm4, %xmm5
; SSE2-NEXT: por %xmm1, %xmm4 ; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: por %xmm1, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744071562067968,18446744071562067968] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744071562067968,18446744071562067968]
; SSE2-NEXT: movdqa %xmm4, %xmm0 ; SSE2-NEXT: movdqa %xmm5, %xmm3
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm2, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [18446744069414584320,18446744069414584320] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [18446744069414584320,18446744069414584320]
; SSE2-NEXT: movdqa %xmm0, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE2-NEXT: pand %xmm7, %xmm0 ; SSE2-NEXT: pand %xmm7, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm6 ; SSE2-NEXT: por %xmm3, %xmm6
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm5
; SSE2-NEXT: pandn %xmm1, %xmm6 ; SSE2-NEXT: pandn %xmm1, %xmm6
; SSE2-NEXT: por %xmm4, %xmm6 ; SSE2-NEXT: por %xmm5, %xmm6
; SSE2-NEXT: pxor %xmm3, %xmm2 ; SSE2-NEXT: pxor %xmm0, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pcmpgtd %xmm5, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: pand %xmm4, %xmm2 ; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm3
; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: pandn %xmm1, %xmm3
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm6[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm6[0,2]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_ssat_v4i64_v4i32: ; SSSE3-LABEL: trunc_ssat_v4i64_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [2147483647,2147483647] ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm4
; SSSE3-NEXT: pxor %xmm2, %xmm3 ; SSSE3-NEXT: pxor %xmm2, %xmm4
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295] ; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295]
; SSSE3-NEXT: movdqa %xmm5, %xmm6 ; SSSE3-NEXT: movdqa %xmm5, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm6 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm3 ; SSSE3-NEXT: pcmpeqd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: pand %xmm7, %xmm4 ; SSSE3-NEXT: pand %xmm7, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSSE3-NEXT: por %xmm4, %xmm3 ; SSSE3-NEXT: por %xmm4, %xmm6
; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pandn %xmm8, %xmm3
; SSSE3-NEXT: por %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: pxor %xmm2, %xmm0
; SSSE3-NEXT: movdqa %xmm5, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSSE3-NEXT: pand %xmm6, %xmm0 ; SSSE3-NEXT: pand %xmm6, %xmm0
; SSSE3-NEXT: pandn %xmm3, %xmm6
; SSSE3-NEXT: por %xmm6, %xmm0
; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pxor %xmm2, %xmm4
; SSSE3-NEXT: movdqa %xmm5, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm0, %xmm4 ; SSSE3-NEXT: pand %xmm7, %xmm4
; SSSE3-NEXT: pand %xmm4, %xmm1 ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSSE3-NEXT: pandn %xmm8, %xmm4 ; SSSE3-NEXT: por %xmm4, %xmm5
; SSSE3-NEXT: por %xmm1, %xmm4 ; SSSE3-NEXT: pand %xmm5, %xmm1
; SSSE3-NEXT: pandn %xmm3, %xmm5
; SSSE3-NEXT: por %xmm1, %xmm5
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [18446744071562067968,18446744071562067968] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [18446744071562067968,18446744071562067968]
; SSSE3-NEXT: movdqa %xmm4, %xmm0 ; SSSE3-NEXT: movdqa %xmm5, %xmm3
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [18446744069414584320,18446744069414584320] ; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [18446744069414584320,18446744069414584320]
; SSSE3-NEXT: movdqa %xmm0, %xmm6 ; SSSE3-NEXT: movdqa %xmm3, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm0 ; SSSE3-NEXT: pcmpeqd %xmm4, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSSE3-NEXT: pand %xmm7, %xmm0 ; SSSE3-NEXT: pand %xmm7, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSSE3-NEXT: por %xmm0, %xmm6 ; SSSE3-NEXT: por %xmm3, %xmm6
; SSSE3-NEXT: pand %xmm6, %xmm4 ; SSSE3-NEXT: pand %xmm6, %xmm5
; SSSE3-NEXT: pandn %xmm1, %xmm6 ; SSSE3-NEXT: pandn %xmm1, %xmm6
; SSSE3-NEXT: por %xmm4, %xmm6 ; SSSE3-NEXT: por %xmm5, %xmm6
; SSSE3-NEXT: pxor %xmm3, %xmm2 ; SSSE3-NEXT: pxor %xmm0, %xmm2
; SSSE3-NEXT: movdqa %xmm2, %xmm0 ; SSSE3-NEXT: movdqa %xmm2, %xmm3
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm2 ; SSSE3-NEXT: pcmpeqd %xmm4, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSSE3-NEXT: pand %xmm4, %xmm2 ; SSSE3-NEXT: pand %xmm5, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSSE3-NEXT: por %xmm2, %xmm0 ; SSSE3-NEXT: por %xmm2, %xmm3
; SSSE3-NEXT: pand %xmm0, %xmm3 ; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pandn %xmm1, %xmm0 ; SSSE3-NEXT: pandn %xmm1, %xmm3
; SSSE3-NEXT: por %xmm3, %xmm0 ; SSSE3-NEXT: por %xmm3, %xmm0
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm6[0,2] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm6[0,2]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_ssat_v4i64_v4i32: ; SSE41-LABEL: trunc_ssat_v4i64_v4i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movapd {{.*#+}} xmm4 = [2147483647,2147483647] ; SSE41-NEXT: movapd {{.*#+}} xmm4 = [2147483647,2147483647]
▲ Show 20 Lines • Show All 931 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%5 = trunc <2 x i64> %4 to <2 x i16> %5 = trunc <2 x i64> %4 to <2 x i16>
store <2 x i16> %5, <2 x i16> *%p1 store <2 x i16> %5, <2 x i16> *%p1
ret void ret void
} }
define <4 x i16> @trunc_ssat_v4i64_v4i16(<4 x i64> %a0) { define <4 x i16> @trunc_ssat_v4i64_v4i16(<4 x i64> %a0) {
; SSE2-LABEL: trunc_ssat_v4i64_v4i16: ; SSE2-LABEL: trunc_ssat_v4i64_v4i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [32767,32767] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [32767,32767]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: pxor %xmm2, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [2147516415,2147516415] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [2147516415,2147516415]
; SSE2-NEXT: movdqa %xmm5, %xmm6 ; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pcmpgtd %xmm3, %xmm6 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: pand %xmm7, %xmm4 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm4, %xmm3 ; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm8, %xmm3
; SSE2-NEXT: por %xmm0, %xmm3
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: pcmpgtd %xmm0, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: pandn %xmm3, %xmm6
; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: pxor %xmm2, %xmm4
; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm4 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE2-NEXT: pandn %xmm8, %xmm4 ; SSE2-NEXT: por %xmm4, %xmm5
; SSE2-NEXT: por %xmm1, %xmm4 ; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: pandn %xmm3, %xmm5
; SSE2-NEXT: por %xmm1, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709518848,18446744073709518848] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709518848,18446744073709518848]
; SSE2-NEXT: movdqa %xmm4, %xmm0 ; SSE2-NEXT: movdqa %xmm5, %xmm3
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm2, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562035200,18446744071562035200] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [18446744071562035200,18446744071562035200]
; SSE2-NEXT: movdqa %xmm0, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE2-NEXT: pand %xmm7, %xmm0 ; SSE2-NEXT: pand %xmm7, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm0, %xmm6 ; SSE2-NEXT: por %xmm3, %xmm6
; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm5
; SSE2-NEXT: pandn %xmm1, %xmm6 ; SSE2-NEXT: pandn %xmm1, %xmm6
; SSE2-NEXT: por %xmm4, %xmm6 ; SSE2-NEXT: por %xmm5, %xmm6
; SSE2-NEXT: pxor %xmm3, %xmm2 ; SSE2-NEXT: pxor %xmm0, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pcmpgtd %xmm5, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm4, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: pand %xmm4, %xmm2 ; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm3
; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: pandn %xmm1, %xmm3
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: packssdw %xmm6, %xmm0 ; SSE2-NEXT: packssdw %xmm6, %xmm0
; SSE2-NEXT: packssdw %xmm0, %xmm0 ; SSE2-NEXT: packssdw %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_ssat_v4i64_v4i16: ; SSSE3-LABEL: trunc_ssat_v4i64_v4i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [32767,32767] ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [32767,32767]
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: movdqa %xmm0, %xmm4
; SSSE3-NEXT: pxor %xmm2, %xmm3 ; SSSE3-NEXT: pxor %xmm2, %xmm4
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2147516415,2147516415] ; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2147516415,2147516415]
; SSSE3-NEXT: movdqa %xmm5, %xmm6 ; SSSE3-NEXT: movdqa %xmm5, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm3, %xmm6 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm3 ; SSSE3-NEXT: pcmpeqd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: pand %xmm7, %xmm4 ; SSSE3-NEXT: pand %xmm7, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSSE3-NEXT: por %xmm4, %xmm3 ; SSSE3-NEXT: por %xmm4, %xmm6
; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pandn %xmm8, %xmm3
; SSSE3-NEXT: por %xmm0, %xmm3
; SSSE3-NEXT: movdqa %xmm1, %xmm0
; SSSE3-NEXT: pxor %xmm2, %xmm0
; SSSE3-NEXT: movdqa %xmm5, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSSE3-NEXT: pand %xmm6, %xmm0 ; SSSE3-NEXT: pand %xmm6, %xmm0
; SSSE3-NEXT: pandn %xmm3, %xmm6
; SSSE3-NEXT: por %xmm6, %xmm0
; SSSE3-NEXT: movdqa %xmm1, %xmm4
; SSSE3-NEXT: pxor %xmm2, %xmm4
; SSSE3-NEXT: movdqa %xmm5, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm0, %xmm4 ; SSSE3-NEXT: pand %xmm7, %xmm4
; SSSE3-NEXT: pand %xmm4, %xmm1 ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSSE3-NEXT: pandn %xmm8, %xmm4 ; SSSE3-NEXT: por %xmm4, %xmm5
; SSSE3-NEXT: por %xmm1, %xmm4 ; SSSE3-NEXT: pand %xmm5, %xmm1
; SSSE3-NEXT: pandn %xmm3, %xmm5
; SSSE3-NEXT: por %xmm1, %xmm5
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709518848,18446744073709518848] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709518848,18446744073709518848]
; SSSE3-NEXT: movdqa %xmm4, %xmm0 ; SSSE3-NEXT: movdqa %xmm5, %xmm3
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm2, %xmm3
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562035200,18446744071562035200] ; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [18446744071562035200,18446744071562035200]
; SSSE3-NEXT: movdqa %xmm0, %xmm6 ; SSSE3-NEXT: movdqa %xmm3, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm0 ; SSSE3-NEXT: pcmpeqd %xmm4, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSSE3-NEXT: pand %xmm7, %xmm0 ; SSSE3-NEXT: pand %xmm7, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSSE3-NEXT: por %xmm0, %xmm6 ; SSSE3-NEXT: por %xmm3, %xmm6
; SSSE3-NEXT: pand %xmm6, %xmm4 ; SSSE3-NEXT: pand %xmm6, %xmm5
; SSSE3-NEXT: pandn %xmm1, %xmm6 ; SSSE3-NEXT: pandn %xmm1, %xmm6
; SSSE3-NEXT: por %xmm4, %xmm6 ; SSSE3-NEXT: por %xmm5, %xmm6
; SSSE3-NEXT: pxor %xmm3, %xmm2 ; SSSE3-NEXT: pxor %xmm0, %xmm2
; SSSE3-NEXT: movdqa %xmm2, %xmm0 ; SSSE3-NEXT: movdqa %xmm2, %xmm3
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm2 ; SSSE3-NEXT: pcmpeqd %xmm4, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSSE3-NEXT: pand %xmm4, %xmm2 ; SSSE3-NEXT: pand %xmm5, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSSE3-NEXT: por %xmm2, %xmm0 ; SSSE3-NEXT: por %xmm2, %xmm3
; SSSE3-NEXT: pand %xmm0, %xmm3 ; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pandn %xmm1, %xmm0 ; SSSE3-NEXT: pandn %xmm1, %xmm3
; SSSE3-NEXT: por %xmm3, %xmm0 ; SSSE3-NEXT: por %xmm3, %xmm0
; SSSE3-NEXT: packssdw %xmm6, %xmm0 ; SSSE3-NEXT: packssdw %xmm6, %xmm0
; SSSE3-NEXT: packssdw %xmm0, %xmm0 ; SSSE3-NEXT: packssdw %xmm0, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_ssat_v4i64_v4i16: ; SSE41-LABEL: trunc_ssat_v4i64_v4i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
▲ Show 20 Lines • Show All 976 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: pand %xmm5, %xmm2 ; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm3 ; SSE2-NEXT: por %xmm2, %xmm3
; SSE2-NEXT: pand %xmm3, %xmm0 ; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm1 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [18446744071562067840,18446744071562067840] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [18446744071562067840,18446744071562067840]
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pand %xmm4, %xmm1 ; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_ssat_v2i64_v2i8: ; SSSE3-LABEL: trunc_ssat_v2i64_v2i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; SSSE3-NEXT: movdqa %xmm0, %xmm2 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pxor %xmm1, %xmm2 ; SSSE3-NEXT: pxor %xmm1, %xmm2
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2147483775,2147483775] ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [2147483775,2147483775]
; SSSE3-NEXT: movdqa %xmm3, %xmm4 ; SSSE3-NEXT: movdqa %xmm3, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm3, %xmm2 ; SSSE3-NEXT: pcmpeqd %xmm3, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSSE3-NEXT: pand %xmm5, %xmm2 ; SSSE3-NEXT: pand %xmm5, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm2, %xmm3 ; SSSE3-NEXT: por %xmm2, %xmm3
; SSSE3-NEXT: pand %xmm3, %xmm0 ; SSSE3-NEXT: pand %xmm3, %xmm0
; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSSE3-NEXT: por %xmm0, %xmm3 ; SSSE3-NEXT: por %xmm3, %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm1 ; SSSE3-NEXT: pxor %xmm0, %xmm1
; SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [18446744071562067840,18446744071562067840] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [18446744071562067840,18446744071562067840]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm3
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm0, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm2, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSSE3-NEXT: pand %xmm4, %xmm1 ; SSSE3-NEXT: pand %xmm4, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; SSSE3-NEXT: por %xmm1, %xmm0 ; SSSE3-NEXT: por %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm0, %xmm3 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSSE3-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSSE3-NEXT: por %xmm3, %xmm0 ; SSSE3-NEXT: por %xmm2, %xmm0
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_ssat_v2i64_v2i8: ; SSE41-LABEL: trunc_ssat_v2i64_v2i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: movapd {{.*#+}} xmm2 = [127,127] ; SSE41-NEXT: movapd {{.*#+}} xmm2 = [127,127]
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
▲ Show 20 Lines • Show All 246 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pand %xmm6, %xmm1 ; SSE2-NEXT: pand %xmm6, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm1, %xmm4 ; SSE2-NEXT: por %xmm1, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm0 ; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: pandn %xmm8, %xmm4 ; SSE2-NEXT: pandn %xmm8, %xmm4
; SSE2-NEXT: por %xmm0, %xmm4 ; SSE2-NEXT: por %xmm4, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [18446744073709551488,18446744073709551488] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551488,18446744073709551488]
; SSE2-NEXT: movdqa %xmm4, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: pxor %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm2, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562067840,18446744071562067840] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562067840,18446744071562067840]
; SSE2-NEXT: movdqa %xmm0, %xmm6 ; SSE2-NEXT: movdqa %xmm4, %xmm6
; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE2-NEXT: pcmpgtd %xmm5, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: pand %xmm7, %xmm1 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: pand %xmm0, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: pandn %xmm8, %xmm0 ; SSE2-NEXT: pandn %xmm1, %xmm6
; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: pxor %xmm3, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm2
; SSE2-NEXT: movdqa %xmm2, %xmm1 ; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: pcmpgtd %xmm5, %xmm1 ; SSE2-NEXT: pcmpgtd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm2 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE2-NEXT: pand %xmm4, %xmm2 ; SSE2-NEXT: pand %xmm6, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm4
; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: pand %xmm4, %xmm3
; SSE2-NEXT: pandn %xmm8, %xmm1 ; SSE2-NEXT: pandn %xmm1, %xmm4
; SSE2-NEXT: por %xmm3, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,0,0,0,255,0,0,0]
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm0 ; SSE2-NEXT: packuswb %xmm4, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_ssat_v4i64_v4i8: ; SSSE3-LABEL: trunc_ssat_v4i64_v4i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [127,127] ; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [127,127]
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
Show All 18 Lines
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm5, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSSE3-NEXT: pand %xmm6, %xmm1 ; SSSE3-NEXT: pand %xmm6, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm1, %xmm4 ; SSSE3-NEXT: por %xmm1, %xmm4
; SSSE3-NEXT: pand %xmm4, %xmm0 ; SSSE3-NEXT: pand %xmm4, %xmm0
; SSSE3-NEXT: pandn %xmm8, %xmm4 ; SSSE3-NEXT: pandn %xmm8, %xmm4
; SSSE3-NEXT: por %xmm0, %xmm4 ; SSSE3-NEXT: por %xmm4, %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [18446744073709551488,18446744073709551488] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [18446744073709551488,18446744073709551488]
; SSSE3-NEXT: movdqa %xmm4, %xmm0 ; SSSE3-NEXT: movdqa %xmm0, %xmm4
; SSSE3-NEXT: pxor %xmm2, %xmm0 ; SSSE3-NEXT: pxor %xmm2, %xmm4
; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562067840,18446744071562067840] ; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562067840,18446744071562067840]
; SSSE3-NEXT: movdqa %xmm0, %xmm6 ; SSSE3-NEXT: movdqa %xmm4, %xmm6
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6 ; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm0 ; SSSE3-NEXT: pcmpeqd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: pand %xmm7, %xmm1 ; SSSE3-NEXT: pand %xmm7, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSSE3-NEXT: por %xmm1, %xmm0 ; SSSE3-NEXT: por %xmm4, %xmm6
; SSSE3-NEXT: pand %xmm0, %xmm4 ; SSSE3-NEXT: pand %xmm6, %xmm0
; SSSE3-NEXT: pandn %xmm8, %xmm0 ; SSSE3-NEXT: pandn %xmm1, %xmm6
; SSSE3-NEXT: por %xmm4, %xmm0 ; SSSE3-NEXT: por %xmm6, %xmm0
; SSSE3-NEXT: pxor %xmm3, %xmm2 ; SSSE3-NEXT: pxor %xmm3, %xmm2
; SSSE3-NEXT: movdqa %xmm2, %xmm1 ; SSSE3-NEXT: movdqa %xmm2, %xmm4
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm1 ; SSSE3-NEXT: pcmpgtd %xmm5, %xmm4
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,0,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSSE3-NEXT: pcmpeqd %xmm5, %xmm2 ; SSSE3-NEXT: pcmpeqd %xmm5, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSSE3-NEXT: pand %xmm4, %xmm2 ; SSSE3-NEXT: pand %xmm6, %xmm2
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSSE3-NEXT: por %xmm2, %xmm1 ; SSSE3-NEXT: por %xmm2, %xmm4
; SSSE3-NEXT: pand %xmm1, %xmm3 ; SSSE3-NEXT: pand %xmm4, %xmm3
; SSSE3-NEXT: pandn %xmm8, %xmm1 ; SSSE3-NEXT: pandn %xmm1, %xmm4
; SSSE3-NEXT: por %xmm3, %xmm1 ; SSSE3-NEXT: por %xmm3, %xmm4
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = <0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u> ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = <0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
; SSSE3-NEXT: pshufb %xmm2, %xmm1 ; SSSE3-NEXT: pshufb %xmm1, %xmm4
; SSSE3-NEXT: pshufb %xmm2, %xmm0 ; SSSE3-NEXT: pshufb %xmm1, %xmm0
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_ssat_v4i64_v4i8: ; SSE41-LABEL: trunc_ssat_v4i64_v4i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm2 ; SSE41-NEXT: movdqa %xmm0, %xmm2
; SSE41-NEXT: movapd {{.*#+}} xmm4 = [127,127] ; SSE41-NEXT: movapd {{.*#+}} xmm4 = [127,127]
; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648] ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
▲ Show 20 Lines • Show All 2,002 Lines • ▼ Show 20 Lines
define <4 x i8> @trunc_ssat_v4i32_v4i8(<4 x i32> %a0) { define <4 x i8> @trunc_ssat_v4i32_v4i8(<4 x i32> %a0) {
; SSE2-LABEL: trunc_ssat_v4i32_v4i8: ; SSE2-LABEL: trunc_ssat_v4i32_v4i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [127,127,127,127] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [127,127,127,127]
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm2 ; SSE2-NEXT: pandn %xmm1, %xmm2
; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967168,4294967168,4294967168,4294967168] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967168,4294967168,4294967168,4294967168]
; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: pandn %xmm1, %xmm2
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_ssat_v4i32_v4i8: ; SSSE3-LABEL: trunc_ssat_v4i32_v4i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [127,127,127,127] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [127,127,127,127]
; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: movdqa %xmm1, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2 ; SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
; SSSE3-NEXT: pand %xmm2, %xmm0 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pandn %xmm1, %xmm2 ; SSSE3-NEXT: pandn %xmm1, %xmm2
; SSSE3-NEXT: por %xmm0, %xmm2 ; SSSE3-NEXT: por %xmm2, %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4294967168,4294967168,4294967168,4294967168] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [4294967168,4294967168,4294967168,4294967168]
; SSSE3-NEXT: movdqa %xmm2, %xmm0 ; SSSE3-NEXT: movdqa %xmm0, %xmm2
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
; SSSE3-NEXT: pand %xmm0, %xmm2 ; SSSE3-NEXT: pand %xmm2, %xmm0
; SSSE3-NEXT: pandn %xmm1, %xmm0 ; SSSE3-NEXT: pandn %xmm1, %xmm2
; SSSE3-NEXT: por %xmm2, %xmm0 ; SSSE3-NEXT: por %xmm2, %xmm0
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: trunc_ssat_v4i32_v4i8: ; SSE41-LABEL: trunc_ssat_v4i32_v4i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE41-NEXT: pminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE41-NEXT: pmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE41-NEXT: pmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
▲ Show 20 Lines • Show All 1,360 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-trunc-usat.ll

Show First 20 Lines • Show All 2,042 Lines • ▼ Show 20 Lines
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456]
; SSE2-NEXT: pxor %xmm0, %xmm1 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259711,9223372039002259711] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259711,9223372039002259711]
; SSE2-NEXT: movdqa %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm2, %xmm3
; SSE2-NEXT: pcmpgtd %xmm1, %xmm3 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm2, %xmm1 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: pand %xmm4, %xmm2 ; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,1,3,3]
; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm1 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm1 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm1 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_usat_v2i64_v2i8: ; SSSE3-LABEL: trunc_usat_v2i64_v2i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456]
; SSSE3-NEXT: pxor %xmm0, %xmm1 ; SSSE3-NEXT: pxor %xmm0, %xmm1
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259711,9223372039002259711] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259711,9223372039002259711]
; SSSE3-NEXT: movdqa %xmm2, %xmm3 ; SSSE3-NEXT: movdqa %xmm2, %xmm3
▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%3 = trunc <2 x i64> %2 to <2 x i8> %3 = trunc <2 x i64> %2 to <2 x i8>
store <2 x i8> %3, <2 x i8>* %p1 store <2 x i8> %3, <2 x i8>* %p1
ret void ret void
} }
define <4 x i8> @trunc_usat_v4i64_v4i8(<4 x i64> %a0) { define <4 x i8> @trunc_usat_v4i64_v4i8(<4 x i64> %a0) {
; SSE2-LABEL: trunc_usat_v4i64_v4i8: ; SSE2-LABEL: trunc_usat_v4i64_v4i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255]
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [255,255] ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [9223372039002259456,9223372039002259456]
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] ; SSE2-NEXT: movdqa %xmm0, %xmm4
; SSE2-NEXT: pxor %xmm4, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm4
; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259711,9223372039002259711] ; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259711,9223372039002259711]
; SSE2-NEXT: movdqa %xmm5, %xmm6 ; SSE2-NEXT: movdqa %xmm5, %xmm6
; SSE2-NEXT: pcmpgtd %xmm0, %xmm6 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm6
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE2-NEXT: pand %xmm7, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm3, %xmm0
; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: pandn %xmm8, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm4
; SSE2-NEXT: movdqa %xmm5, %xmm2
; SSE2-NEXT: pcmpgtd %xmm4, %xmm2
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm4 ; SSE2-NEXT: pcmpeqd %xmm5, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: pand %xmm3, %xmm4 ; SSE2-NEXT: pand %xmm7, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE2-NEXT: por %xmm4, %xmm2 ; SSE2-NEXT: por %xmm4, %xmm6
; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: pand %xmm6, %xmm0
; SSE2-NEXT: pandn %xmm8, %xmm2 ; SSE2-NEXT: pandn %xmm2, %xmm6
; SSE2-NEXT: por %xmm1, %xmm2 ; SSE2-NEXT: por %xmm6, %xmm0
; SSE2-NEXT: pand %xmm8, %xmm2 ; SSE2-NEXT: pxor %xmm1, %xmm3
; SSE2-NEXT: pand %xmm8, %xmm0 ; SSE2-NEXT: movdqa %xmm5, %xmm4
; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
; SSE2-NEXT: pcmpeqd %xmm5, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE2-NEXT: pand %xmm6, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE2-NEXT: por %xmm3, %xmm4
; SSE2-NEXT: pand %xmm4, %xmm1
; SSE2-NEXT: pandn %xmm2, %xmm4
; SSE2-NEXT: por %xmm1, %xmm4
; SSE2-NEXT: pand %xmm2, %xmm4
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: packuswb %xmm4, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_usat_v4i64_v4i8: ; SSSE3-LABEL: trunc_usat_v4i64_v4i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [255,255] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [255,255]
; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [9223372039002259456,9223372039002259456] ; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [9223372039002259456,9223372039002259456]
▲ Show 20 Lines • Show All 1,302 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%2 = select <16 x i1> %1, <16 x i64> %a0, <16 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255> %2 = select <16 x i1> %1, <16 x i64> %a0, <16 x i64> <i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255, i64 255>
%3 = trunc <16 x i64> %2 to <16 x i8> %3 = trunc <16 x i64> %2 to <16 x i8>
ret <16 x i8> %3 ret <16 x i8> %3
} }
define <4 x i8> @trunc_usat_v4i32_v4i8(<4 x i32> %a0) { define <4 x i8> @trunc_usat_v4i32_v4i8(<4 x i32> %a0) {
; SSE2-LABEL: trunc_usat_v4i32_v4i8: ; SSE2-LABEL: trunc_usat_v4i32_v4i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; SSE2-NEXT: pxor %xmm0, %xmm2 ; SSE2-NEXT: pxor %xmm0, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483903,2147483903,2147483903,2147483903] ; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483903,2147483903,2147483903,2147483903]
; SSE2-NEXT: pcmpgtd %xmm2, %xmm1 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm1 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: packuswb %xmm1, %xmm1 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: trunc_usat_v4i32_v4i8: ; SSSE3-LABEL: trunc_usat_v4i32_v4i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] ; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; SSSE3-NEXT: pxor %xmm0, %xmm1 ; SSSE3-NEXT: pxor %xmm0, %xmm1
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483903,2147483903,2147483903,2147483903] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483903,2147483903,2147483903,2147483903]
; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
▲ Show 20 Lines • Show All 1,259 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-tzcnt-128.ll

Show First 20 Lines • Show All 429 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv4i32: ; SSE3-LABEL: testv4i32:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: paddd %xmm0, %xmm1 ; SSE3-NEXT: paddd %xmm0, %xmm1
; SSE3-NEXT: pandn %xmm1, %xmm0 ; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv4i32: ; SSSE3-LABEL: testv4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSSE3-NEXT: paddd %xmm0, %xmm1 ; SSSE3-NEXT: paddd %xmm0, %xmm1
; SSSE3-NEXT: pandn %xmm1, %xmm0 ; SSSE3-NEXT: pandn %xmm1, %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: psadbw %xmm0, %xmm2 ; SSE2-NEXT: psadbw %xmm1, %xmm2
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: psadbw %xmm0, %xmm1 ; SSE2-NEXT: psadbw %xmm1, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm1 ; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv4i32u: ; SSE3-LABEL: testv4i32u:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: paddd %xmm0, %xmm1 ; SSE3-NEXT: paddd %xmm0, %xmm1
; SSE3-NEXT: pandn %xmm1, %xmm0 ; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: pxor %xmm0, %xmm0 ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: movdqa %xmm1, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE3-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE3-NEXT: psadbw %xmm0, %xmm2 ; SSE3-NEXT: psadbw %xmm1, %xmm2
; SSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE3-NEXT: psadbw %xmm0, %xmm1 ; SSE3-NEXT: psadbw %xmm1, %xmm0
; SSE3-NEXT: packuswb %xmm2, %xmm1 ; SSE3-NEXT: packuswb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv4i32u: ; SSSE3-LABEL: testv4i32u:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSSE3-NEXT: paddd %xmm0, %xmm1 ; SSSE3-NEXT: paddd %xmm0, %xmm1
; SSSE3-NEXT: pandn %xmm1, %xmm0 ; SSSE3-NEXT: pandn %xmm1, %xmm0
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv8i16: ; SSE3-LABEL: testv8i16:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: paddw %xmm0, %xmm1 ; SSE3-NEXT: paddw %xmm0, %xmm1
; SSE3-NEXT: pandn %xmm1, %xmm0 ; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv8i16: ; SSSE3-LABEL: testv8i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSSE3-NEXT: paddw %xmm0, %xmm1 ; SSSE3-NEXT: paddw %xmm0, %xmm1
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: psrlw $2, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddb %xmm2, %xmm0 ; SSE2-NEXT: paddb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: psrlw $4, %xmm1
; SSE2-NEXT: paddb %xmm0, %xmm1 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psllw $8, %xmm0 ; SSE2-NEXT: psllw $8, %xmm1
; SSE2-NEXT: paddb %xmm1, %xmm0 ; SSE2-NEXT: paddb %xmm1, %xmm0
; SSE2-NEXT: psrlw $8, %xmm0 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: testv8i16u: ; SSE3-LABEL: testv8i16u:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSE3-NEXT: paddw %xmm0, %xmm1 ; SSE3-NEXT: paddw %xmm0, %xmm1
; SSE3-NEXT: pandn %xmm1, %xmm0 ; SSE3-NEXT: pandn %xmm1, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $1, %xmm1 ; SSE3-NEXT: psrlw $1, %xmm1
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE3-NEXT: psubb %xmm1, %xmm0 ; SSE3-NEXT: psubb %xmm1, %xmm0
; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; SSE3-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; SSE3-NEXT: movdqa %xmm0, %xmm2 ; SSE3-NEXT: movdqa %xmm0, %xmm2
; SSE3-NEXT: pand %xmm1, %xmm2 ; SSE3-NEXT: pand %xmm1, %xmm2
; SSE3-NEXT: psrlw $2, %xmm0 ; SSE3-NEXT: psrlw $2, %xmm0
; SSE3-NEXT: pand %xmm1, %xmm0 ; SSE3-NEXT: pand %xmm1, %xmm0
; SSE3-NEXT: paddb %xmm2, %xmm0 ; SSE3-NEXT: paddb %xmm2, %xmm0
; SSE3-NEXT: movdqa %xmm0, %xmm1 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psrlw $4, %xmm1 ; SSE3-NEXT: psrlw $4, %xmm1
; SSE3-NEXT: paddb %xmm0, %xmm1 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE3-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE3-NEXT: movdqa %xmm1, %xmm0 ; SSE3-NEXT: movdqa %xmm0, %xmm1
; SSE3-NEXT: psllw $8, %xmm0 ; SSE3-NEXT: psllw $8, %xmm1
; SSE3-NEXT: paddb %xmm1, %xmm0 ; SSE3-NEXT: paddb %xmm1, %xmm0
; SSE3-NEXT: psrlw $8, %xmm0 ; SSE3-NEXT: psrlw $8, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: testv8i16u: ; SSSE3-LABEL: testv8i16u:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1 ; SSSE3-NEXT: pcmpeqd %xmm1, %xmm1
; SSSE3-NEXT: paddw %xmm0, %xmm1 ; SSSE3-NEXT: paddw %xmm0, %xmm1
▲ Show 20 Lines • Show All 747 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vselect-packss.ll

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,0,3,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,0,3,2]
; SSE2-NEXT: pand %xmm2, %xmm3 ; SSE2-NEXT: pand %xmm2, %xmm3
; SSE2-NEXT: packssdw %xmm4, %xmm3 ; SSE2-NEXT: packssdw %xmm4, %xmm3
; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm1 ; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,3,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,3,2]
; SSE2-NEXT: pand %xmm1, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2
; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm0 ; SSE2-NEXT: pcmpeqd {{[0-9]+}}(%rsp), %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,3,2]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: packssdw %xmm2, %xmm1
; SSE2-NEXT: packssdw %xmm3, %xmm1
; SSE2-NEXT: packsswb %xmm5, %xmm1
; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: pandn {{[0-9]+}}(%rsp), %xmm1 ; SSE2-NEXT: packssdw %xmm2, %xmm0
; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: packssdw %xmm3, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: packsswb %xmm5, %xmm0
; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn {{[0-9]+}}(%rsp), %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: vselect_packss_v16i64: ; SSE42-LABEL: vselect_packss_v16i64:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: pcmpeqq {{[0-9]+}}(%rsp), %xmm7 ; SSE42-NEXT: pcmpeqq {{[0-9]+}}(%rsp), %xmm7
; SSE42-NEXT: pcmpeqq {{[0-9]+}}(%rsp), %xmm6 ; SSE42-NEXT: pcmpeqq {{[0-9]+}}(%rsp), %xmm6
; SSE42-NEXT: packssdw %xmm7, %xmm6 ; SSE42-NEXT: packssdw %xmm7, %xmm6
; SSE42-NEXT: pcmpeqq {{[0-9]+}}(%rsp), %xmm5 ; SSE42-NEXT: pcmpeqq {{[0-9]+}}(%rsp), %xmm5
▲ Show 20 Lines • Show All 209 Lines • Show Last 20 Lines