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Differential D112520

[NFC][tblgen] rename function name Decode* to decode*
AbandonedPublic

Authored by achieveartificialintelligence on Oct 26 2021, 12:49 AM.

Details

Reviewers
craig.topper
MaskRay
arsenm
frasercrmck
t.p.northover
kparzysz

Diff Detail

Event Timeline

achieveartificialintelligence created this revision.Oct 26 2021, 12:49 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 25 others. · View Herald TranscriptOct 26 2021, 12:49 AM
achieveartificialintelligence requested review of this revision.Oct 26 2021, 12:49 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 26 2021, 12:49 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
achieveartificialintelligence added a reviewer: MaskRay.Oct 26 2021, 12:50 AM
Harbormaster completed remote builds in B130622: Diff 382213.Oct 26 2021, 1:00 AM
achieveartificialintelligence mentioned this in D93298: [RISCV] add the MC layer support of Zfinx extension.Oct 26 2021, 1:10 AM
frasercrmck added a comment.Oct 26 2021, 1:52 AM

I don't really have a problem with this, but you'd need to update *all* targets - not just RISC-V. Therefore I think it should be opened up to a wider audience.

achieveartificialintelligence retitled this revision from [NFC][tblgen][RISCV] rename function name Decode* to decode* to [NFC][tblgen] rename function name Decode* to decode*.Oct 26 2021, 2:45 AM
achieveartificialintelligence added reviewers: arsenm, frasercrmck, t.p.northover, kparzysz.
Herald added a subscriber: wdng. · View Herald TranscriptOct 26 2021, 2:45 AM
achieveartificialintelligence updated this revision to Diff 382239.Oct 26 2021, 2:46 AM

Update all targets

Herald added subscribers: foad, kerbowa, atanasyan and 8 others. · View Herald TranscriptOct 26 2021, 2:46 AM
achieveartificialintelligence updated this revision to Diff 382241.Oct 26 2021, 2:48 AM

clang-format

Harbormaster completed remote builds in B130646: Diff 382241.Oct 26 2021, 3:27 AM
jrtc27 added a comment.Oct 26 2021, 4:21 AM

What does this actually achieve? As a downstream that adds register classes to multiple backends, whilst it's not difficult to adapt to, it's an annoyance to layer on top of all the other conflicts and refactorings that happen during each release cycle that has very little benefit I can see.

achieveartificialintelligence added a comment.Oct 26 2021, 6:48 AM
In D112520#3086940, @jrtc27 wrote:

What does this actually achieve? As a downstream that adds register classes to multiple backends, whilst it's not difficult to adapt to, it's an annoyance to layer on top of all the other conflicts and refactorings that happen during each release cycle that has very little benefit I can see.

I'm trying to comply with Coding Standards, and I guess other targets may need to do the same?

jrtc27 added a comment.Oct 26 2021, 7:22 AM
In D112520#3087270, @achieveartificialintelligence wrote:
In D112520#3086940, @jrtc27 wrote:

What does this actually achieve? As a downstream that adds register classes to multiple backends, whilst it's not difficult to adapt to, it's an annoyance to layer on top of all the other conflicts and refactorings that happen during each release cycle that has very little benefit I can see.

I'm trying to comply with Coding Standards, and I guess other targets may need to do the same?

I realise, but there are countless violations of that throughout the tree, so I don't get why this one is so special that it needs changing now. Note that the coding standards *also* say:

There are some conventions that are not uniformly followed in the code base (e.g. the naming convention). This is because they are relatively new, and a lot of code was written before they were put in place. Our long term goal is for the entire codebase to follow the convention, but we explicitly do not want patches that do large-scale reformatting of existing code. On the other hand, it is reasonable to rename the methods of a class if you’re about to change it in some other way. Please commit such changes separately to make code review easier.

achieveartificialintelligence abandoned this revision.Oct 31 2021, 9:20 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
2 lines
Disassembler/
322 lines
AMDGPU/
Disassembler/
10 lines
20 lines
ARC/
Disassembler/
22 lines
ARM/
8 lines
6 lines
Disassembler/
656 lines
AVR/
Disassembler/
28 lines
BPF/
Disassembler/
4 lines
Hexagon/
Disassembler/
90 lines
Lanai/
Disassembler/
4 lines
MSP430/
Disassembler/
8 lines
14 lines
Mips/
Disassembler/
124 lines
2 lines
PowerPC/
Disassembler/
42 lines
RISCV/
Disassembler/
48 lines
Sparc/
Disassembler/
74 lines
SystemZ/
Disassembler/
26 lines
VE/
Disassembler/
50 lines
XCore/
Disassembler/
124 lines
utils/
TableGen/
8 lines

Diff 382239

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Show First 20 Lines • Show All 1,349 Lines • ▼ Show 20 Linesclass MatrixTileListAsmOperand : AsmOperandClass {
let Name = "MatrixTileList"; let Name = "MatrixTileList";
let ParserMethod = "tryParseMatrixTileList"; let ParserMethod = "tryParseMatrixTileList";
let RenderMethod = "addMatrixTileListOperands"; let RenderMethod = "addMatrixTileListOperands";
let PredicateMethod = "isMatrixTileList"; let PredicateMethod = "isMatrixTileList";
} }
class MatrixTileListOperand : Operand<i8> { class MatrixTileListOperand : Operand<i8> {
let ParserMatchClass = MatrixTileListAsmOperand<>; let ParserMatchClass = MatrixTileListAsmOperand<>;
let DecoderMethod = "DecodeMatrixTileListRegisterClass"; let DecoderMethod = "decodeMatrixTileListRegisterClass";
let EncoderMethod = "EncodeMatrixTileListRegisterClass"; let EncoderMethod = "EncodeMatrixTileListRegisterClass";
let PrintMethod = "printMatrixTileList"; let PrintMethod = "printMatrixTileList";
} }
def MatrixTileList : MatrixTileListOperand<>; def MatrixTileList : MatrixTileListOperand<>;
def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)> { def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)> {
let DiagnosticType = "InvalidMatrixIndexGPR32_12_15"; let DiagnosticType = "InvalidMatrixIndexGPR32_12_15";
Show All 21 Lines

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// //
Show All 22 Lines
#define DEBUG_TYPE "aarch64-disassembler" #define DEBUG_TYPE "aarch64-disassembler"
// Pull DecodeStatus and its enum values into the global namespace. // Pull DecodeStatus and its enum values into the global namespace.
using DecodeStatus = MCDisassembler::DecodeStatus; using DecodeStatus = MCDisassembler::DecodeStatus;
// Forward declare these because the autogenerated code will reference them. // Forward declare these because the autogenerated code will reference them.
// Definitions are further down. // Definitions are further down.
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, static DecodeStatus decodeFPR128RegisterClass(MCInst &Inst,
unsigned RegNo, uint64_t Address, unsigned RegNo, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, static DecodeStatus decodeFPR128_loRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, static DecodeStatus decodeGPR64x8ClassRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, static DecodeStatus decodeGPR64spRegisterClass(MCInst &Inst,
unsigned RegNo, uint64_t Address, unsigned RegNo, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, static DecodeStatus decodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, static DecodeStatus decodeGPR32spRegisterClass(MCInst &Inst,
unsigned RegNo, uint64_t Address, unsigned RegNo, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
template <unsigned NumBitsForTile> template <unsigned NumBitsForTile>
static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, static DecodeStatus decodeMatrixTileListRegisterClass(MCInst &Inst,
unsigned RegMask, unsigned RegMask,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
uint64_t Address, uint64_t Address,
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder); uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder); uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder); uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder); uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, static DecodeStatus decodeWSeqPairsClassRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, static DecodeStatus decodeXSeqPairsClassRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
template <int Bits> template <int Bits>
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Linesextern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(), TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
createAArch64Disassembler); createAArch64Disassembler);
TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(), TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
createAArch64ExternalSymbolizer); createAArch64ExternalSymbolizer);
} }
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return Fail; return Fail;
return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); return decodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
} }
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 30) if (RegNo > 30)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister( AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
RegNo); RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst, static DecodeStatus decodeGPR64x8ClassRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 22) if (RegNo > 22)
return Fail; return Fail;
if (RegNo & 1) if (RegNo & 1)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister( AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
RegNo >> 1); RegNo >> 1);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, static DecodeStatus decodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 3) if (RegNo > 3)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID] AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
.getRegister(RegNo); .getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void* Decoder) { const void* Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return Fail; return Fail;
return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return Fail; return Fail;
return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void* Decoder) { const void* Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void* Decoder) { const void* Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void* Decoder) { const void* Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, static DecodeStatus decodeMatrixTileListRegisterClass(MCInst &Inst,
unsigned RegMask, unsigned RegMask,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegMask > 0xFF) if (RegMask > 0xFF)
return Fail; return Fail;
Inst.addOperand(MCOperand::createImm(RegMask)); Inst.addOperand(MCOperand::createImm(RegMask));
return Success; return Success;
} }
Show All 16 Linesstatic DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
unsigned LastReg = (1 << NumBitsForTile) - 1; unsigned LastReg = (1 << NumBitsForTile) - 1;
if (RegNo > LastReg) if (RegNo > LastReg)
return Fail; return Fail;
Inst.addOperand( Inst.addOperand(
MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo])); MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
return Success; return Success;
} }
static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void* Decoder) { const void* Decoder) {
if (RegNo > 7) if (RegNo > 7)
return Fail; return Fail;
// Just reuse the PPR decode table // Just reuse the PPR decode table
return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); return decodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
} }
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
} }
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return Fail; return Fail;
unsigned Register = unsigned Register =
AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo); AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return Success; return Success;
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
const void *Decoder) { const void *Decoder) {
// This decoder exists to add the dummy Lane operand to the MCInst, which must // This decoder exists to add the dummy Lane operand to the MCInst, which must
// be 1 in assembly but has no other real manifestation. // be 1 in assembly but has no other real manifestation.
unsigned Rd = fieldFromInstruction(Insn, 0, 5); unsigned Rd = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5); unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
if (IsToVec) { if (IsToVec) {
DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); decodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); decodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
} else { } else {
DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); decodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); decodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
} }
// Add the lane // Add the lane
Inst.addOperand(MCOperand::createImm(1)); Inst.addOperand(MCOperand::createImm(1));
return Success; return Success;
} }
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
case AArch64::BICSWrs: case AArch64::BICSWrs:
case AArch64::ORRWrs: case AArch64::ORRWrs:
case AArch64::ORNWrs: case AArch64::ORNWrs:
case AArch64::EORWrs: case AArch64::EORWrs:
case AArch64::EONWrs: { case AArch64::EONWrs: {
// if sf == '0' and imm6<5> == '1' then ReservedValue() // if sf == '0' and imm6<5> == '1' then ReservedValue()
if (shiftLo >> 5 == 1) if (shiftLo >> 5 == 1)
return Fail; return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
} }
case AArch64::ADDXrs: case AArch64::ADDXrs:
case AArch64::ADDSXrs: case AArch64::ADDSXrs:
case AArch64::SUBXrs: case AArch64::SUBXrs:
case AArch64::SUBSXrs: case AArch64::SUBSXrs:
// if shift == '11' then ReservedValue() // if shift == '11' then ReservedValue()
if (shiftHi == 0x3) if (shiftHi == 0x3)
return Fail; return Fail;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::ANDXrs: case AArch64::ANDXrs:
case AArch64::ANDSXrs: case AArch64::ANDSXrs:
case AArch64::BICXrs: case AArch64::BICXrs:
case AArch64::BICSXrs: case AArch64::BICSXrs:
case AArch64::ORRXrs: case AArch64::ORRXrs:
case AArch64::ORNXrs: case AArch64::ORNXrs:
case AArch64::EORXrs: case AArch64::EORXrs:
case AArch64::EONXrs: case AArch64::EONXrs:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
} }
Inst.addOperand(MCOperand::createImm(shift)); Inst.addOperand(MCOperand::createImm(shift));
return Success; return Success;
} }
static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned imm = fieldFromInstruction(insn, 5, 16); unsigned imm = fieldFromInstruction(insn, 5, 16);
unsigned shift = fieldFromInstruction(insn, 21, 2); unsigned shift = fieldFromInstruction(insn, 21, 2);
shift <<= 4; shift <<= 4;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: default:
return Fail; return Fail;
case AArch64::MOVZWi: case AArch64::MOVZWi:
case AArch64::MOVNWi: case AArch64::MOVNWi:
case AArch64::MOVKWi: case AArch64::MOVKWi:
if (shift & (1U << 5)) if (shift & (1U << 5))
return Fail; return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
break; break;
case AArch64::MOVZXi: case AArch64::MOVZXi:
case AArch64::MOVNXi: case AArch64::MOVNXi:
case AArch64::MOVKXi: case AArch64::MOVKXi:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
break; break;
} }
if (Inst.getOpcode() == AArch64::MOVKWi || if (Inst.getOpcode() == AArch64::MOVKWi ||
Inst.getOpcode() == AArch64::MOVKXi) Inst.getOpcode() == AArch64::MOVKXi)
Inst.addOperand(Inst.getOperand(0)); Inst.addOperand(Inst.getOperand(0));
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
Show All 20 Linesstatic DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
case AArch64::STRBBui: case AArch64::STRBBui:
case AArch64::LDRBBui: case AArch64::LDRBBui:
case AArch64::LDRSBWui: case AArch64::LDRSBWui:
case AArch64::STRHHui: case AArch64::STRHHui:
case AArch64::LDRHHui: case AArch64::LDRHHui:
case AArch64::LDRSHWui: case AArch64::LDRSHWui:
case AArch64::STRWui: case AArch64::STRWui:
case AArch64::LDRWui: case AArch64::LDRWui:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDRSBXui: case AArch64::LDRSBXui:
case AArch64::LDRSHXui: case AArch64::LDRSHXui:
case AArch64::LDRSWui: case AArch64::LDRSWui:
case AArch64::STRXui: case AArch64::STRXui:
case AArch64::LDRXui: case AArch64::LDRXui:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDRQui: case AArch64::LDRQui:
case AArch64::STRQui: case AArch64::STRQui:
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDRDui: case AArch64::LDRDui:
case AArch64::STRDui: case AArch64::STRDui:
DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDRSui: case AArch64::LDRSui:
case AArch64::STRSui: case AArch64::STRSui:
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDRHui: case AArch64::LDRHui:
case AArch64::STRHui: case AArch64::STRHui:
DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDRBui: case AArch64::LDRBui:
case AArch64::STRBui: case AArch64::STRBui:
DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
} }
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Inst.addOperand(MCOperand::createImm(offset)); Inst.addOperand(MCOperand::createImm(offset));
return Success; return Success;
} }
static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
case AArch64::LDRHpre: case AArch64::LDRHpre:
case AArch64::STRHpre: case AArch64::STRHpre:
case AArch64::LDRHpost: case AArch64::LDRHpost:
case AArch64::STRHpost: case AArch64::STRHpost:
case AArch64::LDRBpre: case AArch64::LDRBpre:
case AArch64::STRBpre: case AArch64::STRBpre:
case AArch64::LDRBpost: case AArch64::LDRBpost:
case AArch64::STRBpost: case AArch64::STRBpost:
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
break; break;
} }
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: default:
return Fail; return Fail;
case AArch64::PRFUMi: case AArch64::PRFUMi:
// Rt is an immediate in prefetch. // Rt is an immediate in prefetch.
Show All 34 Linesstatic DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
case AArch64::STLURBi: case AArch64::STLURBi:
case AArch64::STLURHi: case AArch64::STLURHi:
case AArch64::STLURWi: case AArch64::STLURWi:
case AArch64::LDAPURBi: case AArch64::LDAPURBi:
case AArch64::LDAPURSBWi: case AArch64::LDAPURSBWi:
case AArch64::LDAPURHi: case AArch64::LDAPURHi:
case AArch64::LDAPURSHWi: case AArch64::LDAPURSHWi:
case AArch64::LDAPURi: case AArch64::LDAPURi:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDURSBXi: case AArch64::LDURSBXi:
case AArch64::LDURSHXi: case AArch64::LDURSHXi:
case AArch64::LDURSWi: case AArch64::LDURSWi:
case AArch64::STURXi: case AArch64::STURXi:
case AArch64::LDURXi: case AArch64::LDURXi:
case AArch64::LDTRSBXi: case AArch64::LDTRSBXi:
case AArch64::LDTRSHXi: case AArch64::LDTRSHXi:
Show All 10 Linesstatic DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
case AArch64::STRXpost: case AArch64::STRXpost:
case AArch64::LDRSWpost: case AArch64::LDRSWpost:
case AArch64::LDRXpost: case AArch64::LDRXpost:
case AArch64::LDAPURSWi: case AArch64::LDAPURSWi:
case AArch64::LDAPURSHXi: case AArch64::LDAPURSHXi:
case AArch64::LDAPURSBXi: case AArch64::LDAPURSBXi:
case AArch64::STLURXi: case AArch64::STLURXi:
case AArch64::LDAPURXi: case AArch64::LDAPURXi:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDURQi: case AArch64::LDURQi:
case AArch64::STURQi: case AArch64::STURQi:
case AArch64::LDRQpre: case AArch64::LDRQpre:
case AArch64::STRQpre: case AArch64::STRQpre:
case AArch64::LDRQpost: case AArch64::LDRQpost:
case AArch64::STRQpost: case AArch64::STRQpost:
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDURDi: case AArch64::LDURDi:
case AArch64::STURDi: case AArch64::STURDi:
case AArch64::LDRDpre: case AArch64::LDRDpre:
case AArch64::STRDpre: case AArch64::STRDpre:
case AArch64::LDRDpost: case AArch64::LDRDpost:
case AArch64::STRDpost: case AArch64::STRDpost:
DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDURSi: case AArch64::LDURSi:
case AArch64::STURSi: case AArch64::STURSi:
case AArch64::LDRSpre: case AArch64::LDRSpre:
case AArch64::STRSpre: case AArch64::STRSpre:
case AArch64::LDRSpost: case AArch64::LDRSpost:
case AArch64::STRSpost: case AArch64::STRSpost:
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDURHi: case AArch64::LDURHi:
case AArch64::STURHi: case AArch64::STURHi:
case AArch64::LDRHpre: case AArch64::LDRHpre:
case AArch64::STRHpre: case AArch64::STRHpre:
case AArch64::LDRHpost: case AArch64::LDRHpost:
case AArch64::STRHpost: case AArch64::STRHpost:
DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::LDURBi: case AArch64::LDURBi:
case AArch64::STURBi: case AArch64::STURBi:
case AArch64::LDRBpre: case AArch64::LDRBpre:
case AArch64::STRBpre: case AArch64::STRBpre:
case AArch64::LDRBpost: case AArch64::LDRBpost:
case AArch64::STRBpost: case AArch64::STRBpost:
DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
} }
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(offset)); Inst.addOperand(MCOperand::createImm(offset));
bool IsLoad = fieldFromInstruction(insn, 22, 1); bool IsLoad = fieldFromInstruction(insn, 22, 1);
bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
bool IsFP = fieldFromInstruction(insn, 26, 1); bool IsFP = fieldFromInstruction(insn, 26, 1);
// Cannot write back to a transfer register (but xzr != sp). // Cannot write back to a transfer register (but xzr != sp).
if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
Show All 15 Linesstatic DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
default: default:
return Fail; return Fail;
case AArch64::STLXRW: case AArch64::STLXRW:
case AArch64::STLXRB: case AArch64::STLXRB:
case AArch64::STLXRH: case AArch64::STLXRH:
case AArch64::STXRW: case AArch64::STXRW:
case AArch64::STXRB: case AArch64::STXRB:
case AArch64::STXRH: case AArch64::STXRH:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::LDARW: case AArch64::LDARW:
case AArch64::LDARB: case AArch64::LDARB:
case AArch64::LDARH: case AArch64::LDARH:
case AArch64::LDAXRW: case AArch64::LDAXRW:
case AArch64::LDAXRB: case AArch64::LDAXRB:
case AArch64::LDAXRH: case AArch64::LDAXRH:
case AArch64::LDXRW: case AArch64::LDXRW:
case AArch64::LDXRB: case AArch64::LDXRB:
case AArch64::LDXRH: case AArch64::LDXRH:
case AArch64::STLRW: case AArch64::STLRW:
case AArch64::STLRB: case AArch64::STLRB:
case AArch64::STLRH: case AArch64::STLRH:
case AArch64::STLLRW: case AArch64::STLLRW:
case AArch64::STLLRB: case AArch64::STLLRB:
case AArch64::STLLRH: case AArch64::STLLRH:
case AArch64::LDLARW: case AArch64::LDLARW:
case AArch64::LDLARB: case AArch64::LDLARB:
case AArch64::LDLARH: case AArch64::LDLARH:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::STLXRX: case AArch64::STLXRX:
case AArch64::STXRX: case AArch64::STXRX:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::LDARX: case AArch64::LDARX:
case AArch64::LDAXRX: case AArch64::LDAXRX:
case AArch64::LDXRX: case AArch64::LDXRX:
case AArch64::STLRX: case AArch64::STLRX:
case AArch64::LDLARX: case AArch64::LDLARX:
case AArch64::STLLRX: case AArch64::STLLRX:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
break; break;
case AArch64::STLXPW: case AArch64::STLXPW:
case AArch64::STXPW: case AArch64::STXPW:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::LDAXPW: case AArch64::LDAXPW:
case AArch64::LDXPW: case AArch64::LDXPW:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
break; break;
case AArch64::STLXPX: case AArch64::STLXPX:
case AArch64::STXPX: case AArch64::STXPX:
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::LDAXPX: case AArch64::LDAXPX:
case AArch64::LDXPX: case AArch64::LDXPX:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
break; break;
} }
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
// You shouldn't load to the same register twice in an instruction... // You shouldn't load to the same register twice in an instruction...
if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
Rt == Rt2) Rt == Rt2)
return SoftFail; return SoftFail;
return Success; return Success;
Show All 39 Linesstatic DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
case AArch64::LDPDpre: case AArch64::LDPDpre:
case AArch64::STPDpre: case AArch64::STPDpre:
case AArch64::LDPSpost: case AArch64::LDPSpost:
case AArch64::STPSpost: case AArch64::STPSpost:
case AArch64::LDPSpre: case AArch64::LDPSpre:
case AArch64::STPSpre: case AArch64::STPSpre:
case AArch64::STGPpre: case AArch64::STGPpre:
case AArch64::STGPpost: case AArch64::STGPpost:
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
break; break;
} }
switch (Opcode) { switch (Opcode) {
default: default:
return Fail; return Fail;
case AArch64::LDPXpost: case AArch64::LDPXpost:
case AArch64::STPXpost: case AArch64::STPXpost:
case AArch64::LDPSWpost: case AArch64::LDPSWpost:
case AArch64::LDPXpre: case AArch64::LDPXpre:
case AArch64::STPXpre: case AArch64::STPXpre:
case AArch64::LDPSWpre: case AArch64::LDPSWpre:
case AArch64::STGPpre: case AArch64::STGPpre:
case AArch64::STGPpost: case AArch64::STGPpost:
NeedsDisjointWritebackTransfer = true; NeedsDisjointWritebackTransfer = true;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::LDNPXi: case AArch64::LDNPXi:
case AArch64::STNPXi: case AArch64::STNPXi:
case AArch64::LDPXi: case AArch64::LDPXi:
case AArch64::STPXi: case AArch64::STPXi:
case AArch64::LDPSWi: case AArch64::LDPSWi:
case AArch64::STGPi: case AArch64::STGPi:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
break; break;
case AArch64::LDPWpost: case AArch64::LDPWpost:
case AArch64::STPWpost: case AArch64::STPWpost:
case AArch64::LDPWpre: case AArch64::LDPWpre:
case AArch64::STPWpre: case AArch64::STPWpre:
NeedsDisjointWritebackTransfer = true; NeedsDisjointWritebackTransfer = true;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case AArch64::LDNPWi: case AArch64::LDNPWi:
case AArch64::STNPWi: case AArch64::STNPWi:
case AArch64::LDPWi: case AArch64::LDPWi:
case AArch64::STPWi: case AArch64::STPWi:
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
break; break;
case AArch64::LDNPQi: case AArch64::LDNPQi:
case AArch64::STNPQi: case AArch64::STNPQi:
case AArch64::LDPQpost: case AArch64::LDPQpost:
case AArch64::STPQpost: case AArch64::STPQpost:
case AArch64::LDPQi: case AArch64::LDPQi:
case AArch64::STPQi: case AArch64::STPQi:
case AArch64::LDPQpre: case AArch64::LDPQpre:
case AArch64::STPQpre: case AArch64::STPQpre:
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); decodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
break; break;
case AArch64::LDNPDi: case AArch64::LDNPDi:
case AArch64::STNPDi: case AArch64::STNPDi:
case AArch64::LDPDpost: case AArch64::LDPDpost:
case AArch64::STPDpost: case AArch64::STPDpost:
case AArch64::LDPDi: case AArch64::LDPDi:
case AArch64::STPDi: case AArch64::STPDi:
case AArch64::LDPDpre: case AArch64::LDPDpre:
case AArch64::STPDpre: case AArch64::STPDpre:
DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); decodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
break; break;
case AArch64::LDNPSi: case AArch64::LDNPSi:
case AArch64::STNPSi: case AArch64::STNPSi:
case AArch64::LDPSpost: case AArch64::LDPSpost:
case AArch64::STPSpost: case AArch64::STPSpost:
case AArch64::LDPSi: case AArch64::LDPSi:
case AArch64::STPSi: case AArch64::STPSi:
case AArch64::LDPSpre: case AArch64::LDPSpre:
case AArch64::STPSpre: case AArch64::STPSpre:
DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); decodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
break; break;
} }
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(offset)); Inst.addOperand(MCOperand::createImm(offset));
// You shouldn't load to the same register twice in an instruction... // You shouldn't load to the same register twice in an instruction...
if (IsLoad && Rt == Rt2) if (IsLoad && Rt == Rt2)
return SoftFail; return SoftFail;
// ... or do any operation that writes-back to a transfer register. But note // ... or do any operation that writes-back to a transfer register. But note
// that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
Show All 12 Lines uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
fieldFromInstruction(insn, 12, 9); fieldFromInstruction(insn, 12, 9);
unsigned writeback = fieldFromInstruction(insn, 11, 1); unsigned writeback = fieldFromInstruction(insn, 11, 1);
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: default:
return Fail; return Fail;
case AArch64::LDRAAwriteback: case AArch64::LDRAAwriteback:
case AArch64::LDRABwriteback: case AArch64::LDRABwriteback:
DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr, decodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
Decoder); Decoder);
break; break;
case AArch64::LDRAAindexed: case AArch64::LDRAAindexed:
case AArch64::LDRABindexed: case AArch64::LDRABindexed:
break; break;
} }
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeSImm<10>(Inst, offset, Addr, Decoder); DecodeSImm<10>(Inst, offset, Addr, Decoder);
if (writeback && Rt == Rn && Rn != 31) { if (writeback && Rt == Rn && Rn != 31) {
return SoftFail; return SoftFail;
} }
return Success; return Success;
} }
Show All 10 Linesstatic DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
if (shift > 4) if (shift > 4)
return Fail; return Fail;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: default:
return Fail; return Fail;
case AArch64::ADDWrx: case AArch64::ADDWrx:
case AArch64::SUBWrx: case AArch64::SUBWrx:
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
case AArch64::ADDSWrx: case AArch64::ADDSWrx:
case AArch64::SUBSWrx: case AArch64::SUBSWrx:
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
case AArch64::ADDXrx: case AArch64::ADDXrx:
case AArch64::SUBXrx: case AArch64::SUBXrx:
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
case AArch64::ADDSXrx: case AArch64::ADDSXrx:
case AArch64::SUBSXrx: case AArch64::SUBSXrx:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
case AArch64::ADDXrx64: case AArch64::ADDXrx64:
case AArch64::SUBXrx64: case AArch64::SUBXrx64:
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
case AArch64::SUBSXrx64: case AArch64::SUBSXrx64:
case AArch64::ADDSXrx64: case AArch64::ADDSXrx64:
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
break; break;
} }
Inst.addOperand(MCOperand::createImm(extend)); Inst.addOperand(MCOperand::createImm(extend));
return Success; return Success;
} }
static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Datasize = fieldFromInstruction(insn, 31, 1); unsigned Datasize = fieldFromInstruction(insn, 31, 1);
unsigned imm; unsigned imm;
if (Datasize) { if (Datasize) {
if (Inst.getOpcode() == AArch64::ANDSXri) if (Inst.getOpcode() == AArch64::ANDSXri)
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
else else
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 13); imm = fieldFromInstruction(insn, 10, 13);
if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
return Fail; return Fail;
} else { } else {
if (Inst.getOpcode() == AArch64::ANDSWri) if (Inst.getOpcode() == AArch64::ANDSWri)
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
else else
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
imm = fieldFromInstruction(insn, 10, 12); imm = fieldFromInstruction(insn, 10, 12);
if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
return Fail; return Fail;
} }
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return Success; return Success;
} }
static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4); unsigned cmode = fieldFromInstruction(insn, 12, 4);
unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
imm |= fieldFromInstruction(insn, 5, 5); imm |= fieldFromInstruction(insn, 5, 5);
if (Inst.getOpcode() == AArch64::MOVID) if (Inst.getOpcode() == AArch64::MOVID)
DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
else else
DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); decodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: default:
break; break;
case AArch64::MOVIv4i16: case AArch64::MOVIv4i16:
case AArch64::MOVIv8i16: case AArch64::MOVIv8i16:
Show All 20 Linesstatic DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4); unsigned cmode = fieldFromInstruction(insn, 12, 4);
unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
imm |= fieldFromInstruction(insn, 5, 5); imm |= fieldFromInstruction(insn, 5, 5);
// Tied operands added twice. // Tied operands added twice.
DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); decodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder); decodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
return Success; return Success;
} }
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
imm |= fieldFromInstruction(insn, 29, 2); imm |= fieldFromInstruction(insn, 29, 2);
const AArch64Disassembler *Dis = const AArch64Disassembler *Dis =
static_cast<const AArch64Disassembler *>(Decoder); static_cast<const AArch64Disassembler *>(Decoder);
// Sign-extend the 21-bit immediate. // Sign-extend the 21-bit immediate.
if (imm & (1 << (21 - 1))) if (imm & (1 << (21 - 1)))
imm |= ~((1LL << 21) - 1); imm |= ~((1LL << 21) - 1);
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return Success; return Success;
} }
static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5); unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Imm = fieldFromInstruction(insn, 10, 14); unsigned Imm = fieldFromInstruction(insn, 10, 14);
unsigned S = fieldFromInstruction(insn, 29, 1); unsigned S = fieldFromInstruction(insn, 29, 1);
unsigned Datasize = fieldFromInstruction(insn, 31, 1); unsigned Datasize = fieldFromInstruction(insn, 31, 1);
unsigned ShifterVal = (Imm >> 12) & 3; unsigned ShifterVal = (Imm >> 12) & 3;
unsigned ImmVal = Imm & 0xFFF; unsigned ImmVal = Imm & 0xFFF;
const AArch64Disassembler *Dis = const AArch64Disassembler *Dis =
static_cast<const AArch64Disassembler *>(Decoder); static_cast<const AArch64Disassembler *>(Decoder);
if (ShifterVal != 0 && ShifterVal != 1) if (ShifterVal != 0 && ShifterVal != 1)
return Fail; return Fail;
if (Datasize) { if (Datasize) {
if (Rd == 31 && !S) if (Rd == 31 && !S)
DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
else else
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
} else { } else {
if (Rd == 31 && !S) if (Rd == 31 && !S)
DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
else else
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); decodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
} }
if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Inst.addOperand(MCOperand::createImm(ImmVal)); Inst.addOperand(MCOperand::createImm(ImmVal));
Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
return Success; return Success;
} }
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
const AArch64Disassembler *Dis = const AArch64Disassembler *Dis =
static_cast<const AArch64Disassembler *>(Decoder); static_cast<const AArch64Disassembler *>(Decoder);
// Sign-extend 14-bit immediate. // Sign-extend 14-bit immediate.
if (dst & (1 << (14 - 1))) if (dst & (1 << (14 - 1)))
dst |= ~((1LL << 14) - 1); dst |= ~((1LL << 14) - 1);
if (fieldFromInstruction(insn, 31, 1) == 0) if (fieldFromInstruction(insn, 31, 1) == 0)
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
else else
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); decodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(bit)); Inst.addOperand(MCOperand::createImm(bit));
if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Inst.addOperand(MCOperand::createImm(dst)); Inst.addOperand(MCOperand::createImm(dst));
return Success; return Success;
} }
static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
unsigned RegClassID, unsigned RegClassID,
unsigned RegNo, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
// Register number must be even (see CASP instruction) // Register number must be even (see CASP instruction)
if (RegNo & 0x1) if (RegNo & 0x1)
return Fail; return Fail;
unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return Success; return Success;
} }
static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, static DecodeStatus decodeWSeqPairsClassRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
return DecodeGPRSeqPairsClassRegisterClass(Inst, return decodeGPRSeqPairsClassRegisterClass(Inst,
AArch64::WSeqPairsClassRegClassID, AArch64::WSeqPairsClassRegClassID,
RegNo, Addr, Decoder); RegNo, Addr, Decoder);
} }
static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, static DecodeStatus decodeXSeqPairsClassRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
return DecodeGPRSeqPairsClassRegisterClass(Inst, return decodeGPRSeqPairsClassRegisterClass(Inst,
AArch64::XSeqPairsClassRegClassID, AArch64::XSeqPairsClassRegClassID,
RegNo, Addr, Decoder); RegNo, Addr, Decoder);
} }
static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
unsigned Zdn = fieldFromInstruction(insn, 0, 5); unsigned Zdn = fieldFromInstruction(insn, 0, 5);
unsigned imm = fieldFromInstruction(insn, 5, 13); unsigned imm = fieldFromInstruction(insn, 5, 13);
if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
return Fail; return Fail;
// The same (tied) operand is added twice to the instruction. // The same (tied) operand is added twice to the instruction.
DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); decodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
if (Inst.getOpcode() != AArch64::DUPM_ZI) if (Inst.getOpcode() != AArch64::DUPM_ZI)
DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); decodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return Success; return Success;
} }
template <int Bits> template <int Bits>
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address, static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (Imm & ~((1LL << Bits) - 1)) if (Imm & ~((1LL << Bits) - 1))
Show All 38 Lines

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

//===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Linesstatic DecodeStatus StaticDecoderName(MCInst &Inst, \
unsigned Imm, \ unsigned Imm, \
uint64_t /*Addr*/, \ uint64_t /*Addr*/, \
const void *Decoder) { \ const void *Decoder) { \
auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
return addOperand(Inst, DAsm->DecoderName(Imm)); \ return addOperand(Inst, DAsm->DecoderName(Imm)); \
} }
#define DECODE_OPERAND_REG(RegClass) \ #define DECODE_OPERAND_REG(RegClass) \
DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) DECODE_OPERAND(decode##RegClass##RegisterClass, decodeOperand_##RegClass)
DECODE_OPERAND_REG(VGPR_32) DECODE_OPERAND_REG(VGPR_32)
DECODE_OPERAND_REG(VRegOrLds_32) DECODE_OPERAND_REG(VRegOrLds_32)
DECODE_OPERAND_REG(VS_32) DECODE_OPERAND_REG(VS_32)
DECODE_OPERAND_REG(VS_64) DECODE_OPERAND_REG(VS_64)
DECODE_OPERAND_REG(VS_128) DECODE_OPERAND_REG(VS_128)
DECODE_OPERAND_REG(VReg_64) DECODE_OPERAND_REG(VReg_64)
▲ Show 20 Lines • Show All 214 Lines • ▼ Show 20 Lines if (TSFlags & SIInstrFlags::DS) {
if ((int)Inst.getNumOperands() == Data2Idx && if ((int)Inst.getNumOperands() == Data2Idx &&
IsAGPROperand(Inst, DataIdx, MRI)) IsAGPROperand(Inst, DataIdx, MRI))
Imm |= 512; Imm |= 512;
} }
} }
return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
} }
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, static DecodeStatus decodeAVLdSt_32RegisterClass(MCInst &Inst,
unsigned Imm, unsigned Imm,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
return decodeOperand_AVLdSt_Any(Inst, Imm, return decodeOperand_AVLdSt_Any(Inst, Imm,
AMDGPUDisassembler::OPW32, Decoder); AMDGPUDisassembler::OPW32, Decoder);
} }
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, static DecodeStatus decodeAVLdSt_64RegisterClass(MCInst &Inst,
unsigned Imm, unsigned Imm,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
return decodeOperand_AVLdSt_Any(Inst, Imm, return decodeOperand_AVLdSt_Any(Inst, Imm,
AMDGPUDisassembler::OPW64, Decoder); AMDGPUDisassembler::OPW64, Decoder);
} }
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, static DecodeStatus decodeAVLdSt_96RegisterClass(MCInst &Inst,
unsigned Imm, unsigned Imm,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
return decodeOperand_AVLdSt_Any(Inst, Imm, return decodeOperand_AVLdSt_Any(Inst, Imm,
AMDGPUDisassembler::OPW96, Decoder); AMDGPUDisassembler::OPW96, Decoder);
} }
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, static DecodeStatus decodeAVLdSt_128RegisterClass(MCInst &Inst,
unsigned Imm, unsigned Imm,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
return decodeOperand_AVLdSt_Any(Inst, Imm, return decodeOperand_AVLdSt_Any(Inst, Imm,
AMDGPUDisassembler::OPW128, Decoder); AMDGPUDisassembler::OPW128, Decoder);
} }
static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
▲ Show 20 Lines • Show All 1,572 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Show First 20 Lines • Show All 1,010 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm VSrc : RegImmOperand<"VS", "VSrc">; defm VSrc : RegImmOperand<"VS", "VSrc">;
def VSrc_128 : RegisterOperand<VReg_128> { def VSrc_128 : RegisterOperand<VReg_128> {
let DecoderMethod = "DecodeVS_128RegisterClass"; let DecoderMethod = "decodeVS_128RegisterClass";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use // VSrc_*_Deferred Operands with an SGPR, VGPR or a 32-bit immediate for use
// with FMAMK/FMAAK // with FMAMK/FMAAK
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass SIRegOperand32_Deferred <string rc, string MatchName, string opType, multiclass SIRegOperand32_Deferred <string rc, string MatchName, string opType,
Show All 18 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VRegSrc_* Operands with a VGPR // VRegSrc_* Operands with a VGPR
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// This is for operands with the enum(9), VSrc encoding restriction, // This is for operands with the enum(9), VSrc encoding restriction,
// but only allows VGPRs. // but only allows VGPRs.
def VRegSrc_32 : RegisterOperand<VGPR_32> { def VRegSrc_32 : RegisterOperand<VGPR_32> {
//let ParserMatchClass = RegImmMatcher<"VRegSrc32">; //let ParserMatchClass = RegImmMatcher<"VRegSrc32">;
let DecoderMethod = "DecodeVS_32RegisterClass"; let DecoderMethod = "decodeVS_32RegisterClass";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ASrc_* Operands with an AccVGPR // ASrc_* Operands with an AccVGPR
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ARegSrc_32 : RegisterOperand<AGPR_32> { def ARegSrc_32 : RegisterOperand<AGPR_32> {
let DecoderMethod = "DecodeAGPR_32RegisterClass"; let DecoderMethod = "decodeAGPR_32RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VCSrc_* Operands with an SGPR, VGPR or an inline constant // VCSrc_* Operands with an SGPR, VGPR or an inline constant
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm VCSrc : RegInlineOperand<"VS", "VCSrc">; defm VCSrc : RegInlineOperand<"VS", "VCSrc">;
Show All 11 Lines
defm VISrc_512 : RegInlineOperandAC<"VReg", "VISrc_512", "_512">; defm VISrc_512 : RegInlineOperandAC<"VReg", "VISrc_512", "_512">;
defm VISrc_1024 : RegInlineOperandAC<"VReg", "VISrc_1024", "_1024">; defm VISrc_1024 : RegInlineOperandAC<"VReg", "VISrc_1024", "_1024">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AVSrc_* Operands with an AGPR or VGPR // AVSrc_* Operands with an AGPR or VGPR
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def AVSrc_32 : RegisterOperand<AV_32> { def AVSrc_32 : RegisterOperand<AV_32> {
let DecoderMethod = "DecodeAV_32RegisterClass"; let DecoderMethod = "decodeAV_32RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
def AVSrc_64 : RegisterOperand<AV_64> { def AVSrc_64 : RegisterOperand<AV_64> {
let DecoderMethod = "DecodeAV_64RegisterClass"; let DecoderMethod = "decodeAV_64RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
def AVLdSt_32 : RegisterOperand<AV_32> { def AVLdSt_32 : RegisterOperand<AV_32> {
let DecoderMethod = "DecodeAVLdSt_32RegisterClass"; let DecoderMethod = "decodeAVLdSt_32RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
def AVLdSt_64 : RegisterOperand<AV_64> { def AVLdSt_64 : RegisterOperand<AV_64> {
let DecoderMethod = "DecodeAVLdSt_64RegisterClass"; let DecoderMethod = "decodeAVLdSt_64RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
def AVLdSt_96 : RegisterOperand<AV_96> { def AVLdSt_96 : RegisterOperand<AV_96> {
let DecoderMethod = "DecodeAVLdSt_96RegisterClass"; let DecoderMethod = "decodeAVLdSt_96RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
def AVLdSt_128 : RegisterOperand<AV_128> { def AVLdSt_128 : RegisterOperand<AV_128> {
let DecoderMethod = "DecodeAVLdSt_128RegisterClass"; let DecoderMethod = "decodeAVLdSt_128RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
def AVLdSt_160 : RegisterOperand<AV_160> { def AVLdSt_160 : RegisterOperand<AV_160> {
let DecoderMethod = "DecodeAVLdSt_160RegisterClass"; let DecoderMethod = "decodeAVLdSt_160RegisterClass";
let EncoderMethod = "getAVOperandEncoding"; let EncoderMethod = "getAVOperandEncoding";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ACSrc_* Operands with an AGPR or an inline constant // ACSrc_* Operands with an AGPR or an inline constant
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">; defm AISrc : RegInlineOperandAC<"AGPR", "AISrc">;
defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">; defm AISrc_128 : RegInlineOperandAC<"AReg", "AISrc_128", "_128">;
defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">; defm AISrc_512 : RegInlineOperandAC<"AReg", "AISrc_512", "_512">;
defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">; defm AISrc_1024 : RegInlineOperandAC<"AReg", "AISrc_1024", "_1024">;
let DecoderMethod = "decodeOperand_AReg_64" in let DecoderMethod = "decodeOperand_AReg_64" in
defm AISrc_64 : RegInlineOperandAC64<"AReg", "AISrc_64", "_64">; defm AISrc_64 : RegInlineOperandAC64<"AReg", "AISrc_64", "_64">;
let DecoderMethod = "decodeOperand_AReg_256" in let DecoderMethod = "decodeOperand_AReg_256" in
defm AISrc_256 : RegInlineOperandAC64<"AReg", "AISrc_256", "_256">; defm AISrc_256 : RegInlineOperandAC64<"AReg", "AISrc_256", "_256">;

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
static const uint16_t GPR32DecoderTable[] = { static const uint16_t GPR32DecoderTable[] = {
ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6, ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13, ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20, ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP, ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK}; ARC::SP, ARC::ILINK, ARC::R30, ARC::BLINK};
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) { if (RegNo >= 32) {
LLVM_DEBUG(dbgs() << "Not a GPR32 register."); LLVM_DEBUG(dbgs() << "Not a GPR32 register.");
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
unsigned Reg = GPR32DecoderTable[RegNo]; unsigned Reg = GPR32DecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
// Enumerates registers from ranges [r0-r3],[r12-r15]. // Enumerates registers from ranges [r0-r3],[r12-r15].
if (RegNo > 3) if (RegNo > 3)
RegNo += 8; // 4 for r12, etc... RegNo += 8; // 4 for r12, etc...
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); return decodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
} }
#include "ARCGenDisassemblerTables.inc" #include "ARCGenDisassemblerTables.inc"
static unsigned decodeCField(unsigned Insn) { static unsigned decodeCField(unsigned Insn) {
return fieldFromInstruction(Insn, 6, 6); return fieldFromInstruction(Insn, 6, 6);
} }
static unsigned decodeBField(unsigned Insn) { static unsigned decodeBField(unsigned Insn) {
return (fieldFromInstruction(Insn, 12, 3) << 3) | return (fieldFromInstruction(Insn, 12, 3) << 3) |
fieldFromInstruction(Insn, 24, 3); fieldFromInstruction(Insn, 24, 3);
} }
static unsigned decodeAField(unsigned Insn) { static unsigned decodeAField(unsigned Insn) {
return fieldFromInstruction(Insn, 0, 6); return fieldFromInstruction(Insn, 0, 6);
} }
static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Dec) { const void *Dec) {
// We have the 9-bit immediate in the low bits, 6-bit register in high bits. // We have the 9-bit immediate in the low bits, 6-bit register in high bits.
unsigned S9 = Insn & 0x1ff; unsigned S9 = Insn & 0x1ff;
unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9; unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
DecodeGPR32RegisterClass(Inst, R, Address, Dec); decodeGPR32RegisterClass(Inst, R, Address, Dec);
Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9))); Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S9)));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address, static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address,
uint64_t Value, const void *Decoder) { uint64_t Value, const void *Decoder) {
static const uint64_t AtLeast = 2; static const uint64_t AtLeast = 2;
// TODO: Try to force emitter to use MCDisassembler* instead of void*. // TODO: Try to force emitter to use MCDisassembler* instead of void*.
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn,
const void *Decoder) { const void *Decoder) {
unsigned SrcC, DstB, LImm; unsigned SrcC, DstB, LImm;
DstB = decodeBField(Insn); DstB = decodeBField(Insn);
if (DstB != 62) { if (DstB != 62) {
LLVM_DEBUG(dbgs() << "Decoding StLImm found non-limm register."); LLVM_DEBUG(dbgs() << "Decoding StLImm found non-limm register.");
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
SrcC = decodeCField(Insn); SrcC = decodeCField(Insn);
DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder); decodeGPR32RegisterClass(Inst, SrcC, Address, Decoder);
LImm = (Insn >> 32); LImm = (Insn >> 32);
Inst.addOperand(MCOperand::createImm(LImm)); Inst.addOperand(MCOperand::createImm(LImm));
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned DstA, SrcB, LImm; unsigned DstA, SrcB, LImm;
LLVM_DEBUG(dbgs() << "Decoding LdLImm:\n"); LLVM_DEBUG(dbgs() << "Decoding LdLImm:\n");
SrcB = decodeBField(Insn); SrcB = decodeBField(Insn);
if (SrcB != 62) { if (SrcB != 62) {
LLVM_DEBUG(dbgs() << "Decoding LdLImm found non-limm register."); LLVM_DEBUG(dbgs() << "Decoding LdLImm found non-limm register.");
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
DstA = decodeAField(Insn); DstA = decodeAField(Insn);
DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder); decodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
LImm = (Insn >> 32); LImm = (Insn >> 32);
Inst.addOperand(MCOperand::createImm(LImm)); Inst.addOperand(MCOperand::createImm(LImm));
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned DstA, SrcB; unsigned DstA, SrcB;
LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n"); LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n");
DstA = decodeAField(Insn); DstA = decodeAField(Insn);
DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder); decodeGPR32RegisterClass(Inst, DstA, Address, Decoder);
SrcB = decodeBField(Insn); SrcB = decodeBField(Insn);
DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder); decodeGPR32RegisterClass(Inst, SrcB, Address, Decoder);
if (decodeCField(Insn) != 62) { if (decodeCField(Insn) != 62) {
LLVM_DEBUG(dbgs() << "Decoding LdRLimm found non-limm register."); LLVM_DEBUG(dbgs() << "Decoding LdRLimm found non-limm register.");
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32))); Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> 32)));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
Show All 9 Linesstatic DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum, auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum,
Field Value) { Field Value) {
if (30 == RegNum) { if (30 == RegNum) {
Inst.addOperand(MCOperand::createImm(Value)); Inst.addOperand(MCOperand::createImm(Value));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder); return decodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
}; };
if (MCDisassembler::Success != DecodeRegisterOrImm(G, 0)) if (MCDisassembler::Success != DecodeRegisterOrImm(G, 0))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return DecodeRegisterOrImm(H, Insn >> 16u); return DecodeRegisterOrImm(H, Insn >> 16u);
} }
static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn, static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned DstB; unsigned DstB;
LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n"); LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n");
DstB = decodeBField(Insn); DstB = decodeBField(Insn);
DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); decodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
using Field = decltype(Insn); using Field = decltype(Insn);
Field U6Field = fieldFromInstruction(Insn, 6, 6); Field U6Field = fieldFromInstruction(Insn, 6, 6);
Inst.addOperand(MCOperand::createImm(U6Field)); Inst.addOperand(MCOperand::createImm(U6Field));
Field CCField = fieldFromInstruction(Insn, 0, 4); Field CCField = fieldFromInstruction(Insn, 0, 4);
Inst.addOperand(MCOperand::createImm(CCField)); Inst.addOperand(MCOperand::createImm(CCField));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn, static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned DstB = decodeBField(Insn); unsigned DstB = decodeBField(Insn);
DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); decodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
using Field = decltype(Insn); using Field = decltype(Insn);
Field U6 = fieldFromInstruction(Insn, 6, 6); Field U6 = fieldFromInstruction(Insn, 6, 6);
Inst.addOperand(MCOperand::createImm(U6)); Inst.addOperand(MCOperand::createImm(U6));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn, static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned DstB = decodeBField(Insn); unsigned DstB = decodeBField(Insn);
DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder); decodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
using Field = decltype(Insn); using Field = decltype(Insn);
Field Lower = fieldFromInstruction(Insn, 6, 6); Field Lower = fieldFromInstruction(Insn, 6, 6);
Field Upper = fieldFromInstruction(Insn, 0, 5); Field Upper = fieldFromInstruction(Insn, 0, 5);
Field Sign = fieldFromInstruction(Insn, 5, 1) ? -1 : 1; Field Sign = fieldFromInstruction(Insn, 5, 1) ? -1 : 1;
Field Result = Sign * ((Upper << 6) + Lower); Field Result = Sign * ((Upper << 6) + Lower);
Inst.addOperand(MCOperand::createImm(Result)); Inst.addOperand(MCOperand::createImm(Result));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
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llvm/lib/Target/ARM/ARMInstrInfo.td

Show First 20 Lines • Show All 1,276 Lines • ▼ Show 20 Lines
} }
def am6offset : MemOperand, def am6offset : MemOperand,
ComplexPattern<i32, 1, "SelectAddrMode6Offset", ComplexPattern<i32, 1, "SelectAddrMode6Offset",
[], [SDNPWantRoot]> { [], [SDNPWantRoot]> {
let PrintMethod = "printAddrMode6OffsetOperand"; let PrintMethod = "printAddrMode6OffsetOperand";
let MIOperandInfo = (ops GPR); let MIOperandInfo = (ops GPR);
let EncoderMethod = "getAddrMode6OffsetOpValue"; let EncoderMethod = "getAddrMode6OffsetOpValue";
let DecoderMethod = "DecodeGPRRegisterClass"; let DecoderMethod = "decodeGPRRegisterClass";
} }
// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
// (single element from one lane) for size 32. // (single element from one lane) for size 32.
def addrmode6oneL32 : MemOperand, def addrmode6oneL32 : MemOperand,
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
let PrintMethod = "printAddrMode6Operand"; let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm); let MIOperandInfo = (ops GPR:$addr, i32imm);
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Linesdef addr_offset_none : MemOperand,
let ParserMatchClass = MemNoOffsetAsmOperand; let ParserMatchClass = MemNoOffsetAsmOperand;
let MIOperandInfo = (ops GPR:$base); let MIOperandInfo = (ops GPR:$base);
} }
// t_addr_offset_none := reg [r0-r7] // t_addr_offset_none := reg [r0-r7]
def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; } def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; }
def t_addr_offset_none : MemOperand { def t_addr_offset_none : MemOperand {
let PrintMethod = "printAddrMode7Operand"; let PrintMethod = "printAddrMode7Operand";
let DecoderMethod = "DecodetGPRRegisterClass"; let DecoderMethod = "decodetGPRRegisterClass";
let ParserMatchClass = MemNoOffsetTAsmOperand; let ParserMatchClass = MemNoOffsetTAsmOperand;
let MIOperandInfo = (ops tGPR:$base); let MIOperandInfo = (ops tGPR:$base);
} }
def nohash_imm : Operand<i32> { def nohash_imm : Operand<i32> {
let PrintMethod = "printNoHashImmediate"; let PrintMethod = "printNoHashImmediate";
} }
▲ Show 20 Lines • Show All 2,642 Lines • ▼ Show 20 Linesdef : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),
(SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>; (SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos), def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
(SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>; (SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>;
def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos), def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>; (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos), def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
(SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
(SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos), def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos), def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
(USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Bitwise Instructions. // Bitwise Instructions.
// //
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llvm/lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// Define Thumb2 specific addressing modes. // Define Thumb2 specific addressing modes.
// t2_addr_offset_none := reg // t2_addr_offset_none := reg
def MemNoOffsetT2AsmOperand def MemNoOffsetT2AsmOperand
: AsmOperandClass { let Name = "MemNoOffsetT2"; } : AsmOperandClass { let Name = "MemNoOffsetT2"; }
def t2_addr_offset_none : MemOperand { def t2_addr_offset_none : MemOperand {
let PrintMethod = "printAddrMode7Operand"; let PrintMethod = "printAddrMode7Operand";
let DecoderMethod = "DecodeGPRnopcRegisterClass"; let DecoderMethod = "decodeGPRnopcRegisterClass";
let ParserMatchClass = MemNoOffsetT2AsmOperand; let ParserMatchClass = MemNoOffsetT2AsmOperand;
let MIOperandInfo = (ops GPRnopc:$base); let MIOperandInfo = (ops GPRnopc:$base);
} }
// t2_nosp_addr_offset_none := reg // t2_nosp_addr_offset_none := reg
def MemNoOffsetT2NoSpAsmOperand def MemNoOffsetT2NoSpAsmOperand
: AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; } : AsmOperandClass { let Name = "MemNoOffsetT2NoSp"; }
def t2_nosp_addr_offset_none : MemOperand { def t2_nosp_addr_offset_none : MemOperand {
let PrintMethod = "printAddrMode7Operand"; let PrintMethod = "printAddrMode7Operand";
let DecoderMethod = "DecoderGPRRegisterClass"; let DecoderMethod = "decoderGPRRegisterClass";
let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand; let ParserMatchClass = MemNoOffsetT2NoSpAsmOperand;
let MIOperandInfo = (ops rGPR:$base); let MIOperandInfo = (ops rGPR:$base);
} }
// t2addrmode_imm12 := reg + imm12 // t2addrmode_imm12 := reg + imm12
def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";} def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
def t2addrmode_imm12 : MemOperand, def t2addrmode_imm12 : MemOperand,
ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
▲ Show 20 Lines • Show All 2,924 Lines • ▼ Show 20 Linesdef t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
[(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>; [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>;
def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb", def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb",
[(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>; [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
[(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>; [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)), def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)),
(t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,
(sext_bottom_16 rGPR:$Rm))), (sext_bottom_16 rGPR:$Rm))),
(t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn,
(sext_top_16 rGPR:$Rm))), (sext_top_16 rGPR:$Rm))),
(t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn), def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn),
sext_16_node:$Rm)), sext_16_node:$Rm)),
(t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>;
▲ Show 20 Lines • Show All 2,500 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "ARMBaseInstrInfo.h" #include "ARMBaseInstrInfo.h"
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines case MCDisassembler::Fail:
Out = In; Out = In;
return false; return false;
} }
llvm_unreachable("Invalid DecodeStatus!"); llvm_unreachable("Invalid DecodeStatus!");
} }
// Forward declare these because the autogenerated code will reference them. // Forward declare these because the autogenerated code will reference them.
// Definitions are further down. // Definitions are further down.
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus static DecodeStatus
DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, decodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRnopcRegisterClass(MCInst &Inst,
unsigned RegNo, uint64_t Address, unsigned RegNo, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRwithAPSRRegisterClass(MCInst &Inst,
unsigned RegNo, uint64_t Address, unsigned RegNo, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRwithZRRegisterClass(MCInst &Inst,
unsigned RegNo, uint64_t Address, unsigned RegNo, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPRwithZRnospRegisterClass( static DecodeStatus decodeGPRwithZRnospRegisterClass(
MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, static DecodeStatus decodeDPR_VFP2RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, static DecodeStatus decodeDPairSpacedRegisterClass(MCInst &Inst,
unsigned RegNo, uint64_t Address, unsigned RegNo, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
▲ Show 20 Lines • Show All 883 Lines • ▼ Show 20 Lines
static const uint16_t CLRMGPRDecoderTable[] = { static const uint16_t CLRMGPRDecoderTable[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R12, 0, ARM::LR, ARM::APSR ARM::R12, 0, ARM::LR, ARM::APSR
}; };
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo]; unsigned Register = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = CLRMGPRDecoderTable[RegNo]; unsigned Register = CLRMGPRDecoderTable[RegNo];
if (Register == 0) if (Register == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus static DecodeStatus
DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, decodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (RegNo == 15) if (RegNo == 15)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, decodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (RegNo == 15) if (RegNo == 15)
{ {
Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, decodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (RegNo == 15) if (RegNo == 15)
{ {
Inst.addOperand(MCOperand::createReg(ARM::ZR)); Inst.addOperand(MCOperand::createReg(ARM::ZR));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
if (RegNo == 13) if (RegNo == 13)
Check(S, MCDisassembler::SoftFail); Check(S, MCDisassembler::SoftFail);
Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, decodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (RegNo == 13) if (RegNo == 13)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); Check(S, decodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
return S; return S;
} }
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static const uint16_t GPRPairDecoderTable[] = { static const uint16_t GPRPairDecoderTable[] = {
ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
ARM::R8_R9, ARM::R10_R11, ARM::R12_SP ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
}; };
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
// According to the Arm ARM RegNo = 14 is undefined, but we return fail // According to the Arm ARM RegNo = 14 is undefined, but we return fail
// rather than SoftFail as there is no GPRPair table entry for index 7. // rather than SoftFail as there is no GPRPair table entry for index 7.
if (RegNo > 13) if (RegNo > 13)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (RegNo & 1) if (RegNo & 1)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Inst.addOperand(MCOperand::createReg(RegisterPair)); Inst.addOperand(MCOperand::createReg(RegisterPair));
return S; return S;
} }
static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 13) if (RegNo > 13)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Inst.addOperand(MCOperand::createReg(RegisterPair)); Inst.addOperand(MCOperand::createReg(RegisterPair));
if ((RegNo & 1) || RegNo > 10) if ((RegNo & 1) || RegNo > 10)
return MCDisassembler::SoftFail; return MCDisassembler::SoftFail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo != 13) if (RegNo != 13)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo]; unsigned Register = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned Register = 0; unsigned Register = 0;
switch (RegNo) { switch (RegNo) {
case 0: case 0:
Register = ARM::R0; Register = ARM::R0;
break; break;
case 1: case 1:
Register = ARM::R1; Register = ARM::R1;
Show All 13 Lines switch (RegNo) {
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
const FeatureBitset &featureBits = const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); Check(S, decodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
return S; return S;
} }
static const uint16_t SPRDecoderTable[] = { static const uint16_t SPRDecoderTable[] = {
ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S0, ARM::S1, ARM::S2, ARM::S3,
ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S4, ARM::S5, ARM::S6, ARM::S7,
ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S8, ARM::S9, ARM::S10, ARM::S11,
ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S12, ARM::S13, ARM::S14, ARM::S15,
ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S16, ARM::S17, ARM::S18, ARM::S19,
ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S20, ARM::S21, ARM::S22, ARM::S23,
ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S24, ARM::S25, ARM::S26, ARM::S27,
ARM::S28, ARM::S29, ARM::S30, ARM::S31 ARM::S28, ARM::S29, ARM::S30, ARM::S31
}; };
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = SPRDecoderTable[RegNo]; unsigned Register = SPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static const uint16_t DPRDecoderTable[] = { static const uint16_t DPRDecoderTable[] = {
ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D0, ARM::D1, ARM::D2, ARM::D3,
ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D4, ARM::D5, ARM::D6, ARM::D7,
ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D8, ARM::D9, ARM::D10, ARM::D11,
ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D12, ARM::D13, ARM::D14, ARM::D15,
ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D16, ARM::D17, ARM::D18, ARM::D19,
ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D20, ARM::D21, ARM::D22, ARM::D23,
ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D24, ARM::D25, ARM::D26, ARM::D27,
ARM::D28, ARM::D29, ARM::D30, ARM::D31 ARM::D28, ARM::D29, ARM::D30, ARM::D31
}; };
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
const FeatureBitset &featureBits = const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
bool hasD32 = featureBits[ARM::FeatureD32]; bool hasD32 = featureBits[ARM::FeatureD32];
if (RegNo > 31 || (!hasD32 && RegNo > 15)) if (RegNo > 31 || (!hasD32 && RegNo > 15))
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = DPRDecoderTable[RegNo]; unsigned Register = DPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus static DecodeStatus
DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, decodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static const uint16_t QPRDecoderTable[] = { static const uint16_t QPRDecoderTable[] = {
ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
}; };
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 31 || (RegNo & 1) != 0) if (RegNo > 31 || (RegNo & 1) != 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
RegNo >>= 1; RegNo >>= 1;
unsigned Register = QPRDecoderTable[RegNo]; unsigned Register = QPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static const uint16_t DPairDecoderTable[] = { static const uint16_t DPairDecoderTable[] = {
ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
ARM::Q15 ARM::Q15
}; };
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 30) if (RegNo > 30)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = DPairDecoderTable[RegNo]; unsigned Register = DPairDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static const uint16_t DPairSpacedDecoderTable[] = { static const uint16_t DPairSpacedDecoderTable[] = {
ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
ARM::D28_D30, ARM::D29_D31 ARM::D28_D30, ARM::D29_D31
}; };
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, static DecodeStatus decodeDPairSpacedRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 29) if (RegNo > 29)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = DPairSpacedDecoderTable[RegNo]; unsigned Register = DPairSpacedDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
Show All 30 Linesstatic DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction(Val, 0, 4); unsigned Rm = fieldFromInstruction(Val, 0, 4);
unsigned type = fieldFromInstruction(Val, 5, 2); unsigned type = fieldFromInstruction(Val, 5, 2);
unsigned imm = fieldFromInstruction(Val, 7, 5); unsigned imm = fieldFromInstruction(Val, 7, 5);
// Register-immediate // Register-immediate
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl; ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) { switch (type) {
case 0: case 0:
Shift = ARM_AM::lsl; Shift = ARM_AM::lsl;
break; break;
case 1: case 1:
Show All 20 Linesstatic DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction(Val, 0, 4); unsigned Rm = fieldFromInstruction(Val, 0, 4);
unsigned type = fieldFromInstruction(Val, 5, 2); unsigned type = fieldFromInstruction(Val, 5, 2);
unsigned Rs = fieldFromInstruction(Val, 8, 4); unsigned Rs = fieldFromInstruction(Val, 8, 4);
// Register-register // Register-register
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl; ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) { switch (type) {
case 0: case 0:
Shift = ARM_AM::lsl; Shift = ARM_AM::lsl;
break; break;
case 1: case 1:
Show All 38 Lines case ARM::t2CLRM:
break; break;
} }
// Empty register lists are not allowed. // Empty register lists are not allowed.
if (Val == 0) return MCDisassembler::Fail; if (Val == 0) return MCDisassembler::Fail;
for (unsigned i = 0; i < 16; ++i) { for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) { if (Val & (1 << i)) {
if (CLRM) { if (CLRM) {
if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { if (!Check(S, decodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
} else { } else {
if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, i, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Writeback not allowed if Rn is in the target list. // Writeback not allowed if Rn is in the target list.
if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Check(S, MCDisassembler::SoftFail); Check(S, MCDisassembler::SoftFail);
} }
} }
} }
Show All 9 Linesstatic DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
// In case of unpredictable encoding, tweak the operands. // In case of unpredictable encoding, tweak the operands.
if (regs == 0 || (Vd + regs) > 32) { if (regs == 0 || (Vd + regs) > 32) {
regs = Vd + regs > 32 ? 32 - Vd : regs; regs = Vd + regs > 32 ? 32 - Vd : regs;
regs = std::max( 1u, regs); regs = std::max( 1u, regs);
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
} }
if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) if (!Check(S, decodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
for (unsigned i = 0; i < (regs - 1); ++i) { for (unsigned i = 0; i < (regs - 1); ++i) {
if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) if (!Check(S, decodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return S; return S;
} }
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Vd = fieldFromInstruction(Val, 8, 5); unsigned Vd = fieldFromInstruction(Val, 8, 5);
unsigned regs = fieldFromInstruction(Val, 1, 7); unsigned regs = fieldFromInstruction(Val, 1, 7);
// In case of unpredictable encoding, tweak the operands. // In case of unpredictable encoding, tweak the operands.
if (regs == 0 || regs > 16 || (Vd + regs) > 32) { if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
regs = Vd + regs > 32 ? 32 - Vd : regs; regs = Vd + regs > 32 ? 32 - Vd : regs;
regs = std::max( 1u, regs); regs = std::max( 1u, regs);
regs = std::min(16u, regs); regs = std::min(16u, regs);
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
for (unsigned i = 0; i < (regs - 1); ++i) { for (unsigned i = 0; i < (regs - 1); ++i) {
if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return S; return S;
} }
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines default:
break; break;
} }
if (featureBits[ARM::HasV8Ops] && (coproc != 14)) if (featureBits[ARM::HasV8Ops] && (coproc != 14))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(coproc)); Inst.addOperand(MCOperand::createImm(coproc));
Inst.addOperand(MCOperand::createImm(CRd)); Inst.addOperand(MCOperand::createImm(CRd));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::t2LDC2_OFFSET: case ARM::t2LDC2_OFFSET:
case ARM::t2LDC2L_OFFSET: case ARM::t2LDC2L_OFFSET:
case ARM::t2LDC2_PRE: case ARM::t2LDC2_PRE:
case ARM::t2LDC2L_PRE: case ARM::t2LDC2L_PRE:
case ARM::t2STC2_OFFSET: case ARM::t2STC2_OFFSET:
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines switch (Inst.getOpcode()) {
case ARM::STR_POST_IMM: case ARM::STR_POST_IMM:
case ARM::STR_POST_REG: case ARM::STR_POST_REG:
case ARM::STRB_POST_IMM: case ARM::STRB_POST_IMM:
case ARM::STRB_POST_REG: case ARM::STRB_POST_REG:
case ARM::STRT_POST_REG: case ARM::STRT_POST_REG:
case ARM::STRT_POST_IMM: case ARM::STRT_POST_IMM:
case ARM::STRBT_POST_REG: case ARM::STRBT_POST_REG:
case ARM::STRBT_POST_IMM: case ARM::STRBT_POST_IMM:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// On loads, the writeback operand comes after Rt. // On loads, the writeback operand comes after Rt.
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::LDR_POST_IMM: case ARM::LDR_POST_IMM:
case ARM::LDR_POST_REG: case ARM::LDR_POST_REG:
case ARM::LDRB_POST_IMM: case ARM::LDRB_POST_IMM:
case ARM::LDRB_POST_REG: case ARM::LDRB_POST_REG:
case ARM::LDRBT_POST_REG: case ARM::LDRBT_POST_REG:
case ARM::LDRBT_POST_IMM: case ARM::LDRBT_POST_IMM:
case ARM::LDRT_POST_REG: case ARM::LDRT_POST_REG:
case ARM::LDRT_POST_IMM: case ARM::LDRT_POST_IMM:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
ARM_AM::AddrOpc Op = ARM_AM::add; ARM_AM::AddrOpc Op = ARM_AM::add;
if (!fieldFromInstruction(Insn, 23, 1)) if (!fieldFromInstruction(Insn, 23, 1))
Op = ARM_AM::sub; Op = ARM_AM::sub;
bool writeback = (P == 0) || (W == 1); bool writeback = (P == 0) || (W == 1);
unsigned idx_mode = 0; unsigned idx_mode = 0;
if (P && writeback) if (P && writeback)
idx_mode = ARMII::IndexModePre; idx_mode = ARMII::IndexModePre;
else if (!P && writeback) else if (!P && writeback)
idx_mode = ARMII::IndexModePost; idx_mode = ARMII::IndexModePost;
if (writeback && (Rn == 15 || Rn == Rt)) if (writeback && (Rn == 15 || Rn == Rt))
S = MCDisassembler::SoftFail; // UNPREDICTABLE S = MCDisassembler::SoftFail; // UNPREDICTABLE
if (reg) { if (reg) {
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
ARM_AM::ShiftOpc Opc = ARM_AM::lsl; ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
switch( fieldFromInstruction(Insn, 5, 2)) { switch( fieldFromInstruction(Insn, 5, 2)) {
case 0: case 0:
Opc = ARM_AM::lsl; Opc = ARM_AM::lsl;
break; break;
case 1: case 1:
Opc = ARM_AM::lsr; Opc = ARM_AM::lsr;
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines switch (type) {
case 3: case 3:
ShOp = ARM_AM::ror; ShOp = ARM_AM::ror;
break; break;
} }
if (ShOp == ARM_AM::ror && imm == 0) if (ShOp == ARM_AM::ror && imm == 0)
ShOp = ARM_AM::rrx; ShOp = ARM_AM::rrx;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned shift; unsigned shift;
if (U) if (U)
shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
else else
shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Inst.addOperand(MCOperand::createImm(shift)); Inst.addOperand(MCOperand::createImm(shift));
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines if (writeback) { // Writeback
// On stores, the writeback operand precedes Rt. // On stores, the writeback operand precedes Rt.
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::STRD: case ARM::STRD:
case ARM::STRD_PRE: case ARM::STRD_PRE:
case ARM::STRD_POST: case ARM::STRD_POST:
case ARM::STRH: case ARM::STRH:
case ARM::STRH_PRE: case ARM::STRH_PRE:
case ARM::STRH_POST: case ARM::STRH_POST:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::STRD: case ARM::STRD:
case ARM::STRD_PRE: case ARM::STRD_PRE:
case ARM::STRD_POST: case ARM::STRD_POST:
case ARM::LDRD: case ARM::LDRD:
case ARM::LDRD_PRE: case ARM::LDRD_PRE:
case ARM::LDRD_POST: case ARM::LDRD_POST:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
if (writeback) { if (writeback) {
// On loads, the writeback operand comes after Rt. // On loads, the writeback operand comes after Rt.
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::LDRD: case ARM::LDRD:
case ARM::LDRD_PRE: case ARM::LDRD_PRE:
case ARM::LDRD_POST: case ARM::LDRD_POST:
case ARM::LDRH: case ARM::LDRH:
case ARM::LDRH_PRE: case ARM::LDRH_PRE:
case ARM::LDRH_POST: case ARM::LDRH_POST:
case ARM::LDRSH: case ARM::LDRSH:
case ARM::LDRSH_PRE: case ARM::LDRSH_PRE:
case ARM::LDRSH_POST: case ARM::LDRSH_POST:
case ARM::LDRSB: case ARM::LDRSB:
case ARM::LDRSB_PRE: case ARM::LDRSB_PRE:
case ARM::LDRSB_POST: case ARM::LDRSB_POST:
case ARM::LDRHTr: case ARM::LDRHTr:
case ARM::LDRSBTr: case ARM::LDRSBTr:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (type) { if (type) {
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
} else { } else {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(U)); Inst.addOperand(MCOperand::createImm(U));
} }
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
Show All 17 Lines case 2:
mode = ARM_AM::db; mode = ARM_AM::db;
break; break;
case 3: case 3:
mode = ARM_AM::ib; mode = ARM_AM::ib;
break; break;
} }
Inst.addOperand(MCOperand::createImm(mode)); Inst.addOperand(MCOperand::createImm(mode));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (pred == 0xF) if (pred == 0xF)
return DecodeCPSInstruction(Inst, Insn, Address, Decoder); return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
unsigned Insn, unsigned Insn,
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines if (fieldFromInstruction(Insn, 20, 1) == 0) {
Inst.addOperand( Inst.addOperand(
MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
return S; return S;
} }
return DecodeRFEInstruction(Inst, Insn, Address, Decoder); return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; // Tied return MCDisassembler::Fail; // Tied
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
unsigned imm = 0; unsigned imm = 0;
imm |= (fieldFromInstruction(Insn, 0, 8) << 0); imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
imm |= (fieldFromInstruction(Insn, 12, 3) << 8); imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
imm |= (fieldFromInstruction(Insn, 16, 4) << 12); imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
imm |= (fieldFromInstruction(Insn, 26, 1) << 11); imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
if (Inst.getOpcode() == ARM::t2MOVTi16) if (Inst.getOpcode() == ARM::t2MOVTi16)
if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return S; return S;
} }
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
unsigned imm = 0; unsigned imm = 0;
imm |= (fieldFromInstruction(Insn, 0, 12) << 0); imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
imm |= (fieldFromInstruction(Insn, 16, 4) << 12); imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
if (Inst.getOpcode() == ARM::MOVTi16) if (Inst.getOpcode() == ARM::MOVTi16)
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 16, 4); unsigned Rd = fieldFromInstruction(Insn, 16, 4);
unsigned Rn = fieldFromInstruction(Insn, 0, 4); unsigned Rn = fieldFromInstruction(Insn, 0, 4);
unsigned Rm = fieldFromInstruction(Insn, 8, 4); unsigned Rm = fieldFromInstruction(Insn, 8, 4);
unsigned Ra = fieldFromInstruction(Insn, 12, 4); unsigned Ra = fieldFromInstruction(Insn, 12, 4);
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (pred == 0xF) if (pred == 0xF)
return DecodeCPSInstruction(Inst, Insn, Address, Decoder); return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Pred = fieldFromInstruction(Insn, 28, 4); unsigned Pred = fieldFromInstruction(Insn, 28, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
if (Pred == 0xF) if (Pred == 0xF)
return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
Show All 27 Lines
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned add = fieldFromInstruction(Val, 12, 1); unsigned add = fieldFromInstruction(Val, 12, 1);
unsigned imm = fieldFromInstruction(Val, 0, 12); unsigned imm = fieldFromInstruction(Val, 0, 12);
unsigned Rn = fieldFromInstruction(Val, 13, 4); unsigned Rn = fieldFromInstruction(Val, 13, 4);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!add) imm *= -1; if (!add) imm *= -1;
if (imm == 0 && !add) imm = INT32_MIN; if (imm == 0 && !add) imm = INT32_MIN;
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
if (Rn == 15) if (Rn == 15)
tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
return S; return S;
} }
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 9, 4); unsigned Rn = fieldFromInstruction(Val, 9, 4);
// U == 1 to add imm, 0 to subtract it. // U == 1 to add imm, 0 to subtract it.
unsigned U = fieldFromInstruction(Val, 8, 1); unsigned U = fieldFromInstruction(Val, 8, 1);
unsigned imm = fieldFromInstruction(Val, 0, 8); unsigned imm = fieldFromInstruction(Val, 0, 8);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (U) if (U)
Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
else else
Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
return S; return S;
} }
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 9, 4); unsigned Rn = fieldFromInstruction(Val, 9, 4);
// U == 1 to add imm, 0 to subtract it. // U == 1 to add imm, 0 to subtract it.
unsigned U = fieldFromInstruction(Val, 8, 1); unsigned U = fieldFromInstruction(Val, 8, 1);
unsigned imm = fieldFromInstruction(Val, 0, 8); unsigned imm = fieldFromInstruction(Val, 0, 8);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (U) if (U)
Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
else else
Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
return S; return S;
} }
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); return decodeGPRRegisterClass(Inst, Val, Address, Decoder);
} }
static DecodeStatus static DecodeStatus
DecodeT2BInstruction(MCInst &Inst, unsigned Insn, DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus Status = MCDisassembler::Success; DecodeStatus Status = MCDisassembler::Success;
// Note the J1 and J2 values are from the encoded instruction. So here // Note the J1 and J2 values are from the encoded instruction. So here
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction(Val, 0, 4); unsigned Rm = fieldFromInstruction(Val, 0, 4);
unsigned align = fieldFromInstruction(Val, 4, 2); unsigned align = fieldFromInstruction(Val, 4, 2);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!align) if (!align)
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
else else
Inst.addOperand(MCOperand::createImm(4 << align)); Inst.addOperand(MCOperand::createImm(4 << align));
return S; return S;
} }
Show All 15 Linesstatic DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VLD2b16: case ARM::VLD2b16:
case ARM::VLD2b32: case ARM::VLD2b32:
case ARM::VLD2b8: case ARM::VLD2b8:
case ARM::VLD2b16wb_fixed: case ARM::VLD2b16wb_fixed:
case ARM::VLD2b16wb_register: case ARM::VLD2b16wb_register:
case ARM::VLD2b32wb_fixed: case ARM::VLD2b32wb_fixed:
case ARM::VLD2b32wb_register: case ARM::VLD2b32wb_register:
case ARM::VLD2b8wb_fixed: case ARM::VLD2b8wb_fixed:
case ARM::VLD2b8wb_register: case ARM::VLD2b8wb_register:
if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
// Second output register // Second output register
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VLD3d8: case ARM::VLD3d8:
case ARM::VLD3d16: case ARM::VLD3d16:
case ARM::VLD3d32: case ARM::VLD3d32:
case ARM::VLD3d8_UPD: case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD: case ARM::VLD3d16_UPD:
case ARM::VLD3d32_UPD: case ARM::VLD3d32_UPD:
case ARM::VLD4d8: case ARM::VLD4d8:
case ARM::VLD4d16: case ARM::VLD4d16:
case ARM::VLD4d32: case ARM::VLD4d32:
case ARM::VLD4d8_UPD: case ARM::VLD4d8_UPD:
case ARM::VLD4d16_UPD: case ARM::VLD4d16_UPD:
case ARM::VLD4d32_UPD: case ARM::VLD4d32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VLD3q8: case ARM::VLD3q8:
case ARM::VLD3q16: case ARM::VLD3q16:
case ARM::VLD3q32: case ARM::VLD3q32:
case ARM::VLD3q8_UPD: case ARM::VLD3q8_UPD:
case ARM::VLD3q16_UPD: case ARM::VLD3q16_UPD:
case ARM::VLD3q32_UPD: case ARM::VLD3q32_UPD:
case ARM::VLD4q8: case ARM::VLD4q8:
case ARM::VLD4q16: case ARM::VLD4q16:
case ARM::VLD4q32: case ARM::VLD4q32:
case ARM::VLD4q8_UPD: case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD: case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD: case ARM::VLD4q32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
// Third output register // Third output register
switch(Inst.getOpcode()) { switch(Inst.getOpcode()) {
case ARM::VLD3d8: case ARM::VLD3d8:
case ARM::VLD3d16: case ARM::VLD3d16:
case ARM::VLD3d32: case ARM::VLD3d32:
case ARM::VLD3d8_UPD: case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD: case ARM::VLD3d16_UPD:
case ARM::VLD3d32_UPD: case ARM::VLD3d32_UPD:
case ARM::VLD4d8: case ARM::VLD4d8:
case ARM::VLD4d16: case ARM::VLD4d16:
case ARM::VLD4d32: case ARM::VLD4d32:
case ARM::VLD4d8_UPD: case ARM::VLD4d8_UPD:
case ARM::VLD4d16_UPD: case ARM::VLD4d16_UPD:
case ARM::VLD4d32_UPD: case ARM::VLD4d32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VLD3q8: case ARM::VLD3q8:
case ARM::VLD3q16: case ARM::VLD3q16:
case ARM::VLD3q32: case ARM::VLD3q32:
case ARM::VLD3q8_UPD: case ARM::VLD3q8_UPD:
case ARM::VLD3q16_UPD: case ARM::VLD3q16_UPD:
case ARM::VLD3q32_UPD: case ARM::VLD3q32_UPD:
case ARM::VLD4q8: case ARM::VLD4q8:
case ARM::VLD4q16: case ARM::VLD4q16:
case ARM::VLD4q32: case ARM::VLD4q32:
case ARM::VLD4q8_UPD: case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD: case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD: case ARM::VLD4q32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
// Fourth output register // Fourth output register
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VLD4d8: case ARM::VLD4d8:
case ARM::VLD4d16: case ARM::VLD4d16:
case ARM::VLD4d32: case ARM::VLD4d32:
case ARM::VLD4d8_UPD: case ARM::VLD4d8_UPD:
case ARM::VLD4d16_UPD: case ARM::VLD4d16_UPD:
case ARM::VLD4d32_UPD: case ARM::VLD4d32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VLD4q8: case ARM::VLD4q8:
case ARM::VLD4q16: case ARM::VLD4q16:
case ARM::VLD4q32: case ARM::VLD4q32:
case ARM::VLD4q8_UPD: case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD: case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD: case ARM::VLD4q32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
// Writeback operand // Writeback operand
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines switch (Inst.getOpcode()) {
case ARM::VLD3q16_UPD: case ARM::VLD3q16_UPD:
case ARM::VLD3q32_UPD: case ARM::VLD3q32_UPD:
case ARM::VLD4d8_UPD: case ARM::VLD4d8_UPD:
case ARM::VLD4d16_UPD: case ARM::VLD4d16_UPD:
case ARM::VLD4d32_UPD: case ARM::VLD4d32_UPD:
case ARM::VLD4q8_UPD: case ARM::VLD4q8_UPD:
case ARM::VLD4q16_UPD: case ARM::VLD4q16_UPD:
case ARM::VLD4q32_UPD: case ARM::VLD4q32_UPD:
if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, wb, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
// AddrMode6 Base (register+alignment) // AddrMode6 Base (register+alignment)
if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
Show All 37 Linesstatic DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
case ARM::VLD1q8wb_register: case ARM::VLD1q8wb_register:
case ARM::VLD1q16wb_register: case ARM::VLD1q16wb_register:
case ARM::VLD1q32wb_register: case ARM::VLD1q32wb_register:
case ARM::VLD1q64wb_register: case ARM::VLD1q64wb_register:
// The fixed offset post-increment encodes Rm == 0xd. The no-writeback // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
// variant encodes Rm == 0xf. Anything else is a register offset post- // variant encodes Rm == 0xf. Anything else is a register offset post-
// increment and we need to add the register operand to the instruction. // increment and we need to add the register operand to the instruction.
if (Rm != 0xD && Rm != 0xF && if (Rm != 0xD && Rm != 0xF &&
!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) !Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_fixed:
case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_fixed:
case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_fixed:
case ARM::VLD2b8wb_fixed: case ARM::VLD2b8wb_fixed:
case ARM::VLD2b16wb_fixed: case ARM::VLD2b16wb_fixed:
case ARM::VLD2b32wb_fixed: case ARM::VLD2b32wb_fixed:
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines switch (Inst.getOpcode()) {
case ARM::VST3q16_UPD: case ARM::VST3q16_UPD:
case ARM::VST3q32_UPD: case ARM::VST3q32_UPD:
case ARM::VST4d8_UPD: case ARM::VST4d8_UPD:
case ARM::VST4d16_UPD: case ARM::VST4d16_UPD:
case ARM::VST4d32_UPD: case ARM::VST4d32_UPD:
case ARM::VST4q8_UPD: case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD: case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD: case ARM::VST4q32_UPD:
if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, wb, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
// AddrMode6 Base (register+alignment) // AddrMode6 Base (register+alignment)
if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// AddrMode6 Offset (register) // AddrMode6 Offset (register)
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: default:
if (Rm == 0xD) if (Rm == 0xD)
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) { else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
break; break;
case ARM::VST1d8wb_fixed: case ARM::VST1d8wb_fixed:
case ARM::VST1d16wb_fixed: case ARM::VST1d16wb_fixed:
case ARM::VST1d32wb_fixed: case ARM::VST1d32wb_fixed:
case ARM::VST1d64wb_fixed: case ARM::VST1d64wb_fixed:
case ARM::VST1q8wb_fixed: case ARM::VST1q8wb_fixed:
Show All 38 Linesstatic DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
case ARM::VST2d32: case ARM::VST2d32:
case ARM::VST2d8: case ARM::VST2d8:
case ARM::VST2d16wb_fixed: case ARM::VST2d16wb_fixed:
case ARM::VST2d16wb_register: case ARM::VST2d16wb_register:
case ARM::VST2d32wb_fixed: case ARM::VST2d32wb_fixed:
case ARM::VST2d32wb_register: case ARM::VST2d32wb_register:
case ARM::VST2d8wb_fixed: case ARM::VST2d8wb_fixed:
case ARM::VST2d8wb_register: case ARM::VST2d8wb_register:
if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VST2b16: case ARM::VST2b16:
case ARM::VST2b32: case ARM::VST2b32:
case ARM::VST2b8: case ARM::VST2b8:
case ARM::VST2b16wb_fixed: case ARM::VST2b16wb_fixed:
case ARM::VST2b16wb_register: case ARM::VST2b16wb_register:
case ARM::VST2b32wb_fixed: case ARM::VST2b32wb_fixed:
case ARM::VST2b32wb_register: case ARM::VST2b32wb_register:
case ARM::VST2b8wb_fixed: case ARM::VST2b8wb_fixed:
case ARM::VST2b8wb_register: case ARM::VST2b8wb_register:
if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
// Second input register // Second input register
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VST3d8: case ARM::VST3d8:
case ARM::VST3d16: case ARM::VST3d16:
case ARM::VST3d32: case ARM::VST3d32:
case ARM::VST3d8_UPD: case ARM::VST3d8_UPD:
case ARM::VST3d16_UPD: case ARM::VST3d16_UPD:
case ARM::VST3d32_UPD: case ARM::VST3d32_UPD:
case ARM::VST4d8: case ARM::VST4d8:
case ARM::VST4d16: case ARM::VST4d16:
case ARM::VST4d32: case ARM::VST4d32:
case ARM::VST4d8_UPD: case ARM::VST4d8_UPD:
case ARM::VST4d16_UPD: case ARM::VST4d16_UPD:
case ARM::VST4d32_UPD: case ARM::VST4d32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VST3q8: case ARM::VST3q8:
case ARM::VST3q16: case ARM::VST3q16:
case ARM::VST3q32: case ARM::VST3q32:
case ARM::VST3q8_UPD: case ARM::VST3q8_UPD:
case ARM::VST3q16_UPD: case ARM::VST3q16_UPD:
case ARM::VST3q32_UPD: case ARM::VST3q32_UPD:
case ARM::VST4q8: case ARM::VST4q8:
case ARM::VST4q16: case ARM::VST4q16:
case ARM::VST4q32: case ARM::VST4q32:
case ARM::VST4q8_UPD: case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD: case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD: case ARM::VST4q32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
// Third input register // Third input register
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VST3d8: case ARM::VST3d8:
case ARM::VST3d16: case ARM::VST3d16:
case ARM::VST3d32: case ARM::VST3d32:
case ARM::VST3d8_UPD: case ARM::VST3d8_UPD:
case ARM::VST3d16_UPD: case ARM::VST3d16_UPD:
case ARM::VST3d32_UPD: case ARM::VST3d32_UPD:
case ARM::VST4d8: case ARM::VST4d8:
case ARM::VST4d16: case ARM::VST4d16:
case ARM::VST4d32: case ARM::VST4d32:
case ARM::VST4d8_UPD: case ARM::VST4d8_UPD:
case ARM::VST4d16_UPD: case ARM::VST4d16_UPD:
case ARM::VST4d32_UPD: case ARM::VST4d32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VST3q8: case ARM::VST3q8:
case ARM::VST3q16: case ARM::VST3q16:
case ARM::VST3q32: case ARM::VST3q32:
case ARM::VST3q8_UPD: case ARM::VST3q8_UPD:
case ARM::VST3q16_UPD: case ARM::VST3q16_UPD:
case ARM::VST3q32_UPD: case ARM::VST3q32_UPD:
case ARM::VST4q8: case ARM::VST4q8:
case ARM::VST4q16: case ARM::VST4q16:
case ARM::VST4q32: case ARM::VST4q32:
case ARM::VST4q8_UPD: case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD: case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD: case ARM::VST4q32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
// Fourth input register // Fourth input register
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VST4d8: case ARM::VST4d8:
case ARM::VST4d16: case ARM::VST4d16:
case ARM::VST4d32: case ARM::VST4d32:
case ARM::VST4d8_UPD: case ARM::VST4d8_UPD:
case ARM::VST4d16_UPD: case ARM::VST4d16_UPD:
case ARM::VST4d32_UPD: case ARM::VST4d32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VST4q8: case ARM::VST4q8:
case ARM::VST4q16: case ARM::VST4q16:
case ARM::VST4q32: case ARM::VST4q32:
case ARM::VST4q8_UPD: case ARM::VST4q8_UPD:
case ARM::VST4q16_UPD: case ARM::VST4q16_UPD:
case ARM::VST4q32_UPD: case ARM::VST4q32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
return S; return S;
} }
Show All 13 Lines if (size == 0 && align == 1)
return MCDisassembler::Fail; return MCDisassembler::Fail;
align *= (1 << size); align *= (1 << size);
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
} }
if (Rm != 0xF) { if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
// The fixed offset post-increment encodes Rm == 0xd. The no-writeback // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
// variant encodes Rm == 0xf. Anything else is a register offset post- // variant encodes Rm == 0xf. Anything else is a register offset post-
// increment and we need to add the register operand to the instruction. // increment and we need to add the register operand to the instruction.
if (Rm != 0xD && Rm != 0xF && if (Rm != 0xD && Rm != 0xF &&
!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) !Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
Rd |= fieldFromInstruction(Insn, 22, 1) << 4; Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
unsigned align = fieldFromInstruction(Insn, 4, 1); unsigned align = fieldFromInstruction(Insn, 4, 1);
unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
align *= 2*size; align *= 2*size;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
} }
if (Rm != 0xF) if (Rm != 0xF)
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xD && Rm != 0xF) { if (Rm != 0xD && Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return S; return S;
} }
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
Rd |= fieldFromInstruction(Insn, 22, 1) << 4; Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Rm != 0xF) { if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
if (Rm == 0xD) if (Rm == 0xD)
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) { else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return S; return S;
} }
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 15 Lines if (size == 0x3) {
if (size == 2) { if (size == 2) {
align *= 8; align *= 8;
} else { } else {
size = 1 << size; size = 1 << size;
align *= 4*size; align *= 4*size;
} }
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Rm != 0xF) { if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm == 0xD) if (Rm == 0xD)
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) { else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
Rd |= fieldFromInstruction(Insn, 22, 1) << 4; Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
unsigned imm = fieldFromInstruction(Insn, 0, 4); unsigned imm = fieldFromInstruction(Insn, 0, 4);
imm |= fieldFromInstruction(Insn, 16, 3) << 4; imm |= fieldFromInstruction(Insn, 16, 3) << 4;
imm |= fieldFromInstruction(Insn, 24, 1) << 7; imm |= fieldFromInstruction(Insn, 24, 1) << 7;
imm |= fieldFromInstruction(Insn, 8, 4) << 8; imm |= fieldFromInstruction(Insn, 8, 4) << 8;
imm |= fieldFromInstruction(Insn, 5, 1) << 12; imm |= fieldFromInstruction(Insn, 5, 1) << 12;
unsigned Q = fieldFromInstruction(Insn, 6, 1); unsigned Q = fieldFromInstruction(Insn, 6, 1);
if (Q) { if (Q) {
if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else { } else {
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VORRiv4i16: case ARM::VORRiv4i16:
case ARM::VORRiv2i32: case ARM::VORRiv2i32:
case ARM::VBICiv4i16: case ARM::VBICiv4i16:
case ARM::VBICiv2i32: case ARM::VBICiv2i32:
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::VORRiv8i16: case ARM::VORRiv8i16:
case ARM::VORRiv4i32: case ARM::VORRiv4i32:
case ARM::VBICiv8i16: case ARM::VBICiv8i16:
case ARM::VBICiv4i32: case ARM::VBICiv4i32:
if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
return S; return S;
} }
Show All 10 LinesDecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
imm |= fieldFromInstruction(Insn, 16, 3) << 4; imm |= fieldFromInstruction(Insn, 16, 3) << 4;
imm |= fieldFromInstruction(Insn, 28, 1) << 7; imm |= fieldFromInstruction(Insn, 28, 1) << 7;
imm |= cmode << 8; imm |= cmode << 8;
imm |= fieldFromInstruction(Insn, 5, 1) << 12; imm |= fieldFromInstruction(Insn, 5, 1) << 12;
if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
Inst.addOperand(MCOperand::createImm(ARMVCC::None)); Inst.addOperand(MCOperand::createImm(ARMVCC::None));
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
return S; return S;
} }
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Qd = fieldFromInstruction(Insn, 13, 3); unsigned Qd = fieldFromInstruction(Insn, 13, 3);
Qd |= fieldFromInstruction(Insn, 22, 1) << 3; Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
unsigned Qn = fieldFromInstruction(Insn, 17, 3); unsigned Qn = fieldFromInstruction(Insn, 17, 3);
Qn |= fieldFromInstruction(Insn, 7, 1) << 3; Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Qm = fieldFromInstruction(Insn, 1, 3); unsigned Qm = fieldFromInstruction(Insn, 1, 3);
Qm |= fieldFromInstruction(Insn, 5, 1) << 3; Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
Inst.addOperand(MCOperand::createImm(Qd)); Inst.addOperand(MCOperand::createImm(Qd));
return S; return S;
} }
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
Rd |= fieldFromInstruction(Insn, 22, 1) << 4; Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Rm |= fieldFromInstruction(Insn, 5, 1) << 4; Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
unsigned size = fieldFromInstruction(Insn, 18, 2); unsigned size = fieldFromInstruction(Insn, 18, 2);
if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(8 << size)); Inst.addOperand(MCOperand::createImm(8 << size));
return S; return S;
} }
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 26 Linesstatic DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
Rd |= fieldFromInstruction(Insn, 22, 1) << 4; Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Rn |= fieldFromInstruction(Insn, 7, 1) << 4; Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Rm |= fieldFromInstruction(Insn, 5, 1) << 4; Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
unsigned op = fieldFromInstruction(Insn, 6, 1); unsigned op = fieldFromInstruction(Insn, 6, 1);
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (op) { if (op) {
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; // Writeback return MCDisassembler::Fail; // Writeback
} }
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VTBL2: case ARM::VTBL2:
case ARM::VTBX2: case ARM::VTBX2:
if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned dst = fieldFromInstruction(Insn, 8, 3); unsigned dst = fieldFromInstruction(Insn, 8, 3);
unsigned imm = fieldFromInstruction(Insn, 0, 8); unsigned imm = fieldFromInstruction(Insn, 0, 8);
if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) if (!Check(S, decodetGPRRegisterClass(Inst, dst, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
switch(Inst.getOpcode()) { switch(Inst.getOpcode()) {
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
case ARM::tADR: case ARM::tADR:
break; // tADR does not explicitly represent the PC as an operand. break; // tADR does not explicitly represent the PC as an operand.
case ARM::tADDrSPi: case ARM::tADDrSPi:
Show All 31 Lines
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 0, 3); unsigned Rn = fieldFromInstruction(Val, 0, 3);
unsigned Rm = fieldFromInstruction(Val, 3, 3); unsigned Rm = fieldFromInstruction(Val, 3, 3);
if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 0, 3); unsigned Rn = fieldFromInstruction(Val, 0, 3);
unsigned imm = fieldFromInstruction(Val, 3, 5); unsigned imm = fieldFromInstruction(Val, 3, 5);
if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return S; return S;
} }
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 28 Linesstatic DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
case ARM::t2STRs: case ARM::t2STRs:
if (Rn == 15) if (Rn == 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return S; return S;
} }
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines case ARM::t2PLIs:
if (!hasV7Ops) if (!hasV7Ops)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::t2PLDWs: case ARM::t2PLDWs:
if (!hasV7Ops || !hasMP) if (!hasV7Ops || !hasMP)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
unsigned addrmode = fieldFromInstruction(Insn, 4, 2); unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines case ARM::t2PLIi8:
if (!hasV7Ops) if (!hasV7Ops)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::t2PLDWi8: case ARM::t2PLDWi8:
if (!hasV7Ops || !hasMP) if (!hasV7Ops || !hasMP)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines case ARM::t2PLIi12:
if (!hasV7Ops) if (!hasV7Ops)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::t2PLDWi12: case ARM::t2PLDWi12:
if (!hasV7Ops || !hasMP) if (!hasV7Ops || !hasMP)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
Show All 24 Lines case ARM::t2LDRSHT:
Inst.setOpcode(ARM::t2LDRSHpci); Inst.setOpcode(ARM::t2LDRSHpci);
break; break;
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
} }
if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
uint64_t Address, const void* Decoder) { uint64_t Address, const void* Decoder) {
Show All 27 Linesstatic DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
switch(Inst.getOpcode()) { switch(Inst.getOpcode()) {
case ARM::t2PLDpci: case ARM::t2PLDpci:
break; break;
case ARM::t2PLIpci: case ARM::t2PLIpci:
if (!hasV7Ops) if (!hasV7Ops)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!U) { if (!U) {
// Special case for #-0. // Special case for #-0.
if (imm == 0) if (imm == 0)
imm = INT32_MIN; imm = INT32_MIN;
else else
Show All 35 Lines
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 9, 4); unsigned Rn = fieldFromInstruction(Val, 9, 4);
unsigned imm = fieldFromInstruction(Val, 0, 9); unsigned imm = fieldFromInstruction(Val, 0, 9);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 8, 4); unsigned Rn = fieldFromInstruction(Val, 8, 4);
unsigned imm = fieldFromInstruction(Val, 0, 8); unsigned imm = fieldFromInstruction(Val, 0, 8);
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 8, 4); unsigned Rn = fieldFromInstruction(Val, 8, 4);
unsigned imm = fieldFromInstruction(Val, 0, 8); unsigned imm = fieldFromInstruction(Val, 0, 8);
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return S; return S;
} }
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines switch (Inst.getOpcode()) {
case ARM::t2STRBT: case ARM::t2STRBT:
case ARM::t2STRHT: case ARM::t2STRHT:
imm |= 0x100; imm |= 0x100;
break; break;
default: default:
break; break;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
template<int shift> template<int shift>
static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 8, 3); unsigned Rn = fieldFromInstruction(Val, 8, 3);
unsigned imm = fieldFromInstruction(Val, 0, 8); unsigned imm = fieldFromInstruction(Val, 0, 8);
if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
template<int shift, int WriteBack> template<int shift, int WriteBack>
static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 8, 4); unsigned Rn = fieldFromInstruction(Val, 8, 4);
unsigned imm = fieldFromInstruction(Val, 0, 8); unsigned imm = fieldFromInstruction(Val, 0, 8);
if (WriteBack) { if (WriteBack) {
if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) } else if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Show All 34 Lines case ARM::t2LDRSH_POST:
break; break;
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
} }
if (!load) { if (!load) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (load) { if (load) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
Show All 12 Linesstatic DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
case ARM::t2STRHi12: case ARM::t2STRHi12:
if (Rn == 15) if (Rn == 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
default: default:
break; break;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
return S; return S;
} }
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 9 Lines
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (Inst.getOpcode() == ARM::tADDrSP) { if (Inst.getOpcode() == ARM::tADDrSP) {
unsigned Rdm = fieldFromInstruction(Insn, 0, 3); unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(ARM::SP)); Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else if (Inst.getOpcode() == ARM::tADDspr) { } else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction(Insn, 3, 4); unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Inst.addOperand(MCOperand::createReg(ARM::SP)); Inst.addOperand(MCOperand::createReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP)); Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return S; return S;
} }
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
unsigned flags = fieldFromInstruction(Insn, 0, 3); unsigned flags = fieldFromInstruction(Insn, 0, 3);
Inst.addOperand(MCOperand::createImm(imod)); Inst.addOperand(MCOperand::createImm(imod));
Inst.addOperand(MCOperand::createImm(flags)); Inst.addOperand(MCOperand::createImm(flags));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
unsigned add = fieldFromInstruction(Insn, 4, 1); unsigned add = fieldFromInstruction(Insn, 4, 1);
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(add)); Inst.addOperand(MCOperand::createImm(add));
return S; return S;
} }
static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Insn, 3, 4); unsigned Rn = fieldFromInstruction(Insn, 3, 4);
unsigned Qm = fieldFromInstruction(Insn, 0, 3); unsigned Qm = fieldFromInstruction(Insn, 0, 3);
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
template<int shift> template<int shift>
static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Qm = fieldFromInstruction(Insn, 8, 3); unsigned Qm = fieldFromInstruction(Insn, 8, 3);
int imm = fieldFromInstruction(Insn, 0, 7); int imm = fieldFromInstruction(Insn, 0, 7);
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if(!fieldFromInstruction(Insn, 7, 1)) { if(!fieldFromInstruction(Insn, 7, 1)) {
if (imm == 0) if (imm == 0)
imm = INT32_MIN; // indicate -0 imm = INT32_MIN; // indicate -0
else else
imm *= -1; imm *= -1;
} }
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 LinesDecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
const FeatureBitset &FeatureBits = const FeatureBitset &FeatureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (Rn == 0xF) if (Rn == 0xF)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rd = fieldFromInstruction(Insn, 12, 4); unsigned Rd = fieldFromInstruction(Insn, 12, 4);
unsigned Rt = fieldFromInstruction(Insn, 0, 4); unsigned Rt = fieldFromInstruction(Insn, 0, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned imm = fieldFromInstruction(Insn, 0, 12); unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= fieldFromInstruction(Insn, 16, 4) << 13; imm |= fieldFromInstruction(Insn, 16, 4) << 13;
imm |= fieldFromInstruction(Insn, 23, 1) << 12; imm |= fieldFromInstruction(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned imm = fieldFromInstruction(Insn, 0, 12); unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= fieldFromInstruction(Insn, 16, 4) << 13; imm |= fieldFromInstruction(Insn, 16, 4) << 13;
imm |= fieldFromInstruction(Insn, 23, 1) << 12; imm |= fieldFromInstruction(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
if (Rm == 0xF) S = MCDisassembler::SoftFail; if (Rm == 0xF) S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned imm = fieldFromInstruction(Insn, 0, 12); unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= fieldFromInstruction(Insn, 16, 4) << 13; imm |= fieldFromInstruction(Insn, 16, 4) << 13;
imm |= fieldFromInstruction(Insn, 23, 1) << 12; imm |= fieldFromInstruction(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned imm = fieldFromInstruction(Insn, 0, 12); unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= fieldFromInstruction(Insn, 16, 4) << 13; imm |= fieldFromInstruction(Insn, 16, 4) << 13;
imm |= fieldFromInstruction(Insn, 23, 1) << 12; imm |= fieldFromInstruction(Insn, 23, 1) << 12;
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
Show All 36 Lines case 2:
case 3: case 3:
align = 4; break; align = 4; break;
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
break; break;
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 34 Lines case 2:
align = 4; break; align = 4; break;
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
break; break;
} }
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 29 Lines case 2:
index = fieldFromInstruction(Insn, 7, 1); index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 4, 1) != 0) if (fieldFromInstruction(Insn, 4, 1) != 0)
align = 8; align = 8;
if (fieldFromInstruction(Insn, 6, 1)) if (fieldFromInstruction(Insn, 6, 1))
inc = 2; inc = 2;
break; break;
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 30 Lines case 2:
if (fieldFromInstruction(Insn, 4, 1) != 0) if (fieldFromInstruction(Insn, 4, 1) != 0)
align = 8; align = 8;
if (fieldFromInstruction(Insn, 6, 1)) if (fieldFromInstruction(Insn, 6, 1))
inc = 2; inc = 2;
break; break;
} }
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 27 Lines case 2:
if (fieldFromInstruction(Insn, 4, 2)) if (fieldFromInstruction(Insn, 4, 2))
return MCDisassembler::Fail; // UNDEFINED return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction(Insn, 7, 1); index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 6, 1)) if (fieldFromInstruction(Insn, 6, 1))
inc = 2; inc = 2;
break; break;
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 28 Lines case 2:
return MCDisassembler::Fail; // UNDEFINED return MCDisassembler::Fail; // UNDEFINED
index = fieldFromInstruction(Insn, 7, 1); index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 6, 1)) if (fieldFromInstruction(Insn, 6, 1))
inc = 2; inc = 2;
break; break;
} }
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 34 Lines case 2:
} }
index = fieldFromInstruction(Insn, 7, 1); index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 6, 1)) if (fieldFromInstruction(Insn, 6, 1))
inc = 2; inc = 2;
break; break;
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 35 Lines case 2:
index = fieldFromInstruction(Insn, 7, 1); index = fieldFromInstruction(Insn, 7, 1);
if (fieldFromInstruction(Insn, 6, 1)) if (fieldFromInstruction(Insn, 6, 1))
inc = 2; inc = 2;
break; break;
} }
if (Rm != 0xF) { // Writeback if (Rm != 0xF) { // Writeback
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(align)); Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) { if (Rm != 0xF) {
if (Rm != 0xD) { if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else } else
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
} }
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(index)); Inst.addOperand(MCOperand::createImm(index));
return S; return S;
} }
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 5, 1); unsigned Rm = fieldFromInstruction(Insn, 5, 1);
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
Rm |= fieldFromInstruction(Insn, 0, 4) << 1; Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) if (!Check(S, decodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) if (!Check(S, decodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
unsigned Rm = fieldFromInstruction(Insn, 5, 1); unsigned Rm = fieldFromInstruction(Insn, 5, 1);
unsigned pred = fieldFromInstruction(Insn, 28, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4);
Rm |= fieldFromInstruction(Insn, 0, 4) << 1; Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) if (!Check(S, decodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) if (!Check(S, decodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 LinesDecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
addr |= (U << 8) | (Rn << 9); addr |= (U << 8) | (Rn << 9);
if (writeback && (Rn == Rt || Rn == Rt2)) if (writeback && (Rn == Rt || Rn == Rt2))
Check(S, MCDisassembler::SoftFail); Check(S, MCDisassembler::SoftFail);
if (Rt == Rt2) if (Rt == Rt2)
Check(S, MCDisassembler::SoftFail); Check(S, MCDisassembler::SoftFail);
// Rt // Rt
if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Rt2 // Rt2
if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Writeback operand // Writeback operand
if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// addr // addr
if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
Show All 12 LinesDecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
bool writeback = (W == 1) | (P == 0); bool writeback = (W == 1) | (P == 0);
addr |= (U << 8) | (Rn << 9); addr |= (U << 8) | (Rn << 9);
if (writeback && (Rn == Rt || Rn == Rt2)) if (writeback && (Rn == Rt || Rn == Rt2))
Check(S, MCDisassembler::SoftFail); Check(S, MCDisassembler::SoftFail);
// Writeback operand // Writeback operand
if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Rt // Rt
if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Rt2 // Rt2
if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// addr // addr
if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned sign1 = fieldFromInstruction(Insn, 21, 1); unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
unsigned sign2 = fieldFromInstruction(Insn, 23, 1); unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
if (sign1 != sign2) return MCDisassembler::Fail; if (sign1 != sign2) return MCDisassembler::Fail;
const unsigned Rd = fieldFromInstruction(Insn, 8, 4); const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); DecodeStatus S = decoderGPRRegisterClass(Inst, Rd, Address, Decoder);
unsigned Val = fieldFromInstruction(Insn, 0, 8); unsigned Val = fieldFromInstruction(Insn, 0, 8);
Val |= fieldFromInstruction(Insn, 12, 3) << 8; Val |= fieldFromInstruction(Insn, 12, 3) << 8;
Val |= fieldFromInstruction(Insn, 26, 1) << 11; Val |= fieldFromInstruction(Insn, 26, 1) << 11;
// If sign, then it is decreasing the address. // If sign, then it is decreasing the address.
if (sign1) { if (sign1) {
// Following ARMv7 Architecture Manual, when the offset // Following ARMv7 Architecture Manual, when the offset
// is zero, it is decoded as a subw, not as a adr.w // is zero, it is decoded as a subw, not as a adr.w
Show All 28 Linesstatic DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
if (pred == 0xF) if (pred == 0xF)
return DecodeCPSInstruction(Inst, Insn, Address, Decoder); return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (Rt == Rn || Rn == Rt2) if (Rt == Rn || Rn == Rt2)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines if (hasFullFP16) {
} }
} }
} }
return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
} }
if (!(imm & 0x20)) return MCDisassembler::Fail; if (!(imm & 0x20)) return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(64 - imm)); Inst.addOperand(MCOperand::createImm(64 - imm));
return S; return S;
} }
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
Show All 40 Lines if (hasFullFP16) {
} }
} }
} }
return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
} }
if (!(imm & 0x20)) return MCDisassembler::Fail; if (!(imm & 0x20)) return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) if (!Check(S, decodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) if (!Check(S, decodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(64 - imm)); Inst.addOperand(MCOperand::createImm(64 - imm));
return S; return S;
} }
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; auto DestRegDecoder = q ? decodeQPRRegisterClass : decodeDPRRegisterClass;
if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) if (!Check(S, decodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// The lane index does not have any bits in the encoding, because it can only // The lane index does not have any bits in the encoding, because it can only
// be 0. // be 0.
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
Inst.addOperand(MCOperand::createImm(rotate)); Inst.addOperand(MCOperand::createImm(rotate));
return S; return S;
} }
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rn = fieldFromInstruction(Val, 16, 4); unsigned Rn = fieldFromInstruction(Val, 16, 4);
unsigned Rt = fieldFromInstruction(Val, 12, 4); unsigned Rt = fieldFromInstruction(Val, 12, 4);
unsigned Rm = fieldFromInstruction(Val, 0, 4); unsigned Rm = fieldFromInstruction(Val, 0, 4);
Rm |= (fieldFromInstruction(Val, 23, 1) << 4); Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
unsigned Cond = fieldFromInstruction(Val, 28, 4); unsigned Cond = fieldFromInstruction(Val, 28, 4);
if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Show All 22 Linesstatic DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
// registers so it's tablegen desc has has two // registers so it's tablegen desc has has two
// outputs whereas MCRR doesn't store to any // outputs whereas MCRR doesn't store to any
// registers so all of it's operands are listed // registers so all of it's operands are listed
// as inputs, therefore the operand order for // as inputs, therefore the operand order for
// MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
// and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
if (Inst.getOpcode() == ARM::MRRC2) { if (Inst.getOpcode() == ARM::MRRC2) {
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Inst.addOperand(MCOperand::createImm(cop)); Inst.addOperand(MCOperand::createImm(cop));
Inst.addOperand(MCOperand::createImm(opc1)); Inst.addOperand(MCOperand::createImm(opc1));
if (Inst.getOpcode() == ARM::MCRR2) { if (Inst.getOpcode() == ARM::MCRR2) {
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Inst.addOperand(MCOperand::createImm(CRm)); Inst.addOperand(MCOperand::createImm(CRm));
return S; return S;
} }
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
Show All 15 Linesstatic DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
} }
if (Inst.getOpcode() != ARM::FMSTAT) { if (Inst.getOpcode() != ARM::FMSTAT) {
unsigned Rt = fieldFromInstruction(Val, 12, 4); unsigned Rt = fieldFromInstruction(Val, 12, 4);
if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
if (Rt == 13 || Rt == 15) if (Rt == 13 || Rt == 15)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder));
} else } else
Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); Check(S, decodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
} }
// Add explicit operand for the source sysreg, similarly to above. // Add explicit operand for the source sysreg, similarly to above.
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM::VMRS_FPSCR_NZCVQC: case ARM::VMRS_FPSCR_NZCVQC:
Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
break; break;
case ARM::VMRS_P0: case ARM::VMRS_P0:
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines case ARM::t2LE:
break; break;
case ARM::t2WLS: case ARM::t2WLS:
case ARM::MVE_WLSTP_8: case ARM::MVE_WLSTP_8:
case ARM::MVE_WLSTP_16: case ARM::MVE_WLSTP_16:
case ARM::MVE_WLSTP_32: case ARM::MVE_WLSTP_32:
case ARM::MVE_WLSTP_64: case ARM::MVE_WLSTP_64:
Inst.addOperand(MCOperand::createReg(ARM::LR)); Inst.addOperand(MCOperand::createReg(ARM::LR));
if (!Check(S, if (!Check(S,
DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), decoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
Address, Decoder)) || Address, Decoder)) ||
!Check(S, DecodeBFLabelOperand<false, false, true, 11>( !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
Inst, Imm, Address, Decoder))) Inst, Imm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case ARM::t2DLS: case ARM::t2DLS:
case ARM::MVE_DLSTP_8: case ARM::MVE_DLSTP_8:
case ARM::MVE_DLSTP_16: case ARM::MVE_DLSTP_16:
case ARM::MVE_DLSTP_32: case ARM::MVE_DLSTP_32:
case ARM::MVE_DLSTP_64: case ARM::MVE_DLSTP_64:
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
if (Rn == 0xF) { if (Rn == 0xF) {
// Enforce all the rest of the instruction bits in LCTP, which // Enforce all the rest of the instruction bits in LCTP, which
// won't have been reliably checked based on LCTP's own tablegen // won't have been reliably checked based on LCTP's own tablegen
// record, because we came to this decode by a roundabout route. // record, because we came to this decode by a roundabout route.
uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
if ((Insn & ~SBZMask) != CanonicalLCTP) if ((Insn & ~SBZMask) != CanonicalLCTP)
return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
if (Insn != CanonicalLCTP) if (Insn != CanonicalLCTP)
Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
Inst.setOpcode(ARM::MVE_LCTP); Inst.setOpcode(ARM::MVE_LCTP);
} else { } else {
Inst.addOperand(MCOperand::createReg(ARM::LR)); Inst.addOperand(MCOperand::createReg(ARM::LR));
if (!Check(S, DecoderGPRRegisterClass(Inst, if (!Check(S, decoderGPRRegisterClass(Inst,
fieldFromInstruction(Insn, 16, 4), fieldFromInstruction(Insn, 16, 4),
Address, Decoder))) Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
break; break;
} }
return S; return S;
} }
static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (Val == 0) if (Val == 0)
Val = 32; Val = 32;
Inst.addOperand(MCOperand::createImm(Val)); Inst.addOperand(MCOperand::createImm(Val));
return S; return S;
} }
static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if ((RegNo) + 1 > 11) if ((RegNo) + 1 > 11)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[(RegNo) + 1]; unsigned Register = GPRDecoderTable[(RegNo) + 1];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if ((RegNo) > 14) if ((RegNo) > 14)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[(RegNo)]; unsigned Register = GPRDecoderTable[(RegNo)];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus static DecodeStatus
DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, decodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo == 15) { if (RegNo == 15) {
Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
unsigned Register = GPRDecoderTable[RegNo]; unsigned Register = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
Show All 25 Lines if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) {
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
} }
Inst.addOperand(MCOperand::createReg(ARM::VPR)); Inst.addOperand(MCOperand::createReg(ARM::VPR));
return S; return S;
} }
static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = QPRDecoderTable[RegNo]; unsigned Register = QPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static const uint16_t QQPRDecoderTable[] = { static const uint16_t QQPRDecoderTable[] = {
ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
}; };
static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 6) if (RegNo > 6)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = QQPRDecoderTable[RegNo]; unsigned Register = QQPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static const uint16_t QQQQPRDecoderTable[] = { static const uint16_t QQQQPRDecoderTable[] = {
ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
}; };
static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 4) if (RegNo > 4)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = QQQQPRDecoderTable[RegNo]; unsigned Register = QQQQPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
Inst.addOperand(MCOperand::createReg(Sysreg)); Inst.addOperand(MCOperand::createReg(Sysreg));
unsigned Rn = fieldFromInstruction(Val, 16, 4); unsigned Rn = fieldFromInstruction(Val, 16, 4);
unsigned addr = fieldFromInstruction(Val, 0, 7) | unsigned addr = fieldFromInstruction(Val, 0, 7) |
(fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
if (Writeback) { if (Writeback) {
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(ARMCC::AL)); Inst.addOperand(MCOperand::createImm(ARMCC::AL));
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
return S; return S;
} }
static inline DecodeStatus DecodeMVE_MEM_pre( static inline DecodeStatus DecodeMVE_MEM_pre(
MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,
unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Qd = fieldFromInstruction(Val, 13, 3); unsigned Qd = fieldFromInstruction(Val, 13, 3);
unsigned addr = fieldFromInstruction(Val, 0, 7) | unsigned addr = fieldFromInstruction(Val, 0, 7) |
(fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
template <int shift> template <int shift>
static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
fieldFromInstruction(Val, 16, 3), fieldFromInstruction(Val, 16, 3),
DecodetGPRRegisterClass, decodetGPRRegisterClass,
DecodeTAddrModeImm7<shift>); DecodeTAddrModeImm7<shift>);
} }
template <int shift> template <int shift>
static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
fieldFromInstruction(Val, 16, 4), fieldFromInstruction(Val, 16, 4),
DecoderGPRRegisterClass, decoderGPRRegisterClass,
DecodeT2AddrModeImm7<shift,1>); DecodeT2AddrModeImm7<shift,1>);
} }
template <int shift> template <int shift>
static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
fieldFromInstruction(Val, 17, 3), fieldFromInstruction(Val, 17, 3),
DecodeMQPRRegisterClass, decodeMQPRRegisterClass,
DecodeMveAddrModeQ<shift>); DecodeMveAddrModeQ<shift>);
} }
template<unsigned MinLog, unsigned MaxLog> template<unsigned MinLog, unsigned MaxLog>
static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
Show All 20 Linesstatic DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction(Insn, 0, 4); unsigned Rt = fieldFromInstruction(Insn, 0, 4);
unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
fieldFromInstruction(Insn, 13, 3)); fieldFromInstruction(Insn, 13, 3));
unsigned index = fieldFromInstruction(Insn, 4, 1); unsigned index = fieldFromInstruction(Insn, 4, 1);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction(Insn, 0, 4); unsigned Rt = fieldFromInstruction(Insn, 0, 4);
unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
fieldFromInstruction(Insn, 13, 3)); fieldFromInstruction(Insn, 13, 3));
unsigned index = fieldFromInstruction(Insn, 4, 1); unsigned index = fieldFromInstruction(Insn, 4, 1);
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) if (!Check(S, decodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
Show All 23 Lines switch (Inst.getOpcode()) {
case ARM::MVE_UQRSHLL: case ARM::MVE_UQRSHLL:
Inst.setOpcode(ARM::MVE_UQRSHL); Inst.setOpcode(ARM::MVE_UQRSHL);
break; break;
default: default:
llvm_unreachable("Unexpected starting opcode!"); llvm_unreachable("Unexpected starting opcode!");
} }
// Rda as output parameter // Rda as output parameter
if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Rda again as input parameter // Rda again as input parameter
if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Rm, the amount to shift by // Rm, the amount to shift by
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (fieldFromInstruction (Insn, 6, 3) != 4) if (fieldFromInstruction (Insn, 6, 3) != 4)
return MCDisassembler::SoftFail; return MCDisassembler::SoftFail;
if (Rda == Rm) if (Rda == Rm)
return MCDisassembler::SoftFail; return MCDisassembler::SoftFail;
return S; return S;
} }
// Otherwise, we decode as whichever opcode our caller has already // Otherwise, we decode as whichever opcode our caller has already
// put into Inst. Those all look the same: // put into Inst. Those all look the same:
// RdaLo,RdaHi as output parameters // RdaLo,RdaHi as output parameters
if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) if (!Check(S, decodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) if (!Check(S, decodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// RdaLo,RdaHi again as input parameters // RdaLo,RdaHi again as input parameters
if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) if (!Check(S, decodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) if (!Check(S, decodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
// Rm, the amount to shift by // Rm, the amount to shift by
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (Inst.getOpcode() == ARM::MVE_SQRSHRL || if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
Inst.getOpcode() == ARM::MVE_UQRSHLL) { Inst.getOpcode() == ARM::MVE_UQRSHLL) {
unsigned Saturate = fieldFromInstruction(Insn, 7, 1); unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
// Saturate, the bit position for saturation // Saturate, the bit position for saturation
Inst.addOperand(MCOperand::createImm(Saturate)); Inst.addOperand(MCOperand::createImm(Saturate));
} }
return S; return S;
} }
static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
fieldFromInstruction(Insn, 13, 3)); fieldFromInstruction(Insn, 13, 3));
unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
fieldFromInstruction(Insn, 1, 3)); fieldFromInstruction(Insn, 1, 3));
unsigned imm6 = fieldFromInstruction(Insn, 16, 6); unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
template<bool scalar, OperandDecoder predicate_decoder> template<bool scalar, OperandDecoder predicate_decoder>
static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
Inst.addOperand(MCOperand::createReg(ARM::VPR)); Inst.addOperand(MCOperand::createReg(ARM::VPR));
unsigned Qn = fieldFromInstruction(Insn, 17, 3); unsigned Qn = fieldFromInstruction(Insn, 17, 3);
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned fc; unsigned fc;
if (scalar) { if (scalar) {
fc = fieldFromInstruction(Insn, 12, 1) << 2 | fc = fieldFromInstruction(Insn, 12, 1) << 2 |
fieldFromInstruction(Insn, 7, 1) | fieldFromInstruction(Insn, 7, 1) |
fieldFromInstruction(Insn, 5, 1) << 1; fieldFromInstruction(Insn, 5, 1) << 1;
unsigned Rm = fieldFromInstruction(Insn, 0, 4); unsigned Rm = fieldFromInstruction(Insn, 0, 4);
if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, decodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} else { } else {
fc = fieldFromInstruction(Insn, 12, 1) << 2 | fc = fieldFromInstruction(Insn, 12, 1) << 2 |
fieldFromInstruction(Insn, 7, 1) | fieldFromInstruction(Insn, 7, 1) |
fieldFromInstruction(Insn, 0, 1) << 1; fieldFromInstruction(Insn, 0, 1) << 1;
unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
fieldFromInstruction(Insn, 1, 3); fieldFromInstruction(Insn, 1, 3);
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) if (!Check(S, decodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(ARMVCC::None)); Inst.addOperand(MCOperand::createImm(ARMVCC::None));
Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createReg(0));
Inst.addOperand(MCOperand::createImm(0)); Inst.addOperand(MCOperand::createImm(0));
return S; return S;
} }
static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
Inst.addOperand(MCOperand::createReg(ARM::VPR)); Inst.addOperand(MCOperand::createReg(ARM::VPR));
unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4);
if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) if (!Check(S, decoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
return S; return S;
} }
static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
Inst.addOperand(MCOperand::createReg(ARM::VPR)); Inst.addOperand(MCOperand::createReg(ARM::VPR));
Show All 13 Linesstatic DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
unsigned sign2 = fieldFromInstruction(Insn, 23, 1); unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
unsigned S = fieldFromInstruction(Insn, 20, 1); unsigned S = fieldFromInstruction(Insn, 20, 1);
if (sign1 != sign2) if (sign1 != sign2)
return MCDisassembler::Fail; return MCDisassembler::Fail;
// T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
DecodeStatus DS = MCDisassembler::Success; DecodeStatus DS = MCDisassembler::Success;
if ((!Check(DS, if ((!Check(DS,
DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst decodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
(!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) (!Check(DS, decodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (TypeT3) { if (TypeT3) {
Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
} else { } else {
Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return DS; return DS;
} }

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
static const uint16_t GPRDecoderTable[] = { static const uint16_t GPRDecoderTable[] = {
AVR::R0, AVR::R1, AVR::R2, AVR::R3, AVR::R4, AVR::R5, AVR::R6, AVR::R0, AVR::R1, AVR::R2, AVR::R3, AVR::R4, AVR::R5, AVR::R6,
AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13, AVR::R7, AVR::R8, AVR::R9, AVR::R10, AVR::R11, AVR::R12, AVR::R13,
AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20, AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27, AVR::R21, AVR::R22, AVR::R23, AVR::R24, AVR::R25, AVR::R26, AVR::R27,
AVR::R28, AVR::R29, AVR::R30, AVR::R31, AVR::R28, AVR::R29, AVR::R30, AVR::R31,
}; };
static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo]; unsigned Register = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo + 16]; unsigned Register = GPRDecoderTable[RegNo + 16];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
// Note: this function must be defined but does not seem to be called. // Note: this function must be defined but does not seem to be called.
assert(false && "unimplemented: PTRREGS register class"); assert(false && "unimplemented: PTRREGS register class");
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
Show All 30 Lines
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned addr = 0; unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4; addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5); unsigned reg = fieldFromInstruction(Insn, 4, 5);
Inst.addOperand(MCOperand::createImm(addr)); Inst.addOperand(MCOperand::createImm(addr));
if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned addr = 0; unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4; addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5); unsigned reg = fieldFromInstruction(Insn, 4, 5);
if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(addr)); Inst.addOperand(MCOperand::createImm(addr));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
Show All 10 Linesstatic DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
// decoder. // decoder.
Inst.addOperand(MCOperand::createImm(Field << 1)); Inst.addOperand(MCOperand::createImm(Field << 1));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 5); unsigned d = fieldFromInstruction(Insn, 4, 5);
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail) if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(AVR::R31R30)); Inst.addOperand(MCOperand::createReg(AVR::R31R30));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 3) + 16; unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
unsigned r = fieldFromInstruction(Insn, 0, 3) + 16; unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned r = fieldFromInstruction(Insn, 4, 4) * 2; unsigned r = fieldFromInstruction(Insn, 4, 4) * 2;
unsigned d = fieldFromInstruction(Insn, 0, 4) * 2; unsigned d = fieldFromInstruction(Insn, 0, 4) * 2;
if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25 unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25
unsigned k = 0; unsigned k = 0;
k |= fieldFromInstruction(Insn, 0, 4); k |= fieldFromInstruction(Insn, 0, 4);
k |= fieldFromInstruction(Insn, 6, 2) << 4; k |= fieldFromInstruction(Insn, 6, 2) << 4;
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(k)); Inst.addOperand(MCOperand::createImm(k));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16; unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;
unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16; unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;
if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, rd, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) == if (decodeGPR8RegisterClass(Inst, rr, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint32_t &Insn) { uint64_t &Size, uint32_t &Insn) {
if (Bytes.size() < 2) { if (Bytes.size() < 2) {
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Linesextern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFDisassembler() {
TargetRegistry::RegisterMCDisassembler(getTheBPFbeTarget(), TargetRegistry::RegisterMCDisassembler(getTheBPFbeTarget(),
createBPFDisassembler); createBPFDisassembler);
} }
static const unsigned GPRDecoderTable[] = { static const unsigned GPRDecoderTable[] = {
BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11}; BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void * /*Decoder*/) { const void * /*Decoder*/) {
if (RegNo > 11) if (RegNo > 11)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = GPRDecoderTable[RegNo]; unsigned Reg = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static const unsigned GPR32DecoderTable[] = { static const unsigned GPR32DecoderTable[] = {
BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5,
BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W10, BPF::W11}; BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W10, BPF::W11};
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void * /*Decoder*/) { const void * /*Decoder*/) {
if (RegNo > 11) if (RegNo > 11)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = GPR32DecoderTable[RegNo]; unsigned Reg = GPR32DecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonBaseInfo.h"
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesstatic void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
int64_t Extended = SignExtend64<32>(FullValue); int64_t Extended = SignExtend64<32>(FullValue);
HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
} }
} }
// Forward declare these because the auto-generated code will reference them. // Forward declare these because the auto-generated code will reference them.
// Definitions are further down. // Definitions are further down.
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeGeneralSubRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus static DecodeStatus
DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, decodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, static DecodeStatus decodeHvxVQRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
uint64_t /*Address*/, const void *Decoder); uint64_t /*Address*/, const void *Decoder);
▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
: MI; : MI;
if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
!HexagonMCInstrInfo::isExtended(*MCII, Inst)) !HexagonMCInstrInfo::isExtended(*MCII, Inst))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return Result; return Result;
} }
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeRegisterClass(MCInst &Inst, unsigned RegNo,
ArrayRef<MCPhysReg> Table) { ArrayRef<MCPhysReg> Table) {
if (RegNo < Table.size()) { if (RegNo < Table.size()) {
Inst.addOperand(MCOperand::createReg(Table[RegNo])); Inst.addOperand(MCOperand::createReg(Table[RegNo]));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); return decodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg IntRegDecoderTable[] = { static const MCPhysReg IntRegDecoderTable[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
Hexagon::R30, Hexagon::R31}; Hexagon::R30, Hexagon::R31};
return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); return decodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
} }
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeGeneralSubRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg GeneralSubRegDecoderTable[] = { static const MCPhysReg GeneralSubRegDecoderTable[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
}; };
return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); return decodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
} }
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg HvxVRDecoderTable[] = { static const MCPhysReg HvxVRDecoderTable[] = {
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
Hexagon::V30, Hexagon::V31}; Hexagon::V30, Hexagon::V31};
return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); return decodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
} }
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg DoubleRegDecoderTable[] = { static const MCPhysReg DoubleRegDecoderTable[] = {
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); return decodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
} }
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( static DecodeStatus decodeGeneralDoubleLow8RegsRegisterClass(
MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); return decodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
} }
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg HvxWRDecoderTable[] = { static const MCPhysReg HvxWRDecoderTable[] = {
Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2, Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7, Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9, Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12, Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14, Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
Hexagon::W15, Hexagon::WR15, Hexagon::W15, Hexagon::WR15,
}; };
return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable); return decodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
} }
LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, static DecodeStatus decodeHvxVQRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg HvxVQRDecoderTable[] = { static const MCPhysReg HvxVQRDecoderTable[] = {
Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7}; Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable); return decodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
} }
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
Hexagon::P2, Hexagon::P3}; Hexagon::P2, Hexagon::P3};
return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); return decodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
} }
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
Hexagon::Q2, Hexagon::Q3}; Hexagon::Q2, Hexagon::Q3};
return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); return decodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
} }
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
using namespace Hexagon; using namespace Hexagon;
static const MCPhysReg CtrlRegDecoderTable[] = { static const MCPhysReg CtrlRegDecoderTable[] = {
/* 0 */ SA0, LC0, SA1, LC1, /* 0 */ SA0, LC0, SA1, LC1,
/* 4 */ P3_0, C5, M0, M1, /* 4 */ P3_0, C5, M0, M1,
/* 8 */ USR, PC, UGP, GP, /* 8 */ USR, PC, UGP, GP,
Show All 11 Linesstatic DecodeStatus decodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
if (CtrlRegDecoderTable[RegNo] == NoRegister) if (CtrlRegDecoderTable[RegNo] == NoRegister)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = CtrlRegDecoderTable[RegNo]; unsigned Register = CtrlRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
using namespace Hexagon; using namespace Hexagon;
static const MCPhysReg CtrlReg64DecoderTable[] = { static const MCPhysReg CtrlReg64DecoderTable[] = {
/* 0 */ C1_0, 0, C3_2, 0, /* 0 */ C1_0, 0, C3_2, 0,
/* 4 */ C5_4, 0, C7_6, 0, /* 4 */ C5_4, 0, C7_6, 0,
/* 8 */ C9_8, 0, C11_10, 0, /* 8 */ C9_8, 0, C11_10, 0,
Show All 11 Linesstatic DecodeStatus decodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
if (CtrlReg64DecoderTable[RegNo] == NoRegister) if (CtrlReg64DecoderTable[RegNo] == NoRegister)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = CtrlReg64DecoderTable[RegNo]; unsigned Register = CtrlReg64DecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
unsigned Register = 0; unsigned Register = 0;
switch (RegNo) { switch (RegNo) {
case 0: case 0:
Register = Hexagon::M0; Register = Hexagon::M0;
break; break;
case 1: case 1:
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linesstatic const uint16_t SysRegDecoderTable[] = {
Hexagon::S63, Hexagon::S64, Hexagon::S65, Hexagon::S63, Hexagon::S64, Hexagon::S65,
Hexagon::S66, Hexagon::S67, Hexagon::S68, Hexagon::S66, Hexagon::S67, Hexagon::S68,
Hexagon::S69, Hexagon::S70, Hexagon::S71, Hexagon::S69, Hexagon::S70, Hexagon::S71,
Hexagon::S72, Hexagon::S73, Hexagon::S74, Hexagon::S72, Hexagon::S73, Hexagon::S74,
Hexagon::S75, Hexagon::S76, Hexagon::S77, Hexagon::S75, Hexagon::S76, Hexagon::S77,
Hexagon::S78, Hexagon::S79, Hexagon::S80, Hexagon::S78, Hexagon::S79, Hexagon::S80,
}; };
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0])) if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0]))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister) if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Show All 10 Linesstatic const uint16_t SysReg64DecoderTable[] = {
Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38, Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46, Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54, Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62, Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70, Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78, Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
}; };
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
RegNo = RegNo >> 1; RegNo = RegNo >> 1;
if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0])) if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0]))
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister) if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = SysReg64DecoderTable[RegNo]; unsigned Register = SysReg64DecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
using namespace Hexagon; using namespace Hexagon;
static const MCPhysReg GuestRegDecoderTable[] = { static const MCPhysReg GuestRegDecoderTable[] = {
/* 0 */ GELR, GSR, GOSP, G3, /* 0 */ GELR, GSR, GOSP, G3,
/* 4 */ G4, G5, G6, G7, /* 4 */ G4, G5, G6, G7,
/* 8 */ G8, G9, G10, G11, /* 8 */ G8, G9, G10, G11,
Show All 9 Linesstatic DecodeStatus decodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister) if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Register = GuestRegDecoderTable[RegNo]; unsigned Register = GuestRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void *Decoder) { const void *Decoder) {
using namespace Hexagon; using namespace Hexagon;
static const MCPhysReg GuestReg64DecoderTable[] = { static const MCPhysReg GuestReg64DecoderTable[] = {
/* 0 */ G1_0, 0, G3_2, 0, /* 0 */ G1_0, 0, G3_2, 0,
/* 4 */ G5_4, 0, G7_6, 0, /* 4 */ G5_4, 0, G7_6, 0,
/* 8 */ G9_8, 0, G11_10, 0, /* 8 */ G9_8, 0, G11_10, 0,
Show All 16 Lines

llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp

Show All 37 Lines TargetRegistry::RegisterMCDisassembler(getTheLanaiTarget(),
createLanaiDisassembler); createLanaiDisassembler);
} }
LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
: MCDisassembler(STI, Ctx) {} : MCDisassembler(STI, Ctx) {}
// Forward declare because the autogenerated code will reference this. // Forward declare because the autogenerated code will reference this.
// Definition is further down. // Definition is further down.
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
static const unsigned GPRDecoderTable[] = { static const unsigned GPRDecoderTable[] = {
Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP, Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,
Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2, Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17, Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23, Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29, Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
Lanai::R30, Lanai::R31}; Lanai::R30, Lanai::R31};
DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, DecodeStatus decodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, uint64_t /*Address*/,
const void * /*Decoder*/) { const void * /*Decoder*/) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = GPRDecoderTable[RegNo]; unsigned Reg = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
static const unsigned GR8DecoderTable[] = { static const unsigned GR8DecoderTable[] = {
MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB, MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB,
MSP430::R4B, MSP430::R5B, MSP430::R6B, MSP430::R7B, MSP430::R4B, MSP430::R5B, MSP430::R6B, MSP430::R7B,
MSP430::R8B, MSP430::R9B, MSP430::R10B, MSP430::R11B, MSP430::R8B, MSP430::R9B, MSP430::R10B, MSP430::R11B,
MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B
}; };
static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo, static DecodeStatus decodeGR8RegisterClass(MCInst &MI, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = GR8DecoderTable[RegNo]; unsigned Reg = GR8DecoderTable[RegNo];
MI.addOperand(MCOperand::createReg(Reg)); MI.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static const unsigned GR16DecoderTable[] = { static const unsigned GR16DecoderTable[] = {
MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG, MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG,
MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7,
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
}; };
static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo, static DecodeStatus decodeGR16RegisterClass(MCInst &MI, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = GR16DecoderTable[RegNo]; unsigned Reg = GR16DecoderTable[RegNo];
MI.addOperand(MCOperand::createReg(Reg)); MI.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
Show All 26 Lines
} }
static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits, static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Reg = Bits & 15; unsigned Reg = Bits & 15;
unsigned Imm = Bits >> 4; unsigned Imm = Bits >> 4;
if (DecodeGR16RegisterClass(MI, Reg, Address, Decoder) != if (decodeGR16RegisterClass(MI, Reg, Address, Decoder) !=
MCDisassembler::Success) MCDisassembler::Success)
return MCDisassembler::Fail; return MCDisassembler::Fail;
MI.addOperand(MCOperand::createImm((int16_t)Imm)); MI.addOperand(MCOperand::createImm((int16_t)Imm));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
enum AddrMode { enum AddrMode {
amInvalid = 0, amInvalid = 0,
amRegister, amRegister,
amIndexed, amIndexed,
▲ Show 20 Lines • Show All 234 Lines • Show Last 20 Lines

llvm/lib/Target/MSP430/MSP430InstrInfo.td

Show All 25 Linesdef SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>,
SDTCisVT<1, i16>]>; SDTCisVT<1, i16>]>;
def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
SDTCisPtrTy<0>]>; SDTCisPtrTy<0>]>;
def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
SDTCisVT<1, i8>]>; SDTCisVT<1, i8>]>;
def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
SDTCisSameAs<1, 2>, SDTCisSameAs<1, 2>,
SDTCisVT<3, i8>]>; SDTCisVT<3, i8>]>;
def SDT_MSP430DAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, def SDT_MSP430DAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
SDTCisSameAs<0, 2>, SDTCisSameAs<0, 2>,
SDTCisInt<0>]>; SDTCisInt<0>]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MSP430 Specific Node Definitions. // MSP430 Specific Node Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesdef IndRegAsmOperand : AsmOperandClass {
let Name = "IndReg"; let Name = "IndReg";
let RenderMethod = "addRegOperands"; let RenderMethod = "addRegOperands";
} }
def indreg : Operand<i16> { def indreg : Operand<i16> {
let PrintMethod = "printIndRegOperand"; let PrintMethod = "printIndRegOperand";
let MIOperandInfo = (ops GR16); let MIOperandInfo = (ops GR16);
let ParserMatchClass = IndRegAsmOperand; let ParserMatchClass = IndRegAsmOperand;
let DecoderMethod = "DecodeGR16RegisterClass"; let DecoderMethod = "decodeGR16RegisterClass";
} }
def PostIndRegAsmOperand : AsmOperandClass { def PostIndRegAsmOperand : AsmOperandClass {
let Name = "PostIndReg"; let Name = "PostIndReg";
let RenderMethod = "addRegOperands"; let RenderMethod = "addRegOperands";
} }
def postreg : Operand<i16> { def postreg : Operand<i16> {
let PrintMethod = "printPostIndRegOperand"; let PrintMethod = "printPostIndRegOperand";
let MIOperandInfo = (ops GR16); let MIOperandInfo = (ops GR16);
let ParserMatchClass = PostIndRegAsmOperand; let ParserMatchClass = PostIndRegAsmOperand;
let DecoderMethod = "DecodeGR16RegisterClass"; let DecoderMethod = "decodeGR16RegisterClass";
} }
// Short jump targets have OtherVT type and are printed as pcrel imm values. // Short jump targets have OtherVT type and are printed as pcrel imm values.
def jmptarget : Operand<OtherVT> { def jmptarget : Operand<OtherVT> {
let PrintMethod = "printPCRelImmOperand"; let PrintMethod = "printPCRelImmOperand";
let EncoderMethod = "getPCRelImmOpValue"; let EncoderMethod = "getPCRelImmOpValue";
} }
▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines def 8mi : I8mi<opcode, (outs), (ins memdst:$dst, i8imm:$imm),
[(store (node (load addr:$dst), (i8 imm:$imm)), addr:$dst), [(store (node (load addr:$dst), (i8 imm:$imm)), addr:$dst),
(implicit SR)]>; (implicit SR)]>;
def 16mi : I16mi<opcode, (outs), (ins memdst:$dst, i16imm:$imm), def 16mi : I16mi<opcode, (outs), (ins memdst:$dst, i16imm:$imm),
!strconcat(asmstring, "\t$imm, $dst"), !strconcat(asmstring, "\t$imm, $dst"),
[(store (node (load addr:$dst), (i16 imm:$imm)), addr:$dst), [(store (node (load addr:$dst), (i16 imm:$imm)), addr:$dst),
(implicit SR)]>; (implicit SR)]>;
def 8mm : I8mm<opcode, (outs), (ins memdst:$dst, memsrc:$src), def 8mm : I8mm<opcode, (outs), (ins memdst:$dst, memsrc:$src),
!strconcat(asmstring, ".b\t$src, $dst"), !strconcat(asmstring, ".b\t$src, $dst"),
[(store (node (load addr:$dst), [(store (node (load addr:$dst),
(i8 (load addr:$src))), addr:$dst), (i8 (load addr:$src))), addr:$dst),
(implicit SR)]>; (implicit SR)]>;
def 16mm : I16mm<opcode, (outs), (ins memdst:$dst, memsrc:$src), def 16mm : I16mm<opcode, (outs), (ins memdst:$dst, memsrc:$src),
!strconcat(asmstring, "\t$src, $dst"), !strconcat(asmstring, "\t$src, $dst"),
[(store (node (load addr:$dst), [(store (node (load addr:$dst),
(i16 (load addr:$src))), addr:$dst), (i16 (load addr:$src))), addr:$dst),
(implicit SR)]>; (implicit SR)]>;
def 8mn : I8mn<opcode, (outs), (ins memdst:$dst, indreg:$rs), def 8mn : I8mn<opcode, (outs), (ins memdst:$dst, indreg:$rs),
!strconcat(asmstring, ".b\t$rs, $dst"), []>; !strconcat(asmstring, ".b\t$rs, $dst"), []>;
def 16mn : I16mn<opcode, (outs), (ins memdst:$dst, indreg:$rs), def 16mn : I16mn<opcode, (outs), (ins memdst:$dst, indreg:$rs),
!strconcat(asmstring, "\t$rs, $dst"), []>; !strconcat(asmstring, "\t$rs, $dst"), []>;
def 8mp : I8mp<opcode, (outs), (ins memdst:$dst, postreg:$rs), def 8mp : I8mp<opcode, (outs), (ins memdst:$dst, postreg:$rs),
!strconcat(asmstring, ".b\t$rs, $dst"), []>; !strconcat(asmstring, ".b\t$rs, $dst"), []>;
▲ Show 20 Lines • Show All 239 Lines • ▼ Show 20 Linesdef CMP16mi : I16mi<0b1001,
(outs), (ins memsrc:$dst, i16imm:$imm), (outs), (ins memsrc:$dst, i16imm:$imm),
"cmp\t$imm, $dst", "cmp\t$imm, $dst",
[(MSP430cmp (load addr:$dst), [(MSP430cmp (load addr:$dst),
(i16 imm:$imm)), (implicit SR)]>; (i16 imm:$imm)), (implicit SR)]>;
def CMP8rm : I8rm<0b1001, def CMP8rm : I8rm<0b1001,
(outs), (ins GR8:$rd, memsrc:$src), (outs), (ins GR8:$rd, memsrc:$src),
"cmp.b\t$src, $rd", "cmp.b\t$src, $rd",
[(MSP430cmp GR8:$rd, (load addr:$src)), [(MSP430cmp GR8:$rd, (load addr:$src)),
(implicit SR)]>; (implicit SR)]>;
def CMP16rm : I16rm<0b1001, def CMP16rm : I16rm<0b1001,
(outs), (ins GR16:$rd, memsrc:$src), (outs), (ins GR16:$rd, memsrc:$src),
"cmp\t$src, $rd", "cmp\t$src, $rd",
[(MSP430cmp GR16:$rd, (load addr:$src)), [(MSP430cmp GR16:$rd, (load addr:$src)),
(implicit SR)]>; (implicit SR)]>;
def CMP8rn : I8rn<0b1001, def CMP8rn : I8rn<0b1001,
Show All 9 Lines
def CMP8mr : I8mr<0b1001, def CMP8mr : I8mr<0b1001,
(outs), (ins memsrc:$dst, GR8:$rs), (outs), (ins memsrc:$dst, GR8:$rs),
"cmp.b\t$rs, $dst", "cmp.b\t$rs, $dst",
[(MSP430cmp (load addr:$dst), GR8:$rs), [(MSP430cmp (load addr:$dst), GR8:$rs),
(implicit SR)]>; (implicit SR)]>;
def CMP16mr : I16mr<0b1001, def CMP16mr : I16mr<0b1001,
(outs), (ins memsrc:$dst, GR16:$rs), (outs), (ins memsrc:$dst, GR16:$rs),
"cmp\t$rs, $dst", "cmp\t$rs, $dst",
[(MSP430cmp (load addr:$dst), GR16:$rs), [(MSP430cmp (load addr:$dst), GR16:$rs),
(implicit SR)]>; (implicit SR)]>;
def CMP8mm : I8mm<0b1001, def CMP8mm : I8mm<0b1001,
(outs), (ins memdst:$dst, memsrc:$src), (outs), (ins memdst:$dst, memsrc:$src),
"cmp.b\t$src, $dst", "cmp.b\t$src, $dst",
[(MSP430cmp (load addr:$dst), (i8 (load addr:$src))), [(MSP430cmp (load addr:$dst), (i8 (load addr:$src))),
(implicit SR)]>; (implicit SR)]>;
def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src), def CMP16mm : I16mm<0b1001, (outs), (ins memdst:$dst, memsrc:$src),
"cmp\t$src, $dst", "cmp\t$src, $dst",
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file is part of the Mips Disassembler. // This file is part of the Mips Disassembler.
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address, ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &CStream) const override; raw_ostream &CStream) const override;
}; };
} // end anonymous namespace } // end anonymous namespace
// Forward declare these because the autogenerated code will reference them. // Forward declare these because the autogenerated code will reference them.
// Definitions are further down. // Definitions are further down.
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, static DecodeStatus decodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, static DecodeStatus decodeGPRMM16RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRMM16ZeroRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, static DecodeStatus decodePtrRegisterClass(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, static DecodeStatus decodeDSPRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, static DecodeStatus decodeFGR64RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, static DecodeStatus decodeFGR32RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, static DecodeStatus decodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, static DecodeStatus decodeFCCRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeHWRegsRegisterClass(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, static DecodeStatus decodeAFGR64RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, static DecodeStatus decodeACC64DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, static DecodeStatus decodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, static DecodeStatus decodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128BRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128HRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128WRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128DRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, static DecodeStatus decodeMSACtrlRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, static DecodeStatus decodeCOP0RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, static DecodeStatus decodeCOP2RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeBranchTarget(MCInst &Inst, static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
// The size of the n field depends on the element size // The size of the n field depends on the element size
// The register class also depends on this. // The register class also depends on this.
InsnType tmp = fieldFromInstruction(insn, 17, 5); InsnType tmp = fieldFromInstruction(insn, 17, 5);
unsigned NSize = 0; unsigned NSize = 0;
DecodeFN RegDecoder = nullptr; DecodeFN RegDecoder = nullptr;
if ((tmp & 0x18) == 0x00) { // INSVE_B if ((tmp & 0x18) == 0x00) { // INSVE_B
NSize = 4; NSize = 4;
RegDecoder = DecodeMSA128BRegisterClass; RegDecoder = decodeMSA128BRegisterClass;
} else if ((tmp & 0x1c) == 0x10) { // INSVE_H } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
NSize = 3; NSize = 3;
RegDecoder = DecodeMSA128HRegisterClass; RegDecoder = decodeMSA128HRegisterClass;
} else if ((tmp & 0x1e) == 0x18) { // INSVE_W } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
NSize = 2; NSize = 2;
RegDecoder = DecodeMSA128WRegisterClass; RegDecoder = decodeMSA128WRegisterClass;
} else if ((tmp & 0x1f) == 0x1c) { // INSVE_D } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
NSize = 1; NSize = 1;
RegDecoder = DecodeMSA128DRegisterClass; RegDecoder = decodeMSA128DRegisterClass;
} else } else
llvm_unreachable("Invalid encoding"); llvm_unreachable("Invalid encoding");
assert(NSize != 0 && RegDecoder != nullptr); assert(NSize != 0 && RegDecoder != nullptr);
// $wd // $wd
tmp = fieldFromInstruction(insn, 6, 5); tmp = fieldFromInstruction(insn, 6, 5);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
▲ Show 20 Lines • Show All 771 Lines • ▼ Show 20 LinesDecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
Result = Result =
decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
if (Result != MCDisassembler::Fail) if (Result != MCDisassembler::Fail)
return Result; return Result;
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, static DecodeStatus decodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, static DecodeStatus decodeGPR64RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, static DecodeStatus decodeGPRMM16RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRMM16ZeroRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, static DecodeStatus decodeGPRMM16MovePRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, static DecodeStatus decodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, static DecodeStatus decodePtrRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); return decodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); return decodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, static DecodeStatus decodeDSPRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); return decodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, static DecodeStatus decodeFGR64RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, static DecodeStatus decodeFGR32RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, static DecodeStatus decodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, static DecodeStatus decodeFCCRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
▲ Show 20 Lines • Show All 224 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeMemMMImm4(MCInst &Inst,
unsigned Offset = Insn & 0xf; unsigned Offset = Insn & 0xf;
unsigned Reg = fieldFromInstruction(Insn, 7, 3); unsigned Reg = fieldFromInstruction(Insn, 7, 3);
unsigned Base = fieldFromInstruction(Insn, 4, 3); unsigned Base = fieldFromInstruction(Insn, 4, 3);
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case Mips::LBU16_MM: case Mips::LBU16_MM:
case Mips::LHU16_MM: case Mips::LHU16_MM:
case Mips::LW16_MM: case Mips::LW16_MM:
if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) if (decodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
== MCDisassembler::Fail) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
case Mips::SB16_MM: case Mips::SB16_MM:
case Mips::SB16_MMR6: case Mips::SB16_MMR6:
case Mips::SH16_MM: case Mips::SH16_MM:
case Mips::SH16_MMR6: case Mips::SH16_MMR6:
case Mips::SW16_MM: case Mips::SW16_MM:
case Mips::SW16_MMR6: case Mips::SW16_MMR6:
if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) if (decodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
== MCDisassembler::Fail) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
break; break;
} }
if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) if (decodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
== MCDisassembler::Fail) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case Mips::LBU16_MM: case Mips::LBU16_MM:
if (Offset == 0xf) if (Offset == 0xf)
Inst.addOperand(MCOperand::createImm(-1)); Inst.addOperand(MCOperand::createImm(-1));
else else
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
Inst.addOperand(MCOperand::createReg(Rt)); Inst.addOperand(MCOperand::createReg(Rt));
Inst.addOperand(MCOperand::createReg(Base)); Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset)); Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeHWRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
// Currently only hardware register 29 is supported. // Currently only hardware register 29 is supported.
if (RegNo != 29) if (RegNo != 29)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(Mips::HWR29)); Inst.addOperand(MCOperand::createReg(Mips::HWR29));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, static DecodeStatus decodeAFGR64RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 30 || RegNo %2) if (RegNo > 30 || RegNo %2)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, static DecodeStatus decodeACC64DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 4) if (RegNo >= 4)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, static DecodeStatus decodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 4) if (RegNo >= 4)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, static DecodeStatus decodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 4) if (RegNo >= 4)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128BRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128HRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128WRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, static DecodeStatus decodeMSA128DRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, static DecodeStatus decodeMSACtrlRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 7) if (RegNo > 7)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, static DecodeStatus decodeCOP0RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, static DecodeStatus decodeCOP2RegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
▲ Show 20 Lines • Show All 274 Lines • ▼ Show 20 Lines if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned RegRs; unsigned RegRs;
if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
RegRs = fieldFromInstruction(Insn, 0, 2) | RegRs = fieldFromInstruction(Insn, 0, 2) |
(fieldFromInstruction(Insn, 3, 1) << 2); (fieldFromInstruction(Insn, 3, 1) << 2);
else else
RegRs = fieldFromInstruction(Insn, 1, 3); RegRs = fieldFromInstruction(Insn, 1, 3);
if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == if (decodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned RegRt = fieldFromInstruction(Insn, 4, 3); unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == if (decodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
MCDisassembler::Fail) MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,167 Lines • ▼ Show 20 Linesdef mem_ea : Operand<iPTR> {
let PrintMethod = "printMemOperandEA"; let PrintMethod = "printMemOperandEA";
let MIOperandInfo = (ops ptr_rc, simm16); let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding"; let EncoderMethod = "getMemEncoding";
let OperandType = "OPERAND_MEMORY"; let OperandType = "OPERAND_MEMORY";
} }
def PtrRC : Operand<iPTR> { def PtrRC : Operand<iPTR> {
let MIOperandInfo = (ops ptr_rc); let MIOperandInfo = (ops ptr_rc);
let DecoderMethod = "DecodePtrRegisterClass"; let DecoderMethod = "decodePtrRegisterClass";
let ParserMatchClass = GPR32AsmOperand; let ParserMatchClass = GPR32AsmOperand;
} }
// size operand of ins instruction // size operand of ins instruction
def size_ins : Operand<i32> { def size_ins : Operand<i32> {
let EncoderMethod = "getSizeInsEncoding"; let EncoderMethod = "getSizeInsEncoding";
let DecoderMethod = "DecodeInsSize"; let DecoderMethod = "DecodeInsSize";
} }
▲ Show 20 Lines • Show All 2,224 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCMCTargetDesc.h"
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
template <std::size_t N> template <std::size_t N>
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
const MCPhysReg (&Regs)[N]) { const MCPhysReg (&Regs)[N]) {
assert(RegNo < N && "Invalid register number"); assert(RegNo < N && "Invalid register number");
Inst.addOperand(MCOperand::createReg(Regs[RegNo])); Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, CRRegs); return decodeRegisterClass(Inst, RegNo, CRRegs);
} }
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, CRBITRegs); return decodeRegisterClass(Inst, RegNo, CRBITRegs);
} }
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, FRegs); return decodeRegisterClass(Inst, RegNo, FRegs);
} }
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, FRegs); return decodeRegisterClass(Inst, RegNo, FRegs);
} }
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, VFRegs); return decodeRegisterClass(Inst, RegNo, VFRegs);
} }
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, VRegs); return decodeRegisterClass(Inst, RegNo, VRegs);
} }
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSRegs); return decodeRegisterClass(Inst, RegNo, VSRegs);
} }
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSFRegs); return decodeRegisterClass(Inst, RegNo, VSFRegs);
} }
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSSRegs); return decodeRegisterClass(Inst, RegNo, VSSRegs);
} }
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, RRegs); return decodeRegisterClass(Inst, RegNo, RRegs);
} }
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, RRegsNoR0); return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
} }
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, XRegs); return decodeRegisterClass(Inst, RegNo, XRegs);
} }
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, XRegs); return decodeRegisterClass(Inst, RegNo, XRegs);
} }
static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, XRegsNoX0); return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
} }
#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass #define decodePointerLikeRegClass0 decodeGPRCRegisterClass
#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass #define decodePointerLikeRegClass1 decodeGPRC_NOR0RegisterClass
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SPERegs); return decodeRegisterClass(Inst, RegNo, SPERegs);
} }
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, ACCRegs); return decodeRegisterClass(Inst, RegNo, ACCRegs);
} }
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSRpRegs); return decodeRegisterClass(Inst, RegNo, VSRpRegs);
} }
#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass #define decodeQSRCRegisterClass decodeQFRCRegisterClass
#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass #define decodeQBRCRegisterClass decodeQFRCRegisterClass
template<unsigned N> template<unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
int64_t Address, const void *Decoder) { int64_t Address, const void *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate"); assert(isUInt<N>(Imm) && "Invalid immediate");
Inst.addOperand(MCOperand::createImm(Imm)); Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
▲ Show 20 Lines • Show All 247 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
// Register the disassembler for each target. // Register the disassembler for each target.
TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(), TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
createRISCVDisassembler); createRISCVDisassembler);
TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(), TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
createRISCVDisassembler); createRISCVDisassembler);
} }
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
const FeatureBitset &FeatureBits = const FeatureBitset &FeatureBits =
static_cast<const MCDisassembler *>(Decoder) static_cast<const MCDisassembler *>(Decoder)
->getSubtargetInfo() ->getSubtargetInfo()
.getFeatureBits(); .getFeatureBits();
bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
return MCDisassembler::Fail; return MCDisassembler::Fail;
MCRegister Reg = RISCV::X0 + RegNo; MCRegister Reg = RISCV::X0 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
MCRegister Reg = RISCV::F0_H + RegNo; MCRegister Reg = RISCV::F0_H + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
MCRegister Reg = RISCV::F0_F + RegNo; MCRegister Reg = RISCV::F0_F + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 8) { if (RegNo >= 8) {
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
MCRegister Reg = RISCV::F8_F + RegNo; MCRegister Reg = RISCV::F8_F + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
MCRegister Reg = RISCV::F0_D + RegNo; MCRegister Reg = RISCV::F0_D + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 8) { if (RegNo >= 8) {
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
MCRegister Reg = RISCV::F8_D + RegNo; MCRegister Reg = RISCV::F8_D + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo == 0) { if (RegNo == 0) {
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); return decodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo == 2) { if (RegNo == 2) {
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); return decodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
} }
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 8) if (RegNo >= 8)
return MCDisassembler::Fail; return MCDisassembler::Fail;
MCRegister Reg = RISCV::X8 + RegNo; MCRegister Reg = RISCV::X8 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
MCRegister Reg = RISCV::V0 + RegNo; MCRegister Reg = RISCV::V0 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (RegNo % 2) if (RegNo % 2)
return MCDisassembler::Fail; return MCDisassembler::Fail;
const RISCVDisassembler *Dis = const RISCVDisassembler *Dis =
static_cast<const RISCVDisassembler *>(Decoder); static_cast<const RISCVDisassembler *>(Decoder);
const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
MCRegister Reg = MCRegister Reg =
RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
&RISCVMCRegisterClasses[RISCV::VRM2RegClassID]); &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (RegNo % 4) if (RegNo % 4)
return MCDisassembler::Fail; return MCDisassembler::Fail;
const RISCVDisassembler *Dis = const RISCVDisassembler *Dis =
static_cast<const RISCVDisassembler *>(Decoder); static_cast<const RISCVDisassembler *>(Decoder);
const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo(); const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
MCRegister Reg = MCRegister Reg =
RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
&RISCVMCRegisterClasses[RISCV::VRM4RegClassID]); &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if (RegNo % 8) if (RegNo % 8)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Show All 29 Lines
static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) { static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP || if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP || Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
Inst.getOpcode() == RISCV::C_FLWSP || Inst.getOpcode() == RISCV::C_FLWSP ||
Inst.getOpcode() == RISCV::C_FSWSP || Inst.getOpcode() == RISCV::C_FSWSP ||
Inst.getOpcode() == RISCV::C_FLDSP || Inst.getOpcode() == RISCV::C_FLDSP ||
Inst.getOpcode() == RISCV::C_FSDSP || Inst.getOpcode() == RISCV::C_FSDSP ||
Inst.getOpcode() == RISCV::C_ADDI4SPN) { Inst.getOpcode() == RISCV::C_ADDI4SPN) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder); decodeGPRRegisterClass(Inst, 2, Address, Decoder);
} }
if (Inst.getOpcode() == RISCV::C_ADDI16SP) { if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder); decodeGPRRegisterClass(Inst, 2, Address, Decoder);
DecodeGPRRegisterClass(Inst, 2, Address, Decoder); decodeGPRRegisterClass(Inst, 2, Address, Decoder);
} }
} }
template <unsigned N> template <unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
int64_t Address, const void *Decoder) { int64_t Address, const void *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate"); assert(isUInt<N>(Imm) && "Invalid immediate");
addImplySP(Inst, Address, Decoder); addImplySP(Inst, Address, Decoder);
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Linesstatic DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
(void)Result; (void)Result;
assert(Result == MCDisassembler::Success && "Invalid immediate"); assert(Result == MCDisassembler::Success && "Invalid immediate");
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeGPRRegisterClass(Inst, 0, Address, Decoder); decodeGPRRegisterClass(Inst, 0, Address, Decoder);
uint64_t SImm6 = uint64_t SImm6 =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
(void)Result; (void)Result;
assert(Result == MCDisassembler::Success && "Invalid immediate"); assert(Result == MCDisassembler::Success && "Invalid immediate");
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
DecodeGPRRegisterClass(Inst, 0, Address, Decoder); decodeGPRRegisterClass(Inst, 0, Address, Decoder);
Inst.addOperand(Inst.getOperand(0)); Inst.addOperand(Inst.getOperand(0));
uint64_t UImm6 = uint64_t UImm6 =
fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
(void)Result; (void)Result;
assert(Result == MCDisassembler::Success && "Invalid immediate"); assert(Result == MCDisassembler::Success && "Invalid immediate");
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned Rd = fieldFromInstruction(Insn, 7, 5); unsigned Rd = fieldFromInstruction(Insn, 7, 5);
unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); decodeGPRRegisterClass(Inst, Rd, Address, Decoder);
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); decodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Rd = fieldFromInstruction(Insn, 7, 5); unsigned Rd = fieldFromInstruction(Insn, 7, 5);
unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); decodeGPRRegisterClass(Inst, Rd, Address, Decoder);
Inst.addOperand(Inst.getOperand(0)); Inst.addOperand(Inst.getOperand(0));
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); decodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
return MCDisassembler::Success; return MCDisassembler::Success;
} }
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes, ArrayRef<uint8_t> Bytes,
uint64_t Address, uint64_t Address,
raw_ostream &CS) const { raw_ostream &CS) const {
// TODO: This will need modification when supporting instruction set // TODO: This will need modification when supporting instruction set
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===// //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file is part of the Sparc Disassembler. // This file is part of the Sparc Disassembler.
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
static const uint16_t CPPairDecoderTable[] = { static const uint16_t CPPairDecoderTable[] = {
SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
}; };
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeIntRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = IntRegDecoderTable[RegNo]; unsigned Reg = IntRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, static DecodeStatus decodeI64RegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = IntRegDecoderTable[RegNo]; unsigned Reg = IntRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeFPRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = FPRegDecoderTable[RegNo]; unsigned Reg = FPRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeDFPRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = DFPRegDecoderTable[RegNo]; unsigned Reg = DFPRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeQFPRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = QFPRegDecoderTable[RegNo]; unsigned Reg = QFPRegDecoderTable[RegNo];
if (Reg == ~0U) if (Reg == ~0U)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeCPRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = CPRegDecoderTable[RegNo]; unsigned Reg = CPRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 3) if (RegNo > 3)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo >= array_lengthof(PRRegDecoderTable)) if (RegNo >= array_lengthof(PRRegDecoderTable))
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
if ((RegNo & 1)) if ((RegNo & 1))
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
unsigned RegisterPair = IntPairDecoderTable[RegNo/2]; unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
Inst.addOperand(MCOperand::createReg(RegisterPair)); Inst.addOperand(MCOperand::createReg(RegisterPair));
return S; return S;
} }
static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
if (RegNo > 31) if (RegNo > 31)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned RegisterPair = CPPairDecoderTable[RegNo/2]; unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
Inst.addOperand(MCOperand::createReg(RegisterPair)); Inst.addOperand(MCOperand::createReg(RegisterPair));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
DecodeStatus status; DecodeStatus status;
if (isLoad) { if (isLoad) {
status = DecodeRD(MI, rd, Address, Decoder); status = DecodeRD(MI, rd, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
// Decode rs1. // Decode rs1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
// Decode imm|rs2. // Decode imm|rs2.
if (isImm) if (isImm)
MI.addOperand(MCOperand::createImm(simm13)); MI.addOperand(MCOperand::createImm(simm13));
else { else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
if (hasAsi) if (hasAsi)
MI.addOperand(MCOperand::createImm(asi)); MI.addOperand(MCOperand::createImm(asi));
if (!isLoad) { if (!isLoad) {
status = DecodeRD(MI, rd, Address, Decoder); status = DecodeRD(MI, rd, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeIntRegsRegisterClass); decodeIntRegsRegisterClass);
} }
static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeIntPairRegisterClass); decodeIntPairRegisterClass);
} }
static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeFPRegsRegisterClass); decodeFPRegsRegisterClass);
} }
static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeDFPRegsRegisterClass); decodeDFPRegsRegisterClass);
} }
static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeQFPRegsRegisterClass); decodeQFPRegsRegisterClass);
} }
static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeCPRegsRegisterClass); decodeCPRegsRegisterClass);
} }
static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, return DecodeMem(Inst, insn, Address, Decoder, true,
DecodeCPPairRegisterClass); decodeCPPairRegisterClass);
} }
static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeIntRegsRegisterClass); decodeIntRegsRegisterClass);
} }
static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeIntPairRegisterClass); decodeIntPairRegisterClass);
} }
static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeFPRegsRegisterClass); decodeFPRegsRegisterClass);
} }
static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeDFPRegsRegisterClass); decodeDFPRegsRegisterClass);
} }
static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeQFPRegsRegisterClass); decodeQFPRegsRegisterClass);
} }
static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeCPRegsRegisterClass); decodeCPRegsRegisterClass);
} }
static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, return DecodeMem(Inst, insn, Address, Decoder, false,
DecodeCPPairRegisterClass); decodeCPPairRegisterClass);
} }
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
uint64_t Address, uint64_t Offset, uint64_t Address, uint64_t Offset,
uint64_t Width, MCInst &MI, uint64_t Width, MCInst &MI,
const void *Decoder) { const void *Decoder) {
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
Show All 26 Linesstatic DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
unsigned rs2 = 0; unsigned rs2 = 0;
unsigned simm13 = 0; unsigned simm13 = 0;
if (isImm) if (isImm)
simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
else else
rs2 = fieldFromInstruction(insn, 0, 5); rs2 = fieldFromInstruction(insn, 0, 5);
// Decode RD. // Decode RD.
DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); DecodeStatus status = decodeIntRegsRegisterClass(MI, rd, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
// Decode RS1. // Decode RS1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
// Decode RS1 | SIMM13. // Decode RS1 | SIMM13.
if (isImm) if (isImm)
MI.addOperand(MCOperand::createImm(simm13)); MI.addOperand(MCOperand::createImm(simm13));
else { else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned rs1 = fieldFromInstruction(insn, 14, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5);
unsigned isImm = fieldFromInstruction(insn, 13, 1); unsigned isImm = fieldFromInstruction(insn, 13, 1);
unsigned rs2 = 0; unsigned rs2 = 0;
unsigned simm13 = 0; unsigned simm13 = 0;
if (isImm) if (isImm)
simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
else else
rs2 = fieldFromInstruction(insn, 0, 5); rs2 = fieldFromInstruction(insn, 0, 5);
// Decode RS1. // Decode RS1.
DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); DecodeStatus status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
// Decode RS2 | SIMM13. // Decode RS2 | SIMM13.
if (isImm) if (isImm)
MI.addOperand(MCOperand::createImm(simm13)); MI.addOperand(MCOperand::createImm(simm13));
else { else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned rd = fieldFromInstruction(insn, 25, 5); unsigned rd = fieldFromInstruction(insn, 25, 5);
unsigned rs1 = fieldFromInstruction(insn, 14, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5);
unsigned isImm = fieldFromInstruction(insn, 13, 1); unsigned isImm = fieldFromInstruction(insn, 13, 1);
bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
unsigned asi = fieldFromInstruction(insn, 5, 8); unsigned asi = fieldFromInstruction(insn, 5, 8);
unsigned rs2 = 0; unsigned rs2 = 0;
unsigned simm13 = 0; unsigned simm13 = 0;
if (isImm) if (isImm)
simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
else else
rs2 = fieldFromInstruction(insn, 0, 5); rs2 = fieldFromInstruction(insn, 0, 5);
// Decode RD. // Decode RD.
DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); DecodeStatus status = decodeIntRegsRegisterClass(MI, rd, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
// Decode RS1. // Decode RS1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
// Decode RS1 | SIMM13. // Decode RS1 | SIMM13.
if (isImm) if (isImm)
MI.addOperand(MCOperand::createImm(simm13)); MI.addOperand(MCOperand::createImm(simm13));
else { else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
if (hasAsi) if (hasAsi)
MI.addOperand(MCOperand::createImm(asi)); MI.addOperand(MCOperand::createImm(asi));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address, static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned rs1 = fieldFromInstruction(insn, 14, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5);
unsigned isImm = fieldFromInstruction(insn, 13, 1); unsigned isImm = fieldFromInstruction(insn, 13, 1);
unsigned cc =fieldFromInstruction(insn, 25, 4); unsigned cc =fieldFromInstruction(insn, 25, 4);
unsigned rs2 = 0; unsigned rs2 = 0;
unsigned imm7 = 0; unsigned imm7 = 0;
if (isImm) if (isImm)
imm7 = fieldFromInstruction(insn, 0, 7); imm7 = fieldFromInstruction(insn, 0, 7);
else else
rs2 = fieldFromInstruction(insn, 0, 5); rs2 = fieldFromInstruction(insn, 0, 5);
// Decode RS1. // Decode RS1.
DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); DecodeStatus status = decodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
// Decode RS1 | IMM7. // Decode RS1 | IMM7.
if (isImm) if (isImm)
MI.addOperand(MCOperand::createImm(imm7)); MI.addOperand(MCOperand::createImm(imm7));
else { else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); status = decodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
// Decode CC // Decode CC
MI.addOperand(MCOperand::createImm(cc)); MI.addOperand(MCOperand::createImm(cc));
return MCDisassembler::Success; return MCDisassembler::Success;
} }

llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Linesstatic DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
assert(RegNo < Size && "Invalid register"); assert(RegNo < Size && "Invalid register");
RegNo = Regs[RegNo]; RegNo = Regs[RegNo];
if (RegNo == 0) if (RegNo == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(RegNo)); Inst.addOperand(MCOperand::createReg(RegNo));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
} }
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
} }
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
} }
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
} }
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
} }
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
} }
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
} }
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
} }
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32); return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
} }
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32); return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
} }
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32); return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
} }
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
} }
static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16); return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
} }
template<unsigned N> template<unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
if (!isUInt<N>(Imm)) if (!isUInt<N>(Imm))
▲ Show 20 Lines • Show All 310 Lines • Show Last 20 Lines

llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Linesstatic const unsigned MiscRegDecoderTable[] = {
VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR, VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
VE::PMC12, VE::PMC13, VE::PMC14}; VE::PMC12, VE::PMC13, VE::PMC14};
static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeI32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 63) if (RegNo > 63)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = I32RegDecoderTable[RegNo]; unsigned Reg = I32RegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeI64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 63) if (RegNo > 63)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = I64RegDecoderTable[RegNo]; unsigned Reg = I64RegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 63) if (RegNo > 63)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = F32RegDecoderTable[RegNo]; unsigned Reg = F32RegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeF128RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo % 2 || RegNo > 63) if (RegNo % 2 || RegNo > 63)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = F128RegDecoderTable[RegNo / 2]; unsigned Reg = F128RegDecoderTable[RegNo / 2];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeV64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Reg = VE::NoRegister; unsigned Reg = VE::NoRegister;
if (RegNo == 255) if (RegNo == 255)
Reg = VE::VIX; Reg = VE::VIX;
else if (RegNo > 63) else if (RegNo > 63)
return MCDisassembler::Fail; return MCDisassembler::Fail;
else else
Reg = V64RegDecoderTable[RegNo]; Reg = V64RegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeVMRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = VMRegDecoderTable[RegNo]; unsigned Reg = VMRegDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeVM512RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo % 2 || RegNo > 15) if (RegNo % 2 || RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = VM512RegDecoderTable[RegNo / 2]; unsigned Reg = VM512RegDecoderTable[RegNo / 2];
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus decodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
if (RegNo > 30) if (RegNo > 30)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = MiscRegDecoderTable[RegNo]; unsigned Reg = MiscRegDecoderTable[RegNo];
if (Reg == VE::NoRegister) if (Reg == VE::NoRegister)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,
bool cy = fieldFromInstruction(insn, 47, 1); bool cy = fieldFromInstruction(insn, 47, 1);
unsigned sz = fieldFromInstruction(insn, 32, 7); unsigned sz = fieldFromInstruction(insn, 32, 7);
bool cz = fieldFromInstruction(insn, 39, 1); bool cz = fieldFromInstruction(insn, 39, 1);
uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
DecodeStatus status; DecodeStatus status;
// Decode sz. // Decode sz.
if (cz) { if (cz) {
status = DecodeI64RegisterClass(MI, sz, Address, Decoder); status = decodeI64RegisterClass(MI, sz, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} else { } else {
MI.addOperand(MCOperand::createImm(0)); MI.addOperand(MCOperand::createImm(0));
} }
// Decode sy. // Decode sy.
if (cy) { if (cy) {
status = DecodeI64RegisterClass(MI, sy, Address, Decoder); status = decodeI64RegisterClass(MI, sy, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} else { } else {
MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
} }
// Decode simm32. // Decode simm32.
MI.addOperand(MCOperand::createImm(simm32)); MI.addOperand(MCOperand::createImm(simm32));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address, static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned sz = fieldFromInstruction(insn, 32, 7); unsigned sz = fieldFromInstruction(insn, 32, 7);
bool cz = fieldFromInstruction(insn, 39, 1); bool cz = fieldFromInstruction(insn, 39, 1);
uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32)); uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
DecodeStatus status; DecodeStatus status;
// Decode sz. // Decode sz.
if (cz) { if (cz) {
status = DecodeI64RegisterClass(MI, sz, Address, Decoder); status = decodeI64RegisterClass(MI, sz, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} else { } else {
MI.addOperand(MCOperand::createImm(0)); MI.addOperand(MCOperand::createImm(0));
} }
// Decode simm32. // Decode simm32.
MI.addOperand(MCOperand::createImm(simm32)); MI.addOperand(MCOperand::createImm(simm32));
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines if (!isLoad) {
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} }
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address, static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass); return DecodeMem(Inst, insn, Address, Decoder, true, decodeI32RegisterClass);
} }
static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn, static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass); return DecodeMem(Inst, insn, Address, Decoder, false, decodeI32RegisterClass);
} }
static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address, static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); return DecodeMem(Inst, insn, Address, Decoder, true, decodeI64RegisterClass);
} }
static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn, static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass); return DecodeMem(Inst, insn, Address, Decoder, false, decodeI64RegisterClass);
} }
static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address, static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass); return DecodeMem(Inst, insn, Address, Decoder, true, decodeF32RegisterClass);
} }
static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn, static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass); return DecodeMem(Inst, insn, Address, Decoder, false, decodeF32RegisterClass);
} }
static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn, static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMemAS(Inst, insn, Address, Decoder, true, return DecodeMemAS(Inst, insn, Address, Decoder, true,
DecodeI64RegisterClass); decodeI64RegisterClass);
} }
static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn, static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
return DecodeMemAS(Inst, insn, Address, Decoder, false, return DecodeMemAS(Inst, insn, Address, Decoder, false,
DecodeI64RegisterClass); decodeI64RegisterClass);
} }
static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address, static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder, bool isImmOnly, bool isUImm, const void *Decoder, bool isImmOnly, bool isUImm,
DecodeFunc DecodeSX) { DecodeFunc DecodeSX) {
unsigned sx = fieldFromInstruction(insn, 48, 7); unsigned sx = fieldFromInstruction(insn, 48, 7);
bool cy = fieldFromInstruction(insn, 47, 1); bool cy = fieldFromInstruction(insn, 47, 1);
unsigned sy = fieldFromInstruction(insn, 40, 7); unsigned sy = fieldFromInstruction(insn, 40, 7);
Show All 27 Lines if (status != MCDisassembler::Success)
return status; return status;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address, static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeCAS(MI, insn, Address, Decoder, false, true, return DecodeCAS(MI, insn, Address, Decoder, false, true,
DecodeI64RegisterClass); decodeI64RegisterClass);
} }
static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address, static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeCAS(MI, insn, Address, Decoder, false, true, return DecodeCAS(MI, insn, Address, Decoder, false, true,
DecodeI32RegisterClass); decodeI32RegisterClass);
} }
static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address, static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeCAS(MI, insn, Address, Decoder, false, false, return DecodeCAS(MI, insn, Address, Decoder, false, false,
DecodeI64RegisterClass); decodeI64RegisterClass);
} }
static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address, static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeCAS(MI, insn, Address, Decoder, false, false, return DecodeCAS(MI, insn, Address, Decoder, false, false,
DecodeI32RegisterClass); decodeI32RegisterClass);
} }
static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address, static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass); return DecodeMem(Inst, insn, Address, Decoder, true, decodeI64RegisterClass);
} }
static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address, static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
uint64_t tgt = SignExtend64<7>(insn); uint64_t tgt = SignExtend64<7>(insn);
MI.addOperand(MCOperand::createImm(tgt)); MI.addOperand(MCOperand::createImm(tgt));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn,
unsigned sy = fieldFromInstruction(insn, 40, 7); unsigned sy = fieldFromInstruction(insn, 40, 7);
// Decode cf. // Decode cf.
MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI)))); MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
// Decode sy. // Decode sy.
DecodeStatus status; DecodeStatus status;
if (cy) { if (cy) {
status = DecodeI64RegisterClass(MI, sy, Address, Decoder); status = decodeI64RegisterClass(MI, sy, Address, Decoder);
if (status != MCDisassembler::Success) if (status != MCDisassembler::Success)
return status; return status;
} else { } else {
MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy))); MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
} }
// Decode MEMri. // Decode MEMri.
return DecodeAS(MI, insn, Address, Decoder); return DecodeAS(MI, insn, Address, Decoder);
} }
static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn, static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
// Decode MEMri. // Decode MEMri.
return DecodeAS(MI, insn, Address, Decoder); return DecodeAS(MI, insn, Address, Decoder);
} }

llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// ///
/// \file /// \file
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
} }
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D); const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
return *(RegInfo->getRegClass(RC).begin() + RegNo); return *(RegInfo->getRegClass(RC).begin() + RegNo);
} }
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeGRRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeRRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
#include "XCoreGenDisassemblerTables.inc" #include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeGRRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) const void *Decoder)
{ {
if (RegNo > 11) if (RegNo > 11)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, static DecodeStatus decodeRRegsRegisterClass(MCInst &Inst,
unsigned RegNo, unsigned RegNo,
uint64_t Address, uint64_t Address,
const void *Decoder) const void *Decoder)
{ {
if (RegNo > 15) if (RegNo > 15)
return MCDisassembler::Fail; return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
static DecodeStatus static DecodeStatus
Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
Inst.addOperand(MCOperand::createImm(Op1)); Inst.addOperand(MCOperand::createImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
Inst.addOperand(MCOperand::createImm(Op2)); Inst.addOperand(MCOperand::createImm(Op2));
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder); DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder); DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
// Try and decode as a L3R / L2RUS instruction. // Try and decode as a L3R / L2RUS instruction.
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
Op1, Op2); Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2; unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
Op1, Op2); Op1, Op2);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
Inst.addOperand(MCOperand::createImm(Op1)); Inst.addOperand(MCOperand::createImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Inst.addOperand(MCOperand::createImm(Op3)); Inst.addOperand(MCOperand::createImm(Op3));
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeBitpOperand(Inst, Op3, Address, Decoder); DecodeBitpOperand(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Inst.addOperand(MCOperand::createImm(Op3)); Inst.addOperand(MCOperand::createImm(Op3));
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeBitpOperand(Inst, Op3, Address, Decoder); DecodeBitpOperand(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3, Op4, Op5, Op6; unsigned Op1, Op2, Op3, Op4, Op5, Op6;
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return S; return S;
S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return S; return S;
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
// Try and decode as a L6R instruction. // Try and decode as a L6R instruction.
Inst.clear(); Inst.clear();
Show All 13 LinesDecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
if (S != MCDisassembler::Success) if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction(Insn, 16, 4); unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); S = decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
} }
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
static DecodeStatus static DecodeStatus
DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) { const void *Decoder) {
unsigned Op1, Op2, Op3; unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction(Insn, 16, 4); unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
DecodeStatus S = DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); S = decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
} }
if (S == MCDisassembler::Success) { if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); decodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
} }
return S; return S;
} }
MCDisassembler::DecodeStatus MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address, ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &cStream) const { raw_ostream &cStream) const {
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/utils/TableGen/FixedLenDecoderEmitter.cpp

//===------------ FixedLenDecoderEmitter.cpp - Decoder Generator ----------===// //===------------ FixedLenDecoderEmitter.cpp - Decoder Generator ----------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// It contains the tablegen backend that emits the decoder functions for // It contains the tablegen backend that emits the decoder functions for
▲ Show 20 Lines • Show All 1,788 Lines • ▼ Show 20 Lines if (String) {
if (!Decoder.empty()) if (!Decoder.empty())
return Decoder; return Decoder;
} }
if (Record->isSubClassOf("RegisterOperand")) if (Record->isSubClassOf("RegisterOperand"))
Record = Record->getValueAsDef("RegClass"); Record = Record->getValueAsDef("RegClass");
if (Record->isSubClassOf("RegisterClass")) { if (Record->isSubClassOf("RegisterClass")) {
Decoder = "Decode" + Record->getName().str() + "RegisterClass"; Decoder = "decode" + Record->getName().str() + "RegisterClass";
} else if (Record->isSubClassOf("PointerLikeRegClass")) { } else if (Record->isSubClassOf("PointerLikeRegClass")) {
Decoder = "DecodePointerLikeRegClass" + Decoder = "decodePointerLikeRegClass" +
utostr(Record->getValueAsInt("RegClassKind")); utostr(Record->getValueAsInt("RegClassKind"));
} }
return Decoder; return Decoder;
} }
static bool static bool
populateInstruction(CodeGenTarget &Target, const Record &EncodingDef, populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
if (DefInit *DI = cast<DefInit>(Arg)) if (DefInit *DI = cast<DefInit>(Arg))
TypeRecord = DI->getDef(); TypeRecord = DI->getDef();
} }
bool isReg = false; bool isReg = false;
if (TypeRecord->isSubClassOf("RegisterOperand")) if (TypeRecord->isSubClassOf("RegisterOperand"))
TypeRecord = TypeRecord->getValueAsDef("RegClass"); TypeRecord = TypeRecord->getValueAsDef("RegClass");
if (TypeRecord->isSubClassOf("RegisterClass")) { if (TypeRecord->isSubClassOf("RegisterClass")) {
Decoder = "Decode" + TypeRecord->getName().str() + "RegisterClass"; Decoder = "decode" + TypeRecord->getName().str() + "RegisterClass";
isReg = true; isReg = true;
} else if (TypeRecord->isSubClassOf("PointerLikeRegClass")) { } else if (TypeRecord->isSubClassOf("PointerLikeRegClass")) {
Decoder = "DecodePointerLikeRegClass" + Decoder = "decodePointerLikeRegClass" +
utostr(TypeRecord->getValueAsInt("RegClassKind")); utostr(TypeRecord->getValueAsInt("RegClassKind"));
isReg = true; isReg = true;
} }
DecoderString = TypeRecord->getValue("DecoderMethod"); DecoderString = TypeRecord->getValue("DecoderMethod");
String = DecoderString ? String = DecoderString ?
dyn_cast<StringInit>(DecoderString->getValue()) : nullptr; dyn_cast<StringInit>(DecoderString->getValue()) : nullptr;
if (!isReg && String && String->getValue() != "") if (!isReg && String && String->getValue() != "")
▲ Show 20 Lines • Show All 570 Lines • Show Last 20 Lines