[PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[kamaub]

Summary

The builtin __rlwnm is currently constrained to accept only constants
for the shift parameter but the instructions emitted for it have no such
constraint, this patch allows the builtins to accept variable shift.

[NeHuang]

clang/test/CodeGen/builtins-ppc-xlcompat-error.c

44–45

Please also remove __builtin_ppc_rlwnm(ui, shift, 7); in this test. We only keep cases trigger sema check errors.

[kamaub]

Addressing review request to remove unnecessary testing line.

[NeHuang]

Please check and add a test in clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c with shift as a variable.

[kamaub]

Adding shift variable test case to builtins-ppc-xlcompat-rotate.c as per
review comment request.

[NeHuang]

Thanks. LGTM. One minor can be addressed when commit it.

clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

71

please remove shift = 31, in the comment

[amyk]

Aside from the comment made by Victor, also LGTM.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
 BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")
 BUILTIN(__builtin_ppc_mulhw, "iii", "")
 BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
 BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load
 BUILTIN(__builtin_ppc_load2r, "UsUs*", "")
 BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
 BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
 // store
 BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")

clang/lib/Sema/SemaChecking.cpp

return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
                             diag::err_ppc_builtin_only_on_arch, "9");
   case PPC::BI__builtin_ppc_cmprb:
     return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
                             diag::err_ppc_builtin_only_on_arch, "9") ||
            SemaBuiltinConstantArgRange(TheCall, 0, 0, 1);
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-    return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-           SemaValueIsRunOfOnes(TheCall, 2);
+    return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
     return SemaBuiltinConstantArg(TheCall, 2, Result) ||
            SemaValueIsRunOfOnes(TheCall, 3);
   case PPC::BI__builtin_ppc_extract_exp:
   case PPC::BI__builtin_ppc_extract_sig:
   case PPC::BI__builtin_ppc_insert_exp:
     return SemaFeatureCheck(*this, TheCall, "power9-vector",

clang/test/CodeGen/builtins-ppc-xlcompat-error.c

void test_builtin_ppc_rlwimi() {
   unsigned int shift;
   unsigned int mask;
   unsigned int res = __builtin_ppc_rlwimi(ui, ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
   res = __builtin_ppc_rlwimi(ui, ui, 31, mask);              // expected-error {{argument to '__builtin_ppc_rlwimi' must be a constant integer}}
   res = __builtin_ppc_rlwimi(ui, ui, 31, 0xFFFF0F00);        // expected-error {{argument 3 value should represent a contiguous bit field}}
 }
 
 void test_builtin_ppc_rlwnm() {
-  unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
-  res = __builtin_ppc_rlwnm(ui, 31, mask);              // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, mask);              // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);        // expected-error {{argument 2 value should represent a contiguous bit field}}
 }
 
 extern unsigned int usi;
 extern double d;
 extern float f;
 
 void testMathBuiltin(void) {

clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

void test_builtin_ppc_rlwnm() {
   // CHECK-NEXT:  [[RC:%[0-9]+]] = and i32 [[RB]], 511
   // CHECK-NEXT:  store i32 [[RC]], i32* %res, align 4
   // CHECK-NEXT:  ret void
 
   /*shift = 31, mask = 0x1FF = 511*/
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
 
+void test_builtin_ppc_rlwnm2(unsigned int shift) {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm2
+  // CHECK:       %shift.addr = alloca i32, align 4
+  // CHECK-NEXT:  %res = alloca i32, align 4
+  // CHECK-NEXT:  store i32 %shift, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 [[RB]])
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 511
+  // CHECK-NEXT:  store i32 [[RD]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
+}
+
 // CHECK-LABEL: @testrotatel4(
 // CHECK:         [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.*}}, i32 {{%.*}})
 // CHECK-NEXT:    ret i32 [[TMP]]
 //
 unsigned int testrotatel4(unsigned int rs, unsigned int shift) {
   return __rotatel4(rs, shift);
 }