Implemented functions in the SelectionDAG legalizer for integer type promotion, vector widening, and vector splitting for vp_load and vp_store nodes.
Yes you should be able to test this with RISCV. Anything that's not i1/i8/i16/i32 but is less than i64 will need promoting. Also see D108288 for examples.
I don't think we expect EVL to need promoting - do we? It should always be a legal target-specific type, reported by TLI.getVPExplicitVectorLengthTy(). I don't know how well we're asserting on that right now.
GetPromotedInteger -> ZExtPromotedInteger. We need to force the upper bits to 0.
5 -> 6 if I've counted the number of operands correctly.
Should we assert that the store isn't indexed since this call would be incorrect if it was?
GetPromotedInteger -> ZExtPromotedInteger.
Added more legalization to this patch rather than putting it into another patch. Added another form of getLoadVP that was needed by the legalization. Expanded tests to cover vector splitting.
Why does this use isIndexed() but load uses N->getAddressingMode() == ISD::UNINDEXED. Are the interfaces for checking indexed different for loads and stores?
Why should this be different than the assert in getLoad?
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We shouldn't put RISC-V tests in Generic unless we know the target is built. So either this needs to use REQUIRES: or we put it in CodeGen/RISCV. I prefer the latter as that's where I've seen all other target-specific legalization tests go.