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Differential D109322

[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.
ClosedPublic

Authored by HsiangKai on Sep 6 2021, 6:44 AM.

Details

Reviewers
craig.topper
frasercrmck
rogfer01
kito-cheng
khchen
arcbbb
evandro
Commits
rG7afa61e71877: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.
Summary

Add the tail policy argument to Clang builtins. There
are two policies for tail elements. Tail agnostic means users do not
care about the values in the tail elements and tail undisturbed means
the values in the tail elements need to be kept after the operation. In
order to let users control the tail policy, we add an additional
argument at the end of the argument list.

For unmasked operations, we have no maskedoff and the tail policy is
always tail agnostic. If users want to keep tail elements under unmasked
operations, they could use all one mask in the masked operations to do
it. So, we only add the additional argument for masked operations for
most cases. There are exceptions listed below.

In this patch, we do not handle the following cases to reduce the
complexity of the patch. There could be two separate patches for them.

Use dest argument to control tail policy
vmerge.vvm/vmerge.vxm/vmerge.vim (add _t builtins with additional dest
argument)
vfmerge.vfm (add _t builtins with additional dest argument)
vmv.v.v (add _t builtins with additional dest argument)
vmv.v.x (add _t builtins with additional dest argument)
vmv.v.i (add _t builtins with additional dest argument)
vfmv.v.f (add _t builtins with additional dest argument)
vadc.vvm/vadc.vxm/vadc.vim (add _t builtins with additional dest
argument)
vsbc.vvm/vsbc.vxm (add _t builtins with additional dest argument)

Always has tail argument for masked/unmasked intrinsics
Vector Single-Width Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Widening Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Single-Width Floating-Point Fused Multiply-Add Instructions (add
_t and _mt builtins)
Vector Widening Floating-Point Fused Multiply-Add Instructions (add _t
and _mt builtins)
Vector Reduction Operations (add _t and _mt builtins)
Vector Slideup Instructions (add _t and _mt builtins)
Vector Slidedown Instructions (add _t and _mt builtins)

Discussion: https://github.com/riscv/rvv-intrinsic-doc/pull/101

Diff Detail

Event Timeline

HsiangKai created this revision.Sep 6 2021, 6:44 AM
Herald added subscribers: StephenFan, vkmr, luismarques and 21 others. · View Herald TranscriptSep 6 2021, 6:44 AM
HsiangKai requested review of this revision.Sep 6 2021, 6:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 6 2021, 6:44 AM
Herald added subscribers: cfe-commits, MaskRay. · View Herald Transcript
HsiangKai mentioned this in D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics..Sep 6 2021, 6:45 AM
HsiangKai added a parent revision: D105092: [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics..
Harbormaster completed remote builds in B122760: Diff 370909.Sep 6 2021, 7:25 AM
HsiangKai added a comment.Sep 6 2021, 6:48 PM

I didn't attach all the test update in this patch. It is too huge to collect them in one patch.

I ever ran check-clang and all tests pass after I updated all the clang test cases.

khchen added inline comments.Sep 23 2021, 12:57 AM
clang/include/clang/Basic/riscv_vector.td
181

Add more comment like:
If HasPolicy, masked operation have tail policy argument in the last position, and append t in function name.
and update the HasVL comment too.

personally, I prefer the naming like HasTailPolicy, HasTail or HasTailOperand.

2198

It seems like we can rewrite vsetvli/vsetvl and vsetvlmax instructions by using the RVVHeader mechanism?
We only need to have one mechanism to dump header code.

clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
14

Nit: we don't need to add a space here.

clang/utils/TableGen/RISCVVEmitter.cpp
1180

Nit: update this comment

Herald added a subscriber: achieveartificialintelligence. · View Herald TranscriptSep 23 2021, 12:57 AM
HsiangKai added inline comments.Sep 23 2021, 2:01 AM
clang/include/clang/Basic/riscv_vector.td
2198

Should we create vsetvli/vsetvlmax builtins? If we should, we may not be able to use RVVHeader for these intrinsics.

HsiangKai updated this revision to Diff 374482.Sep 23 2021, 2:06 AM

Update comments.

Harbormaster completed remote builds in B125299: Diff 374482.Sep 23 2021, 2:07 AM
khchen accepted this revision.Sep 23 2021, 3:01 AM

LGTM.

clang/include/clang/Basic/riscv_vector.td
2198

oh, you are right. I forget that.
Could you please move class definition in top of this file due to all class centralized there.

This revision is now accepted and ready to land.Sep 23 2021, 3:01 AM
craig.topper added inline comments.Sep 23 2021, 5:41 PM
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
8

Please pre-commit this change to reduce noise

This revision was landed with ongoing or failed builds.Sep 24 2021, 2:11 AM
Closed by commit rG7afa61e71877: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics. (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rG7afa61e71877: [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics..
HsiangKai added a reverting change: rG7ccd31c900ed: Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.".Oct 13 2021, 4:43 AM

Large Diff

This large diff affects 163 files. Files without inline comments have been collapsed. Expand All Files

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Diff 374765

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Linesclass RVVBuiltin<string suffix, string prototype, string type_range,
// This builtin has a masked form. // This builtin has a masked form.
bit HasMask = true; bit HasMask = true;
// If HasMask, this flag states that this builtin has a maskedoff operand. It // If HasMask, this flag states that this builtin has a maskedoff operand. It
// is always the first operand in builtin and IR intrinsic. // is always the first operand in builtin and IR intrinsic.
bit HasMaskedOffOperand = true; bit HasMaskedOffOperand = true;
// This builtin has a granted vector length parameter in the last position. // This builtin has a granted vector length parameter.
bit HasVL = true; bit HasVL = true;
// There are several cases for specifying tail policy.
// 1. Add tail policy argument to masked intrinsics. It may have the maskedoff
// argument or not.
// * Have the maskedoff argument: (HasPolicy = true, HasMaskedOffOperand = true)
// Ex: vadd_vv_i8m1_mt(mask, maskedoff, op1, op2, vl, ta);
// * Do not have the maskedoff argument: (HasPolicy = true, HasMaskedOffOperand = false)
khchenUnsubmitted
Not Done
ReplyInline Actions

Add more comment like:
If HasPolicy, masked operation have tail policy argument in the last position, and append t in function name.
and update the HasVL comment too.

personally, I prefer the naming like HasTailPolicy, HasTail or HasTailOperand.

khchen: Add more comment like: If `HasPolicy`, masked operation have tail policy argument in the last…
// Ex: vmacc_vv_i8m1_mt(mask, vd, vs1, vs2, vl, ta);
// 2. Add dest argument for no mask intrinsics. (TODO)
// Ex: vmv_v_x_i8m1_t(dest, src, vl);
// 3. Always tail agnostic. (HasPolicy = false)
// Ex: vmseq_vv_i8m1_b8_m(mask, maskedoff, op1, op2, vl);
// The tail policy argument is located at the last position.
bit HasPolicy = true;
// This builtin supports non-masked function overloading api. // This builtin supports non-masked function overloading api.
// All masked operations support overloading api. // All masked operations support overloading api.
bit HasNoMaskedOverloaded = true; bit HasNoMaskedOverloaded = true;
// Reads or writes "memory" or has other side-effects. // Reads or writes "memory" or has other side-effects.
bit HasSideEffects = false; bit HasSideEffects = false;
// This builtin is valid for the given Log2LMULs. // This builtin is valid for the given Log2LMULs.
Show All 22 Linesclass RVVBuiltin<string suffix, string prototype, string type_range,
// Sub extension of vector spec. Currently only support Zvamo or Zvlsseg. // Sub extension of vector spec. Currently only support Zvamo or Zvlsseg.
string RequiredExtension = ""; string RequiredExtension = "";
// Number of fields for Zvlsseg. // Number of fields for Zvlsseg.
int NF = 1; int NF = 1;
} }
class RVVHeader
{
code HeaderCode;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Basic classes with automatic codegen. // Basic classes with automatic codegen.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class RVVOutBuiltin<string suffix, string prototype, string type_range> class RVVOutBuiltin<string suffix, string prototype, string type_range>
: RVVBuiltin<suffix, prototype, type_range> { : RVVBuiltin<suffix, prototype, type_range> {
let IntrinsicTypes = [-1]; let IntrinsicTypes = [-1];
} }
▲ Show 20 Lines • Show All 330 Lines • ▼ Show 20 Linesdefvar EEWList = [["8", "(Log2EEW:3)"],
["32", "(Log2EEW:5)"], ["32", "(Log2EEW:5)"],
["64", "(Log2EEW:6)"]]; ["64", "(Log2EEW:6)"]];
class IsFloat<string type> { class IsFloat<string type> {
bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d")); bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d"));
} }
let HasNoMaskedOverloaded = false, let HasNoMaskedOverloaded = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
// Move mask to right before vl. // Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
IntrinsicTypes = {ResultType, Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[3]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in { }] in {
class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> { class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
let Name = "vle1_v"; let Name = "vle1_v";
let IRName = "vle1"; let IRName = "vle1";
let HasMask = false; let HasMask = false;
} }
}
let HasNoMaskedOverloaded = false,
ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}],
ManualCodegenMask= [{
// Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
IntrinsicTypes = {ResultType, Ops[3]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in {
multiclass RVVVLEBuiltin<list<string> types> { multiclass RVVVLEBuiltin<list<string> types> {
let Name = NAME # "_v", let Name = NAME # "_v",
IRName = "vle", IRName = "vle",
IRNameMask ="vle_mask" in { IRNameMask ="vle_mask" in {
foreach type = types in { foreach type = types in {
def : RVVBuiltin<"v", "vPCe", type>; def : RVVBuiltin<"v", "vPCe", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "UvPCUe", type>; def : RVVBuiltin<"Uv", "UvPCUe", type>;
Show All 23 Lines let Name = NAME # "_v",
Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {1}), Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {1}),
Address(NewVL, Align)); Address(NewVL, Align));
return V; return V;
} }
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
{ {
// Move mask to right before vl. // Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
IntrinsicTypes = {ResultType, Ops[4]->getType()}; IntrinsicTypes = {ResultType, Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
Value *NewVL = Ops[2]; Value *NewVL = Ops[2];
Ops.erase(Ops.begin() + 2); Ops.erase(Ops.begin() + 2);
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Ops, ""); llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0}); llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
// Store new_vl. // Store new_vl.
Show All 20 Lines let Name = NAME # "_v",
IRNameMask ="vlse_mask", IRNameMask ="vlse_mask",
HasNoMaskedOverloaded = false, HasNoMaskedOverloaded = false,
ManualCodegen = [{ ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[2]->getType()}; IntrinsicTypes = {ResultType, Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
// Move mask to right before vl. // Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
IntrinsicTypes = {ResultType, Ops[4]->getType()}; IntrinsicTypes = {ResultType, Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in { }] in {
foreach type = types in { foreach type = types in {
def : RVVBuiltin<"v", "vPCet", type>; def : RVVBuiltin<"v", "vPCet", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "UvPCUet", type>; def : RVVBuiltin<"Uv", "UvPCUet", type>;
} }
} }
} }
} }
multiclass RVVIndexedLoad<string op> { multiclass RVVIndexedLoad<string op> {
let ManualCodegen = [{ let ManualCodegen = [{
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
// Move mask to right before vl. // Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops[4]->getType()}; IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in { }] in {
foreach type = TypeList in { foreach type = TypeList in {
foreach eew_list = EEWList in { foreach eew_list = EEWList in {
defvar eew = eew_list[0]; defvar eew = eew_list[0];
defvar eew_type = eew_list[1]; defvar eew_type = eew_list[1];
let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in { let Name = op # eew # "_v", IRName = op, IRNameMask = op # "_mask" in {
def: RVVBuiltin<"v", "vPCe" # eew_type # "Uv", type>; def: RVVBuiltin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def: RVVBuiltin<"Uv", "UvPCUe" # eew_type # "Uv", type>; def: RVVBuiltin<"Uv", "UvPCUe" # eew_type # "Uv", type>;
} }
} }
} }
} }
} }
} }
let HasMaskedOffOperand = false, let HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
// Builtin: (ptr, value, vl). Intrinsic: (value, ptr, vl) // Builtin: (ptr, value, vl). Intrinsic: (value, ptr, vl)
std::swap(Ops[0], Ops[1]); std::swap(Ops[0], Ops[1]);
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType()};
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
// Builtin: (mask, ptr, value, vl). Intrinsic: (value, ptr, mask, vl) // Builtin: (mask, ptr, value, vl). Intrinsic: (value, ptr, mask, vl)
std::swap(Ops[0], Ops[2]); std::swap(Ops[0], Ops[2]);
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
}] in { }] in {
class RVVVSEMaskBuiltin : RVVBuiltin<"m", "0PUem", "c"> { class RVVVSEMaskBuiltin : RVVBuiltin<"m", "0PUem", "c"> {
let Name = "vse1_v"; let Name = "vse1_v";
let IRName = "vse1"; let IRName = "vse1";
let HasMask = false; let HasMask = false;
} }
}
let HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{
// Builtin: (ptr, value, vl). Intrinsic: (value, ptr, vl)
std::swap(Ops[0], Ops[1]);
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType()};
}],
ManualCodegenMask= [{
// Builtin: (mask, ptr, value, vl). Intrinsic: (value, ptr, mask, vl)
std::swap(Ops[0], Ops[2]);
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
}] in {
multiclass RVVVSEBuiltin<list<string> types> { multiclass RVVVSEBuiltin<list<string> types> {
let Name = NAME # "_v", let Name = NAME # "_v",
IRName = "vse", IRName = "vse",
IRNameMask = "vse_mask" in { IRNameMask = "vse_mask" in {
foreach type = types in { foreach type = types in {
def : RVVBuiltin<"v", "0Pev", type>; def : RVVBuiltin<"v", "0Pev", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUeUv", type>; def : RVVBuiltin<"Uv", "0PUeUv", type>;
} }
} }
} }
} }
} }
multiclass RVVVSSEBuiltin<list<string> types> { multiclass RVVVSSEBuiltin<list<string> types> {
let Name = NAME # "_v", let Name = NAME # "_v",
IRName = "vsse", IRName = "vsse",
IRNameMask = "vsse_mask", IRNameMask = "vsse_mask",
HasMaskedOffOperand = false, HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
// Builtin: (ptr, stride, value, vl). Intrinsic: (value, ptr, stride, vl) // Builtin: (ptr, stride, value, vl). Intrinsic: (value, ptr, stride, vl)
std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3); std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
// Builtin: (mask, ptr, stride, value, vl). Intrinsic: (value, ptr, stride, mask, vl) // Builtin: (mask, ptr, stride, value, vl). Intrinsic: (value, ptr, stride, mask, vl)
std::swap(Ops[0], Ops[3]); std::swap(Ops[0], Ops[3]);
Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[4]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[4]->getType()};
}] in { }] in {
foreach type = types in { foreach type = types in {
def : RVVBuiltin<"v", "0Petv", type>; def : RVVBuiltin<"v", "0Petv", type>;
if !not(IsFloat<type>.val) then { if !not(IsFloat<type>.val) then {
def : RVVBuiltin<"Uv", "0PUetUv", type>; def : RVVBuiltin<"Uv", "0PUetUv", type>;
} }
} }
} }
} }
multiclass RVVIndexedStore<string op> { multiclass RVVIndexedStore<string op> {
let HasMaskedOffOperand = false, let HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
// Builtin: (ptr, index, value, vl). Intrinsic: (value, ptr, index, vl) // Builtin: (ptr, index, value, vl). Intrinsic: (value, ptr, index, vl)
std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3); std::rotate(Ops.begin(), Ops.begin() + 2, Ops.begin() + 3);
Ops[1] = Builder.CreateBitCast(Ops[1],Ops[0]->getType()->getPointerTo()); Ops[1] = Builder.CreateBitCast(Ops[1],Ops[0]->getType()->getPointerTo());
IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[3]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType(), Ops[3]->getType()};
}], }],
ManualCodegenMask= [{ ManualCodegenMask= [{
// Builtin: (mask, ptr, index, value, vl). Intrinsic: (value, ptr, index, mask, vl) // Builtin: (mask, ptr, index, value, vl). Intrinsic: (value, ptr, index, mask, vl)
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines defvar eew = !cond(!eq(type, "c") : "8",
IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()), IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()),
Ops[2 * NF + 2]->getType()}; Ops[2 * NF + 2]->getType()};
SmallVector<llvm::Value*, 12> Operands; SmallVector<llvm::Value*, 12> Operands;
for (unsigned I = 0; I < NF; ++I) for (unsigned I = 0; I < NF; ++I)
Operands.push_back(Ops[NF + I + 1]); Operands.push_back(Ops[NF + I + 1]);
Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 1]);
Operands.push_back(Ops[NF]); Operands.push_back(Ops[NF]);
Operands.push_back(Ops[2 * NF + 2]); Operands.push_back(Ops[2 * NF + 2]);
assert(Operands.size() == NF + 3); Operands.push_back(Ops[2 * NF + 3]);
assert(Operands.size() == NF + 4);
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align = clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType()); CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
llvm::Value *V; llvm::Value *V;
for (unsigned I = 0; I < NF; ++I) { for (unsigned I = 0; I < NF; ++I) {
V = Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}), V = Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}),
Address(Ops[I], Align)); Address(Ops[I], Align));
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines defvar eew = !cond(!eq(type, "c") : "8",
IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()), IntrinsicTypes = {ConvertType(E->getArg(0)->getType()->getPointeeType()),
Ops[2 * NF + 3]->getType()}; Ops[2 * NF + 3]->getType()};
SmallVector<llvm::Value*, 12> Operands; SmallVector<llvm::Value*, 12> Operands;
for (unsigned I = 0; I < NF; ++I) for (unsigned I = 0; I < NF; ++I)
Operands.push_back(Ops[NF + I + 1]); Operands.push_back(Ops[NF + I + 1]);
Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 1]);
Operands.push_back(Ops[NF]); Operands.push_back(Ops[NF]);
Operands.push_back(Ops[2 * NF + 3]); Operands.push_back(Ops[2 * NF + 3]);
Operands.push_back(Ops[2 * NF + 4]);
Value *NewVL = Ops[2 * NF + 2]; Value *NewVL = Ops[2 * NF + 2];
assert(Operands.size() == NF + 3); assert(Operands.size() == NF + 4);
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align = clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType()); CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
for (unsigned I = 0; I < NF; ++I) { for (unsigned I = 0; I < NF; ++I) {
Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}), Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}),
Address(Ops[I], Align)); Address(Ops[I], Align));
} }
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines defvar eew = !cond(!eq(type, "c") : "8",
Ops[2 * NF + 3]->getType()}; Ops[2 * NF + 3]->getType()};
SmallVector<llvm::Value*, 12> Operands; SmallVector<llvm::Value*, 12> Operands;
for (unsigned I = 0; I < NF; ++I) for (unsigned I = 0; I < NF; ++I)
Operands.push_back(Ops[NF + I + 1]); Operands.push_back(Ops[NF + I + 1]);
Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 1]);
Operands.push_back(Ops[2 * NF + 2]); Operands.push_back(Ops[2 * NF + 2]);
Operands.push_back(Ops[NF]); Operands.push_back(Ops[NF]);
Operands.push_back(Ops[2 * NF + 3]); Operands.push_back(Ops[2 * NF + 3]);
assert(Operands.size() == NF + 4); Operands.push_back(Ops[2 * NF + 4]);
assert(Operands.size() == NF + 5);
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align = clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType()); CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
llvm::Value *V; llvm::Value *V;
for (unsigned I = 0; I < NF; ++I) { for (unsigned I = 0; I < NF; ++I) {
V = Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}), V = Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}),
Address(Ops[I], Align)); Address(Ops[I], Align));
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines foreach eew_info = EEWList in {
// intrinsic: (maskedoff0, ..., ptr, index, mask, vl) // intrinsic: (maskedoff0, ..., ptr, index, mask, vl)
SmallVector<llvm::Value*, 12> Operands; SmallVector<llvm::Value*, 12> Operands;
for (unsigned I = 0; I < NF; ++I) for (unsigned I = 0; I < NF; ++I)
Operands.push_back(Ops[NF + I + 1]); Operands.push_back(Ops[NF + I + 1]);
Operands.push_back(Ops[2 * NF + 1]); Operands.push_back(Ops[2 * NF + 1]);
Operands.push_back(Ops[2 * NF + 2]); Operands.push_back(Ops[2 * NF + 2]);
Operands.push_back(Ops[NF]); Operands.push_back(Ops[NF]);
Operands.push_back(Ops[2 * NF + 3]); Operands.push_back(Ops[2 * NF + 3]);
assert(Operands.size() == NF + 4); Operands.push_back(Ops[2 * NF + 4]);
assert(Operands.size() == NF + 5);
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes); llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Operands, ""); llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
clang::CharUnits Align = clang::CharUnits Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType()); CGM.getNaturalPointeeTypeAlignment(E->getArg(0)->getType());
llvm::Value *V; llvm::Value *V;
for (unsigned I = 0; I < NF; ++I) { for (unsigned I = 0; I < NF; ++I) {
V = Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}), V = Builder.CreateStore(Builder.CreateExtractValue(LoadValue, {I}),
Address(Ops[I], Align)); Address(Ops[I], Align));
Show All 33 Lines defvar eew = !cond(!eq(type, "c") : "8",
!eq(type, "f") : "32", !eq(type, "f") : "32",
!eq(type, "d") : "64"); !eq(type, "d") : "64");
foreach nf = NFList in { foreach nf = NFList in {
let Name = op # nf # "e" # eew # "_v", let Name = op # nf # "e" # eew # "_v",
IRName = op # nf, IRName = op # nf,
IRNameMask = op # nf # "_mask", IRNameMask = op # nf # "_mask",
NF = nf, NF = nf,
HasMaskedOffOperand = false, HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
{ {
// Builtin: (ptr, val0, val1, ..., vl) // Builtin: (ptr, val0, val1, ..., vl)
// Intrinsic: (val0, val1, ..., ptr, vl) // Intrinsic: (val0, val1, ..., ptr, vl)
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()};
assert(Ops.size() == NF + 2); assert(Ops.size() == NF + 2);
} }
Show All 29 Lines defvar eew = !cond(!eq(type, "c") : "8",
!eq(type, "f") : "32", !eq(type, "f") : "32",
!eq(type, "d") : "64"); !eq(type, "d") : "64");
foreach nf = NFList in { foreach nf = NFList in {
let Name = op # nf # "e" # eew # "_v", let Name = op # nf # "e" # eew # "_v",
IRName = op # nf, IRName = op # nf,
IRNameMask = op # nf # "_mask", IRNameMask = op # nf # "_mask",
NF = nf, NF = nf,
HasMaskedOffOperand = false, HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
{ {
// Builtin: (ptr, stride, val0, val1, ..., vl). // Builtin: (ptr, stride, val0, val1, ..., vl).
// Intrinsic: (val0, val1, ..., ptr, stride, vl) // Intrinsic: (val0, val1, ..., ptr, stride, vl)
std::rotate(Ops.begin(), Ops.begin() + 2, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 2, Ops.end() - 1);
IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()}; IntrinsicTypes = {Ops[0]->getType(), Ops[NF + 1]->getType()};
assert(Ops.size() == NF + 3); assert(Ops.size() == NF + 3);
} }
Show All 25 Lines foreach eew_info = EEWList in {
defvar eew = eew_info[0]; defvar eew = eew_info[0];
defvar eew_type = eew_info[1]; defvar eew_type = eew_info[1];
foreach nf = NFList in { foreach nf = NFList in {
let Name = op # nf # "ei" # eew # "_v", let Name = op # nf # "ei" # eew # "_v",
IRName = op # nf, IRName = op # nf,
IRNameMask = op # nf # "_mask", IRNameMask = op # nf # "_mask",
NF = nf, NF = nf,
HasMaskedOffOperand = false, HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
{ {
// Builtin: (ptr, index, val0, val1, ..., vl) // Builtin: (ptr, index, val0, val1, ..., vl)
// Intrinsic: (val0, val1, ..., ptr, index, vl) // Intrinsic: (val0, val1, ..., ptr, index, vl)
std::rotate(Ops.begin(), Ops.begin() + 2, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 2, Ops.end() - 1);
IntrinsicTypes = {Ops[0]->getType(), IntrinsicTypes = {Ops[0]->getType(),
Ops[NF + 1]->getType(), Ops[NF + 2]->getType()}; Ops[NF + 1]->getType(), Ops[NF + 2]->getType()};
assert(Ops.size() == NF + 3); assert(Ops.size() == NF + 3);
Show All 28 Linesmulticlass RVVAMOBuiltinSet<bit has_signed = false, bit has_unsigned = false,
foreach type = type_list in foreach type = type_list in
foreach eew_list = EEWList in { foreach eew_list = EEWList in {
defvar eew = eew_list[0]; defvar eew = eew_list[0];
defvar eew_index = eew_list[1]; defvar eew_index = eew_list[1];
let Name = NAME # "ei" # eew # "_" # "v", let Name = NAME # "ei" # eew # "_" # "v",
IRName = NAME, IRName = NAME,
IRNameMask = NAME # "_mask", IRNameMask = NAME # "_mask",
HasMaskedOffOperand = false, HasMaskedOffOperand = false,
HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
// base, bindex, value, vl // base, bindex, value, vl
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()};
Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo()); Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[4]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[4]->getType()};
Show All 18 Lines let Name = NAME,
cast<llvm::VectorType>(ResultType)->getElementType(), cast<llvm::VectorType>(ResultType)->getElementType(),
Ops[1]->getType()}; Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[1])); Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[1]));
break; break;
} }
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
{ {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
// maskedoff, op1, mask, vl // maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType, IntrinsicTypes = {ResultType,
cast<llvm::VectorType>(ResultType)->getElementType(), cast<llvm::VectorType>(ResultType)->getElementType(),
Ops[3]->getType()}; Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[1])); Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[1]));
break; break;
} }
}] in { }] in {
Show All 13 Lines let Name = NAME,
Ops[1]->getType()}; Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, Ops.insert(Ops.begin() + 1,
llvm::Constant::getAllOnesValue(IntrinsicTypes[1])); llvm::Constant::getAllOnesValue(IntrinsicTypes[1]));
break; break;
} }
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
{ {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
// maskedoff, op1, mask, vl // maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType, IntrinsicTypes = {ResultType,
cast<llvm::VectorType>(ResultType)->getElementType(), cast<llvm::VectorType>(ResultType)->getElementType(),
Ops[3]->getType()}; Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, Ops.insert(Ops.begin() + 2,
llvm::Constant::getAllOnesValue(IntrinsicTypes[1])); llvm::Constant::getAllOnesValue(IntrinsicTypes[1]));
break; break;
} }
Show All 30 Lines let Name = NAME,
IntrinsicTypes = {ResultType, IntrinsicTypes = {ResultType,
Ops[0]->getType(), Ops[1]->getType()}; Ops[0]->getType(), Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, Ops[0]); Ops.insert(Ops.begin() + 1, Ops[0]);
break; break;
} }
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
{ {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
// maskedoff, op1, mask, vl // maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType, IntrinsicTypes = {ResultType,
Ops[1]->getType(), Ops[1]->getType(),
Ops[3]->getType()}; Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, Ops[1]); Ops.insert(Ops.begin() + 2, Ops[1]);
break; break;
} }
}] in { }] in {
Show All 15 Lines let Name = NAME,
cast<llvm::VectorType>(Ops[0]->getType())->getElementType(), cast<llvm::VectorType>(Ops[0]->getType())->getElementType(),
Ops[1]->getType()}; Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[2])); Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[2]));
break; break;
} }
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
{ {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
// maskedoff, op1, mask, vl // maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType, IntrinsicTypes = {ResultType,
Ops[1]->getType(), Ops[1]->getType(),
cast<llvm::VectorType>(Ops[1]->getType())->getElementType(), cast<llvm::VectorType>(Ops[1]->getType())->getElementType(),
Ops[3]->getType()}; Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[2])); Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[2]));
break; break;
} }
Show All 18 Lines let Name = NAME,
Ops[1]->getType(), Ops[1]->getType(),
Ops[1]->getType()}; Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[2])); Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[2]));
break; break;
} }
}], }],
ManualCodegenMask = [{ ManualCodegenMask = [{
{ {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);
// maskedoff, op1, mask, vl // maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType, IntrinsicTypes = {ResultType,
Ops[1]->getType(), Ops[1]->getType(),
Ops[3]->getType(), Ops[3]->getType(),
Ops[3]->getType()}; Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[2])); Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[2]));
break; break;
} }
}] in { }] in {
foreach s_p = suffixes_prototypes in { foreach s_p = suffixes_prototypes in {
def : RVVBuiltin<s_p[0], s_p[1], type_range>; def : RVVBuiltin<s_p[0], s_p[1], type_range>;
} }
} }
} }
// 6. Configuration-Setting Instructions // 6. Configuration-Setting Instructions
// 6.1. vsetvli/vsetvl instructions // 6.1. vsetvli/vsetvl instructions
let HasVL = false, let HasVL = false,
HasMask = false, HasMask = false,
HasSideEffects = true, HasSideEffects = true,
HasPolicy = false,
Log2LMUL = [0], Log2LMUL = [0],
ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type
{ {
// vsetvl is a macro because for it require constant integers in SEW and LMUL. // vsetvl is a macro because for it require constant integers in SEW and LMUL.
let HeaderCode = let HeaderCode =
[{ [{
#define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5) #define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
#define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6) #define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Lineslet Log2LMUL = [-3, -2, -1, 0, 1] in {
def vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">; def vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">;
} }
let Log2LMUL = [-3, -2, -1, 0] in { let Log2LMUL = [-3, -2, -1, 0] in {
def vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">; def vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">;
def vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">; def vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">;
} }
// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions // 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
let HasMask = false in { let HasMask = false, HasPolicy = false in {
defm vadc : RVVCarryinBuiltinSet; defm vadc : RVVCarryinBuiltinSet;
defm vmadc : RVVCarryOutInBuiltinSet<"vmadc_carry_in">; defm vmadc : RVVCarryOutInBuiltinSet<"vmadc_carry_in">;
defm vmadc : RVVIntMaskOutBuiltinSet; defm vmadc : RVVIntMaskOutBuiltinSet;
defm vsbc : RVVCarryinBuiltinSet; defm vsbc : RVVCarryinBuiltinSet;
defm vmsbc : RVVCarryOutInBuiltinSet<"vmsbc_borrow_in">; defm vmsbc : RVVCarryOutInBuiltinSet<"vmsbc_borrow_in">;
defm vmsbc : RVVIntMaskOutBuiltinSet; defm vmsbc : RVVIntMaskOutBuiltinSet;
} }
Show All 11 Lines
// 12.7. Vector Narrowing Integer Right Shift Instructions // 12.7. Vector Narrowing Integer Right Shift Instructions
defm vnsrl : RVVUnsignedNShiftBuiltinSet; defm vnsrl : RVVUnsignedNShiftBuiltinSet;
defm vnsra : RVVSignedNShiftBuiltinSet; defm vnsra : RVVSignedNShiftBuiltinSet;
defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi", defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi",
[["v", "vw"], [["v", "vw"],
["Uv", "UvUw"]]>; ["Uv", "UvUw"]]>;
// 12.8. Vector Integer Comparison Instructions // 12.8. Vector Integer Comparison Instructions
let HasPolicy = false in {
defm vmseq : RVVIntMaskOutBuiltinSet; defm vmseq : RVVIntMaskOutBuiltinSet;
defm vmsne : RVVIntMaskOutBuiltinSet; defm vmsne : RVVIntMaskOutBuiltinSet;
defm vmsltu : RVVUnsignedMaskOutBuiltinSet; defm vmsltu : RVVUnsignedMaskOutBuiltinSet;
defm vmslt : RVVSignedMaskOutBuiltinSet; defm vmslt : RVVSignedMaskOutBuiltinSet;
defm vmsleu : RVVUnsignedMaskOutBuiltinSet; defm vmsleu : RVVUnsignedMaskOutBuiltinSet;
defm vmsle : RVVSignedMaskOutBuiltinSet; defm vmsle : RVVSignedMaskOutBuiltinSet;
defm vmsgtu : RVVUnsignedMaskOutBuiltinSet; defm vmsgtu : RVVUnsignedMaskOutBuiltinSet;
defm vmsgt : RVVSignedMaskOutBuiltinSet; defm vmsgt : RVVSignedMaskOutBuiltinSet;
defm vmsgeu : RVVUnsignedMaskOutBuiltinSet; defm vmsgeu : RVVUnsignedMaskOutBuiltinSet;
defm vmsge : RVVSignedMaskOutBuiltinSet; defm vmsge : RVVSignedMaskOutBuiltinSet;
}
// 12.9. Vector Integer Min/Max Instructions // 12.9. Vector Integer Min/Max Instructions
defm vminu : RVVUnsignedBinBuiltinSet; defm vminu : RVVUnsignedBinBuiltinSet;
defm vmin : RVVSignedBinBuiltinSet; defm vmin : RVVSignedBinBuiltinSet;
defm vmaxu : RVVUnsignedBinBuiltinSet; defm vmaxu : RVVUnsignedBinBuiltinSet;
defm vmax : RVVSignedBinBuiltinSet; defm vmax : RVVSignedBinBuiltinSet;
// 12.10. Vector Single-Width Integer Multiply Instructions // 12.10. Vector Single-Width Integer Multiply Instructions
Show All 19 Linesdefm vwmulu : RVVOutOp0Op1BuiltinSet<"vwmulu", "csi",
[["vv", "Uw", "UwUvUv"], [["vv", "Uw", "UwUvUv"],
["vx", "Uw", "UwUvUe"]]>; ["vx", "Uw", "UwUvUe"]]>;
defm vwmulsu : RVVOutOp0Op1BuiltinSet<"vwmulsu", "csi", defm vwmulsu : RVVOutOp0Op1BuiltinSet<"vwmulsu", "csi",
[["vv", "w", "wvUv"], [["vv", "w", "wvUv"],
["vx", "w", "wvUe"]]>; ["vx", "w", "wvUe"]]>;
} }
// 12.13. Vector Single-Width Integer Multiply-Add Instructions // 12.13. Vector Single-Width Integer Multiply-Add Instructions
let HasPolicy = false in {
defm vmacc : RVVIntTerBuiltinSet; defm vmacc : RVVIntTerBuiltinSet;
defm vnmsac : RVVIntTerBuiltinSet; defm vnmsac : RVVIntTerBuiltinSet;
defm vmadd : RVVIntTerBuiltinSet; defm vmadd : RVVIntTerBuiltinSet;
defm vnmsub : RVVIntTerBuiltinSet; defm vnmsub : RVVIntTerBuiltinSet;
// 12.14. Vector Widening Integer Multiply-Add Instructions // 12.14. Vector Widening Integer Multiply-Add Instructions
let HasMaskedOffOperand = false, let HasMaskedOffOperand = false,
Log2LMUL = [-3, -2, -1, 0, 1, 2] in { Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
defm vwmaccu : RVVOutOp1Op2BuiltinSet<"vwmaccu", "csi", defm vwmaccu : RVVOutOp1Op2BuiltinSet<"vwmaccu", "csi",
[["vv", "Uw", "UwUwUvUv"], [["vv", "Uw", "UwUwUvUv"],
["vx", "Uw", "UwUwUeUv"]]>; ["vx", "Uw", "UwUwUeUv"]]>;
defm vwmacc : RVVOutOp1Op2BuiltinSet<"vwmacc", "csi", defm vwmacc : RVVOutOp1Op2BuiltinSet<"vwmacc", "csi",
[["vv", "w", "wwvv"], [["vv", "w", "wwvv"],
["vx", "w", "wwev"]]>; ["vx", "w", "wwev"]]>;
defm vwmaccsu : RVVOutOp1Op2BuiltinSet<"vwmaccsu", "csi", defm vwmaccsu : RVVOutOp1Op2BuiltinSet<"vwmaccsu", "csi",
[["vv", "w", "wwvUv"], [["vv", "w", "wwvUv"],
["vx", "w", "wweUv"]]>; ["vx", "w", "wweUv"]]>;
defm vwmaccus : RVVOutOp1Op2BuiltinSet<"vwmaccus", "csi", defm vwmaccus : RVVOutOp1Op2BuiltinSet<"vwmaccus", "csi",
[["vx", "w", "wwUev"]]>; [["vx", "w", "wwUev"]]>;
} }
}
// 12.15. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
// C/C++ Operand: (mask, op1, op2, vl), Intrinsic: (op1, op2, mask, vl) // C/C++ Operand: (mask, op1, op2, vl), Intrinsic: (op1, op2, mask, vl)
let HasMask = false, let HasMask = false, HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3);
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()};
}] in { }] in {
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "csil", defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "csil",
[["vvm", "v", "vmvv"], [["vvm", "v", "vmvv"],
["vxm", "v", "vmve"], ["vxm", "v", "vmve"],
["vvm", "Uv", "UvmUvUv"], ["vvm", "Uv", "UvmUvUv"],
["vxm", "Uv", "UvmUvUe"]]>; ["vxm", "Uv", "UvmUvUe"]]>;
} }
// 12.16. Vector Integer Move Instructions // 12.16. Vector Integer Move Instructions
let HasMask = false in { let HasMask = false, HasPolicy = false in {
let MangledName = "vmv_v" in { let MangledName = "vmv_v" in {
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil", defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil",
[["v", "Uv", "UvUv"]]>; [["v", "Uv", "UvUv"]]>;
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilxfd", defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilxfd",
[["v", "v", "vv"]]>; [["v", "v", "vv"]]>;
} }
let HasNoMaskedOverloaded = false in let HasNoMaskedOverloaded = false in
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil", defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
// 14.5. Vector Widening Floating-Point Multiply // 14.5. Vector Widening Floating-Point Multiply
let Log2LMUL = [-2, -1, 0, 1, 2] in { let Log2LMUL = [-2, -1, 0, 1, 2] in {
defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf", defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf",
[["vv", "w", "wvv"], [["vv", "w", "wvv"],
["vf", "w", "wve"]]>; ["vf", "w", "wve"]]>;
} }
// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions // 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
let HasPolicy = false in {
defm vfmacc : RVVFloatingTerBuiltinSet; defm vfmacc : RVVFloatingTerBuiltinSet;
defm vfnmacc : RVVFloatingTerBuiltinSet; defm vfnmacc : RVVFloatingTerBuiltinSet;
defm vfmsac : RVVFloatingTerBuiltinSet; defm vfmsac : RVVFloatingTerBuiltinSet;
defm vfnmsac : RVVFloatingTerBuiltinSet; defm vfnmsac : RVVFloatingTerBuiltinSet;
defm vfmadd : RVVFloatingTerBuiltinSet; defm vfmadd : RVVFloatingTerBuiltinSet;
defm vfnmadd : RVVFloatingTerBuiltinSet; defm vfnmadd : RVVFloatingTerBuiltinSet;
defm vfmsub : RVVFloatingTerBuiltinSet; defm vfmsub : RVVFloatingTerBuiltinSet;
defm vfnmsub : RVVFloatingTerBuiltinSet; defm vfnmsub : RVVFloatingTerBuiltinSet;
// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm vfwmacc : RVVFloatingWidenTerBuiltinSet; defm vfwmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwnmacc : RVVFloatingWidenTerBuiltinSet; defm vfwnmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwmsac : RVVFloatingWidenTerBuiltinSet; defm vfwmsac : RVVFloatingWidenTerBuiltinSet;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSet; defm vfwnmsac : RVVFloatingWidenTerBuiltinSet;
}
// 14.8. Vector Floating-Point Square-Root Instruction // 14.8. Vector Floating-Point Square-Root Instruction
def vfsqrt : RVVFloatingUnaryVVBuiltin; def vfsqrt : RVVFloatingUnaryVVBuiltin;
// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction // 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
def vfrsqrt7 : RVVFloatingUnaryVVBuiltin; def vfrsqrt7 : RVVFloatingUnaryVVBuiltin;
// 14.10. Vector Floating-Point Reciprocal Estimate Instruction // 14.10. Vector Floating-Point Reciprocal Estimate Instruction
def vfrec7 : RVVFloatingUnaryVVBuiltin; def vfrec7 : RVVFloatingUnaryVVBuiltin;
// 14.11. Vector Floating-Point MIN/MAX Instructions // 14.11. Vector Floating-Point MIN/MAX Instructions
defm vfmin : RVVFloatingBinBuiltinSet; defm vfmin : RVVFloatingBinBuiltinSet;
defm vfmax : RVVFloatingBinBuiltinSet; defm vfmax : RVVFloatingBinBuiltinSet;
// 14.12. Vector Floating-Point Sign-Injection Instructions // 14.12. Vector Floating-Point Sign-Injection Instructions
defm vfsgnj : RVVFloatingBinBuiltinSet; defm vfsgnj : RVVFloatingBinBuiltinSet;
defm vfsgnjn : RVVFloatingBinBuiltinSet; defm vfsgnjn : RVVFloatingBinBuiltinSet;
defm vfsgnjx : RVVFloatingBinBuiltinSet; defm vfsgnjx : RVVFloatingBinBuiltinSet;
defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">; defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">;
defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">; defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">;
// 14.13. Vector Floating-Point Compare Instructions // 14.13. Vector Floating-Point Compare Instructions
let HasPolicy = false in {
defm vmfeq : RVVFloatingMaskOutBuiltinSet; defm vmfeq : RVVFloatingMaskOutBuiltinSet;
defm vmfne : RVVFloatingMaskOutBuiltinSet; defm vmfne : RVVFloatingMaskOutBuiltinSet;
defm vmflt : RVVFloatingMaskOutBuiltinSet; defm vmflt : RVVFloatingMaskOutBuiltinSet;
defm vmfle : RVVFloatingMaskOutBuiltinSet; defm vmfle : RVVFloatingMaskOutBuiltinSet;
defm vmfgt : RVVFloatingMaskOutBuiltinSet; defm vmfgt : RVVFloatingMaskOutBuiltinSet;
defm vmfge : RVVFloatingMaskOutBuiltinSet; defm vmfge : RVVFloatingMaskOutBuiltinSet;
}
// 14.14. Vector Floating-Point Classify Instruction // 14.14. Vector Floating-Point Classify Instruction
let Name = "vfclass_v" in let Name = "vfclass_v", HasPolicy = false in
def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">; def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">;
// 14.15. Vector Floating-Point Merge Instructio // 14.15. Vector Floating-Point Merge Instructio
// C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl) // C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl)
let HasMask = false, let HasMask = false, HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3);
IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[3]->getType()};
}] in { }] in {
defm vmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd", defm vmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
[["vvm", "v", "vmvv"]]>; [["vvm", "v", "vmvv"]]>;
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd", defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
[["vfm", "v", "vmve"]]>; [["vfm", "v", "vmve"]]>;
} }
// 14.16. Vector Floating-Point Move Instruction // 14.16. Vector Floating-Point Move Instruction
let HasMask = false, HasNoMaskedOverloaded = false in let HasMask = false, HasNoMaskedOverloaded = false, HasPolicy = false in
defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd", defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd",
[["f", "v", "ve"]]>; [["f", "v", "ve"]]>;
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">; def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">;
def vfcvt_x_f_v : RVVConvToSignedBuiltin<"vfcvt_x">; def vfcvt_x_f_v : RVVConvToSignedBuiltin<"vfcvt_x">;
def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">; def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">;
def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">; def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
Show All 20 Lineslet Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">; def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">;
def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">; def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;
def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">; def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">; def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
} }
// 15. Vector Reduction Operations // 15. Vector Reduction Operations
// 15.1. Vector Single-Width Integer Reduction Instructions // 15.1. Vector Single-Width Integer Reduction Instructions
let HasPolicy = false in {
defm vredsum : RVVIntReductionBuiltinSet; defm vredsum : RVVIntReductionBuiltinSet;
defm vredmaxu : RVVUnsignedReductionBuiltin; defm vredmaxu : RVVUnsignedReductionBuiltin;
defm vredmax : RVVSignedReductionBuiltin; defm vredmax : RVVSignedReductionBuiltin;
defm vredminu : RVVUnsignedReductionBuiltin; defm vredminu : RVVUnsignedReductionBuiltin;
defm vredmin : RVVSignedReductionBuiltin; defm vredmin : RVVSignedReductionBuiltin;
defm vredand : RVVIntReductionBuiltinSet; defm vredand : RVVIntReductionBuiltinSet;
defm vredor : RVVIntReductionBuiltinSet; defm vredor : RVVIntReductionBuiltinSet;
defm vredxor : RVVIntReductionBuiltinSet; defm vredxor : RVVIntReductionBuiltinSet;
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defm vfredmax : RVVFloatingReductionBuiltin; defm vfredmax : RVVFloatingReductionBuiltin;
defm vfredmin : RVVFloatingReductionBuiltin; defm vfredmin : RVVFloatingReductionBuiltin;
defm vfredsum : RVVFloatingReductionBuiltin; defm vfredsum : RVVFloatingReductionBuiltin;
defm vfredosum : RVVFloatingReductionBuiltin; defm vfredosum : RVVFloatingReductionBuiltin;
// 15.4. Vector Widening Floating-Point Reduction Instructions // 15.4. Vector Widening Floating-Point Reduction Instructions
defm vfwredsum : RVVFloatingWidenReductionBuiltin; defm vfwredsum : RVVFloatingWidenReductionBuiltin;
defm vfwredosum : RVVFloatingWidenReductionBuiltin; defm vfwredosum : RVVFloatingWidenReductionBuiltin;
}
// 16. Vector Mask Instructions // 16. Vector Mask Instructions
// 16.1. Vector Mask-Register Logical Instructions // 16.1. Vector Mask-Register Logical Instructions
def vmand : RVVMaskBinBuiltin; def vmand : RVVMaskBinBuiltin;
def vmnand : RVVMaskBinBuiltin; def vmnand : RVVMaskBinBuiltin;
def vmandnot : RVVMaskBinBuiltin; def vmandnot : RVVMaskBinBuiltin;
def vmxor : RVVMaskBinBuiltin; def vmxor : RVVMaskBinBuiltin;
def vmor : RVVMaskBinBuiltin; def vmor : RVVMaskBinBuiltin;
def vmnor : RVVMaskBinBuiltin; def vmnor : RVVMaskBinBuiltin;
def vmornot : RVVMaskBinBuiltin; def vmornot : RVVMaskBinBuiltin;
def vmxnor : RVVMaskBinBuiltin; def vmxnor : RVVMaskBinBuiltin;
// pseudoinstructions // pseudoinstructions
def vmclr : RVVMaskNullaryBuiltin; def vmclr : RVVMaskNullaryBuiltin;
def vmset : RVVMaskNullaryBuiltin; def vmset : RVVMaskNullaryBuiltin;
defm vmmv_m : RVVPseudoMaskBuiltin<"vmand", "c">; defm vmmv_m : RVVPseudoMaskBuiltin<"vmand", "c">;
defm vmnot_m : RVVPseudoMaskBuiltin<"vmnand", "c">; defm vmnot_m : RVVPseudoMaskBuiltin<"vmnand", "c">;
let HasPolicy = false in {
// 16.2. Vector mask population count vpopc // 16.2. Vector mask population count vpopc
def vpopc : RVVMaskOp0Builtin<"um">; def vpopc : RVVMaskOp0Builtin<"um">;
// 16.3. vfirst find-first-set mask bit // 16.3. vfirst find-first-set mask bit
def vfirst : RVVMaskOp0Builtin<"lm">; def vfirst : RVVMaskOp0Builtin<"lm">;
// 16.4. vmsbf.m set-before-first mask bit // 16.4. vmsbf.m set-before-first mask bit
def vmsbf : RVVMaskUnaryBuiltin; def vmsbf : RVVMaskUnaryBuiltin;
// 16.5. vmsif.m set-including-first mask bit // 16.5. vmsif.m set-including-first mask bit
def vmsif : RVVMaskUnaryBuiltin; def vmsif : RVVMaskUnaryBuiltin;
// 16.6. vmsof.m set-only-first mask bit // 16.6. vmsof.m set-only-first mask bit
def vmsof : RVVMaskUnaryBuiltin; def vmsof : RVVMaskUnaryBuiltin;
let HasNoMaskedOverloaded = false in { let HasNoMaskedOverloaded = false in {
// 16.8. Vector Iota Instruction // 16.8. Vector Iota Instruction
defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>; defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;
// 16.9. Vector Element Index Instruction // 16.9. Vector Element Index Instruction
defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"], defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"],
["v", "Uv", "Uv"]]>; ["v", "Uv", "Uv"]]>;
} }
}
// 17. Vector Permutation Instructions // 17. Vector Permutation Instructions
// 17.1. Integer Scalar Move Instructions // 17.1. Integer Scalar Move Instructions
let HasMask = false in { let HasMask = false, HasPolicy = false in {
let HasVL = false, MangledName = "vmv_x" in let HasVL = false, MangledName = "vmv_x" in
defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil", defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil",
[["s", "ve", "ev"], [["s", "ve", "ev"],
["s", "UvUe", "UeUv"]]>; ["s", "UvUe", "UeUv"]]>;
let MangledName = "vmv_s" in let MangledName = "vmv_s" in
defm vmv_s : RVVOutBuiltinSet<"vmv_s_x", "csil", defm vmv_s : RVVOutBuiltinSet<"vmv_s_x", "csil",
[["x", "v", "vve"], [["x", "v", "vve"],
["x", "Uv", "UvUvUe"]]>; ["x", "Uv", "UvUvUe"]]>;
} }
// 17.2. Floating-Point Scalar Move Instructions // 17.2. Floating-Point Scalar Move Instructions
let HasMask = false in { let HasMask = false, HasPolicy = false in {
let HasVL = false, MangledName = "vfmv_f" in let HasVL = false, MangledName = "vfmv_f" in
defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "xfd", defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "xfd",
[["s", "ve", "ev"]]>; [["s", "ve", "ev"]]>;
let MangledName = "vfmv_s" in let MangledName = "vfmv_s" in
defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd", defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd",
[["f", "v", "vve"], [["f", "v", "vve"],
["x", "Uv", "UvUvUe"]]>; ["x", "Uv", "UvUvUe"]]>;
} }
// 17.3. Vector Slide Instructions // 17.3. Vector Slide Instructions
let HasPolicy = false in {
// 17.3.1. Vector Slideup Instructions // 17.3.1. Vector Slideup Instructions
defm vslideup : RVVSlideBuiltinSet; defm vslideup : RVVSlideBuiltinSet;
// 17.3.2. Vector Slidedown Instructions // 17.3.2. Vector Slidedown Instructions
defm vslidedown : RVVSlideBuiltinSet; defm vslidedown : RVVSlideBuiltinSet;
}
// 17.3.3. Vector Slide1up Instructions // 17.3.3. Vector Slide1up Instructions
defm vslide1up : RVVSlideOneBuiltinSet; defm vslide1up : RVVSlideOneBuiltinSet;
defm vfslide1up : RVVFloatingBinVFBuiltinSet; defm vfslide1up : RVVFloatingBinVFBuiltinSet;
// 17.3.4. Vector Slide1down Instruction // 17.3.4. Vector Slide1down Instruction
defm vslide1down : RVVSlideOneBuiltinSet; defm vslide1down : RVVSlideOneBuiltinSet;
defm vfslide1down : RVVFloatingBinVFBuiltinSet; defm vfslide1down : RVVFloatingBinVFBuiltinSet;
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defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csil", defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csil",
[["vv", "Uv", "UvUvUv"]]>; [["vv", "Uv", "UvUvUv"]]>;
defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csil", defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "csil",
[["vx", "Uv", "UvUvz"]]>; [["vx", "Uv", "UvUvz"]]>;
defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csil", defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csil",
[["vv", "Uv", "UvUv(Log2EEW:4)Uv"]]>; [["vv", "Uv", "UvUv(Log2EEW:4)Uv"]]>;
// 17.5. Vector Compress Instruction // 17.5. Vector Compress Instruction
let HasMask = false, let HasMask = false, HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3); std::rotate(Ops.begin(), Ops.begin() + 1, Ops.begin() + 3);
IntrinsicTypes = {ResultType, Ops[3]->getType()}; IntrinsicTypes = {ResultType, Ops[3]->getType()};
}] in { }] in {
// signed and floating type // signed and floating type
defm vcompress : RVVOutBuiltinSet<"vcompress", "csilxfd", defm vcompress : RVVOutBuiltinSet<"vcompress", "csilxfd",
[["vm", "v", "vmvv"]]>; [["vm", "v", "vmvv"]]>;
// unsigned type // unsigned type
defm vcompress : RVVOutBuiltinSet<"vcompress", "csil", defm vcompress : RVVOutBuiltinSet<"vcompress", "csil",
[["vm", "Uv", "UvmUvUv"]]>; [["vm", "Uv", "UvmUvUv"]]>;
} }
// Miscellaneous // Miscellaneous
let HasMask = false, HasVL = false, IRName = "" in { let HasMask = false, HasVL = false, IRName = "" in {
let Name = "vreinterpret_v", let Name = "vreinterpret_v", HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
return Builder.CreateBitCast(Ops[0], ResultType); return Builder.CreateBitCast(Ops[0], ResultType);
}] in { }] in {
// Reinterpret between different type under the same SEW and LMUL // Reinterpret between different type under the same SEW and LMUL
def vreinterpret_i_u : RVVBuiltin<"Uvv", "vUv", "csil", "v">; def vreinterpret_i_u : RVVBuiltin<"Uvv", "vUv", "csil", "v">;
def vreinterpret_i_f : RVVBuiltin<"Fvv", "vFv", "sil", "v">; def vreinterpret_i_f : RVVBuiltin<"Fvv", "vFv", "sil", "v">;
def vreinterpret_u_i : RVVBuiltin<"vUv", "Uvv", "csil", "Uv">; def vreinterpret_u_i : RVVBuiltin<"vUv", "Uvv", "csil", "Uv">;
def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "sil", "Uv">; def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "sil", "Uv">;
def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "sil", "Fv">; def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "sil", "Fv">;
def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "sil", "Fv">; def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "sil", "Fv">;
// Reinterpret between different SEW under the same LMUL // Reinterpret between different SEW under the same LMUL
foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)", foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)",
"(FixedSEW:64)"] in { "(FixedSEW:64)"] in {
def vreinterpret_i_ # dst_sew : RVVBuiltin<"v" # dst_sew # "v", def vreinterpret_i_ # dst_sew : RVVBuiltin<"v" # dst_sew # "v",
dst_sew # "vv", "csil", dst_sew # "v">; dst_sew # "vv", "csil", dst_sew # "v">;
def vreinterpret_u_ # dst_sew : RVVBuiltin<"Uv" # dst_sew # "Uv", def vreinterpret_u_ # dst_sew : RVVBuiltin<"Uv" # dst_sew # "Uv",
dst_sew # "UvUv", "csil", dst_sew # "Uv">; dst_sew # "UvUv", "csil", dst_sew # "Uv">;
} }
} }
let Name = "vundefined", HasNoMaskedOverloaded = false, let Name = "vundefined", HasNoMaskedOverloaded = false, HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
return llvm::UndefValue::get(ResultType); return llvm::UndefValue::get(ResultType);
}] in { }] in {
def vundefined : RVVBuiltin<"v", "v", "csilxfd">; def vundefined : RVVBuiltin<"v", "v", "csilxfd">;
def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">; def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">;
} }
// LMUL truncation // LMUL truncation
// C/C++ Operand: VecTy, IR Operand: VecTy, Index // C/C++ Operand: VecTy, IR Operand: VecTy, Index
let Name = "vlmul_trunc_v", MangledName = "vlmul_trunc", let Name = "vlmul_trunc_v", MangledName = "vlmul_trunc", HasPolicy = false,
ManualCodegen = [{ { ManualCodegen = [{ {
ID = Intrinsic::experimental_vector_extract; ID = Intrinsic::experimental_vector_extract;
IntrinsicTypes = {ResultType, Ops[0]->getType()}; IntrinsicTypes = {ResultType, Ops[0]->getType()};
Ops.push_back(ConstantInt::get(Int64Ty, 0)); Ops.push_back(ConstantInt::get(Int64Ty, 0));
return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
} }] in { } }] in {
foreach dst_lmul = ["(SFixedLog2LMUL:-3)", "(SFixedLog2LMUL:-2)", "(SFixedLog2LMUL:-1)", foreach dst_lmul = ["(SFixedLog2LMUL:-3)", "(SFixedLog2LMUL:-2)", "(SFixedLog2LMUL:-1)",
"(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { "(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
def vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", def vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
dst_lmul # "vv", "csilxfd", dst_lmul # "v">; dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
def vlmul_trunc_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", def vlmul_trunc_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv",
dst_lmul # "UvUv", "csil", dst_lmul # "Uv">; dst_lmul # "UvUv", "csil", dst_lmul # "Uv">;
} }
} }
// LMUL extension // LMUL extension
// C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index // C/C++ Operand: SubVecTy, IR Operand: VecTy, SubVecTy, Index
let Name = "vlmul_ext_v", MangledName = "vlmul_ext", let Name = "vlmul_ext_v", MangledName = "vlmul_ext", HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
ID = Intrinsic::experimental_vector_insert; ID = Intrinsic::experimental_vector_insert;
IntrinsicTypes = {ResultType, Ops[0]->getType()}; IntrinsicTypes = {ResultType, Ops[0]->getType()};
Ops.push_back(llvm::UndefValue::get(ResultType)); Ops.push_back(llvm::UndefValue::get(ResultType));
std::swap(Ops[0], Ops[1]); std::swap(Ops[0], Ops[1]);
Ops.push_back(ConstantInt::get(Int64Ty, 0)); Ops.push_back(ConstantInt::get(Int64Ty, 0));
return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
}] in { }] in {
foreach dst_lmul = ["(LFixedLog2LMUL:-2)", "(LFixedLog2LMUL:-1)", "(LFixedLog2LMUL:-0)", foreach dst_lmul = ["(LFixedLog2LMUL:-2)", "(LFixedLog2LMUL:-1)", "(LFixedLog2LMUL:-0)",
"(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { "(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
def vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", def vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v",
dst_lmul # "vv", "csilxfd", dst_lmul # "v">; dst_lmul # "vv", "csilxfd", dst_lmul # "v">;
def vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", def vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv",
dst_lmul # "UvUv", "csil", dst_lmul # "Uv">; dst_lmul # "UvUv", "csil", dst_lmul # "Uv">;
} }
} }
let Name = "vget_v", let Name = "vget_v", HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
{ {
ID = Intrinsic::experimental_vector_extract; ID = Intrinsic::experimental_vector_extract;
ScalableVectorType *VecTy = cast<ScalableVectorType>(ResultType); ScalableVectorType *VecTy = cast<ScalableVectorType>(ResultType);
Ops[1] = Builder.CreateMul(Ops[1], Ops[1] = Builder.CreateMul(Ops[1],
ConstantInt::get(Ops[1]->getType(), ConstantInt::get(Ops[1]->getType(),
VecTy->getMinNumElements())); VecTy->getMinNumElements()));
IntrinsicTypes = {ResultType, Ops[0]->getType()}; IntrinsicTypes = {ResultType, Ops[0]->getType()};
return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
} }
}] in { }] in {
foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">; def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">;
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">;
} }
} }
let Name = "vset_v", Log2LMUL = [0, 1, 2], let Name = "vset_v", Log2LMUL = [0, 1, 2], HasPolicy = false,
ManualCodegen = [{ ManualCodegen = [{
{ {
ID = Intrinsic::experimental_vector_insert; ID = Intrinsic::experimental_vector_insert;
IntrinsicTypes = {ResultType, Ops[2]->getType()}; IntrinsicTypes = {ResultType, Ops[2]->getType()};
ScalableVectorType *VecTy = cast<ScalableVectorType>(Ops[2]->getType()); ScalableVectorType *VecTy = cast<ScalableVectorType>(Ops[2]->getType());
Ops[1] = Builder.CreateMul(Ops[1], Ops[1] = Builder.CreateMul(Ops[1],
ConstantInt::get(Ops[1]->getType(), ConstantInt::get(Ops[1]->getType(),
VecTy->getMinNumElements())); VecTy->getMinNumElements()));
std::swap(Ops[1], Ops[2]); std::swap(Ops[1], Ops[2]);
return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, ""); return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
} }
}] in { }] in {
foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">; def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
} }
} }
} }
let HeaderCode = [{
#define VE_TAIL_UNDISTURBED 0
#define VE_TAIL_AGNOSTIC 1
}] in
def policy : RVVHeader;
khchenUnsubmitted
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It seems like we can rewrite vsetvli/vsetvl and vsetvlmax instructions by using the RVVHeader mechanism?
We only need to have one mechanism to dump header code.

khchen: It seems like we can rewrite `vsetvli/vsetvl` and ` vsetvlmax` instructions by using the…
HsiangKaiAuthorUnsubmitted
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Should we create vsetvli/vsetvlmax builtins? If we should, we may not be able to use RVVHeader for these intrinsics.

HsiangKai: Should we create `vsetvli/vsetvlmax` builtins? If we should, we may not be able to use…
khchenUnsubmitted
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oh, you are right. I forget that.
Could you please move class definition in top of this file due to all class centralized there.

khchen: oh, you are right. I forget that. Could you please move class definition in top of this file…

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
//
craig.topperUnsubmitted
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Please pre-commit this change to reduce noise

craig.topper: Please pre-commit this change to reduce noise
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vadd_vx_i8mf8(vint8mf8_t op1, int8_t op2, size_t vl) { vint8mf8_t test_vadd_vx_i8mf8(vint8mf8_t op1, int8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf4( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vadd_vv_i8mf4(vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vadd_vv_i8mf4(vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf4( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vadd_vx_i8mf4(vint8mf4_t op1, int8_t op2, size_t vl) { vint8mf4_t test_vadd_vx_i8mf4(vint8mf4_t op1, int8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf2( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vadd_vv_i8mf2(vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vadd_vv_i8mf2(vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf2( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vadd_vx_i8mf2(vint8mf2_t op1, int8_t op2, size_t vl) { vint8mf2_t test_vadd_vx_i8mf2(vint8mf2_t op1, int8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m1( // CHECK-RV64-LABEL: @test_vadd_vv_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vadd_vv_i8m1(vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vadd_vv_i8m1(vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m1( // CHECK-RV64-LABEL: @test_vadd_vx_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vadd_vx_i8m1(vint8m1_t op1, int8_t op2, size_t vl) { vint8m1_t test_vadd_vx_i8m1(vint8m1_t op1, int8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m2( // CHECK-RV64-LABEL: @test_vadd_vv_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vadd_vv_i8m2(vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vadd_vv_i8m2(vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m2( // CHECK-RV64-LABEL: @test_vadd_vx_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vadd_vx_i8m2(vint8m2_t op1, int8_t op2, size_t vl) { vint8m2_t test_vadd_vx_i8m2(vint8m2_t op1, int8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m4( // CHECK-RV64-LABEL: @test_vadd_vv_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vadd_vv_i8m4(vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vadd_vv_i8m4(vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m4( // CHECK-RV64-LABEL: @test_vadd_vx_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vadd_vx_i8m4(vint8m4_t op1, int8_t op2, size_t vl) { vint8m4_t test_vadd_vx_i8m4(vint8m4_t op1, int8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m8( // CHECK-RV64-LABEL: @test_vadd_vv_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vadd_vv_i8m8(vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vadd_vv_i8m8(vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m8( // CHECK-RV64-LABEL: @test_vadd_vx_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vadd_vx_i8m8(vint8m8_t op1, int8_t op2, size_t vl) { vint8m8_t test_vadd_vx_i8m8(vint8m8_t op1, int8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf4( // CHECK-RV64-LABEL: @test_vadd_vv_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vadd_vv_i16mf4(vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vadd_vv_i16mf4(vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf4( // CHECK-RV64-LABEL: @test_vadd_vx_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vadd_vx_i16mf4(vint16mf4_t op1, int16_t op2, size_t vl) { vint16mf4_t test_vadd_vx_i16mf4(vint16mf4_t op1, int16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf2( // CHECK-RV64-LABEL: @test_vadd_vv_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vadd_vv_i16mf2(vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vadd_vv_i16mf2(vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf2( // CHECK-RV64-LABEL: @test_vadd_vx_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vadd_vx_i16mf2(vint16mf2_t op1, int16_t op2, size_t vl) { vint16mf2_t test_vadd_vx_i16mf2(vint16mf2_t op1, int16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m1( // CHECK-RV64-LABEL: @test_vadd_vv_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vadd_vv_i16m1(vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vadd_vv_i16m1(vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m1( // CHECK-RV64-LABEL: @test_vadd_vx_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vadd_vx_i16m1(vint16m1_t op1, int16_t op2, size_t vl) { vint16m1_t test_vadd_vx_i16m1(vint16m1_t op1, int16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m2( // CHECK-RV64-LABEL: @test_vadd_vv_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vadd_vv_i16m2(vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vadd_vv_i16m2(vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m2( // CHECK-RV64-LABEL: @test_vadd_vx_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vadd_vx_i16m2(vint16m2_t op1, int16_t op2, size_t vl) { vint16m2_t test_vadd_vx_i16m2(vint16m2_t op1, int16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m4( // CHECK-RV64-LABEL: @test_vadd_vv_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vadd_vv_i16m4(vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vadd_vv_i16m4(vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m4( // CHECK-RV64-LABEL: @test_vadd_vx_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vadd_vx_i16m4(vint16m4_t op1, int16_t op2, size_t vl) { vint16m4_t test_vadd_vx_i16m4(vint16m4_t op1, int16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m8( // CHECK-RV64-LABEL: @test_vadd_vv_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vadd_vv_i16m8(vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vadd_vv_i16m8(vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m8( // CHECK-RV64-LABEL: @test_vadd_vx_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vadd_vx_i16m8(vint16m8_t op1, int16_t op2, size_t vl) { vint16m8_t test_vadd_vx_i16m8(vint16m8_t op1, int16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32mf2( // CHECK-RV64-LABEL: @test_vadd_vv_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vadd_vv_i32mf2(vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vadd_vv_i32mf2(vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32mf2( // CHECK-RV64-LABEL: @test_vadd_vx_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vadd_vx_i32mf2(vint32mf2_t op1, int32_t op2, size_t vl) { vint32mf2_t test_vadd_vx_i32mf2(vint32mf2_t op1, int32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m1( // CHECK-RV64-LABEL: @test_vadd_vv_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vadd_vv_i32m1(vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vadd_vv_i32m1(vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m1( // CHECK-RV64-LABEL: @test_vadd_vx_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vadd_vx_i32m1(vint32m1_t op1, int32_t op2, size_t vl) { vint32m1_t test_vadd_vx_i32m1(vint32m1_t op1, int32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m2( // CHECK-RV64-LABEL: @test_vadd_vv_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vadd_vv_i32m2(vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vadd_vv_i32m2(vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m2( // CHECK-RV64-LABEL: @test_vadd_vx_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vadd_vx_i32m2(vint32m2_t op1, int32_t op2, size_t vl) { vint32m2_t test_vadd_vx_i32m2(vint32m2_t op1, int32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m4( // CHECK-RV64-LABEL: @test_vadd_vv_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vadd_vv_i32m4(vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vadd_vv_i32m4(vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m4( // CHECK-RV64-LABEL: @test_vadd_vx_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vadd_vx_i32m4(vint32m4_t op1, int32_t op2, size_t vl) { vint32m4_t test_vadd_vx_i32m4(vint32m4_t op1, int32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m8( // CHECK-RV64-LABEL: @test_vadd_vv_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vadd_vv_i32m8(vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vadd_vv_i32m8(vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m8( // CHECK-RV64-LABEL: @test_vadd_vx_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vadd_vx_i32m8(vint32m8_t op1, int32_t op2, size_t vl) { vint32m8_t test_vadd_vx_i32m8(vint32m8_t op1, int32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m1( // CHECK-RV64-LABEL: @test_vadd_vv_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vadd_vv_i64m1(vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vadd_vv_i64m1(vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m1( // CHECK-RV64-LABEL: @test_vadd_vx_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vadd_vx_i64m1(vint64m1_t op1, int64_t op2, size_t vl) { vint64m1_t test_vadd_vx_i64m1(vint64m1_t op1, int64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m2( // CHECK-RV64-LABEL: @test_vadd_vv_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vadd_vv_i64m2(vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vadd_vv_i64m2(vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m2( // CHECK-RV64-LABEL: @test_vadd_vx_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vadd_vx_i64m2(vint64m2_t op1, int64_t op2, size_t vl) { vint64m2_t test_vadd_vx_i64m2(vint64m2_t op1, int64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m4( // CHECK-RV64-LABEL: @test_vadd_vv_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vadd_vv_i64m4(vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vadd_vv_i64m4(vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m4( // CHECK-RV64-LABEL: @test_vadd_vx_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vadd_vx_i64m4(vint64m4_t op1, int64_t op2, size_t vl) { vint64m4_t test_vadd_vx_i64m4(vint64m4_t op1, int64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m8( // CHECK-RV64-LABEL: @test_vadd_vv_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vadd_vv_i64m8(vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vadd_vv_i64m8(vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m8( // CHECK-RV64-LABEL: @test_vadd_vx_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vadd_vx_i64m8(vint64m8_t op1, int64_t op2, size_t vl) { vint64m8_t test_vadd_vx_i64m8(vint64m8_t op1, int64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vadd_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vadd_vv_u8mf8(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vadd_vx_u8mf8(vuint8mf8_t op1, uint8_t op2, size_t vl) { vuint8mf8_t test_vadd_vx_u8mf8(vuint8mf8_t op1, uint8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf4( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vadd_vv_u8mf4(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vadd_vv_u8mf4(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf4( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vadd_vx_u8mf4(vuint8mf4_t op1, uint8_t op2, size_t vl) { vuint8mf4_t test_vadd_vx_u8mf4(vuint8mf4_t op1, uint8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf2( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vadd_vv_u8mf2(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vadd_vv_u8mf2(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf2( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vadd_vx_u8mf2(vuint8mf2_t op1, uint8_t op2, size_t vl) { vuint8mf2_t test_vadd_vx_u8mf2(vuint8mf2_t op1, uint8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m1( // CHECK-RV64-LABEL: @test_vadd_vv_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vadd_vv_u8m1(vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vadd_vv_u8m1(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m1( // CHECK-RV64-LABEL: @test_vadd_vx_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vadd_vx_u8m1(vuint8m1_t op1, uint8_t op2, size_t vl) { vuint8m1_t test_vadd_vx_u8m1(vuint8m1_t op1, uint8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m2( // CHECK-RV64-LABEL: @test_vadd_vv_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vadd_vv_u8m2(vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vadd_vv_u8m2(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m2( // CHECK-RV64-LABEL: @test_vadd_vx_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vadd_vx_u8m2(vuint8m2_t op1, uint8_t op2, size_t vl) { vuint8m2_t test_vadd_vx_u8m2(vuint8m2_t op1, uint8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m4( // CHECK-RV64-LABEL: @test_vadd_vv_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vadd_vv_u8m4(vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vadd_vv_u8m4(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m4( // CHECK-RV64-LABEL: @test_vadd_vx_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vadd_vx_u8m4(vuint8m4_t op1, uint8_t op2, size_t vl) { vuint8m4_t test_vadd_vx_u8m4(vuint8m4_t op1, uint8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m8( // CHECK-RV64-LABEL: @test_vadd_vv_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vadd_vv_u8m8(vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vadd_vv_u8m8(vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m8( // CHECK-RV64-LABEL: @test_vadd_vx_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vadd_vx_u8m8(vuint8m8_t op1, uint8_t op2, size_t vl) { vuint8m8_t test_vadd_vx_u8m8(vuint8m8_t op1, uint8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf4( // CHECK-RV64-LABEL: @test_vadd_vv_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vadd_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vadd_vv_u16mf4(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf4( // CHECK-RV64-LABEL: @test_vadd_vx_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vadd_vx_u16mf4(vuint16mf4_t op1, uint16_t op2, size_t vl) { vuint16mf4_t test_vadd_vx_u16mf4(vuint16mf4_t op1, uint16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf2( // CHECK-RV64-LABEL: @test_vadd_vv_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vadd_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vadd_vv_u16mf2(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf2( // CHECK-RV64-LABEL: @test_vadd_vx_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vadd_vx_u16mf2(vuint16mf2_t op1, uint16_t op2, size_t vl) { vuint16mf2_t test_vadd_vx_u16mf2(vuint16mf2_t op1, uint16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m1( // CHECK-RV64-LABEL: @test_vadd_vv_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vadd_vv_u16m1(vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vadd_vv_u16m1(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m1( // CHECK-RV64-LABEL: @test_vadd_vx_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vadd_vx_u16m1(vuint16m1_t op1, uint16_t op2, size_t vl) { vuint16m1_t test_vadd_vx_u16m1(vuint16m1_t op1, uint16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m2( // CHECK-RV64-LABEL: @test_vadd_vv_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vadd_vv_u16m2(vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vadd_vv_u16m2(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m2( // CHECK-RV64-LABEL: @test_vadd_vx_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vadd_vx_u16m2(vuint16m2_t op1, uint16_t op2, size_t vl) { vuint16m2_t test_vadd_vx_u16m2(vuint16m2_t op1, uint16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m4( // CHECK-RV64-LABEL: @test_vadd_vv_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vadd_vv_u16m4(vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vadd_vv_u16m4(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m4( // CHECK-RV64-LABEL: @test_vadd_vx_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vadd_vx_u16m4(vuint16m4_t op1, uint16_t op2, size_t vl) { vuint16m4_t test_vadd_vx_u16m4(vuint16m4_t op1, uint16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m8( // CHECK-RV64-LABEL: @test_vadd_vv_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vadd_vv_u16m8(vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vadd_vv_u16m8(vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m8( // CHECK-RV64-LABEL: @test_vadd_vx_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vadd_vx_u16m8(vuint16m8_t op1, uint16_t op2, size_t vl) { vuint16m8_t test_vadd_vx_u16m8(vuint16m8_t op1, uint16_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32mf2( // CHECK-RV64-LABEL: @test_vadd_vv_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vadd_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vadd_vv_u32mf2(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32mf2( // CHECK-RV64-LABEL: @test_vadd_vx_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vadd_vx_u32mf2(vuint32mf2_t op1, uint32_t op2, size_t vl) { vuint32mf2_t test_vadd_vx_u32mf2(vuint32mf2_t op1, uint32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m1( // CHECK-RV64-LABEL: @test_vadd_vv_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vadd_vv_u32m1(vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vadd_vv_u32m1(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m1( // CHECK-RV64-LABEL: @test_vadd_vx_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vadd_vx_u32m1(vuint32m1_t op1, uint32_t op2, size_t vl) { vuint32m1_t test_vadd_vx_u32m1(vuint32m1_t op1, uint32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m2( // CHECK-RV64-LABEL: @test_vadd_vv_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vadd_vv_u32m2(vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vadd_vv_u32m2(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m2( // CHECK-RV64-LABEL: @test_vadd_vx_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vadd_vx_u32m2(vuint32m2_t op1, uint32_t op2, size_t vl) { vuint32m2_t test_vadd_vx_u32m2(vuint32m2_t op1, uint32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m4( // CHECK-RV64-LABEL: @test_vadd_vv_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vadd_vv_u32m4(vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vadd_vv_u32m4(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m4( // CHECK-RV64-LABEL: @test_vadd_vx_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vadd_vx_u32m4(vuint32m4_t op1, uint32_t op2, size_t vl) { vuint32m4_t test_vadd_vx_u32m4(vuint32m4_t op1, uint32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m8( // CHECK-RV64-LABEL: @test_vadd_vv_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vadd_vv_u32m8(vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vadd_vv_u32m8(vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m8( // CHECK-RV64-LABEL: @test_vadd_vx_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vadd_vx_u32m8(vuint32m8_t op1, uint32_t op2, size_t vl) { vuint32m8_t test_vadd_vx_u32m8(vuint32m8_t op1, uint32_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m1( // CHECK-RV64-LABEL: @test_vadd_vv_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vadd_vv_u64m1(vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vadd_vv_u64m1(vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m1( // CHECK-RV64-LABEL: @test_vadd_vx_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vadd_vx_u64m1(vuint64m1_t op1, uint64_t op2, size_t vl) { vuint64m1_t test_vadd_vx_u64m1(vuint64m1_t op1, uint64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m2( // CHECK-RV64-LABEL: @test_vadd_vv_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vadd_vv_u64m2(vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vadd_vv_u64m2(vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m2( // CHECK-RV64-LABEL: @test_vadd_vx_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vadd_vx_u64m2(vuint64m2_t op1, uint64_t op2, size_t vl) { vuint64m2_t test_vadd_vx_u64m2(vuint64m2_t op1, uint64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m4( // CHECK-RV64-LABEL: @test_vadd_vv_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vadd_vv_u64m4(vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vadd_vv_u64m4(vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m4( // CHECK-RV64-LABEL: @test_vadd_vx_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vadd_vx_u64m4(vuint64m4_t op1, uint64_t op2, size_t vl) { vuint64m4_t test_vadd_vx_u64m4(vuint64m4_t op1, uint64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m8( // CHECK-RV64-LABEL: @test_vadd_vv_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vadd_vv_u64m8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vadd_vv_u64m8(vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m8( // CHECK-RV64-LABEL: @test_vadd_vx_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vadd_vx_u64m8(vuint64m8_t op1, uint64_t op2, size_t vl) { vuint64m8_t test_vadd_vx_u64m8(vuint64m8_t op1, uint64_t op2, size_t vl) {
return vadd(op1, op2, vl); return vadd(op1, op2, vl);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) { vint8mf8_t test_vadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) { vint8mf4_t test_vadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) { vint8mf2_t test_vadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vadd_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vadd_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vadd_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) { vint8m1_t test_vadd_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vadd_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vadd_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vadd_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) { vint8m2_t test_vadd_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vadd_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vadd_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vadd_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) { vint8m4_t test_vadd_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vadd_vv_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vadd_vv_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vadd_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, int8_t op2, size_t vl) { vint8m8_t test_vadd_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, int8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) { vint16mf4_t test_vadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) { vint16mf2_t test_vadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vadd_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vadd_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vadd_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) { vint16m1_t test_vadd_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vadd_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vadd_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vadd_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) { vint16m2_t test_vadd_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vadd_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vadd_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vadd_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) { vint16m4_t test_vadd_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vadd_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vadd_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vadd_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, int16_t op2, size_t vl) { vint16m8_t test_vadd_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, int16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) { vint32mf2_t test_vadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vadd_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vadd_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vadd_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) { vint32m1_t test_vadd_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vadd_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vadd_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vadd_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) { vint32m2_t test_vadd_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vadd_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vadd_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vadd_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) { vint32m4_t test_vadd_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vadd_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vadd_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vadd_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, int32_t op2, size_t vl) { vint32m8_t test_vadd_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, int32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vadd_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vadd_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vadd_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, int64_t op2, size_t vl) { vint64m1_t test_vadd_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, int64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vadd_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vadd_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vadd_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, int64_t op2, size_t vl) { vint64m2_t test_vadd_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, int64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vadd_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vadd_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vadd_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, int64_t op2, size_t vl) { vint64m4_t test_vadd_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, int64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vadd_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vadd_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vadd_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, int64_t op2, size_t vl) { vint64m8_t test_vadd_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, int64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) { vuint8mf8_t test_vadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) { vuint8mf4_t test_vadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) { vuint8mf2_t test_vadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) { vuint8m1_t test_vadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) { vuint8m2_t test_vadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) { vuint8m4_t test_vadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, uint8_t op2, size_t vl) { vuint8m8_t test_vadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, uint8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) { vuint16mf4_t test_vadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) { vuint16mf2_t test_vadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) { vuint16m1_t test_vadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) { vuint16m2_t test_vadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) { vuint16m4_t test_vadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint16_t op2, size_t vl) { vuint16m8_t test_vadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint16_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) { vuint32mf2_t test_vadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) { vuint32m1_t test_vadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) { vuint32m2_t test_vadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) { vuint32m4_t test_vadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint32_t op2, size_t vl) { vuint32m8_t test_vadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint32_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint64_t op2, size_t vl) { vuint64m1_t test_vadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint64_t op2, size_t vl) { vuint64m2_t test_vadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint64_t op2, size_t vl) { vuint64m4_t test_vadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }
//
// CHECK-RV64-LABEL: @test_vadd_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl); return vadd(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vadd-policy.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg \
// RUN: | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vadd_vv_i8mf8(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
khchenUnsubmitted
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Nit: we don't need to add a space here.

khchen: Nit: we don't need to add a space here.
return vadd_vv_i8mf8(op1, op2, vl); return vadd_vv_i8mf8(op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
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// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vadd_vx_u64m8(vuint64m8_t op1, uint64_t op2, size_t vl) { vuint64m8_t test_vadd_vx_u64m8(vuint64m8_t op1, uint64_t op2, size_t vl) {
return vadd_vx_u64m8(op1, op2, vl); return vadd_vx_u64m8(op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) { vint8mf8_t test_vadd_vv_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
return vadd_vv_i8mf8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i8mf8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) { vint8mf8_t test_vadd_vx_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) {
return vadd_vx_i8mf8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i8mf8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) { vint8mf4_t test_vadd_vv_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
return vadd_vv_i8mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i8mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) { vint8mf4_t test_vadd_vx_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) {
return vadd_vx_i8mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i8mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) { vint8mf2_t test_vadd_vv_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
return vadd_vv_i8mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i8mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) { vint8mf2_t test_vadd_vx_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) {
return vadd_vx_i8mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i8mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vadd_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) { vint8m1_t test_vadd_vv_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) {
return vadd_vv_i8m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i8m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vadd_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) { vint8m1_t test_vadd_vx_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) {
return vadd_vx_i8m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i8m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vadd_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) { vint8m2_t test_vadd_vv_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) {
return vadd_vv_i8m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i8m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vadd_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) { vint8m2_t test_vadd_vx_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) {
return vadd_vx_i8m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i8m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vadd_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) { vint8m4_t test_vadd_vv_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) {
return vadd_vv_i8m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i8m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vadd_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) { vint8m4_t test_vadd_vx_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) {
return vadd_vx_i8m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i8m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vadd_vv_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vint8m8_t op2, size_t vl) { vint8m8_t test_vadd_vv_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vint8m8_t op2, size_t vl) {
return vadd_vv_i8m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i8m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i8m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vadd_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, int8_t op2, size_t vl) { vint8m8_t test_vadd_vx_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, int8_t op2, size_t vl) {
return vadd_vx_i8m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i8m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) { vint16mf4_t test_vadd_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
return vadd_vv_i16mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i16mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) { vint16mf4_t test_vadd_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) {
return vadd_vx_i16mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i16mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) { vint16mf2_t test_vadd_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
return vadd_vv_i16mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i16mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) { vint16mf2_t test_vadd_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) {
return vadd_vx_i16mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i16mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i16m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vadd_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) { vint16m1_t test_vadd_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) {
return vadd_vv_i16m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i16m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i16m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vadd_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) { vint16m1_t test_vadd_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) {
return vadd_vx_i16m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i16m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i16m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vadd_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) { vint16m2_t test_vadd_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) {
return vadd_vv_i16m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i16m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i16m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vadd_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) { vint16m2_t test_vadd_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) {
return vadd_vx_i16m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i16m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i16m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vadd_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) { vint16m4_t test_vadd_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) {
return vadd_vv_i16m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i16m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i16m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vadd_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) { vint16m4_t test_vadd_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) {
return vadd_vx_i16m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i16m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i16m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vadd_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vint16m8_t op2, size_t vl) { vint16m8_t test_vadd_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vint16m8_t op2, size_t vl) {
return vadd_vv_i16m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i16m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i16m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vadd_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, int16_t op2, size_t vl) { vint16m8_t test_vadd_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, int16_t op2, size_t vl) {
return vadd_vx_i16m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i16m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) { vint32mf2_t test_vadd_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
return vadd_vv_i32mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i32mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) { vint32mf2_t test_vadd_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) {
return vadd_vx_i32mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i32mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i32m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vadd_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) { vint32m1_t test_vadd_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) {
return vadd_vv_i32m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i32m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i32m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vadd_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) { vint32m1_t test_vadd_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) {
return vadd_vx_i32m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i32m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i32m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vadd_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) { vint32m2_t test_vadd_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) {
return vadd_vv_i32m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i32m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i32m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vadd_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) { vint32m2_t test_vadd_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) {
return vadd_vx_i32m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i32m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i32m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vadd_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) { vint32m4_t test_vadd_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) {
return vadd_vv_i32m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i32m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i32m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vadd_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) { vint32m4_t test_vadd_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) {
return vadd_vx_i32m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i32m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i32m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vadd_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vint32m8_t op2, size_t vl) { vint32m8_t test_vadd_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vint32m8_t op2, size_t vl) {
return vadd_vv_i32m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i32m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i32m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vadd_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, int32_t op2, size_t vl) { vint32m8_t test_vadd_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, int32_t op2, size_t vl) {
return vadd_vx_i32m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i32m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i64m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vadd_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vint64m1_t op2, size_t vl) { vint64m1_t test_vadd_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vint64m1_t op2, size_t vl) {
return vadd_vv_i64m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i64m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i64m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vadd_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, int64_t op2, size_t vl) { vint64m1_t test_vadd_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, int64_t op2, size_t vl) {
return vadd_vx_i64m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i64m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i64m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vadd_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vint64m2_t op2, size_t vl) { vint64m2_t test_vadd_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vint64m2_t op2, size_t vl) {
return vadd_vv_i64m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i64m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i64m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vadd_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, int64_t op2, size_t vl) { vint64m2_t test_vadd_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, int64_t op2, size_t vl) {
return vadd_vx_i64m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i64m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i64m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vadd_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vint64m4_t op2, size_t vl) { vint64m4_t test_vadd_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vint64m4_t op2, size_t vl) {
return vadd_vv_i64m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i64m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i64m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vadd_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, int64_t op2, size_t vl) { vint64m4_t test_vadd_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, int64_t op2, size_t vl) {
return vadd_vx_i64m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i64m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i64m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vadd_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vint64m8_t op2, size_t vl) { vint64m8_t test_vadd_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vint64m8_t op2, size_t vl) {
return vadd_vv_i64m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_i64m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_i64m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_i64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vadd_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, int64_t op2, size_t vl) { vint64m8_t test_vadd_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, int64_t op2, size_t vl) {
return vadd_vx_i64m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_i64m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) { vuint8mf8_t test_vadd_vv_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
return vadd_vv_u8mf8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u8mf8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) { vuint8mf8_t test_vadd_vx_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
return vadd_vx_u8mf8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u8mf8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) { vuint8mf4_t test_vadd_vv_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
return vadd_vv_u8mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u8mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) { vuint8mf4_t test_vadd_vx_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
return vadd_vx_u8mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u8mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) { vuint8mf2_t test_vadd_vv_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
return vadd_vv_u8mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u8mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) { vuint8mf2_t test_vadd_vx_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
return vadd_vx_u8mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u8mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u8m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) { vuint8m1_t test_vadd_vv_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
return vadd_vv_u8m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u8m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u8m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) { vuint8m1_t test_vadd_vx_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
return vadd_vx_u8m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u8m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u8m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) { vuint8m2_t test_vadd_vv_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
return vadd_vv_u8m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u8m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u8m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) { vuint8m2_t test_vadd_vx_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
return vadd_vx_u8m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u8m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u8m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) { vuint8m4_t test_vadd_vv_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
return vadd_vv_u8m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u8m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u8m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) { vuint8m4_t test_vadd_vx_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
return vadd_vx_u8m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u8m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u8m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t op2, size_t vl) { vuint8m8_t test_vadd_vv_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t op2, size_t vl) {
return vadd_vv_u8m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u8m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u8m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u8m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, uint8_t op2, size_t vl) { vuint8m8_t test_vadd_vx_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, uint8_t op2, size_t vl) {
return vadd_vx_u8m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u8m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) { vuint16mf4_t test_vadd_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
return vadd_vv_u16mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u16mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) { vuint16mf4_t test_vadd_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
return vadd_vx_u16mf4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u16mf4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) { vuint16mf2_t test_vadd_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
return vadd_vv_u16mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u16mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) { vuint16mf2_t test_vadd_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
return vadd_vx_u16mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u16mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u16m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) { vuint16m1_t test_vadd_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
return vadd_vv_u16m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u16m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u16m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) { vuint16m1_t test_vadd_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
return vadd_vx_u16m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u16m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u16m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) { vuint16m2_t test_vadd_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
return vadd_vv_u16m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u16m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u16m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) { vuint16m2_t test_vadd_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
return vadd_vx_u16m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u16m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u16m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) { vuint16m4_t test_vadd_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
return vadd_vv_u16m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u16m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u16m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) { vuint16m4_t test_vadd_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
return vadd_vx_u16m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u16m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u16m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t op2, size_t vl) { vuint16m8_t test_vadd_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t op2, size_t vl) {
return vadd_vv_u16m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u16m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u16m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u16m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint16_t op2, size_t vl) { vuint16m8_t test_vadd_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint16_t op2, size_t vl) {
return vadd_vx_u16m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u16m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) { vuint32mf2_t test_vadd_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
return vadd_vv_u32mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u32mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u32mf2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32mf2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) { vuint32mf2_t test_vadd_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
return vadd_vx_u32mf2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u32mf2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u32m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) { vuint32m1_t test_vadd_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
return vadd_vv_u32m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u32m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u32m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) { vuint32m1_t test_vadd_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
return vadd_vx_u32m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u32m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u32m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) { vuint32m2_t test_vadd_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
return vadd_vv_u32m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u32m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u32m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) { vuint32m2_t test_vadd_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
return vadd_vx_u32m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u32m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u32m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) { vuint32m4_t test_vadd_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
return vadd_vv_u32m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u32m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u32m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) { vuint32m4_t test_vadd_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
return vadd_vx_u32m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u32m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u32m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t op2, size_t vl) { vuint32m8_t test_vadd_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t op2, size_t vl) {
return vadd_vv_u32m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u32m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u32m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u32m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint32_t op2, size_t vl) { vuint32m8_t test_vadd_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint32_t op2, size_t vl) {
return vadd_vx_u32m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u32m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u64m1_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t op2, size_t vl) { vuint64m1_t test_vadd_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t op2, size_t vl) {
return vadd_vv_u64m1_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u64m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u64m1_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint64_t op2, size_t vl) { vuint64m1_t test_vadd_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint64_t op2, size_t vl) {
return vadd_vx_u64m1_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u64m1_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u64m2_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t op2, size_t vl) { vuint64m2_t test_vadd_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t op2, size_t vl) {
return vadd_vv_u64m2_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u64m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u64m2_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint64_t op2, size_t vl) { vuint64m2_t test_vadd_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint64_t op2, size_t vl) {
return vadd_vx_u64m2_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u64m2_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u64m4_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t op2, size_t vl) { vuint64m4_t test_vadd_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t op2, size_t vl) {
return vadd_vv_u64m4_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u64m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u64m4_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint64_t op2, size_t vl) { vuint64m4_t test_vadd_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint64_t op2, size_t vl) {
return vadd_vx_u64m4_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u64m4_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_u64m8_m( // CHECK-RV64-LABEL: @test_vadd_vv_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t op2, size_t vl) { vuint64m8_t test_vadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t op2, size_t vl) {
return vadd_vv_u64m8_m(mask, maskedoff, op1, op2, vl); return vadd_vv_u64m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vx_u64m8_m( // CHECK-RV64-LABEL: @test_vadd_vx_u64m8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) { vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
return vadd_vx_u64m8_m(mask, maskedoff, op1, op2, vl); return vadd_vx_u64m8_m(mask, maskedoff, op1, op2, vl);
} }
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vadd_vv_i8mf8_mt(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i8mf8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vint8mf8_t test_vadd_vx_i8mf8_mt(vbool64_t mask, vint8mf8_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i8mf8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vadd_vv_i8mf4_mt(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i8mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vint8mf4_t test_vadd_vx_i8mf4_mt(vbool32_t mask, vint8mf4_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i8mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i8mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vadd_vv_i8mf2_mt(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i8mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i8mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vint8mf2_t test_vadd_vx_i8mf2_mt(vbool16_t mask, vint8mf2_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i8mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i8m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vadd_vv_i8m1_mt(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i8m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i8m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vint8m1_t test_vadd_vx_i8m1_mt(vbool8_t mask, vint8m1_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i8m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i8m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vadd_vv_i8m2_mt(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i8m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i8m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vint8m2_t test_vadd_vx_i8m2_mt(vbool4_t mask, vint8m2_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i8m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i8m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vadd_vv_i8m4_mt(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i8m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i8m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vint8m4_t test_vadd_vx_i8m4_mt(vbool2_t mask, vint8m4_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i8m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i8m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vadd_vv_i8m8_mt(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, vint8m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i8m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i8m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vint8m8_t test_vadd_vx_i8m8_mt(vbool1_t mask, vint8m8_t maskedoff, vint8m8_t op1, int8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i8m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vadd_vv_i16mf4_mt(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i16mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vint16mf4_t test_vadd_vx_i16mf4_mt(vbool64_t mask, vint16mf4_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i16mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i16mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vadd_vv_i16mf2_mt(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i16mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i16mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vint16mf2_t test_vadd_vx_i16mf2_mt(vbool32_t mask, vint16mf2_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i16mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i16m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vadd_vv_i16m1_mt(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i16m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i16m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vint16m1_t test_vadd_vx_i16m1_mt(vbool16_t mask, vint16m1_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i16m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i16m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vadd_vv_i16m2_mt(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i16m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i16m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vint16m2_t test_vadd_vx_i16m2_mt(vbool8_t mask, vint16m2_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i16m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i16m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vadd_vv_i16m4_mt(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i16m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i16m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vint16m4_t test_vadd_vx_i16m4_mt(vbool4_t mask, vint16m4_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i16m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i16m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vadd_vv_i16m8_mt(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, vint16m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i16m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i16m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vint16m8_t test_vadd_vx_i16m8_mt(vbool2_t mask, vint16m8_t maskedoff, vint16m8_t op1, int16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i16m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i32mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vadd_vv_i32mf2_mt(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i32mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i32mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vint32mf2_t test_vadd_vx_i32mf2_mt(vbool64_t mask, vint32mf2_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i32mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i32m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vadd_vv_i32m1_mt(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i32m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i32m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vint32m1_t test_vadd_vx_i32m1_mt(vbool32_t mask, vint32m1_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i32m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i32m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vadd_vv_i32m2_mt(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i32m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i32m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vint32m2_t test_vadd_vx_i32m2_mt(vbool16_t mask, vint32m2_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i32m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i32m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vadd_vv_i32m4_mt(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i32m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i32m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vint32m4_t test_vadd_vx_i32m4_mt(vbool8_t mask, vint32m4_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i32m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i32m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vadd_vv_i32m8_mt(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, vint32m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i32m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i32m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vint32m8_t test_vadd_vx_i32m8_mt(vbool4_t mask, vint32m8_t maskedoff, vint32m8_t op1, int32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i32m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i64m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vadd_vv_i64m1_mt(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, vint64m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i64m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i64m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vint64m1_t test_vadd_vx_i64m1_mt(vbool64_t mask, vint64m1_t maskedoff, vint64m1_t op1, int64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i64m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i64m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vadd_vv_i64m2_mt(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, vint64m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i64m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i64m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vint64m2_t test_vadd_vx_i64m2_mt(vbool32_t mask, vint64m2_t maskedoff, vint64m2_t op1, int64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i64m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i64m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vadd_vv_i64m4_mt(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, vint64m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i64m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i64m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vint64m4_t test_vadd_vx_i64m4_mt(vbool16_t mask, vint64m4_t maskedoff, vint64m4_t op1, int64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i64m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_i64m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vadd_vv_i64m8_mt(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, vint64m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_i64m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_i64m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vint64m8_t test_vadd_vx_i64m8_mt(vbool8_t mask, vint64m8_t maskedoff, vint64m8_t op1, int64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_i64m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vadd_vv_u8mf8_mt(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u8mf8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
//
vuint8mf8_t test_vadd_vx_u8mf8_mt(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u8mf8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vadd_vv_u8mf4_mt(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u8mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
//
vuint8mf4_t test_vadd_vx_u8mf4_mt(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u8mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u8mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vadd_vv_u8mf2_mt(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u8mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u8mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
//
vuint8mf2_t test_vadd_vx_u8mf2_mt(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u8mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u8m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vadd_vv_u8m1_mt(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u8m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u8m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
//
vuint8m1_t test_vadd_vx_u8m1_mt(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u8m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u8m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vadd_vv_u8m2_mt(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u8m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u8m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
vuint8m2_t test_vadd_vx_u8m2_mt(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u8m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u8m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vadd_vv_u8m4_mt(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u8m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u8m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
//
vuint8m4_t test_vadd_vx_u8m4_mt(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u8m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u8m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], <vscale x 64 x i8> [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vadd_vv_u8m8_mt(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, vuint8m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u8m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u8m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
//
vuint8m8_t test_vadd_vx_u8m8_mt(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t op1, uint8_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u8m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vadd_vv_u16mf4_mt(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u16mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
//
vuint16mf4_t test_vadd_vx_u16mf4_mt(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u16mf4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u16mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vadd_vv_u16mf2_mt(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u16mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u16mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
//
vuint16mf2_t test_vadd_vx_u16mf2_mt(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u16mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u16m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vadd_vv_u16m1_mt(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u16m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u16m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
//
vuint16m1_t test_vadd_vx_u16m1_mt(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u16m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u16m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vadd_vv_u16m2_mt(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u16m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u16m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
//
vuint16m2_t test_vadd_vx_u16m2_mt(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u16m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u16m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vadd_vv_u16m4_mt(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u16m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u16m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
//
vuint16m4_t test_vadd_vx_u16m4_mt(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u16m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u16m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], <vscale x 32 x i16> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vadd_vv_u16m8_mt(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, vuint16m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u16m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u16m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
//
vuint16m8_t test_vadd_vx_u16m8_mt(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t op1, uint16_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u16m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u32mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vadd_vv_u32mf2_mt(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u32mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u32mf2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
//
vuint32mf2_t test_vadd_vx_u32mf2_mt(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u32mf2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u32m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vadd_vv_u32m1_mt(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u32m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u32m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
//
vuint32m1_t test_vadd_vx_u32m1_mt(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u32m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u32m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vadd_vv_u32m2_mt(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u32m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u32m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
//
vuint32m2_t test_vadd_vx_u32m2_mt(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u32m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u32m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vadd_vv_u32m4_mt(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u32m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u32m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
//
vuint32m4_t test_vadd_vx_u32m4_mt(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u32m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u32m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], <vscale x 16 x i32> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vadd_vv_u32m8_mt(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, vuint32m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u32m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u32m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
//
vuint32m8_t test_vadd_vx_u32m8_mt(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t op1, uint32_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u32m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u64m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], <vscale x 1 x i64> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vadd_vv_u64m1_mt(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, vuint64m1_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u64m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u64m1_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
//
vuint64m1_t test_vadd_vx_u64m1_mt(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t op1, uint64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u64m1_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u64m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vadd_vv_u64m2_mt(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, vuint64m2_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u64m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u64m2_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
//
vuint64m2_t test_vadd_vx_u64m2_mt(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t op1, uint64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u64m2_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u64m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], <vscale x 4 x i64> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vadd_vv_u64m4_mt(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, vuint64m4_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u64m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u64m4_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
//
vuint64m4_t test_vadd_vx_u64m4_mt(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t op1, uint64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u64m4_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vv_u64m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], <vscale x 8 x i64> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vadd_vv_u64m8_mt(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, vuint64m8_t op2, size_t vl, uint8_t ta) {
return vadd_vv_u64m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}
// CHECK-RV64-LABEL: @test_vadd_vx_u64m8_mt(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64> [[OP1:%.*]], i64 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
//
vuint64m8_t test_vadd_vx_u64m8_mt(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl, uint8_t ta) {
return vadd_vx_u64m8_mt(mask, maskedoff, op1, op2, vl, VE_TAIL_AGNOSTIC);
}

clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c

clang/utils/TableGen/RISCVVEmitter.cpp

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
private: private:
std::string Name; // Builtin name std::string Name; // Builtin name
std::string MangledName; std::string MangledName;
std::string IRName; std::string IRName;
bool HasSideEffects; bool HasSideEffects;
bool IsMask; bool IsMask;
bool HasMaskedOffOperand; bool HasMaskedOffOperand;
bool HasVL; bool HasVL;
bool HasPolicy;
bool HasNoMaskedOverloaded; bool HasNoMaskedOverloaded;
bool HasAutoDef; // There is automiatic definition in header bool HasAutoDef; // There is automiatic definition in header
std::string ManualCodegen; std::string ManualCodegen;
RVVTypePtr OutputType; // Builtin output type RVVTypePtr OutputType; // Builtin output type
RVVTypes InputTypes; // Builtin input types RVVTypes InputTypes; // Builtin input types
// The types we use to obtain the specific LLVM intrinsic. They are index of // The types we use to obtain the specific LLVM intrinsic. They are index of
// InputTypes. -1 means the return type. // InputTypes. -1 means the return type.
std::vector<int64_t> IntrinsicTypes; std::vector<int64_t> IntrinsicTypes;
uint8_t RISCVExtensions = 0; uint8_t RISCVExtensions = 0;
unsigned NF = 1; unsigned NF = 1;
public: public:
RVVIntrinsic(StringRef Name, StringRef Suffix, StringRef MangledName, RVVIntrinsic(StringRef Name, StringRef Suffix, StringRef MangledName,
StringRef MangledSuffix, StringRef IRName, bool HasSideEffects, StringRef MangledSuffix, StringRef IRName, bool HasSideEffects,
bool IsMask, bool HasMaskedOffOperand, bool HasVL, bool IsMask, bool HasMaskedOffOperand, bool HasVL,
bool HasNoMaskedOverloaded, bool HasAutoDef, bool HasPolicy, bool HasNoMaskedOverloaded, bool HasAutoDef,
StringRef ManualCodegen, const RVVTypes &Types, StringRef ManualCodegen, const RVVTypes &Types,
const std::vector<int64_t> &IntrinsicTypes, const std::vector<int64_t> &IntrinsicTypes,
StringRef RequiredExtension, unsigned NF); StringRef RequiredExtension, unsigned NF);
~RVVIntrinsic() = default; ~RVVIntrinsic() = default;
StringRef getName() const { return Name; } StringRef getName() const { return Name; }
StringRef getMangledName() const { return MangledName; } StringRef getMangledName() const { return MangledName; }
bool hasSideEffects() const { return HasSideEffects; } bool hasSideEffects() const { return HasSideEffects; }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; } bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; } bool hasVL() const { return HasVL; }
bool hasPolicy() const { return HasPolicy; }
bool hasNoMaskedOverloaded() const { return HasNoMaskedOverloaded; } bool hasNoMaskedOverloaded() const { return HasNoMaskedOverloaded; }
bool hasManualCodegen() const { return !ManualCodegen.empty(); } bool hasManualCodegen() const { return !ManualCodegen.empty(); }
bool hasAutoDef() const { return HasAutoDef; } bool hasAutoDef() const { return HasAutoDef; }
bool isMask() const { return IsMask; } bool isMask() const { return IsMask; }
StringRef getIRName() const { return IRName; } StringRef getIRName() const { return IRName; }
StringRef getManualCodegen() const { return ManualCodegen; } StringRef getManualCodegen() const { return ManualCodegen; }
uint8_t getRISCVExtensions() const { return RISCVExtensions; } uint8_t getRISCVExtensions() const { return RISCVExtensions; }
unsigned getNF() const { return NF; } unsigned getNF() const { return NF; }
// Return the type string for a BUILTIN() macro in Builtins.def. // Return the type string for a BUILTIN() macro in Builtins.def.
std::string getBuiltinTypeStr() const; std::string getBuiltinTypeStr() const;
// Emit the code block for switch body in EmitRISCVBuiltinExpr, it should // Emit the code block for switch body in EmitRISCVBuiltinExpr, it should
// init the RVVIntrinsic ID and IntrinsicTypes. // init the RVVIntrinsic ID and IntrinsicTypes.
void emitCodeGenSwitchBody(raw_ostream &o) const; void emitCodeGenSwitchBody(raw_ostream &o) const;
// Emit the define macors for mask intrinsics using _mt intrinsics.
void emitIntrinsicMaskMacro(raw_ostream &o) const;
// Emit the macros for mapping C/C++ intrinsic function to builtin functions. // Emit the macros for mapping C/C++ intrinsic function to builtin functions.
void emitIntrinsicMacro(raw_ostream &o) const; void emitIntrinsicMacro(raw_ostream &o) const;
// Emit the mangled function definition. // Emit the mangled function definition.
void emitMangledFuncDef(raw_ostream &o) const; void emitMangledFuncDef(raw_ostream &o) const;
}; };
class RVVEmitter { class RVVEmitter {
Show All 16 Linespublic:
/// Emit all the information needed to map builtin -> LLVM IR intrinsic. /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
void createCodeGen(raw_ostream &o); void createCodeGen(raw_ostream &o);
std::string getSuffixStr(char Type, int Log2LMUL, StringRef Prototypes); std::string getSuffixStr(char Type, int Log2LMUL, StringRef Prototypes);
private: private:
/// Create all intrinsics and add them to \p Out /// Create all intrinsics and add them to \p Out
void createRVVIntrinsics(std::vector<std::unique_ptr<RVVIntrinsic>> &Out); void createRVVIntrinsics(std::vector<std::unique_ptr<RVVIntrinsic>> &Out);
/// Create Headers and add them to \p Out
void createRVVHeaders(raw_ostream &OS);
/// Compute output and input types by applying different config (basic type /// Compute output and input types by applying different config (basic type
/// and LMUL with type transformers). It also record result of type in legal /// and LMUL with type transformers). It also record result of type in legal
/// or illegal set to avoid compute the same config again. The result maybe /// or illegal set to avoid compute the same config again. The result maybe
/// have illegal RVVType. /// have illegal RVVType.
Optional<RVVTypes> computeTypes(BasicType BT, int Log2LMUL, unsigned NF, Optional<RVVTypes> computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
ArrayRef<std::string> PrototypeSeq); ArrayRef<std::string> PrototypeSeq);
Optional<RVVTypePtr> computeType(BasicType BT, int Log2LMUL, StringRef Proto); Optional<RVVTypePtr> computeType(BasicType BT, int Log2LMUL, StringRef Proto);
▲ Show 20 Lines • Show All 509 Lines • ▼ Show 20 Lines
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// RVVIntrinsic implementation // RVVIntrinsic implementation
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix, RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
StringRef NewMangledName, StringRef MangledSuffix, StringRef NewMangledName, StringRef MangledSuffix,
StringRef IRName, bool HasSideEffects, bool IsMask, StringRef IRName, bool HasSideEffects, bool IsMask,
bool HasMaskedOffOperand, bool HasVL, bool HasMaskedOffOperand, bool HasVL, bool HasPolicy,
bool HasNoMaskedOverloaded, bool HasAutoDef, bool HasNoMaskedOverloaded, bool HasAutoDef,
StringRef ManualCodegen, const RVVTypes &OutInTypes, StringRef ManualCodegen, const RVVTypes &OutInTypes,
const std::vector<int64_t> &NewIntrinsicTypes, const std::vector<int64_t> &NewIntrinsicTypes,
StringRef RequiredExtension, unsigned NF) StringRef RequiredExtension, unsigned NF)
: IRName(IRName), HasSideEffects(HasSideEffects), IsMask(IsMask), : IRName(IRName), HasSideEffects(HasSideEffects), IsMask(IsMask),
HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL),
HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef), HasPolicy(HasPolicy), HasNoMaskedOverloaded(HasNoMaskedOverloaded),
ManualCodegen(ManualCodegen.str()), NF(NF) { HasAutoDef(HasAutoDef), ManualCodegen(ManualCodegen.str()), NF(NF) {
// Init Name and MangledName // Init Name and MangledName
Name = NewName.str(); Name = NewName.str();
if (NewMangledName.empty()) if (NewMangledName.empty())
MangledName = NewName.split("_").first.str(); MangledName = NewName.split("_").first.str();
else else
MangledName = NewMangledName.str(); MangledName = NewMangledName.str();
if (!Suffix.empty()) if (!Suffix.empty())
Name += "_" + Suffix.str(); Name += "_" + Suffix.str();
if (!MangledSuffix.empty()) if (!MangledSuffix.empty())
MangledName += "_" + MangledSuffix.str(); MangledName += "_" + MangledSuffix.str();
if (IsMask) { if (IsMask) {
Name += "_m"; Name += "_m";
if (HasPolicy)
Name += "t";
} }
// Init RISC-V extensions // Init RISC-V extensions
for (const auto &T : OutInTypes) { for (const auto &T : OutInTypes) {
if (T->isFloatVector(16) || T->isFloat(16)) if (T->isFloatVector(16) || T->isFloat(16))
RISCVExtensions |= RISCVExtension::Zfh; RISCVExtensions |= RISCVExtension::Zfh;
else if (T->isFloatVector(32) || T->isFloat(32)) else if (T->isFloatVector(32) || T->isFloat(32))
RISCVExtensions |= RISCVExtension::F; RISCVExtensions |= RISCVExtension::F;
else if (T->isFloatVector(64) || T->isFloat(64)) else if (T->isFloatVector(64) || T->isFloat(64))
Show All 36 Linesvoid RVVIntrinsic::emitCodeGenSwitchBody(raw_ostream &OS) const {
if (hasManualCodegen()) { if (hasManualCodegen()) {
OS << ManualCodegen; OS << ManualCodegen;
OS << "break;\n"; OS << "break;\n";
return; return;
} }
if (isMask()) { if (isMask()) {
if (hasVL()) { if (hasVL()) {
if (hasPolicy())
OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 2);\n";
else
OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n"; OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
} else { } else {
OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n"; OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
} }
} }
OS << " IntrinsicTypes = {"; OS << " IntrinsicTypes = {";
ListSeparator LS; ListSeparator LS;
for (const auto &Idx : IntrinsicTypes) { for (const auto &Idx : IntrinsicTypes) {
Show All 23 Linesvoid RVVIntrinsic::emitIntrinsicMacro(raw_ostream &OS) const {
if (!InputTypes.empty()) { if (!InputTypes.empty()) {
ListSeparator LS; ListSeparator LS;
for (unsigned i = 0, e = InputTypes.size(); i != e; ++i) for (unsigned i = 0, e = InputTypes.size(); i != e; ++i)
OS << LS << "(" << InputTypes[i]->getTypeStr() << ")(op" << i << ")"; OS << LS << "(" << InputTypes[i]->getTypeStr() << ")(op" << i << ")";
} }
OS << ")\n"; OS << ")\n";
} }
void RVVIntrinsic::emitIntrinsicMaskMacro(raw_ostream &OS) const {
OS << "#define " << getName().drop_back() << "(";
if (!InputTypes.empty()) {
ListSeparator LS;
for (unsigned i = 0, e = InputTypes.size() - 1; i != e; ++i)
OS << LS << "op" << i;
}
OS << ") \\\n";
OS << "__builtin_rvv_" << getName() << "(";
ListSeparator LS;
if (!InputTypes.empty()) {
for (unsigned i = 0, e = InputTypes.size() - 1; i != e; ++i)
OS << LS << "(" << InputTypes[i]->getTypeStr() << ")(op" << i << ")";
}
OS << LS << "(size_t)VE_TAIL_AGNOSTIC";
OS << ")\n";
}
void RVVIntrinsic::emitMangledFuncDef(raw_ostream &OS) const { void RVVIntrinsic::emitMangledFuncDef(raw_ostream &OS) const {
OS << "__attribute__((clang_builtin_alias("; OS << "__attribute__((clang_builtin_alias(";
OS << "__builtin_rvv_" << getName() << ")))\n"; OS << "__builtin_rvv_" << getName() << ")))\n";
OS << OutputType->getTypeStr() << " " << getMangledName() << "("; OS << OutputType->getTypeStr() << " " << getMangledName() << "(";
// Emit function arguments // Emit function arguments
if (!InputTypes.empty()) { if (!InputTypes.empty()) {
ListSeparator LS; ListSeparator LS;
for (unsigned i = 0; i < InputTypes.size(); ++i) for (unsigned i = 0; i < InputTypes.size(); ++i)
Show All 29 Linesvoid RVVEmitter::createHeader(raw_ostream &OS) {
OS << "#ifndef __riscv_vector\n"; OS << "#ifndef __riscv_vector\n";
OS << "#error \"Vector intrinsics require the vector extension.\"\n"; OS << "#error \"Vector intrinsics require the vector extension.\"\n";
OS << "#endif\n\n"; OS << "#endif\n\n";
OS << "#ifdef __cplusplus\n"; OS << "#ifdef __cplusplus\n";
OS << "extern \"C\" {\n"; OS << "extern \"C\" {\n";
OS << "#endif\n\n"; OS << "#endif\n\n";
createRVVHeaders(OS);
std::vector<std::unique_ptr<RVVIntrinsic>> Defs; std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
createRVVIntrinsics(Defs); createRVVIntrinsics(Defs);
// Print header code // Print header code
if (!HeaderCode.empty()) { if (!HeaderCode.empty()) {
OS << HeaderCode; OS << HeaderCode;
} }
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines std::stable_sort(Defs.begin(), Defs.end(),
return A->getRISCVExtensions() < B->getRISCVExtensions(); return A->getRISCVExtensions() < B->getRISCVExtensions();
}); });
// Print intrinsic functions with macro // Print intrinsic functions with macro
emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) { emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
Inst.emitIntrinsicMacro(OS); Inst.emitIntrinsicMacro(OS);
}); });
// Use _mt to implement _m intrinsics.
emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
if (Inst.isMask() && Inst.hasPolicy())
Inst.emitIntrinsicMaskMacro(OS);
});
OS << "#define __riscv_v_intrinsic_overloading 1\n"; OS << "#define __riscv_v_intrinsic_overloading 1\n";
// Print Overloaded APIs // Print Overloaded APIs
OS << "#define __rvv_overloaded static inline " OS << "#define __rvv_overloaded static inline "
"__attribute__((__always_inline__, __nodebug__, __overloadable__))\n"; "__attribute__((__always_inline__, __nodebug__, __overloadable__))\n";
emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) { emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
if (!Inst.isMask() && !Inst.hasNoMaskedOverloaded()) if (!Inst.isMask() && !Inst.hasNoMaskedOverloaded())
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines for (auto *R : RV) {
StringRef SuffixProto = R->getValueAsString("Suffix"); StringRef SuffixProto = R->getValueAsString("Suffix");
StringRef MangledName = R->getValueAsString("MangledName"); StringRef MangledName = R->getValueAsString("MangledName");
StringRef MangledSuffixProto = R->getValueAsString("MangledSuffix"); StringRef MangledSuffixProto = R->getValueAsString("MangledSuffix");
StringRef Prototypes = R->getValueAsString("Prototype"); StringRef Prototypes = R->getValueAsString("Prototype");
StringRef TypeRange = R->getValueAsString("TypeRange"); StringRef TypeRange = R->getValueAsString("TypeRange");
bool HasMask = R->getValueAsBit("HasMask"); bool HasMask = R->getValueAsBit("HasMask");
bool HasMaskedOffOperand = R->getValueAsBit("HasMaskedOffOperand"); bool HasMaskedOffOperand = R->getValueAsBit("HasMaskedOffOperand");
bool HasVL = R->getValueAsBit("HasVL"); bool HasVL = R->getValueAsBit("HasVL");
bool HasPolicy = R->getValueAsBit("HasPolicy");
bool HasNoMaskedOverloaded = R->getValueAsBit("HasNoMaskedOverloaded"); bool HasNoMaskedOverloaded = R->getValueAsBit("HasNoMaskedOverloaded");
bool HasSideEffects = R->getValueAsBit("HasSideEffects"); bool HasSideEffects = R->getValueAsBit("HasSideEffects");
std::vector<int64_t> Log2LMULList = R->getValueAsListOfInts("Log2LMUL"); std::vector<int64_t> Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
StringRef ManualCodegen = R->getValueAsString("ManualCodegen"); StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
StringRef ManualCodegenMask = R->getValueAsString("ManualCodegenMask"); StringRef ManualCodegenMask = R->getValueAsString("ManualCodegenMask");
std::vector<int64_t> IntrinsicTypes = std::vector<int64_t> IntrinsicTypes =
R->getValueAsListOfInts("IntrinsicTypes"); R->getValueAsListOfInts("IntrinsicTypes");
StringRef RequiredExtension = R->getValueAsString("RequiredExtension"); StringRef RequiredExtension = R->getValueAsString("RequiredExtension");
Show All 38 Lines if (HasMask) {
// (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1, // (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
// ...) // ...)
ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1, "m"); ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1, "m");
} else { } else {
// If HasMask, insert 'm' as first input operand. // If HasMask, insert 'm' as first input operand.
ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1, "m"); ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1, "m");
} }
} }
// If HasVL, append 'z' to last operand // If HasVL, append 'z' to the operand list.
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if (HasVL) { if (HasVL) {
ProtoSeq.push_back("z"); ProtoSeq.push_back("z");
ProtoMaskSeq.push_back("z"); ProtoMaskSeq.push_back("z");
} }
if (HasPolicy) {
ProtoMaskSeq.push_back("z");
}
// Create Intrinsics for each type and LMUL. // Create Intrinsics for each type and LMUL.
for (char I : TypeRange) { for (char I : TypeRange) {
for (int Log2LMUL : Log2LMULList) { for (int Log2LMUL : Log2LMULList) {
Optional<RVVTypes> Types = computeTypes(I, Log2LMUL, NF, ProtoSeq); Optional<RVVTypes> Types = computeTypes(I, Log2LMUL, NF, ProtoSeq);
// Ignored to create new intrinsic if there are any illegal types. // Ignored to create new intrinsic if there are any illegal types.
if (!Types.hasValue()) if (!Types.hasValue())
continue; continue;
auto SuffixStr = getSuffixStr(I, Log2LMUL, SuffixProto); auto SuffixStr = getSuffixStr(I, Log2LMUL, SuffixProto);
auto MangledSuffixStr = getSuffixStr(I, Log2LMUL, MangledSuffixProto); auto MangledSuffixStr = getSuffixStr(I, Log2LMUL, MangledSuffixProto);
// Create a non-mask intrinsic // Create a non-mask intrinsic
Out.push_back(std::make_unique<RVVIntrinsic>( Out.push_back(std::make_unique<RVVIntrinsic>(
Name, SuffixStr, MangledName, MangledSuffixStr, IRName, Name, SuffixStr, MangledName, MangledSuffixStr, IRName,
HasSideEffects, /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasSideEffects, /*IsMask=*/false, /*HasMaskedOffOperand=*/false,
HasVL, HasNoMaskedOverloaded, HasAutoDef, ManualCodegen, HasVL, HasPolicy, HasNoMaskedOverloaded, HasAutoDef, ManualCodegen,
Types.getValue(), IntrinsicTypes, RequiredExtension, NF)); Types.getValue(), IntrinsicTypes, RequiredExtension, NF));
if (HasMask) { if (HasMask) {
// Create a mask intrinsic // Create a mask intrinsic
Optional<RVVTypes> MaskTypes = Optional<RVVTypes> MaskTypes =
computeTypes(I, Log2LMUL, NF, ProtoMaskSeq); computeTypes(I, Log2LMUL, NF, ProtoMaskSeq);
Out.push_back(std::make_unique<RVVIntrinsic>( Out.push_back(std::make_unique<RVVIntrinsic>(
Name, SuffixStr, MangledName, MangledSuffixStr, IRNameMask, Name, SuffixStr, MangledName, MangledSuffixStr, IRNameMask,
HasSideEffects, /*IsMask=*/true, HasMaskedOffOperand, HasVL, HasSideEffects, /*IsMask=*/true, HasMaskedOffOperand, HasVL,
HasNoMaskedOverloaded, HasAutoDef, ManualCodegenMask, HasPolicy, HasNoMaskedOverloaded, HasAutoDef, ManualCodegenMask,
MaskTypes.getValue(), IntrinsicTypes, RequiredExtension, NF)); MaskTypes.getValue(), IntrinsicTypes, RequiredExtension, NF));
} }
} // end for Log2LMULList } // end for Log2LMULList
} // end for TypeRange } // end for TypeRange
} }
} }
void RVVEmitter::createRVVHeaders(raw_ostream &OS) {
std::vector<Record *> RVVHeaders =
Records.getAllDerivedDefinitions("RVVHeader");
for (auto *R : RVVHeaders) {
StringRef HeaderCodeStr = R->getValueAsString("HeaderCode");
OS << HeaderCodeStr.str();
}
}
Optional<RVVTypes> Optional<RVVTypes>
RVVEmitter::computeTypes(BasicType BT, int Log2LMUL, unsigned NF, RVVEmitter::computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
ArrayRef<std::string> PrototypeSeq) { ArrayRef<std::string> PrototypeSeq) {
// LMUL x NF must be less than or equal to 8. // LMUL x NF must be less than or equal to 8.
if ((Log2LMUL >= 1) && (1 << Log2LMUL) * NF > 8) if ((Log2LMUL >= 1) && (1 << Log2LMUL) * NF > 8)
return llvm::None; return llvm::None;
RVVTypes Types; RVVTypes Types;
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines