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Teach the AArch64 backend patterns to generate the EOR3 instruction.
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Authored by resistor on Aug 26 2021, 3:52 PM.

Details

Summary

Adds patterns to match the EOR3 instruction.

Diff Detail

Event Timeline

resistor created this revision.Aug 26 2021, 3:52 PM
resistor requested review of this revision.Aug 26 2021, 3:52 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 26 2021, 3:52 PM
MaskRay added inline comments.
llvm/test/CodeGen/AArch64/eor3.ll
5

CHECK-LABEL: eor3_16x8_left:

The diagnostic will be better if something goes off and eor3 v0.16b is absent.

resistor updated this revision to Diff 369006.Aug 26 2021, 4:33 PM

Use CHECK-LABEL

resistor marked an inline comment as done.Aug 26 2021, 4:33 PM

This doesn't look like it even parses correctly! Nice idea though, it sounds good to add patterns for these three way eor's. I'm surprised they weren't added when the intrinsics were added.

llvm/lib/Target/AArch64/AArch64InstrInfo.td
985

There's a comma missing here. The brackets also look off.

988

defm?

llvm/test/CodeGen/AArch64/eor3.ll
2

-mtriple=aarch64-none-eabi?

This file can use update_llc_test_checks. Preferably for run lines with and without +sha3

dmgreen added inline comments.Aug 27 2021, 5:42 AM
llvm/lib/Target/AArch64/AArch64InstrInfo.td
985

Oh xor is also commutative. You likely don't need both the patterns, it will be handled automatically by tablegen.

Having tests that check that sound good to have though.

resistor updated this revision to Diff 369143.Aug 27 2021, 10:52 AM

Update for comments.

resistor marked 3 inline comments as done.Aug 27 2021, 10:52 AM
resistor added inline comments.
llvm/lib/Target/AArch64/AArch64InstrInfo.td
985

I do have tests for the different ways to commute it already. Good call that tblgen should handle the commutation automatically.

resistor marked 2 inline comments as done.Aug 27 2021, 10:53 AM
craig.topper added inline comments.
llvm/lib/Target/AArch64/AArch64InstrInfo.td
983

I don't the AArch64 ISA, but is it possible one of the xors is a vnot. And if that is possible, is EOR3 what you want to generate or would you want XOR+NOT?

resistor added inline comments.Aug 27 2021, 2:28 PM
llvm/lib/Target/AArch64/AArch64InstrInfo.td
983

This still behaves correctly with this patch. XOR + VNOT generates EOR + MVN.

resistor marked an inline comment as done.Aug 27 2021, 2:29 PM
dmgreen added inline comments.Aug 28 2021, 6:44 AM
llvm/lib/Target/AArch64/AArch64InstrInfo.td
983

Sounds like it is worth adding some quick tests.

985

I don't believe those tests are actually commutative. %4 is always on the right hand side.

craig.topper added inline comments.Aug 28 2021, 12:42 PM
llvm/lib/Target/AArch64/AArch64InstrInfo.td
983

Looks like the ImmAllOnesV in the vnot weights as a build_vector plus plus an immediate. Because of that the vnot pattern has complexity 7 and the eor3 pattern has complexity 6. So the vnot gets priority.

resistor updated this revision to Diff 369365.Aug 29 2021, 8:33 PM

Update tests for comments.

resistor marked 2 inline comments as done.Aug 29 2021, 8:34 PM
dmgreen accepted this revision.Aug 30 2021, 4:08 AM

Thanks. LGTM.

This revision is now accepted and ready to land.Aug 30 2021, 4:08 AM
Matt added a subscriber: Matt.Aug 30 2021, 7:42 AM
This revision was landed with ongoing or failed builds.Aug 30 2021, 1:01 PM
This revision was automatically updated to reflect the committed changes.