Teach the AArch64 backend patterns to generate the EOR3 instruction.

[resistor]

Summary

Adds patterns to match the EOR3 instruction.

[MaskRay]

llvm/test/CodeGen/AArch64/eor3.ll

5

CHECK-LABEL: eor3_16x8_left:

The diagnostic will be better if something goes off and eor3 v0.16b is absent.

[resistor]

Use CHECK-LABEL

[dmgreen]

This doesn't look like it even parses correctly! Nice idea though, it sounds good to add patterns for these three way eor's. I'm surprised they weren't added when the intrinsics were added.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

976

There's a comma missing here. The brackets also look off.

979

defm?

llvm/test/CodeGen/AArch64/eor3.ll

1

-mtriple=aarch64-none-eabi?

This file can use update_llc_test_checks. Preferably for run lines with and without +sha3

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

976

Oh xor is also commutative. You likely don't need both the patterns, it will be handled automatically by tablegen.

Having tests that check that sound good to have though.

[resistor]

Update for comments.

[resistor]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

976

I do have tests for the different ways to commute it already. Good call that tblgen should handle the commutation automatically.

[craig.topper]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

974

I don't the AArch64 ISA, but is it possible one of the xors is a vnot. And if that is possible, is EOR3 what you want to generate or would you want XOR+NOT?

[resistor]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

974

This still behaves correctly with this patch. XOR + VNOT generates EOR + MVN.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

974

Sounds like it is worth adding some quick tests.

976

I don't believe those tests are actually commutative. %4 is always on the right hand side.

[craig.topper]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

974

Looks like the ImmAllOnesV in the vnot weights as a build_vector plus plus an immediate. Because of that the vnot pattern has complexity 7 and the eor3 pattern has complexity 6. So the vnot gets priority.

[resistor]

Update tests for comments.

[dmgreen]

Thanks. LGTM.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def : SHA3_pattern<SHA512H2, int_aarch64_crypto_sha512h2, v2i64>;
 def : SHA3_pattern<SHA512SU1, int_aarch64_crypto_sha512su1, v2i64>;
 
 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v16i8>;
 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v8i16>;
 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v4i32>;
 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v2i64>;
 
+multiclass EOR3_pattern<ValueType VecTy> {
+  def : Pat<(xor (xor (VecTy V128:$Vn), (VecTy V128:$Vm)), (VecTy V128:$Va)),
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
+  def : Pat<(xor (VecTy V128:$Vn) (xor (VecTy V128:$Vm), (VecTy V128:$Va)),
+        (EOR3 (VecTy V128:$Vn), (VecTy V128:$Vm), (VecTy V128:$Va))>;
+}
+def : EOR3_pattern<v16i8>;
+def : EOR3_pattern<v8i16>;
+def : EOR3_pattern<v4i32>;
+def : EOR3_pattern<v2i64>;
+
 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v16i8>;
 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v8i16>;
 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v4i32>;
 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v2i64>;
 
 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v16i8>;
 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v8i16>;
 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v4i32>;

llvm/test/CodeGen/AArch64/eor3.ll

+; RUN: llc -march=aarch64 -mattr=+sha3 < %s | FileCheck %s
+
+
+; CHECK-LABEL: eor3_16x8_left:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <16 x i8> @eor3_16x8_left(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
+  %4 = xor <16 x i8> %0, %1
+  %5 = xor <16 x i8> %2, %4
+  ret <16 x i8> %5
+}
+
+; CHECK-LABEL: eor3_16x8_right:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <16 x i8> @eor3_16x8_right(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) {
+  %4 = xor <16 x i8> %1, %2
+  %5 = xor <16 x i8> %0, %4
+  ret <16 x i8> %5
+}
+
+; CHECK-LABEL: eor3_8x16_left:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <8 x i16> @eor3_8x16_left(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) {
+  %4 = xor <8 x i16> %0, %1
+  %5 = xor <8 x i16> %2, %4
+  ret <8 x i16> %5
+}
+
+; CHECK-LABEL: eor3_8x16_right:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <8 x i16> @eor3_8x16_right(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) {
+  %4 = xor <8 x i16> %1, %2
+  %5 = xor <8 x i16> %0, %4
+  ret <8 x i16> %5
+}
+
+; CHECK-LABEL: eor3_4x32_left:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <4 x i32> @eor3_4x32_left(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) {
+  %4 = xor <4 x i32> %0, %1
+  %5 = xor <4 x i32> %2, %4
+  ret <4 x i32> %5
+}
+
+; CHECK-LABEL: eor3_4x32_right:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <4 x i32> @eor3_4x32_right(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) {
+  %4 = xor <4 x i32> %1, %2
+  %5 = xor <4 x i32> %0, %4
+  ret <4 x i32> %5
+}
+
+; CHECK-LABEL: eor3_2x64_left:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <2 x i64> @eor3_2x64_left(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
+  %4 = xor <2 x i64> %0, %1
+  %5 = xor <2 x i64> %2, %4
+  ret <2 x i64> %5
+}
+
+; CHECK-LABEL: eor3_2x64_right:
+; CHECK: eor3 v0.16b
+; CHECK: ret
+define <2 x i64> @eor3_2x64_right(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
+  %4 = xor <2 x i64> %1, %2
+  %5 = xor <2 x i64> %0, %4
+  ret <2 x i64> %5
+}
+