[RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG.

[craig.topper]

Summary

Return false from runOnFunction if nothing changed. Curiously
we already returned a bool from detectAndFoldOffset, but didn't
use it.

Fix a couple breaks after returns that I saw while auditing
detectAndFoldOffset.

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

struct RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
   bool matchLargeOffset(MachineInstr &TailAdd, Register GSReg, int64_t &Offset);
   RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) {}
 
   MachineFunctionProperties getRequiredProperties() const override {
     return MachineFunctionProperties().set(
         MachineFunctionProperties::Property::IsSSA);
   }
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
   StringRef getPassName() const override {
     return RISCV_MERGE_BASE_OFFSET_NAME;
   }
 
 private:
   MachineRegisterInfo *MRI;
   std::set<MachineInstr *> DeadInstrs;
 };
LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:"
                       << Tail);
     return false;
   case RISCV::ADDI: {
     // Offset is simply an immediate operand.
     int64_t Offset = Tail.getOperand(2).getImm();
     LLVM_DEBUG(dbgs() << "  Offset Instr: " << Tail);
     foldOffset(HiLUI, LoADDI, Tail, Offset);
     return true;
-  } break;
+  }
   case RISCV::ADD: {
     // The offset is too large to fit in the immediate field of ADDI.
     // This can be in two forms:
     // 1) LUI hi_Offset followed by:
     //    ADDI lo_offset
     //    This happens in case the offset has non zero bits in
     //    both hi 20 and lo 12 bits.
     // 2) LUI (offset20)
     //    This happens in case the lower 12 bits of the offset are zeros.
     int64_t Offset;
     if (!matchLargeOffset(Tail, DestReg, Offset))
       return false;
     foldOffset(HiLUI, LoADDI, Tail, Offset);
     return true;
-  } break;
+  }
   case RISCV::LB:
   case RISCV::LH:
   case RISCV::LW:
   case RISCV::LBU:
   case RISCV::LHU:
   case RISCV::LWU:
   case RISCV::LD:
   case RISCV::FLH:
case RISCV::FSD: {
     ImmOp.setOffset(Offset);
     Tail.addOperand(ImmOp);
     // Update the base reg in the Tail instruction to feed from LUI.
     // Output of HiLUI is only used in LoADDI, no need to use
     // MRI->replaceRegWith().
     Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
     DeadInstrs.insert(&LoADDI);
     return true;
-  } break;
+  }
   }
   return false;
 }
 
 bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {
   if (skipFunction(Fn.getFunction()))
     return false;
 
+  bool MadeChange = false;
   DeadInstrs.clear();
   MRI = &Fn.getRegInfo();
   for (MachineBasicBlock &MBB : Fn) {
     LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
     for (MachineInstr &HiLUI : MBB) {
       MachineInstr *LoADDI = nullptr;
       if (!detectLuiAddiGlobal(HiLUI, LoADDI))
         continue;
       LLVM_DEBUG(dbgs() << "  Found lowered global address with one use: "
                         << *LoADDI->getOperand(2).getGlobal() << "\n");
       // If the use count is only one, merge the offset
-      detectAndFoldOffset(HiLUI, *LoADDI);
+      MadeChange |= detectAndFoldOffset(HiLUI, *LoADDI);
     }
   }
   // Delete dead instructions.
   for (auto *MI : DeadInstrs)
     MI->eraseFromParent();
-  return true;
+  return MadeChange;
 }
 
 /// Returns an instance of the Merge Base Offset Optimization pass.
 FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() {
   return new RISCVMergeBaseOffsetOpt();
 }