[RISCV] Add new lga pseudoinstruction
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Authored by jrtc27 on Aug 2 2021, 7:43 AM.

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Reviewers

asb
luismarques
MaskRay

Summary

This mirrors lla and is always GOT-relative, allowing an explicit
request to use the GOT without having to expand the instruction. This
then means la is just defined in terms of lla and lga, based on whether
PIC is enabled.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

jrtc27 created this revision.Aug 2 2021, 7:43 AM

Herald added subscribers: vkmr, frasercrmck, evandro and 22 others. · View Herald TranscriptAug 2 2021, 7:43 AM

jrtc27 requested review of this revision.Aug 2 2021, 7:43 AM

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Proposed in https://github.com/riscv/riscv-asm-manual/pull/69

Harbormaster completed remote builds in B117447: Diff 363473.Aug 2 2021, 8:23 AM

Looks great!

llvm/test/MC/RISCV/rvi-pseudos.s
51	This test may be redundant. Having a5 with addend (users should do it, but the assembler currently accepts the form ) below is sufficient.

This revision is now accepted and ready to land.Aug 2 2021, 9:30 AM

Hi @jrtc27. Can you land this patch? :)

Herald added a project: Restricted Project. · View Herald TranscriptJun 8 2022, 7:16 AM

Herald added subscribers: sunshaoce, pcwang-thead, eopXD and 3 others. · View Herald Transcript

Rebased, including new riscv_lga ISD node to match riscv_l(l)a (though I don't understand quite why we bother with these... it seems like extra indirection for no gain?)

Harbormaster completed remote builds in B177482: Diff 447490.Jul 25 2022, 4:22 PM