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Differential D107022

[RISCV] Update test cases for D106939.
AbandonedPublic

Authored by HsiangKai on Jul 28 2021, 7:26 PM.

Details

Reviewers
frasercrmck
khchen
arcbbb
rogfer01
evandro
craig.topper

Diff Detail

Unit TestsFailed

TimeTest
70 msx64 debian > LLVM.CodeGen/RISCV::spill-fpr-scalar.ll
230 msx64 debian > LLVM.CodeGen/RISCV::srem-seteq-illegal-types.ll
240 msx64 debian > LLVM.CodeGen/RISCV::urem-seteq-illegal-types.ll
80 msx64 windows > LLVM.CodeGen/RISCV::spill-fpr-scalar.ll
380 msx64 windows > LLVM.CodeGen/RISCV::srem-seteq-illegal-types.ll
View Full Test Results (6 Failed)

Event Timeline

HsiangKai created this revision.Jul 28 2021, 7:26 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptJul 28 2021, 7:26 PM
HsiangKai requested review of this revision.Jul 28 2021, 7:26 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 28 2021, 7:26 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
HsiangKai added a parent revision: D106939: [RISCV] If the maskedoff is vundefined(), use ta,ma for vsetvli..Jul 28 2021, 7:27 PM
Harbormaster completed remote builds in B116849: Diff 362606.Jul 28 2021, 8:37 PM
HsiangKai updated this revision to Diff 362639.Jul 28 2021, 10:22 PM

Update test cases.

Herald added a subscriber: MatzeB. · View Herald TranscriptJul 28 2021, 10:22 PM
Harbormaster completed remote builds in B116874: Diff 362639.Jul 28 2021, 11:14 PM
HsiangKai updated this revision to Diff 362921.Jul 29 2021, 4:33 PM

Update test cases.

HsiangKai mentioned this in D106939: [RISCV] If the maskedoff is vundefined(), use ta,ma for vsetvli..Jul 29 2021, 4:33 PM
Harbormaster completed remote builds in B117073: Diff 362921.Jul 29 2021, 5:28 PM
frasercrmck added a comment.Aug 2 2021, 9:57 AM

I think the ret alias is tripping up this last test.

craig.topper added a comment.Aug 2 2021, 5:29 PM

This still leaves mu for vcompress and vmv.s.x. Do you plan to fix those?

llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
231

Doesn't need to be fixed in this patch, but this should be ma

HsiangKai added a comment.Aug 3 2021, 1:25 AM
In D107022#2921240, @craig.topper wrote:

This still leaves mu for vcompress and vmv.s.x. Do you plan to fix those?

vcompress and vmv.s.x are exceptions of the rule in D106939.
How about to add a new flag for masked instructions?

HsiangKai abandoned this revision.Dec 16 2021, 12:23 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. · View Herald TranscriptDec 16 2021, 12:23 AM

Large Diff

This large diff affects 673 files. Files without inline comments have been collapsed. Expand All Files

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Diff 362639

llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/combine-sats.ll

llvm/test/CodeGen/RISCV/rvv/combine-splats.ll

llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll

llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll

llvm/test/CodeGen/RISCV/rvv/load-mask.ll

llvm/test/CodeGen/RISCV/rvv/localvar.ll

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll

llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll

llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll

llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll

llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/select-fp.ll

llvm/test/CodeGen/RISCV/rvv/select-int.ll

llvm/test/CodeGen/RISCV/rvv/select-sra.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll

llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll

llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll

llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll

Show First 20 Lines • Show All 222 Lines • ▼ Show 20 Lines
} }
declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i32, i32) declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i32, i32)
define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Doesn't need to be fixed in this patch, but this should be ma

craig.topper: Doesn't need to be fixed in this patch, but this should be ma
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) %a = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, i32); declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, i32);
define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vlse64.v v25, (a0), zero
; CHECK-NEXT: vid.v v26 ; CHECK-NEXT: vid.v v26
; CHECK-NEXT: vmseq.vi v0, v26, 0 ; CHECK-NEXT: vmseq.vi v0, v26, 0
; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) %a = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %0, i64 %1, i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64>, i64, i32); declare <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64>, i64, i32);
define <vscale x 2 x i64> @intrinsic_vmv.s.x_x_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.s.x_x_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vlse64.v v26, (a0), zero
; CHECK-NEXT: vid.v v28 ; CHECK-NEXT: vid.v v28
; CHECK-NEXT: vmseq.vi v0, v28, 0 ; CHECK-NEXT: vmseq.vi v0, v28, 0
; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) %a = call <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64> %0, i64 %1, i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64>, i64, i32); declare <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64>, i64, i32);
define <vscale x 4 x i64> @intrinsic_vmv.s.x_x_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.s.x_x_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vlse64.v v28, (a0), zero
; CHECK-NEXT: vid.v v12 ; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vmseq.vi v0, v12, 0 ; CHECK-NEXT: vmseq.vi v0, v12, 0
; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) %a = call <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64> %0, i64 %1, i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64>, i64, i32); declare <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64>, i64, i32);
define <vscale x 8 x i64> @intrinsic_vmv.s.x_x_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.s.x_x_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vid.v v24 ; CHECK-NEXT: vid.v v24
; CHECK-NEXT: vmseq.vi v0, v24, 0 ; CHECK-NEXT: vmseq.vi v0, v24, 0
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) %a = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> %0, i64 %1, i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vor-vp.ll

llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll

llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll

llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll

llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll

llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll