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[AArch64][SME] Introduce feature for streaming mode
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Authored by c-rhodes on Jul 19 2021, 6:15 AM.

Details

Summary

The Scalable Matrix Extension (SME) introduces a new execution mode
called Streaming SVE mode. In streaming mode a substantial subset of the
SVE and SVE2 instruction set is available, along with new outer product,
load, store, extract and insert instructions that operate on the new
architectural register state for the matrix.

To support streaming mode this patch introduces a new subtarget feature
+streaming-sve. If enabled, the subset of SVE(2) instructions are
available. The existing behaviour for SVE(2) remains unchanged, the
subset of instructions that are legal in streaming mode are enabled if
either +sve[2] or +streaming-sve is specified. Instructions that are
illegal in streaming mode remain predicated on +sve[2].

The SME target feature has been updated to imply +streaming-sve rather
than +sve.

The following changes are made to the SVE(2) tests:

  • For instructions that are legal in streaming mode:
    • added RUN line to verify +streaming-sve enables the instruction.
    • updated diagnostic to 'instruction requires: streaming-sve or sve'.
  • For instructions that are illegal in streaming-mode:
    • added RUN line to verify +streaming-sve does not enable the instruction.

SVE(2) instructions that are legal in streaming mode have:

if !HaveSVE[2]() && !HaveSME() then UNDEFINED;

at the top of the pseudocode in the XML.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions

Diff Detail

Event Timeline

c-rhodes created this revision.Jul 19 2021, 6:15 AM
c-rhodes requested review of this revision.Jul 19 2021, 6:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 19 2021, 6:15 AM
Matt added a subscriber: Matt.Jul 19 2021, 1:24 PM
sdesmalen added inline comments.Jul 21 2021, 2:52 AM
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
618

Instead of moving these around, can you do:

let Predicates = [HasSVEOrStreamingSVE] in {
  ...
  defm SPLICE_ZPZ : sve_int_perm_splice<"splice", AArch64splice>;
}

let Predicates = [HasSVE] in {
  defm COMPACT_ZPZ : sve_int_perm_compact<"compact", int_aarch64_sve_compact>;
}

let Predicates = [HasSVEOrStreamingSVE] in {
  defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>;
  defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
  defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext>;
  ...
}

That makes the patch easier to review, and we could possibly follow this up with a separate NFC change that shuffles these around in the file for readability (although I'm not sure yet if that's necessarily what we want).

c-rhodes updated this revision to Diff 360737.Jul 22 2021, 2:21 AM

Address comments.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
618

Instead of moving these around, can you do:

let Predicates = [HasSVEOrStreamingSVE] in {
  ...
  defm SPLICE_ZPZ : sve_int_perm_splice<"splice", AArch64splice>;
}

let Predicates = [HasSVE] in {
  defm COMPACT_ZPZ : sve_int_perm_compact<"compact", int_aarch64_sve_compact>;
}

let Predicates = [HasSVEOrStreamingSVE] in {
  defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>;
  defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
  defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext>;
  ...
}

That makes the patch easier to review, and we could possibly follow this up with a separate NFC change that shuffles these around in the file for readability (although I'm not sure yet if that's necessarily what we want).

that's a better idea, done :)

This revision is now accepted and ready to land.Jul 23 2021, 6:23 AM

Some things that are missing from this patch, but which can probably be followed up in separate patches:

  • A small subset of the AdvSimd instructions can be used under Streaming SVE, so we'll need something like hasNeonOrStreamingSVE as well.
  • We'll need to change calls to Subtarget->hasSVE() in e.g. AArch64ISelLowering.cpp or AArch64TargetTransformInfo.cpp to use Subtarget->hasSVEOrStreamingSVE() where appropriate.
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
1604–1607

the BFMMLA instructions are illegal under streaming SVE mode.

2202

Patterns must be similarly guarded by HasSVE. They're not valid under HasStreamingSVE because the instructions they target otherwise don't exist.

c-rhodes added inline comments.Jul 27 2021, 8:10 AM
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
1604–1607
2202

Patterns must be similarly guarded by HasSVE. They're not valid under HasStreamingSVE because the instructions they target otherwise don't exist.

Ah good spot, I'll fix this cheers.

c-rhodes updated this revision to Diff 362321.Jul 28 2021, 3:48 AM
c-rhodes set the repository for this revision to rG LLVM Github Monorepo.
  • Update let Predicates = [HasSVE, UseExperimentalZeroingPseudos] ... { for streaming mode.
  • Fix predicates for patterns selecting instructions that are illegal in streaming mode (contiguous non-faulting / first faulting loads).
c-rhodes marked an inline comment as done.Jul 28 2021, 3:52 AM

Some things that are missing from this patch, but which can probably be followed up in separate patches:

  • A small subset of the AdvSimd instructions can be used under Streaming SVE, so we'll need something like hasNeonOrStreamingSVE as well.
  • We'll need to change calls to Subtarget->hasSVE() in e.g. AArch64ISelLowering.cpp or AArch64TargetTransformInfo.cpp to use Subtarget->hasSVEOrStreamingSVE() where appropriate.

I'll follow up with patches for those

This revision was automatically updated to reflect the committed changes.