[AMDGPU] Handle s_branch to another section.

[abidh]

Summary

Currently, if target of s_branch instruction is in another section, it will fail with the error of undefined label. Although in this case, the label is not undefined but present in another section. This patch tries to handle this issue. So while handling fixup_si_sopp_br fixup in getRelocType, if the target label is undefined we issue an error as before. If it is defined, a new relocation type R_AMDGPU_REL16 is returned.

This issue has been reported in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100181 and https://bugs.llvm.org/show_bug.cgi?id=45887. Before https://reviews.llvm.org/D79943, we used to get an crash for this scenario. The crash is fixed now but the we still get an undefined label error. Jumps to other section can arise with hold/cold splitting.

A patch to handle the relocation in lld will follow shortly.

[arsenm]

LGTM with nit

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

87

No else after return

[abidh]

Remove else after the return.

[abidh]

Rebase. One of the test file has moved in the repo so updated the patch accordingly.

llvm/docs/AMDGPUUsage.rst

``R_AMDGPU_ABS32``         Static, 6      ``word32``  S + A
                                 Dynamic
      ``R_AMDGPU_GOTPCREL``      Static  7      ``word32``  G + GOT + A - P
      ``R_AMDGPU_GOTPCREL32_LO`` Static  8      ``word32``  (G + GOT + A - P) & 0xFFFFFFFF
      ``R_AMDGPU_GOTPCREL32_HI`` Static  9      ``word32``  (G + GOT + A - P) >> 32
      ``R_AMDGPU_REL32_LO``      Static  10     ``word32``  (S + A - P) & 0xFFFFFFFF
      ``R_AMDGPU_REL32_HI``      Static  11     ``word32``  (S + A - P) >> 32
      *reserved*                         12
      ``R_AMDGPU_RELATIVE64``    Dynamic 13     ``word64``  B + A
+     ``R_AMDGPU_REL16``         Static  14     ``word16``  ((S + A - P) - 4) / 4
      ========================== ======= =====  ==========  ==============================
 
 ``R_AMDGPU_ABS32_LO`` and ``R_AMDGPU_ABS32_HI`` are only supported by
 the ``mesa3d`` OS, which does not support ``R_AMDGPU_ABS64``.
 
 There is no current OS loader support for 32-bit programs and so
 ``R_AMDGPU_ABS32`` is not used.
 

llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def

 ELF_RELOC(R_AMDGPU_REL64,          5)
 ELF_RELOC(R_AMDGPU_ABS32,          6)
 ELF_RELOC(R_AMDGPU_GOTPCREL,       7)
 ELF_RELOC(R_AMDGPU_GOTPCREL32_LO,  8)
 ELF_RELOC(R_AMDGPU_GOTPCREL32_HI,  9)
 ELF_RELOC(R_AMDGPU_REL32_LO,      10)
 ELF_RELOC(R_AMDGPU_REL32_HI,      11)
 ELF_RELOC(R_AMDGPU_RELATIVE64,    13)
+ELF_RELOC(R_AMDGPU_REL16,         14)

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
   case FK_Data_8:
     return ELF::R_AMDGPU_ABS64;
   }
 
   if (Fixup.getTargetKind() == AMDGPU::fixup_si_sopp_br) {
     const auto *SymA = Target.getSymA();
     assert(SymA);
 
-    Ctx.reportError(Fixup.getLoc(),
-                    Twine("undefined label '") + SymA->getSymbol().getName() + "'");
+    if (SymA->getSymbol().isUndefined()) {
+      Ctx.reportError(Fixup.getLoc(), Twine("undefined label '") +
+                                          SymA->getSymbol().getName() + "'");
       return ELF::R_AMDGPU_NONE;
     }
+    return ELF::R_AMDGPU_REL16;
+  }
 
   llvm_unreachable("unhandled relocation type");
 }
 
 std::unique_ptr<MCObjectTargetWriter>
 llvm::createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
                                   bool HasRelocationAddend,
                                   uint8_t ABIVersion) {
   return std::make_unique<AMDGPUELFObjectWriter>(Is64Bit, OSABI,
                                                   HasRelocationAddend,
                                                   ABIVersion);
 }

llvm/test/MC/AMDGPU/reloc.s

 // RUN: llvm-mc -filetype=obj -triple amdgcn-- -mcpu=kaveri -show-encoding %s | llvm-readobj -relocations - | FileCheck %s
 
 // CHECK: Relocations [
 // CHECK: .rel.text {
 // CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0
 // CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD1
 // CHECK: R_AMDGPU_GOTPCREL global_var0
 // CHECK: R_AMDGPU_GOTPCREL32_LO global_var1
 // CHECK: R_AMDGPU_GOTPCREL32_HI global_var2
 // CHECK: R_AMDGPU_REL32_LO global_var3
 // CHECK: R_AMDGPU_REL32_HI global_var4
+// CHECK: R_AMDGPU_REL16 .text.unlikely
 // CHECK: R_AMDGPU_ABS32 var
 // CHECK: }
 // CHECK: .rel.data {
 // CHECK: R_AMDGPU_ABS64 temp
 // CHECK: R_AMDGPU_REL64 temp
 // CHECK: }
 // CHECK: ]
 
 kernel:
   s_mov_b32 s0, SCRATCH_RSRC_DWORD0
   s_mov_b32 s1, SCRATCH_RSRC_DWORD1
   s_mov_b32 s2, global_var0@GOTPCREL
   s_mov_b32 s3, global_var1@gotpcrel32@lo
   s_mov_b32 s4, global_var2@gotpcrel32@hi
   s_mov_b32 s5, global_var3@rel32@lo
   s_mov_b32 s6, global_var4@rel32@hi
+  s_branch cold
+
+  .section .text.unlikely
+cold:
+  s_add_i32 s15, s15, 1
 
 .globl global_var0
 .globl global_var1
 .globl global_var2
 .globl global_var3
 .globl global_var4
 
 .globl SCRATCH_RSRC_DWORD0

llvm/test/tools/llvm-readobj/ELF/reloc-types-elf-amdgpu.test

 # CHECK-NEXT:   0x0 R_AMDGPU_REL64          - 0x0
 # CHECK-NEXT:   0x0 R_AMDGPU_ABS32          - 0x0
 # CHECK-NEXT:   0x0 R_AMDGPU_GOTPCREL       - 0x0
 # CHECK-NEXT:   0x0 R_AMDGPU_GOTPCREL32_LO  - 0x0
 # CHECK-NEXT:   0x0 R_AMDGPU_GOTPCREL32_HI  - 0x0
 # CHECK-NEXT:   0x0 R_AMDGPU_REL32_LO       - 0x0
 # CHECK-NEXT:   0x0 R_AMDGPU_REL32_HI       - 0x0
 # CHECK-NEXT:   0x0 R_AMDGPU_RELATIVE64     - 0x0
+# CHECK-NEXT:   0x0 R_AMDGPU_REL16          - 0x0
 # CHECK-NEXT: }
 
 !ELF
 FileHeader:
   Class:   ELFCLASS64
   Data:    ELFDATA2LSB
   Type:    ET_REL
   Machine: EM_AMDGPU
Relocations:
       - Type: R_AMDGPU_REL64
       - Type: R_AMDGPU_ABS32
       - Type: R_AMDGPU_GOTPCREL
       - Type: R_AMDGPU_GOTPCREL32_LO
       - Type: R_AMDGPU_GOTPCREL32_HI
       - Type: R_AMDGPU_REL32_LO
       - Type: R_AMDGPU_REL32_HI
       - Type: R_AMDGPU_RELATIVE64
+      - Type: R_AMDGPU_REL16