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dp (Dmitry Preobrazhensky)
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User Since
Feb 16 2017, 7:55 AM (250 w, 3 d)

Recent Activity

Mon, Nov 15

dp committed rG91f4650ebb05: [AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap* (authored by dp).
[AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap*
Mon, Nov 15, 1:49 AM
dp closed D113746: [AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap*.
Mon, Nov 15, 1:48 AM · Restricted Project

Fri, Nov 12

dp added reviewers for D113746: [AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap*: rampitec, foad.
Fri, Nov 12, 3:04 AM · Restricted Project
dp requested review of D113746: [AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap*.
Fri, Nov 12, 1:59 AM · Restricted Project

Oct 6 2021

dp accepted D111067: [AMDGPU] Support shared literals in FMAMK/FMAAK.

Looks fine to me. Maybe a little hacky, but I do not see any possibilities for improvement.

Oct 6 2021, 6:17 AM · Restricted Project

Sep 21 2021

dp committed rG3500e7d2b0f1: [AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap (authored by dp).
[AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap
Sep 21 2021, 8:05 AM
dp closed D109616: [AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap.
Sep 21 2021, 8:05 AM · Restricted Project
dp committed rGb8e7f5320825: [AMDGPU][MC][GFX10] Enabled dlc for FLAT and GLOBAL atomics (authored by dp).
[AMDGPU][MC][GFX10] Enabled dlc for FLAT and GLOBAL atomics
Sep 21 2021, 6:23 AM
dp closed D109614: [AMDGPU][MC][GFX10] Enabled dlc for FLAT and GLOBAL atomics.
Sep 21 2021, 6:23 AM · Restricted Project

Sep 13 2021

dp added a reviewer for D109616: [AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap: critson.
Sep 13 2021, 1:22 AM · Restricted Project
dp added inline comments to D109616: [AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap.
Sep 13 2021, 1:19 AM · Restricted Project

Sep 10 2021

dp requested review of D109616: [AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap.
Sep 10 2021, 10:45 AM · Restricted Project
dp requested review of D109614: [AMDGPU][MC][GFX10] Enabled dlc for FLAT and GLOBAL atomics.
Sep 10 2021, 10:36 AM · Restricted Project

Sep 3 2021

dp committed rG9e3f86e273d0: [AMDGPU][MC][NFC][DOC] Updated description of registers (authored by dp).
[AMDGPU][MC][NFC][DOC] Updated description of registers
Sep 3 2021, 3:13 AM

Aug 27 2021

dp committed rG8ea3e9d9a264: [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. (authored by dp).
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Aug 27 2021, 7:25 AM

Aug 6 2021

dp committed rG02b1c3f0529e: [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. (authored by dp).
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Aug 6 2021, 5:55 AM

Jul 23 2021

dp committed rG424fe903d4d4: [AMDGPU][MC][GFX9][NFC][DOC] Updated AMD GPU assembler syntax description. (authored by dp).
[AMDGPU][MC][GFX9][NFC][DOC] Updated AMD GPU assembler syntax description.
Jul 23 2021, 3:29 AM

Jul 16 2021

dp committed rG09c9f4dc7db2: [AMDGPU][MC] Added missing isCall/isBranch flags (authored by dp).
[AMDGPU][MC] Added missing isCall/isBranch flags
Jul 16 2021, 4:57 AM
dp closed D106072: [AMDGPU][MC] Added missing isCall/isBranch flags.
Jul 16 2021, 4:57 AM · Restricted Project

Jul 15 2021

dp updated the diff for D106072: [AMDGPU][MC] Added missing isCall/isBranch flags.

Updated to address reviewer's comments.

Jul 15 2021, 11:04 AM · Restricted Project
dp added a comment to D106072: [AMDGPU][MC] Added missing isCall/isBranch flags.

Can you just copy it from pseudo TSFlags?

Jul 15 2021, 9:59 AM · Restricted Project
dp added a comment to D106072: [AMDGPU][MC] Added missing isCall/isBranch flags.

Looks like it is not possible to query values of these flags in assembler and I'm not aware of any other tools that would allow this.
The flags are utilized by MCInstrAnalysis.

Jul 15 2021, 9:57 AM · Restricted Project
dp requested review of D106072: [AMDGPU][MC] Added missing isCall/isBranch flags.
Jul 15 2021, 8:41 AM · Restricted Project

Jun 21 2021

dp added inline comments to D103800: [AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions.
Jun 21 2021, 7:42 AM · Restricted Project

Jun 7 2021

dp accepted D103733: [AMDGPU] Allow oversize vaddr in GFX10 MIMG assembly.

LGTM

Jun 7 2021, 4:53 AM · Restricted Project
dp added inline comments to D103733: [AMDGPU] Allow oversize vaddr in GFX10 MIMG assembly.
Jun 7 2021, 3:20 AM · Restricted Project
dp added a comment to D103699: [AMDGPU] Fix MC tests for v_fmaak_f16 and v_fmamk_f16.

The tests you changed had 2 byte constants vs the 4 byte ones in the remaining f32 tests. But I don't know if that is significant.

I assumed that the tests with 2 byte literals were originally supposed to be for the f16 instrucction, and someone just forgot to change the opcodes.

Jun 7 2021, 3:08 AM · Restricted Project

Jun 4 2021

dp accepted D103699: [AMDGPU] Fix MC tests for v_fmaak_f16 and v_fmamk_f16.

LGTM

Jun 4 2021, 9:19 AM · Restricted Project
dp committed rGcd093cbb115a: [AMDGPU][MC][NFC] Fixed typos in parser (authored by dp).
[AMDGPU][MC][NFC] Fixed typos in parser
Jun 4 2021, 5:41 AM
dp closed D103680: [AMDGPU][MC][NFC] Fixed typos in parser.
Jun 4 2021, 5:41 AM · Restricted Project
dp requested review of D103680: [AMDGPU][MC][NFC] Fixed typos in parser.
Jun 4 2021, 3:43 AM · Restricted Project

May 27 2021

dp added inline comments to D103185: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes.
May 27 2021, 5:48 AM · Restricted Project

May 26 2021

dp committed rG13c6568c6e20: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes (authored by dp).
[AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes
May 26 2021, 11:32 AM
dp closed D103185: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes.
May 26 2021, 11:32 AM · Restricted Project
dp requested review of D103185: [AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes.
May 26 2021, 10:08 AM · Restricted Project

May 21 2021

dp abandoned D102837: [AMDGPU][DOC][NFC] Added links to public description of MI100 ISA.

A duplicate of D102859

May 21 2021, 5:11 AM · Restricted Project
dp accepted D102859: [NFC][AMDGPU] Add documentation for AMD Instinct MI100 accelerator.

LGTM

May 21 2021, 5:09 AM · Restricted Project

May 20 2021

dp requested review of D102837: [AMDGPU][DOC][NFC] Added links to public description of MI100 ISA.
May 20 2021, 3:55 AM · Restricted Project

May 15 2021

dp accepted D102526: [AMDGPU] Set unused dst_sel to '?' in the encoding.

LGTM

May 15 2021, 7:35 AM · Restricted Project

May 14 2021

dp committed rG434b278cde81: [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. (authored by dp).
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
May 14 2021, 6:14 AM

May 13 2021

dp accepted D102231: [AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling.

LGTM

May 13 2021, 8:07 AM · Restricted Project
dp added a comment to D102231: [AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling.

Not sure that trying to keep these as two patches was worthwhile.

May 13 2021, 8:06 AM · Restricted Project
dp added inline comments to D102231: [AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling.
May 13 2021, 4:22 AM · Restricted Project

May 11 2021

dp added inline comments to D102231: [AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling.
May 11 2021, 8:06 AM · Restricted Project
dp added a comment to D101619: [AMDGPU][AsmParser] Adjust img instruction address field if a16 present.

The patch looks identical to your previous one. Possibly an update quirk?

May 11 2021, 5:17 AM · Restricted Project

May 6 2021

dp accepted D101930: [AMDGPU] Fix 64 bit DPP validation.

LGTM. I must note that this is a badly documented feature. I found no description of DPP64 limitations in AMD spec and sp3 is of no help either.

May 6 2021, 8:09 AM · Restricted Project

May 4 2021

dp added inline comments to D101620: [AMDGPU][Disassembler] Adjust img instruction address field if a16 present.
May 4 2021, 10:38 AM · Restricted Project
dp added inline comments to D101620: [AMDGPU][Disassembler] Adjust img instruction address field if a16 present.
May 4 2021, 7:47 AM · Restricted Project
dp added inline comments to D101620: [AMDGPU][Disassembler] Adjust img instruction address field if a16 present.
May 4 2021, 7:30 AM · Restricted Project

Apr 19 2021

dp committed rGbcc29e0fcf24: [AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3 (authored by dp).
[AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3
Apr 19 2021, 3:43 AM
dp closed D100642: [AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3.
Apr 19 2021, 3:43 AM · Restricted Project

Apr 16 2021

dp updated the diff for D100642: [AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3.

Updated to silence the linter.

Apr 16 2021, 6:38 AM · Restricted Project
dp requested review of D100642: [AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3.
Apr 16 2021, 5:12 AM · Restricted Project

Apr 12 2021

dp committed rG67b39661c847: [AMDGPU][MC][NFC] Removed extra spaces (authored by dp).
[AMDGPU][MC][NFC] Removed extra spaces
Apr 12 2021, 3:33 AM
dp closed D100173: [AMDGPU][MC][NFC] Removed extra spaces.
Apr 12 2021, 3:33 AM · Restricted Project

Apr 9 2021

dp requested review of D100173: [AMDGPU][MC][NFC] Removed extra spaces.
Apr 9 2021, 3:54 AM · Restricted Project

Apr 6 2021

dp committed rG3eadcb86abd2: [AMDGPU][MC][GFX9] Corrected SMEM decoding (authored by dp).
[AMDGPU][MC][GFX9] Corrected SMEM decoding
Apr 6 2021, 4:11 AM
dp closed D99804: [AMDGPU][MC][GFX9] Corrected SMEM decoding.
Apr 6 2021, 4:11 AM · Restricted Project

Apr 2 2021

dp requested review of D99804: [AMDGPU][MC][GFX9] Corrected SMEM decoding.
Apr 2 2021, 10:37 AM · Restricted Project

Apr 1 2021

dp committed rGcd953434f2a4: [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices (authored by dp).
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
Apr 1 2021, 4:45 AM
dp closed D99413: [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices.
Apr 1 2021, 4:45 AM · Restricted Project
dp committed rG0f5ebbcc7fc3: [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant (authored by dp).
[AMDGPU][MC] Added flag to identify VOP instructions which have a single variant
Apr 1 2021, 3:53 AM
dp closed D99408: [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant.
Apr 1 2021, 3:53 AM · Restricted Project

Mar 30 2021

dp updated the diff for D99408: [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant.

Removed unnecessary code

Mar 30 2021, 10:45 AM · Restricted Project
dp added inline comments to D99408: [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant.
Mar 30 2021, 10:44 AM · Restricted Project
dp updated the summary of D99408: [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant.
Mar 30 2021, 10:00 AM · Restricted Project

Mar 26 2021

dp added a reviewer for D99413: [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices: rampitec.
Mar 26 2021, 4:59 AM · Restricted Project
dp requested review of D99413: [AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices.
Mar 26 2021, 4:58 AM · Restricted Project
dp retitled D99408: [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant from [AMDGPU] Added a flag to identify to [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant.
Mar 26 2021, 3:46 AM · Restricted Project
dp requested review of D99408: [AMDGPU][MC] Added flag to identify VOP instructions which have a single variant.
Mar 26 2021, 3:43 AM · Restricted Project

Mar 16 2021

dp committed rG596db9934b91: [AMDGPU][MC] Disabled lds_direct for GFX90a (authored by dp).
[AMDGPU][MC] Disabled lds_direct for GFX90a
Mar 16 2021, 3:53 AM
dp closed D98626: [AMDGPU][MC] Disabled lds_direct for GFX90a.
Mar 16 2021, 3:53 AM · Restricted Project

Mar 15 2021

dp updated the diff for D98626: [AMDGPU][MC] Disabled lds_direct for GFX90a.

Updated to silence the linter.

Mar 15 2021, 7:27 AM · Restricted Project
dp added a comment to D98631: AMDGPU: Fix allowing immediates for tail call pseudo..

I don't see any restriction noted that this must be a register, so just allow any SSrc_b64 like normal.

Mar 15 2021, 7:21 AM · Restricted Project
dp updated the diff for D98626: [AMDGPU][MC] Disabled lds_direct for GFX90a.

Rebased.

Mar 15 2021, 5:19 AM · Restricted Project
dp requested review of D98626: [AMDGPU][MC] Disabled lds_direct for GFX90a.
Mar 15 2021, 4:23 AM · Restricted Project

Mar 11 2021

dp added a comment to D98397: [AMDGPU] Restrict image_msaa_load to MSAA dimension types.

MC changes look fine.

Mar 11 2021, 6:02 AM · Restricted Project

Mar 9 2021

dp accepted D96469: [AMDGPU] Use single cache policy operand.

LGTM

Mar 9 2021, 11:10 AM · Restricted Project
dp added a comment to D96469: [AMDGPU] Use single cache policy operand.

MC part overall looks good with minor reservations:

  • The change breaks compatibility with existing code. The following code is no longer accepted:
Mar 9 2021, 8:28 AM · Restricted Project

Mar 2 2021

dp committed rG28f164bca724: [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P (authored by dp).
[AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P
Mar 2 2021, 2:03 AM
dp closed D97689: [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P.
Mar 2 2021, 2:02 AM · Restricted Project

Mar 1 2021

dp updated the diff for D97689: [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P.

Corrections to silence the linter

Mar 1 2021, 11:47 AM · Restricted Project
dp updated the diff for D97689: [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P.

Updated encodings in codegen tests; corrected code style as suggested by linter.

Mar 1 2021, 9:17 AM · Restricted Project
dp added a comment to D97689: [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P.

Thanks Joe. I decided to update the encodings because they were added on purpose.

Mar 1 2021, 9:11 AM · Restricted Project
dp added a comment to D97689: [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P.

I was surprised to discover that codegen tests include encodings. Is there any reason for that? Should I remove or update them?

Mar 1 2021, 8:41 AM · Restricted Project
dp requested review of D97689: [AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P.
Mar 1 2021, 7:36 AM · Restricted Project

Feb 24 2021

dp accepted D97295: [AMDGPU] Update s_sendmsg messages.

LGTM

Feb 24 2021, 4:49 AM · Restricted Project

Feb 22 2021

dp committed rG481351809284: [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3 (authored by dp).
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
Feb 22 2021, 4:01 AM
dp closed D97048: [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3.
Feb 22 2021, 4:01 AM · Restricted Project

Feb 19 2021

dp requested review of D97048: [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3.
Feb 19 2021, 7:18 AM · Restricted Project

Feb 16 2021

dp added a comment to D96469: [AMDGPU] Use single cache policy operand.

Overall looks good

Feb 16 2021, 8:29 AM · Restricted Project

Feb 12 2021

dp accepted D96543: [AMDGPU] Allow accvgpr_read/write decode with opsel.

It is a pity we have to use such hacks but I do not see how to make it cleaner.

Feb 12 2021, 6:35 AM · Restricted Project

Feb 11 2021

dp added inline comments to D96469: [AMDGPU] Use single cache policy operand.
Feb 11 2021, 3:47 AM · Restricted Project

Feb 8 2021

dp committed rG05433a8d034f: [AMDGPU][MC] Corrected error position for invalid dim modifiers (authored by dp).
[AMDGPU][MC] Corrected error position for invalid dim modifiers
Feb 8 2021, 3:33 AM
dp closed D96117: [AMDGPU][MC] Corrected error position for invalid dim modifiers.
Feb 8 2021, 3:32 AM · Restricted Project
dp committed rG168ccc8ecb65: [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands (authored by dp).
[AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands
Feb 8 2021, 3:05 AM
dp closed D96118: [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands.
Feb 8 2021, 3:05 AM · Restricted Project

Feb 5 2021

dp updated the diff for D96117: [AMDGPU][MC] Corrected error position for invalid dim modifiers.

Fixed issues found by Jay:

  • Corrected error message;
  • Refactored to avoid duplication of code.
Feb 5 2021, 9:19 AM · Restricted Project
dp requested review of D96118: [AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands.
Feb 5 2021, 4:09 AM · Restricted Project
dp requested review of D96117: [AMDGPU][MC] Corrected error position for invalid dim modifiers.
Feb 5 2021, 4:06 AM · Restricted Project