Some Code Generation optimisation for lowering bit reverse in ISel. It uses vrev32 and vrev64 to optimise the lowering of bit reverse in the cases when VT is v4i32 and v2i64.
Perhaps an assert here for VT == MVT::v4i32 || VT == MVT::v2i64.
How about these SVE checks, do we need tests for that?
Nit: /*OverrideNEON=*/true ?
And we don't need the curly brackets for this if.
then this can be an else.
Wanted add a nit about Bitreverse -> BitReverse, but perhaps we don't need it:
return DAG.getNode(AArch64ISD::NVCAST, DL, VT, DAG.getNode(ISD::BITREVERSE, DL, MVT::v16i8, REVB));
I think he meant to add /*OverrideNEON=*/, as it makes the code easier to read.
If we have the unreachable below, we probably don't need the assert as well.
As the code in each of these case blocks are very similar, is it worth having the switch just set some variables (BitReverseType and RevOpcode), and having the actual code shared below the switch?
Since this change LLVM :: Analysis/CostModel/AArch64/bitreverse.ll is failing.
In case it's not just a forgotten test (didn't fail in buildkite which is odd), you can find the config used here https://lab.llvm.org/buildbot/#/builders/43/builds/6828/steps/3/logs/stdio.