[RISCV][Clang] Add -mno-div option to disable hardware int division

[ksyx]

Summary

With option -mno-div, hardware integral division and modulus instructions in M extension will be disabled, while leaving multiply instructions enabled.

I am not sure whether there is a better way of implementing this, so please point out if there is one, thanks.

Reference: riscv-toolchain-conventions

[craig.topper]

Isn't the gcc name for this -mno-div? Should we be consistent?

clang/lib/Basic/Targets/RISCV.cpp

154

Does gcc also have this define? Why do we need this in addition to not defining __riscv_div.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

223–224

These MUL lines are affected by the disableHardwareIntDiv above. Please split mul and div handling apart.

[jrtc27]

I continue to believe this kind of thing is a bad idea (missing fsqrt for F is another one). M means mul and div, if your hardware lacks div then it's not compliant with the spec. M-mode is free to lie to S-mode and above as to what's supported by the hardware and emulate as needed, but if misa.M is 1 then div must work.

[ksyx]

In D102839#2775732, @craig.topper wrote:

Isn't the gcc name for this -mno-div? Should we be consistent?

I am not sure whether using -mno-div might bring in some confusion since from the name no-div itself it expresses a sense of excluding all hardware division instructions, both float ones and integral ones, from my personal understanding. However, as in the documentation, it only affects the integral ones and float one was controlled by another. Thus for the clearance I used this naming.

I have not much understanding about what compatibility with GCC we need to achieve but I am okay with both kinds of naming and changing this is totally ok if required.

clang/lib/Basic/Targets/RISCV.cpp

154

Ok. I will remove it.

[ksyx]

• remove redundant macro definition
• split mul and div handling in RISCVISelLowering.cpp
• rename no-idiv into no-div

[ksyx]

fix: indent

[luismarques]

clang/include/clang/Driver/Options.td

3149–3152

Remove the redundant "hardware".

BTW, is "integral" actually correct, or should it be "integer division"?

clang/lib/Basic/Targets/RISCV.h

49

DisableHardwareIntDiv -> DisableIntDiv

Also, in general it would be best for the feature to be positive rather than negative, but I'm not sure whether it makes sense to make an exception here, since the option that toggles the feature is also negative.

clang/test/Driver/riscv-no-div.c

1–17

Is not FileCheck the only way to check these do not occur?

33–35

Should we be checking the actual instructions in a Clang test?

llvm/test/CodeGen/RISCV/no-div.ll

29–31

I'm not sure it makes sense to refer to the possibility of the compilation failing. It's just that we shouldn't emit divide instructions.

34–44

@jrtc27 should we use update_llc_test_checks.py instead here?

[kito-cheng]

We have Zmmul extension in the ISA spec now, that's equivalent to -mno-div , so I suggest we should go forward to implement that extension rather than -mno-div.

https://github.com/riscv/riscv-isa-manual/pull/648

[jrtc27]

In D102839#2782557, @kito-cheng wrote:

We have Zmmul extension in the ISA spec now, that's equivalent to -mno-div , so I suggest we should go forward to implement that extension rather than -mno-div.

https://github.com/riscv/riscv-isa-manual/pull/648

Yes, if people want subsets of extensions, that's the way to do it.

[luismarques]

In D102839#2782557, @kito-cheng wrote:

We have Zmmul extension in the ISA spec now, that's equivalent to -mno-div , so I suggest we should go forward to implement that extension rather than -mno-div.
https://github.com/riscv/riscv-isa-manual/pull/648

Thanks for bringing that to our attention, Kito. I had missed that recent PR and its discussion.
If the GNU ecosystem intends to move away from -mno-div soonish then Zmmul is for sure the way to go. I don't see enough benefit for LLVM to add a stop-gap compatibility option.

[ksyx]

So it seems the better way to do this would definitely by adding a subextension as the spec had changed. But I'd like also to ask how will GCC deal with this option, and should we make this option an alias to turn off M extension and turn on ZMMul extension?

[luismarques]

In D102839#2783636, @ksyx wrote:

So it seems the better way to do this would definitely by adding a subextension as the spec had changed. But I'd like also to ask how will GCC deal with this option, and should we make this option an alias to turn off M extension and turn on ZMMul extension?

Regarding "turn off M extension", see Krste's comment in the PR:

I think -mno-div is OK as a compiler option, but it's meaning is for the compiler not to generate divide instructions, not to indicate what the ISA is. So for example, -mno-div should not set ELF flags in binary to indicate ISA doesn't have divide - it should simply not generate divide instructions.

[ksyx]

Implemented Zmmul subextension, and let no-div to be using this subextension instead of M itself.

[ksyx]

In D102839#2784197, @luismarques wrote:

In D102839#2783636, @ksyx wrote:

So it seems the better way to do this would definitely by adding a subextension as the spec had changed. But I'd like also to ask how will GCC deal with this option, and should we make this option an alias to turn off M extension and turn on ZMMul extension?

Regarding "turn off M extension", see Krste's comment in the PR:

I think -mno-div is OK as a compiler option, but it's meaning is for the compiler not to generate divide instructions, not to indicate what the ISA is. So for example, -mno-div should not set ELF flags in binary to indicate ISA doesn't have divide - it should simply not generate divide instructions.

Thanks for mentioning that! Now, I changed the effect of no-div option into choosing a proper extension and implemented the Zmmul subextension. Is this solution acceptable or are there anything need further changes?

[luismarques]

In D102839#2784275, @ksyx wrote:

Thanks for mentioning that! Now, I changed the effect of no-div option into choosing a proper extension and implemented the Zmmul subextension. Is this solution acceptable or are there anything need further changes?

It seems like the community is quickly converging on just using the ISA string with Zmmul, and not using no-div. While being compatible with the GNU tools is nice, if they are planning on dropping support for no-div soonish then we probably shouldn't add support for it. IMO, Zmmul should be a separate patch and presumably (at the moment) be gated by -menable-experimental-extensions.

[kito-cheng]

Personally I prefer to deprecate -mno-div soon, but based on the rule for RISC-V GNU toolchain, it need to wait Zmmul extension frozen.
My plan is deprecate the -mno-div and emit warning to tell user should use Zmmul instead once it frozen.

[asb]

In D102839#2784585, @kito-cheng wrote:

Personally I prefer to deprecate -mno-div soon, but based on the rule for RISC-V GNU toolchain, it need to wait Zmmul extension frozen.
My plan is deprecate the -mno-div and emit warning to tell user should use Zmmul instead once it frozen.

Thanks for clarifying Kito. In that case, I think having clang support -mno-div in order to match the GNU toolchain makes sense, and we can later follow GCC in deprecating it if they do. Given how long it can take to ratify extensions, I'm wary of making assumptions about when zmmul may be ratified.

[ksyx]

In D102839#2784297, @luismarques wrote:

In D102839#2784275, @ksyx wrote:

Thanks for mentioning that! Now, I changed the effect of no-div option into choosing a proper extension and implemented the Zmmul subextension. Is this solution acceptable or are there anything need further changes?

It seems like the community is quickly converging on just using the ISA string with Zmmul, and not using no-div. While being compatible with the GNU tools is nice, if they are planning on dropping support for no-div soonish then we probably shouldn't add support for it. IMO, Zmmul should be a separate patch and presumably (at the moment) be gated by -menable-experimental-extensions.

Thanks for the news and I think having experimental-zmmul a separate patch is a good idea. But which implementation of no-div is better, the one that chooses extension between M and zmmul or the one that simply being an attribute like Diff 3, or are there any other suggestions?

[ksyx]

split Zmmul implementation and -mno-div implementation

clang/include/clang/Driver/Options.td

def mno_relax : Flag<["-"], "mno-relax">, Group<m_Group>,
   HelpText<"Disable linker relaxation">;
 def msmall_data_limit_EQ : Joined<["-"], "msmall-data-limit=">, Group<m_Group>,
   Alias<G>,
   HelpText<"Put global and static data smaller than the limit into a special section">;
 def msave_restore : Flag<["-"], "msave-restore">, Group<m_riscv_Features_Group>,
   HelpText<"Enable using library calls for save and restore">;
 def mno_save_restore : Flag<["-"], "mno-save-restore">, Group<m_riscv_Features_Group>,
   HelpText<"Disable using library calls for save and restore">;
+def mno_div : Flag<["-"], "mno-div">, Group<m_riscv_Features_Group>,
+  HelpText<"Disable hardware integral division instructions in M extension">;
+def mdiv : Flag<["-"], "mdiv">, Group<m_riscv_Features_Group>,
+  HelpText<"Enable hardware integral division instructions in M extension">;
 def mcmodel_EQ_medlow : Flag<["-"], "mcmodel=medlow">, Group<m_riscv_Features_Group>,
   Flags<[CC1Option]>, Alias<mcmodel_EQ>, AliasArgs<["small"]>,
   HelpText<"Equivalent to -mcmodel=small, compatible with RISC-V gcc.">;
 def mcmodel_EQ_medany : Flag<["-"], "mcmodel=medany">, Group<m_riscv_Features_Group>,
   Flags<[CC1Option]>, Alias<mcmodel_EQ>, AliasArgs<["medium"]>,
   HelpText<"Equivalent to -mcmodel=medium, compatible with RISC-V gcc.">;
 def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group<m_Group>,
   HelpText<"Enable use of experimental RISC-V extensions.">;

clang/lib/Basic/Targets/RISCV.h

protected:
   bool HasZbp = false;
   bool HasZbproposedc = false;
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
+  bool DisableHardwareIntDiv = false;
 
   static const Builtin::Info BuiltinInfo[];
 
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     LongDoubleWidth = 128;
     LongDoubleAlign = 128;

clang/lib/Basic/Targets/RISCV.cpp

if (ABIName == "ilp32e")
     Builder.defineMacro("__riscv_abi_rve");
 
   Builder.defineMacro("__riscv_arch_test");
   Builder.defineMacro("__riscv_i", "2000000");
 
   if (HasM) {
     Builder.defineMacro("__riscv_m", "2000000");
     Builder.defineMacro("__riscv_mul");
+    if (!DisableHardwareIntDiv) {
       Builder.defineMacro("__riscv_div");
       Builder.defineMacro("__riscv_muldiv");
     }
+  }
 
   if (HasA) {
     Builder.defineMacro("__riscv_a", "2000000");
     Builder.defineMacro("__riscv_atomic");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
     if (Is64Bit)
       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
   }
 
return llvm::StringSwitch<bool>(Feature)
       .Case("experimental-zbp", HasZbp)
       .Case("experimental-zbproposedc", HasZbproposedc)
       .Case("experimental-zbr", HasZbr)
       .Case("experimental-zbs", HasZbs)
       .Case("experimental-zbt", HasZbt)
       .Case("experimental-zfh", HasZfh)
       .Case("experimental-zvamo", HasZvamo)
       .Case("experimental-zvlsseg", HasZvlsseg)
+      .Case("no-div", DisableHardwareIntDiv)
       .Default(false);
 }
 
 /// Perform initialization based on the user configured set of features.
 bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
                                            DiagnosticsEngine &Diags) {
   for (const auto &Feature : Features) {
     if (Feature == "+m")
for (const auto &Feature : Features) {
     else if (Feature == "+experimental-zbt")
       HasZbt = true;
     else if (Feature == "+experimental-zfh")
       HasZfh = true;
     else if (Feature == "+experimental-zvamo")
       HasZvamo = true;
     else if (Feature == "+experimental-zvlsseg")
       HasZvlsseg = true;
+    else if (Feature == "+no-div")
+      DisableHardwareIntDiv = true;
   }
 
   return true;
 }
 
 bool RISCV32TargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name),
                                    /*Is64Bit=*/false);

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore, false))
     Features.push_back("+save-restore");
   else
     Features.push_back("-save-restore");
 
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(Args, Features, options::OPT_m_riscv_Features_Group);
+  for (auto &Feature : Features)
+    if (Feature == "-div") {
+      Feature = "+no-div";
+    } else if (Feature == "+div") {
+      Feature = "-no-div";
+    }
 }
 
 StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
   assert((Triple.getArch() == llvm::Triple::riscv32 ||
           Triple.getArch() == llvm::Triple::riscv64) &&
          "Unexpected triple");
 
   // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not

clang/test/Driver/riscv-no-div.c

+// RUN: %clang -target riscv32-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-NOERROR %s
+
+// RUN: %clang -target riscv64-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-NOERROR %s
+
+// RUN: %clang -target riscv32-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-DIV %s
+
+// RUN: %clang -target riscv64-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-DIV %s
+
+// RUN: %clang -target riscv32-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-REM %s
+
+// RUN: %clang -target riscv64-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-REM %s
+
+// RUN: %clang -target riscv32-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | FileCheck -check-prefix=CHECK-MUL %s
+
+// RUN: %clang -target riscv64-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | FileCheck -check-prefix=CHECK-MUL %s
+
+// RUN: %clang -target riscv32-unknown-elf %s -S -o - 2>&1 \
+// RUN:   | FileCheck -check-prefixes=CHECK-MUL,CHECK-DIV,CHECK-REM %s
+
+// RUN: %clang -target riscv64-unknown-elf %s -S -o - 2>&1 \
+// RUN:   | FileCheck -check-prefixes=CHECK-MUL,CHECK-DIV,CHECK-REM %s
+
+int foo(int x, int y) {
+  // CHECK-NOERROR: is not a recognized feature for this target
+  // CHECK-DIV: div{{w?}} a{{[0-9]}}, a{{[0-9]}}, a{{[0-9]}}
+  // CHECK-REM: rem{{w?}} a{{[0-9]}}, a{{[0-9]}}, a{{[0-9]}}
+  // CHECK-MUL: mul{{w?}} a{{[0-9]}}, a{{[0-9]}}, a{{[0-9]}}
+  return (x/y)*(x%y);
+}

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureStdExtM
     : SubtargetFeature<"m", "HasStdExtM", "true",
                        "'M' (Integer Multiplication and Division)">;
 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
                            AssemblerPredicate<(all_of FeatureStdExtM),
                            "'M' (Integer Multiplication and Division)">;
 
+def FeatureNoIntDiv : SubtargetFeature<"no-div", "DisableHardwareIntDiv", "true",
+                                       "Disable hardware integral division"
+                                       "instructions from M Extension.">;
+def HasIntDiv : Predicate<"!Subtarget->disableHardwareIntDiv()">,
+                          AssemblerPredicate<(all_of (not FeatureNoIntDiv)),
+                          "Hardware integral division not disabled">;
+
 def FeatureStdExtA
     : SubtargetFeature<"a", "HasStdExtA", "true",
                        "'A' (Atomic Instructions)">;
 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
                            AssemblerPredicate<(all_of FeatureStdExtA),
                            "'A' (Atomic Instructions)">;
 
 def FeatureStdExtF

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit()) {
     setOperationAction(ISD::UADDSAT, MVT::i32, Custom);
     setOperationAction(ISD::USUBSAT, MVT::i32, Custom);
   }
 
   if (!Subtarget.hasStdExtM()) {
     setOperationAction(ISD::MUL, XLenVT, Expand);
     setOperationAction(ISD::MULHS, XLenVT, Expand);
     setOperationAction(ISD::MULHU, XLenVT, Expand);
+  } else {
+    if (Subtarget.is64Bit()) {
+      setOperationAction(ISD::MUL, MVT::i32, Custom);
+      setOperationAction(ISD::MUL, MVT::i128, Custom);
+    } else {
+      setOperationAction(ISD::MUL, MVT::i64, Custom);
+    }
+  }
+
+  if (!Subtarget.hasStdExtM() || Subtarget.disableHardwareIntDiv()) {
     setOperationAction(ISD::SDIV, XLenVT, Expand);
     setOperationAction(ISD::UDIV, XLenVT, Expand);
     setOperationAction(ISD::SREM, XLenVT, Expand);
     setOperationAction(ISD::UREM, XLenVT, Expand);
   } else {
     if (Subtarget.is64Bit()) {
-      setOperationAction(ISD::MUL, MVT::i32, Custom);
-      setOperationAction(ISD::MUL, MVT::i128, Custom);
-
       setOperationAction(ISD::SDIV, MVT::i8, Custom);
       setOperationAction(ISD::UDIV, MVT::i8, Custom);
       setOperationAction(ISD::UREM, MVT::i8, Custom);
       setOperationAction(ISD::SDIV, MVT::i16, Custom);
       setOperationAction(ISD::UDIV, MVT::i16, Custom);
       setOperationAction(ISD::UREM, MVT::i16, Custom);
       setOperationAction(ISD::SDIV, MVT::i32, Custom);
       setOperationAction(ISD::UDIV, MVT::i32, Custom);
       setOperationAction(ISD::UREM, MVT::i32, Custom);
-    } else {
-      setOperationAction(ISD::MUL, MVT::i64, Custom);
     }
   }
 
   setOperationAction(ISD::SDIVREM, XLenVT, Expand);
   setOperationAction(ISD::UDIVREM, XLenVT, Expand);
   setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand);
   setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand);
 

llvm/lib/Target/RISCV/RISCVInstrInfoM.td

 def MUL     : ALU_rr<0b0000001, 0b000, "mul">,
               Sched<[WriteIMul, ReadIMul, ReadIMul]>;
 def MULH    : ALU_rr<0b0000001, 0b001, "mulh">,
               Sched<[WriteIMul, ReadIMul, ReadIMul]>;
 def MULHSU  : ALU_rr<0b0000001, 0b010, "mulhsu">,
               Sched<[WriteIMul, ReadIMul, ReadIMul]>;
 def MULHU   : ALU_rr<0b0000001, 0b011, "mulhu">,
               Sched<[WriteIMul, ReadIMul, ReadIMul]>;
+} // Predicates = [HasStdExtM]
+
+let Predicates = [HasStdExtM, HasIntDiv] in {
 def DIV     : ALU_rr<0b0000001, 0b100, "div">,
               Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
 def DIVU    : ALU_rr<0b0000001, 0b101, "divu">,
               Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
 def REM     : ALU_rr<0b0000001, 0b110, "rem">,
               Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
 def REMU    : ALU_rr<0b0000001, 0b111, "remu">,
               Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
-} // Predicates = [HasStdExtM]
+} // Predicates = [HasStdExtM, HasIntDiv]
 
 let Predicates = [HasStdExtM, IsRV64] in {
 def MULW    : ALUW_rr<0b0000001, 0b000, "mulw">,
               Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
+} // Predicates = [HasStdExtM, IsRV64]
+
+let Predicates = [HasStdExtM, IsRV64, HasIntDiv] in {
 def DIVW    : ALUW_rr<0b0000001, 0b100, "divw">,
               Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
 def DIVUW   : ALUW_rr<0b0000001, 0b101, "divuw">,
               Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
 def REMW    : ALUW_rr<0b0000001, 0b110, "remw">,
               Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
 def REMUW   : ALUW_rr<0b0000001, 0b111, "remuw">,
               Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
-} // Predicates = [HasStdExtM, IsRV64]
+} // Predicates = [HasStdExtM, IsRV64, HasIntDiv]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtM] in {
 def : PatGprGpr<mul, MUL>;
 def : PatGprGpr<mulhs, MULH>;
 def : PatGprGpr<mulhu, MULHU>;
 def : PatGprGpr<riscv_mulhsu, MULHSU>;
+} // Predicates = [HasStdExtM]
+
+let Predicates = [HasStdExtM, HasIntDiv] in {
 def : PatGprGpr<sdiv, DIV>;
 def : PatGprGpr<udiv, DIVU>;
 def : PatGprGpr<srem, REM>;
 def : PatGprGpr<urem, REMU>;
-} // Predicates = [HasStdExtM]
+} // Predicates = [HasStdExtM, HasIntDiv]
 
 let Predicates = [HasStdExtM, IsRV64] in {
 def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
           (MULW GPR:$rs1, GPR:$rs2)>;
+} // Predicates = [HasStdExtM, IsRV64]
 
+let Predicates = [HasStdExtM, IsRV64, HasIntDiv] in {
 def : PatGprGpr<riscv_divw, DIVW>;
 def : PatGprGpr<riscv_divuw, DIVUW>;
 def : PatGprGpr<riscv_remuw, REMUW>;
 
 // Handle the specific cases where using DIVU/REMU would be correct and result
 // in fewer instructions than emitting DIVUW/REMUW then zero-extending the
 // result.
 def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
                             (assertzexti32 GPR:$rs2)), 0xffffffff),
           (DIVU GPR:$rs1, GPR:$rs2)>;
 def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
                             (assertzexti32 GPR:$rs2)), 0xffffffff),
           (REMU GPR:$rs1, GPR:$rs2)>;
 
 // Although the sexti32 operands may not have originated from an i32 srem,
 // this pattern is safe as it is impossible for two sign extended inputs to
 // produce a result where res[63:32]=0 and res[31]=1.
 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
           (REMW GPR:$rs1, GPR:$rs2)>;
-} // Predicates = [HasStdExtM, IsRV64]
+} // Predicates = [HasStdExtM, IsRV64, HasIntDiv]
 
 let Predicates = [HasStdExtM, IsRV64, NotHasStdExtZba] in {
 // Special case for calculating the full 64-bit product of a 32x32 unsigned
 // multiply where the inputs aren't known to be zero extended. We can shift the
 // inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
 // zeroing the upper 32 bits.
 // TODO: If one of the operands is zero extended and the other isn't, we might
 // still be better off shifting both left by 32.

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
+  bool DisableHardwareIntDiv = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   BitVector UserReservedRegister;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
public:
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
+  bool disableHardwareIntDiv() const { return DisableHardwareIntDiv; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
   bool isRegisterReservedByUser(Register i) const {
     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[i];
   }
 

llvm/test/CodeGen/RISCV/no-div.ll

+; RUN: llc -mtriple=riscv32 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-DIV %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-DIV %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-REM %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-REM %s
+
+; RUN: llc -mtriple=riscv32 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-UDIV %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-UDIV %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-UREM %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | not FileCheck -check-prefix=CHECK-UREM %s
+
+; RUN: llc -mtriple=riscv32 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | FileCheck -check-prefix=CHECK-MUL %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+no-div -verify-machineinstrs < %s \
+; RUN:  | FileCheck -check-prefix=CHECK-MUL %s
+
+; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
+; RUN:  | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
+; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
+; RUN:  | FileCheck -check-prefixes=CHECK-MUL,CHECK-UDIV,CHECK-DIV,CHECK-UREM,CHECK-REM %s
+
+; This test makes sure even when both M extension no-div option enabled,
+; the compile would not fail. Instead, it will use a fallback solution like
+; calling builtin library functions.
+
+define i32 @foo(i32 %a, i32 %b) {
+; CHECK-UDIV: divu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
+  %1 = udiv i32 %a, %b
+; CHECK-DIV: div{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
+  %2 = sdiv i32 %a, %1
+; CHECK-MUL: mul{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
+  %3 = mul i32 %b, %2
+; CHECK-UREM: remu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
+  %4 = urem i32 %3, %b
+; CHECK-REM: rem {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
+  %5 = srem i32 %4, %a
+  ret i32 %5
+}

llvm/test/MC/RISCV/rv32m-no-div-div.s

+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+m,+no-div -riscv-no-aliases 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: 5:1: error: instruction requires the following: Hardware integral division not disabled
+div s0, s0, s0
+
+# CHECK-ERROR: 8:1: error: instruction requires the following: Hardware integral division not disabled
+divu gp, a0, a1
+
+# CHECK-ERROR: 11:1: error: instruction requires the following: Hardware integral division not disabled
+rem s2, s2, s8
+
+# CHECK-ERROR: 14:1: error: instruction requires the following: Hardware integral division not disabled
+remu x18, x18, x24

llvm/test/MC/RISCV/rv32m-no-div-mul.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+m,+no-div -riscv-no-aliases 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST %s
+
+# CHECK-INST: mul a4, ra, s0
+mul a4, ra, s0
+
+# CHECK-INST: mulh ra, zero, zero
+mulh x1, x0, x0
+
+# CHECK-INST: mulhsu t0, t2, t1
+mulhsu t0, t2, t1
+
+# CHECK-INST: mulhu a5, a4, a3
+mulhu a5, a4, a3

llvm/test/MC/RISCV/rv64m-no-div-div.s

+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+m,+no-div -riscv-no-aliases 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: 5:1: error: instruction requires the following: Hardware integral division not disabled
+divw tp, t0, t1
+
+# CHECK-ERROR: 8:1: error: instruction requires the following: Hardware integral division not disabled
+divuw t2, s0, s2
+
+# CHECK-ERROR: 11:1: error: instruction requires the following: Hardware integral division not disabled
+remw a0, a1, a2
+
+# CHECK-ERROR: 14:1: error: instruction requires the following: Hardware integral division not disabled
+remuw a3, a4, a5

llvm/test/MC/RISCV/rv64m-no-div-mul.s

+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m,+no-div -riscv-no-aliases 2>&1 \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST %s
+
+# CHECK-INST: mulw ra, sp, gp
+mulw ra, sp, gp