This is an archive of the discontinued LLVM Phabricator instance.

Paths

Table of Contentst

-
clang/
-
lib/CodeGen/
-
CodeGen/
1/2
CodeGenModule.cpp
-
test/OpenMP/
-
OpenMP/
-
cancel_codegen.cpp
-
cancellation_point_codegen.cpp
-
distribute_codegen.cpp
-
distribute_parallel_for_codegen.cpp
-
distribute_parallel_for_reduction_task_codegen.cpp
-
distribute_parallel_for_simd_codegen.cpp
-
distribute_simd_codegen.cpp
-
for_reduction_codegen_UDR.cpp
-
for_reduction_task_codegen.cpp
-
master_taskloop_in_reduction_codegen.cpp
-
master_taskloop_simd_in_reduction_codegen.cpp
-
nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
-
ordered_codegen.cpp
-
parallel_for_codegen.cpp
-
parallel_for_reduction_task_codegen.cpp
-
parallel_master_reduction_task_codegen.cpp
-
parallel_master_taskloop_codegen.cpp
-
parallel_master_taskloop_lastprivate_codegen.cpp
-
parallel_master_taskloop_simd_codegen.cpp
-
parallel_master_taskloop_simd_lastprivate_codegen.cpp
-
parallel_reduction_task_codegen.cpp
-
parallel_sections_reduction_task_codegen.cpp
-
sections_reduction_task_codegen.cpp
-
target_parallel_codegen.cpp
-
target_parallel_for_codegen.cpp
-
target_parallel_for_reduction_task_codegen.cpp
-
target_parallel_for_simd_codegen.cpp
-
target_parallel_reduction_task_codegen.cpp
-
target_teams_codegen.cpp
-
target_teams_distribute_codegen.cpp
-
target_teams_distribute_dist_schedule_codegen.cpp
-
target_teams_distribute_parallel_for_order_codegen.cpp
-
target_teams_distribute_parallel_for_reduction_task_codegen.cpp
-
target_teams_distribute_parallel_for_schedule_codegen.cpp
-
target_teams_distribute_parallel_for_simd_if_codegen.cpp
-
target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
-
target_teams_distribute_simd_codegen.cpp
-
target_teams_distribute_simd_dist_schedule_codegen.cpp
-
task_codegen.cpp
-
task_if_codegen.cpp
-
task_in_reduction_codegen.cpp
-
taskloop_in_reduction_codegen.cpp
-
taskloop_simd_in_reduction_codegen.cpp
-
teams_distribute_dist_schedule_codegen.cpp
-
teams_distribute_parallel_for_reduction_task_codegen.cpp
-
teams_distribute_parallel_for_schedule_codegen.cpp
-
teams_distribute_parallel_for_simd_schedule_codegen.cpp
-
teams_distribute_simd_codegen.cpp
-
teams_distribute_simd_dist_schedule_codegen.cpp

Differential D102361

[OpenMP] Add Module metadata for OpenMP compilation
ClosedPublic

Authored by jhuber6 on May 12 2021, 1:12 PM.

Download Raw Diff

Details

Reviewers

jdoerfert

Commits

rG9ce02ea8c941: [OpenMP] Add Module metadata for OpenMP compilation

Summary

This patch adds a module level metadata flag indicating that the module
was compiled with the -fopenmp flag. This will make it easier for
passes like OpenMPOpt to determine if it should be run.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

jhuber6 created this revision.May 12 2021, 1:12 PM

Herald added subscribers: guansong, yaxunl. · View Herald TranscriptMay 12 2021, 1:12 PM

jhuber6 requested review of this revision.May 12 2021, 1:12 PM

Herald added a project: Restricted Project. · View Herald TranscriptMay 12 2021, 1:12 PM

Herald added subscribers: cfe-commits, sstefan1. · View Herald Transcript

Harbormaster completed remote builds in B104122: Diff 344927.May 12 2021, 3:03 PM

tests missing.

jhuber6 added a child revision: D102423: [OpenMP] Change OpenMPOpt to check openmp metadata.May 13 2021, 10:42 AM

Addings tests and a module flag for openmp target devices.

Harbormaster completed remote builds in B110879: Diff 354324.Jun 24 2021, 12:54 PM

This revision is now accepted and ready to land.Jun 24 2021, 2:42 PM

jdoerfert added inline comments.Jun 24 2021, 2:43 PM

clang/lib/CodeGen/CodeGenModule.cpp
709	Why do we need `OpenMPRuntime` in the conditional?

jhuber6 added inline comments.Jun 24 2021, 2:45 PM

clang/lib/CodeGen/CodeGenModule.cpp
709	Probably don't explicitly need it, I'll remove it.

Removing runtime check.

Harbormaster completed remote builds in B110906: Diff 354368.Jun 24 2021, 4:14 PM

This revision was landed with ongoing or failed builds.Jun 25 2021, 1:35 PM

Closed by commit rG9ce02ea8c941: [OpenMP] Add Module metadata for OpenMP compilation (authored by jhuber6). · Explain Why

This revision was automatically updated to reflect the committed changes.

jhuber6 added a commit: rG9ce02ea8c941: [OpenMP] Add Module metadata for OpenMP compilation.

Revision Contents

Path

Size

clang/

lib/

CodeGen/

CodeGenModule.cpp

7 lines

test/

OpenMP/

cancel_codegen.cpp

232 lines

cancellation_point_codegen.cpp

124 lines

distribute_codegen.cpp

625 lines

distribute_parallel_for_codegen.cpp

849 lines

distribute_parallel_for_reduction_task_codegen.cpp

69 lines

distribute_parallel_for_simd_codegen.cpp

4936 lines

distribute_simd_codegen.cpp

1776 lines

for_reduction_codegen_UDR.cpp

24 lines

for_reduction_task_codegen.cpp

69 lines

master_taskloop_in_reduction_codegen.cpp

121 lines

master_taskloop_simd_in_reduction_codegen.cpp

140 lines

nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp

2376 lines

ordered_codegen.cpp

184 lines

parallel_for_codegen.cpp

2197 lines

parallel_for_reduction_task_codegen.cpp

69 lines

parallel_master_reduction_task_codegen.cpp

69 lines

parallel_master_taskloop_codegen.cpp

648 lines

parallel_master_taskloop_lastprivate_codegen.cpp

523 lines

parallel_master_taskloop_simd_codegen.cpp

1188 lines

parallel_master_taskloop_simd_lastprivate_codegen.cpp

590 lines

parallel_reduction_task_codegen.cpp

69 lines

parallel_sections_reduction_task_codegen.cpp

69 lines

sections_reduction_task_codegen.cpp

69 lines

target_parallel_codegen.cpp

225 lines

target_parallel_for_codegen.cpp

561 lines

target_parallel_for_reduction_task_codegen.cpp

69 lines

target_parallel_for_simd_codegen.cpp

2960 lines

target_parallel_reduction_task_codegen.cpp

69 lines

target_teams_codegen.cpp

369 lines

target_teams_distribute_codegen.cpp

1041 lines

target_teams_distribute_dist_schedule_codegen.cpp

217 lines

target_teams_distribute_parallel_for_order_codegen.cpp

29 lines

target_teams_distribute_parallel_for_reduction_task_codegen.cpp

69 lines

target_teams_distribute_parallel_for_schedule_codegen.cpp

865 lines

target_teams_distribute_parallel_for_simd_if_codegen.cpp

2352 lines

target_teams_distribute_parallel_for_simd_schedule_codegen.cpp

4960 lines

target_teams_distribute_simd_codegen.cpp

3256 lines

target_teams_distribute_simd_dist_schedule_codegen.cpp

648 lines

task_codegen.cpp

1497 lines

task_if_codegen.cpp

969 lines

task_in_reduction_codegen.cpp

113 lines

taskloop_in_reduction_codegen.cpp

121 lines

taskloop_simd_in_reduction_codegen.cpp

140 lines

teams_distribute_dist_schedule_codegen.cpp

217 lines

teams_distribute_parallel_for_reduction_task_codegen.cpp

69 lines

teams_distribute_parallel_for_schedule_codegen.cpp

865 lines

teams_distribute_parallel_for_simd_schedule_codegen.cpp

4720 lines

teams_distribute_simd_codegen.cpp

616 lines

teams_distribute_simd_dist_schedule_codegen.cpp

648 lines

Diff 354592

clang/lib/CodeGen/CodeGenModule.cpp

Show First 20 Lines • Show All 695 Lines • ▼ Show 20 Lines	if (LangOpts.CUDAIsDevice && getTriple().isNVPTX()) {
getModule().addModuleFlag(llvm::Module::Override, "nvvm-reflect-ftz",		getModule().addModuleFlag(llvm::Module::Override, "nvvm-reflect-ftz",
CodeGenOpts.FP32DenormalMode.Output !=		CodeGenOpts.FP32DenormalMode.Output !=
llvm::DenormalMode::IEEE);		llvm::DenormalMode::IEEE);
}		}

if (LangOpts.EHAsynch)		if (LangOpts.EHAsynch)
getModule().addModuleFlag(llvm::Module::Warning, "eh-asynch", 1);		getModule().addModuleFlag(llvm::Module::Warning, "eh-asynch", 1);

		// Indicate whether this Module was compiled with -fopenmp
		if (getLangOpts().OpenMP && !getLangOpts().OpenMPSimd)
		getModule().addModuleFlag(llvm::Module::Max, "openmp", LangOpts.OpenMP);
		if (getLangOpts().OpenMPIsDevice)
		getModule().addModuleFlag(llvm::Module::Max, "openmp-device",
		LangOpts.OpenMP);
		jdoerfertUnsubmitted Not Done Reply Inline Actions Why do we need `OpenMPRuntime` in the conditional? jdoerfert: Why do we need `OpenMPRuntime` in the conditional?
		jhuber6AuthorUnsubmitted Done Reply Inline Actions Probably don't explicitly need it, I'll remove it. jhuber6: Probably don't explicitly need it, I'll remove it.

// Emit OpenCL specific module metadata: OpenCL/SPIR version.		// Emit OpenCL specific module metadata: OpenCL/SPIR version.
if (LangOpts.OpenCL) {		if (LangOpts.OpenCL) {
EmitOpenCLMetadata();		EmitOpenCLMetadata();
// Emit SPIR version.		// Emit SPIR version.
if (getTriple().isSPIR()) {		if (getTriple().isSPIR()) {
// SPIR v2.0 s2.12 - The SPIR version used by the module is stored in the		// SPIR v2.0 s2.12 - The SPIR version used by the module is stored in the
// opencl.spir.version named metadata.		// opencl.spir.version named metadata.
// C++ is backwards compatible with OpenCL v2.0.		// C++ is backwards compatible with OpenCL v2.0.
▲ Show 20 Lines • Show All 5,718 Lines • Show Last 20 Lines

clang/test/OpenMP/cancel_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]			// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK1: .cancel.exit.i:			// CHECK1: .cancel.exit.i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
	// CHECK1: .cancel.continue.i:			// CHECK1: .cancel.continue.i:
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK1: .omp_outlined..1.exit:			// CHECK1: .omp_outlined..1.exit:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]			// CHECK2-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK2: .cancel.exit.i:			// CHECK2: .cancel.exit.i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
	// CHECK2: .cancel.continue.i:			// CHECK2: .cancel.continue.i:
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK2: .omp_outlined..1.exit:			// CHECK2: .omp_outlined..1.exit:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 588 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]
	// CHECK3-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]			// CHECK3-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK3: .cancel.exit.i:			// CHECK3: .cancel.exit.i:
	// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]
	// CHECK3: .cancel.continue.i:			// CHECK3: .cancel.continue.i:
	// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
	// CHECK3: .omp_outlined..exit:			// CHECK3: .omp_outlined..exit:
	// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 588 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]
	// CHECK4-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]			// CHECK4-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK4: .cancel.exit.i:			// CHECK4: .cancel.exit.i:
	// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]
	// CHECK4: .cancel.continue.i:			// CHECK4: .cancel.continue.i:
	// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
	// CHECK4: .omp_outlined..exit:			// CHECK4: .omp_outlined..exit:
	// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK7-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK7-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK7-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK7-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK7-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK7-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK7-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK7-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK7-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK7-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK7-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK7-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK7-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK7-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK7-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK7-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK7-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK7-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK7-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK7-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK7-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK7-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]			// CHECK7-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]
	// CHECK7-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK7-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK7-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK7-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK7: .cancel.exit.i:			// CHECK7: .cancel.exit.i:
	// CHECK7-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK7-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]			// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
	// CHECK7: .cancel.continue.i:			// CHECK7: .cancel.continue.i:
	// CHECK7-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK7-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK7: .omp_outlined..1.exit:			// CHECK7: .omp_outlined..1.exit:
	// CHECK7-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK7-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK7-NEXT: ret i32 0			// CHECK7-NEXT: ret i32 0
	//			//
	//			//
	// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {			// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
	// CHECK7-NEXT: entry:			// CHECK7-NEXT: entry:
	// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK8-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK8-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK8-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK8-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK8-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK8-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK8-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK8-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK8-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK8-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK8-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK8-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK8-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK8-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK8-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK8-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK8-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK8-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK8-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK8-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK8-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK8-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK8-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK8-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK8-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK8-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK8-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK8-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK8-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK8-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]			// CHECK8-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]
	// CHECK8-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK8-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK8-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK8-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK8: .cancel.exit.i:			// CHECK8: .cancel.exit.i:
	// CHECK8-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK8-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]			// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
	// CHECK8: .cancel.continue.i:			// CHECK8: .cancel.continue.i:
	// CHECK8-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK8-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK8-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK8: .omp_outlined..1.exit:			// CHECK8: .omp_outlined..1.exit:
	// CHECK8-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK8-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK8-NEXT: ret i32 0			// CHECK8-NEXT: ret i32 0
	//			//
	//			//
	// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK8-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {			// CHECK8-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
	// CHECK8-NEXT: entry:			// CHECK8-NEXT: entry:
	// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK8-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK8-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 588 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK9-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK9-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK9-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK9-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK9-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK9-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK9-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK9-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK9-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK9-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK9-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK9-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK9-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK9-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK9-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK9-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK9-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK9-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK9-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK9-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK9-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK9-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK9-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK9-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK9-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK9-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]			// CHECK9-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]
	// CHECK9-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]			// CHECK9-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK9: .cancel.exit.i:			// CHECK9: .cancel.exit.i:
	// CHECK9-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK9-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]			// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]
	// CHECK9: .cancel.continue.i:			// CHECK9: .cancel.continue.i:
	// CHECK9-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK9-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]			// CHECK9-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
	// CHECK9: .omp_outlined..exit:			// CHECK9: .omp_outlined..exit:
	// CHECK9-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK9-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK9-NEXT: ret i32 0			// CHECK9-NEXT: ret i32 0
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
	// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {			// CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 588 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK10-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK10-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK10-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK10-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK10-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK10-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK10-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK10-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK10-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK10-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK10-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK10-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK10-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK10-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK10-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK10-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK10-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK10-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK10-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK10-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK10-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK10-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK10-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK10-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK10-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK10-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]			// CHECK10-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB12:[0-9]+]]) #[[ATTR2:[0-9]+]]
	// CHECK10-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]			// CHECK10-NEXT: [[TMP11:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i32 4) #[[ATTR2]]
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK10: .cancel.exit.i:			// CHECK10: .cancel.exit.i:
	// CHECK10-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK10-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]			// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__EXIT:%.*]]
	// CHECK10: .cancel.continue.i:			// CHECK10: .cancel.continue.i:
	// CHECK10-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK10-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]			// CHECK10-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
	// CHECK10: .omp_outlined..exit:			// CHECK10: .omp_outlined..exit:
	// CHECK10-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK10-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK10-NEXT: ret i32 0			// CHECK10-NEXT: ret i32 0
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
	// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {			// CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 282 Lines • Show Last 20 Lines

clang/test/OpenMP/cancellation_point_codegen.cpp

	Show First 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]			// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK1: .cancel.exit.i:			// CHECK1: .cancel.exit.i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
	// CHECK1: .cancel.continue.i:			// CHECK1: .cancel.continue.i:
	// CHECK1-NEXT: [[TMP14:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]			// CHECK1-NEXT: [[TMP14:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT1_I:%.]], label [[DOTCANCEL_CONTINUE2_I:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT1_I:%.]], label [[DOTCANCEL_CONTINUE2_I:%.]]
	// CHECK1: .cancel.exit1.i:			// CHECK1: .cancel.exit1.i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK1: .cancel.continue2.i:			// CHECK1: .cancel.continue2.i:
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK1: .omp_outlined..1.exit:			// CHECK1: .omp_outlined..1.exit:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..3			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..3
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.1 noalias [[TMP1:%.*]]) #[[ATTR4]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.1 noalias [[TMP1:%.*]]) #[[ATTR4]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.]] = alloca i32, align 8
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]			// CHECK1-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK1: .cancel.exit.i:			// CHECK1: .cancel.exit.i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !24
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT:%.*]]
	// CHECK1: .cancel.continue.i:			// CHECK1: .cancel.continue.i:
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !24
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT]]
	// CHECK1: .omp_outlined..2.exit:			// CHECK1: .omp_outlined..2.exit:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !23			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !24
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 536 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META4:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]			// CHECK2-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2:[0-9]+]]
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK2: .cancel.exit.i:			// CHECK2: .cancel.exit.i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
	// CHECK2: .cancel.continue.i:			// CHECK2: .cancel.continue.i:
	// CHECK2-NEXT: [[TMP14:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]			// CHECK2-NEXT: [[TMP14:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT1_I:%.]], label [[DOTCANCEL_CONTINUE2_I:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTCANCEL_EXIT1_I:%.]], label [[DOTCANCEL_CONTINUE2_I:%.]]
	// CHECK2: .cancel.exit1.i:			// CHECK2: .cancel.exit1.i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK2: .cancel.continue2.i:			// CHECK2: .cancel.continue2.i:
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK2: .omp_outlined..1.exit:			// CHECK2: .omp_outlined..1.exit:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !13			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !14
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..3			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..3
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.1 noalias [[TMP1:%.*]]) #[[ATTR4]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.1 noalias [[TMP1:%.*]]) #[[ATTR4]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.]] = alloca i32, align 8
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK2-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]			// CHECK2-NEXT: [[TMP12:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP11]], i32 4) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK2: .cancel.exit.i:			// CHECK2: .cancel.exit.i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !24
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT:%.*]]
	// CHECK2: .cancel.continue.i:			// CHECK2: .cancel.continue.i:
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !24
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__2_EXIT]]
	// CHECK2: .omp_outlined..2.exit:			// CHECK2: .omp_outlined..2.exit:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !23			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !24
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 245 Lines • Show Last 20 Lines

clang/test/OpenMP/distribute_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 590 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9			// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9			// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9			// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK1-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK1-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9			// CHECK1-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 488 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9			// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9			// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9			// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK2-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK2-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9			// CHECK2-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 480 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK3-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK3-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK3-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 480 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK4-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK4-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK4-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK4-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 488 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9			// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9			// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9			// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK5-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9			// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 488 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9			// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9			// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9			// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK6-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK6-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK6-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK6-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9			// CHECK6-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK6-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK6-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 480 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK7-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK7-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK7-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK7-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK7-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK7-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK7-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK7-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK7-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK7-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 480 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK8-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK8-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK8-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK8-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK8-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK8-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK8-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK8-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK8-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK8-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK8-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK8-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK8-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK8-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK8-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK8-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK8-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK8-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 296 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9			// CHECK17-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !11
	// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK17-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9			// CHECK17-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !11
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK17-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK17-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK17-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK17-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9			// CHECK17-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !11
	// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK17-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK17-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK17-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK17-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9			// CHECK17-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !11
	// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK17-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK17-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9			// CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK17-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 289 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9			// CHECK18-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !11
	// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK18-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9			// CHECK18-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !11
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK18-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK18-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK18-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK18-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9			// CHECK18-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !11
	// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK18-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK18-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK18-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK18-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9			// CHECK18-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !11
	// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK18-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK18-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !9			// CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK18-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 281 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK19-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK19-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK19-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK19-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK19-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK19-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK19-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK19-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10			// CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK19-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 281 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK20-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK20-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK20-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK20-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK20-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK20-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK20-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK20-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !10			// CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK20-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]			// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
	// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4			// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_parallel_for_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 2,241 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64			// CHECK1-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]			// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]
	// CHECK1-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK1-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64			// CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]			// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]
	// CHECK1-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !11			// CHECK1-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double [[TMP1]], double* [[TMP29]], align 8, !llvm.access.group !11			// CHECK1-NEXT: store double [[TMP1]], double* [[TMP29]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: store i32* [[I4]], i32** [[TMP30]], align 8, !llvm.access.group !11			// CHECK1-NEXT: store i32* [[I4]], i32** [[TMP30]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store double [[TMP2]], double* [[TMP31]], align 8, !llvm.access.group !11			// CHECK1-NEXT: store double [[TMP2]], double* [[TMP31]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store double [[TMP3]], double* [[TMP32]], align 8, !llvm.access.group !11			// CHECK1-NEXT: store double [[TMP3]], double* [[TMP32]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !11			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP33]], 1			// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP33]], 1
	// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: br label [[OMP_PRECOND_END]]			// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK1: omp.precond.end:			// CHECK1: omp.precond.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64			// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]			// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]
	// CHECK1-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK1-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !14			// CHECK1-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64			// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]			// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]
	// CHECK1-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !14			// CHECK1-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0
	// CHECK1-NEXT: store double [[TMP1]], double* [[TMP30]], align 8, !llvm.access.group !14			// CHECK1-NEXT: store double [[TMP1]], double* [[TMP30]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1			// CHECK1-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1
	// CHECK1-NEXT: store i32* [[I6]], i32** [[TMP31]], align 8, !llvm.access.group !14			// CHECK1-NEXT: store i32* [[I6]], i32** [[TMP31]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2			// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2
	// CHECK1-NEXT: store double [[TMP2]], double* [[TMP32]], align 8, !llvm.access.group !14			// CHECK1-NEXT: store double [[TMP2]], double* [[TMP32]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3			// CHECK1-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3
	// CHECK1-NEXT: store double [[TMP3]], double* [[TMP33]], align 8, !llvm.access.group !14			// CHECK1-NEXT: store double [[TMP3]], double* [[TMP33]], align 8, !llvm.access.group !15
	// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !14			// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], 1			// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], 1
	// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: br label [[OMP_PRECOND_END]]			// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK1: omp.precond.end:			// CHECK1: omp.precond.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	▲ Show 20 Lines • Show All 1,481 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64			// CHECK2-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]			// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]
	// CHECK2-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK2-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK2-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64			// CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]			// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]
	// CHECK2-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !11			// CHECK2-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double [[TMP1]], double* [[TMP29]], align 8, !llvm.access.group !11			// CHECK2-NEXT: store double [[TMP1]], double* [[TMP29]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: store i32* [[I4]], i32** [[TMP30]], align 8, !llvm.access.group !11			// CHECK2-NEXT: store i32* [[I4]], i32** [[TMP30]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store double [[TMP2]], double* [[TMP31]], align 8, !llvm.access.group !11			// CHECK2-NEXT: store double [[TMP2]], double* [[TMP31]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store double [[TMP3]], double* [[TMP32]], align 8, !llvm.access.group !11			// CHECK2-NEXT: store double [[TMP3]], double* [[TMP32]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !11			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP33]], 1			// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP33]], 1
	// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: br label [[OMP_PRECOND_END]]			// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK2: omp.precond.end:			// CHECK2: omp.precond.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64			// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]			// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]
	// CHECK2-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK2-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !14			// CHECK2-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64			// CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]			// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]
	// CHECK2-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !14			// CHECK2-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0
	// CHECK2-NEXT: store double [[TMP1]], double* [[TMP30]], align 8, !llvm.access.group !14			// CHECK2-NEXT: store double [[TMP1]], double* [[TMP30]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1			// CHECK2-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1
	// CHECK2-NEXT: store i32* [[I6]], i32** [[TMP31]], align 8, !llvm.access.group !14			// CHECK2-NEXT: store i32* [[I6]], i32** [[TMP31]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2			// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2
	// CHECK2-NEXT: store double [[TMP2]], double* [[TMP32]], align 8, !llvm.access.group !14			// CHECK2-NEXT: store double [[TMP2]], double* [[TMP32]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3			// CHECK2-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3
	// CHECK2-NEXT: store double [[TMP3]], double* [[TMP33]], align 8, !llvm.access.group !14			// CHECK2-NEXT: store double [[TMP3]], double* [[TMP33]], align 8, !llvm.access.group !15
	// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !14			// CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 8 dereferenceable(32) [[REF_TMP]]), !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], 1			// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP34]], 1
	// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: br label [[OMP_PRECOND_END]]			// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK2: omp.precond.end:			// CHECK2: omp.precond.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	▲ Show 20 Lines • Show All 1,429 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK3-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]
	// CHECK3-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]			// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]
	// CHECK3-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK3-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK3-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]			// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]
	// CHECK3-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double [[TMP1]], double* [[TMP29]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store double [[TMP1]], double* [[TMP29]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: store i32* [[I3]], i32** [[TMP30]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store i32* [[I3]], i32** [[TMP30]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store double [[TMP2]], double* [[TMP31]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store double [[TMP2]], double* [[TMP31]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store double [[TMP3]], double* [[TMP32]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store double [[TMP3]], double* [[TMP32]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !12			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: br label [[OMP_PRECOND_END]]			// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK3: omp.precond.end:			// CHECK3: omp.precond.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]
	// CHECK3-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]			// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]
	// CHECK3-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK3-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK3-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]			// CHECK3-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]
	// CHECK3-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0			// CHECK3-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0
	// CHECK3-NEXT: store double [[TMP1]], double* [[TMP30]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store double [[TMP1]], double* [[TMP30]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1			// CHECK3-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1
	// CHECK3-NEXT: store i32* [[I4]], i32** [[TMP31]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32* [[I4]], i32** [[TMP31]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2			// CHECK3-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2
	// CHECK3-NEXT: store double [[TMP2]], double* [[TMP32]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store double [[TMP2]], double* [[TMP32]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3			// CHECK3-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3
	// CHECK3-NEXT: store double [[TMP3]], double* [[TMP33]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store double [[TMP3]], double* [[TMP33]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !15			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !16
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP34]], 1			// CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP34]], 1
	// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: br label [[OMP_PRECOND_END]]			// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK3: omp.precond.end:			// CHECK3: omp.precond.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	▲ Show 20 Lines • Show All 1,429 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK4-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]
	// CHECK4-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]			// CHECK4-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]
	// CHECK4-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK4-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK4-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]			// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]
	// CHECK4-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP29:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double [[TMP1]], double* [[TMP29]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store double [[TMP1]], double* [[TMP29]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: store i32* [[I3]], i32** [[TMP30]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store i32* [[I3]], i32** [[TMP30]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store double [[TMP2]], double* [[TMP31]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store double [[TMP2]], double* [[TMP31]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_5]], %class.anon.5 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store double [[TMP3]], double* [[TMP32]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store double [[TMP3]], double* [[TMP32]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !12			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE4_clEv"(%class.anon.5* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: br label [[OMP_PRECOND_END]]			// CHECK4-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK4: omp.precond.end:			// CHECK4: omp.precond.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]
	// CHECK4-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]			// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]
	// CHECK4-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK4-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK4-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]			// CHECK4-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]
	// CHECK4-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0			// CHECK4-NEXT: [[TMP30:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 0
	// CHECK4-NEXT: store double [[TMP1]], double* [[TMP30]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store double [[TMP1]], double* [[TMP30]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1			// CHECK4-NEXT: [[TMP31:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 1
	// CHECK4-NEXT: store i32* [[I4]], i32** [[TMP31]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32* [[I4]], i32** [[TMP31]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2			// CHECK4-NEXT: [[TMP32:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 2
	// CHECK4-NEXT: store double [[TMP2]], double* [[TMP32]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store double [[TMP2]], double* [[TMP32]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3			// CHECK4-NEXT: [[TMP33:%.]] = getelementptr inbounds [[CLASS_ANON_6]], %class.anon.6 [[REF_TMP]], i32 0, i32 3
	// CHECK4-NEXT: store double [[TMP3]], double* [[TMP33]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store double [[TMP3]], double* [[TMP33]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !15			// CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE5_clEv"(%class.anon.6* nonnull align 4 dereferenceable(16) [[REF_TMP]]), !llvm.access.group !16
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP34]], 1			// CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP34]], 1
	// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: br label [[OMP_PRECOND_END]]			// CHECK4-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK4: omp.precond.end:			// CHECK4: omp.precond.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	▲ Show 20 Lines • Show All 1,920 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK9-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !18			// CHECK9-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !19
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]
	// CHECK9-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !18			// CHECK9-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !19
	// CHECK9-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !18			// CHECK9-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !19
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64			// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK9-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]			// CHECK9-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]
	// CHECK9-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !18			// CHECK9-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !19
	// CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK9-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !18			// CHECK9-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !19
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64			// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]			// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]
	// CHECK9-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !18			// CHECK9-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !19
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK9: omp.dispatch.end:			// CHECK9: omp.dispatch.end:
	// CHECK9-NEXT: br label [[OMP_PRECOND_END]]			// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK9: omp.precond.end:			// CHECK9: omp.precond.end:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK9-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !21			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !21			// CHECK9-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !21			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]
	// CHECK9-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !21			// CHECK9-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !21			// CHECK9-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !21			// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64			// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]			// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]
	// CHECK9-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !21			// CHECK9-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !22
	// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK9-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !21			// CHECK9-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !21			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64			// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]			// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]
	// CHECK9-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !21			// CHECK9-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !22
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK9: omp.dispatch.end:			// CHECK9: omp.dispatch.end:
	// CHECK9-NEXT: br label [[OMP_PRECOND_END]]			// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK9: omp.precond.end:			// CHECK9: omp.precond.end:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	▲ Show 20 Lines • Show All 1,925 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK9-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !24			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !24			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i64 [[IDXPROM]]
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !24			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64			// CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK9-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i64 [[IDXPROM6]]			// CHECK9-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i64 [[IDXPROM6]]
	// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX7]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX7]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]			// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]
	// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !24			// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64			// CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i64 [[IDXPROM9]]			// CHECK9-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i64 [[IDXPROM9]]
	// CHECK9-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !24			// CHECK9-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK9-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK9: omp.dispatch.end:			// CHECK9: omp.dispatch.end:
	// CHECK9-NEXT: br label [[OMP_PRECOND_END]]			// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK9: omp.precond.end:			// CHECK9: omp.precond.end:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK9-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK9-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !27			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i64 [[IDXPROM]]
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !27			// CHECK9-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64			// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i64 [[IDXPROM8]]			// CHECK9-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i64 [[IDXPROM8]]
	// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX9]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX9]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]			// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !27			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64			// CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i64 [[IDXPROM11]]			// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i64 [[IDXPROM11]]
	// CHECK9-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !27			// CHECK9-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK9: omp.dispatch.end:			// CHECK9: omp.dispatch.end:
	// CHECK9-NEXT: br label [[OMP_PRECOND_END]]			// CHECK9-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK9: omp.precond.end:			// CHECK9: omp.precond.end:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	▲ Show 20 Lines • Show All 1,920 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK10-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !18			// CHECK10-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !19
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i64 [[IDXPROM]]
	// CHECK10-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !18			// CHECK10-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !19
	// CHECK10-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !18			// CHECK10-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !19
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64			// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK10-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]			// CHECK10-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP24]], i64 [[IDXPROM6]]
	// CHECK10-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !18			// CHECK10-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX7]], align 8, !llvm.access.group !19
	// CHECK10-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK10-NEXT: [[ADD8:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK10-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !18			// CHECK10-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !19
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64			// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]			// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds double, double [[TMP27]], i64 [[IDXPROM9]]
	// CHECK10-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !18			// CHECK10-NEXT: store double [[ADD8]], double* [[ARRAYIDX10]], align 8, !llvm.access.group !19
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK10: omp.dispatch.end:			// CHECK10: omp.dispatch.end:
	// CHECK10-NEXT: br label [[OMP_PRECOND_END]]			// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK10: omp.precond.end:			// CHECK10: omp.precond.end:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK10-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !21			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !21			// CHECK10-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 8, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !21			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i64 [[IDXPROM]]
	// CHECK10-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !21			// CHECK10-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 8, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !21			// CHECK10-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 8, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !21			// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64			// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]			// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds double, double [[TMP25]], i64 [[IDXPROM8]]
	// CHECK10-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !21			// CHECK10-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX9]], align 8, !llvm.access.group !22
	// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK10-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !21			// CHECK10-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 8, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !21			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64			// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]			// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds double, double [[TMP28]], i64 [[IDXPROM11]]
	// CHECK10-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !21			// CHECK10-NEXT: store double [[ADD10]], double* [[ARRAYIDX12]], align 8, !llvm.access.group !22
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK10: omp.dispatch.end:			// CHECK10: omp.dispatch.end:
	// CHECK10-NEXT: br label [[OMP_PRECOND_END]]			// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK10: omp.precond.end:			// CHECK10: omp.precond.end:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	▲ Show 20 Lines • Show All 1,925 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK10-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !24			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !24			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i64 [[IDXPROM]]
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !24			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64			// CHECK10-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP25]] to i64
	// CHECK10-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i64 [[IDXPROM6]]			// CHECK10-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i64 [[IDXPROM6]]
	// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX7]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX7]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]			// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]
	// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !24			// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64			// CHECK10-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64
	// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i64 [[IDXPROM9]]			// CHECK10-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i64 [[IDXPROM9]]
	// CHECK10-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !24			// CHECK10-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX10]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK10-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK10-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK10: omp.dispatch.end:			// CHECK10: omp.dispatch.end:
	// CHECK10-NEXT: br label [[OMP_PRECOND_END]]			// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK10: omp.precond.end:			// CHECK10: omp.precond.end:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK10-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK10-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !27			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !27			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 8, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i64 [[IDXPROM]]
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !27			// CHECK10-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 8, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP26:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64			// CHECK10-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP26]] to i64
	// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i64 [[IDXPROM8]]			// CHECK10-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i64 [[IDXPROM8]]
	// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX9]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX9]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]			// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !27			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 8, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64			// CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP29]] to i64
	// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i64 [[IDXPROM11]]			// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i64 [[IDXPROM11]]
	// CHECK10-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !27			// CHECK10-NEXT: store i32 [[ADD10]], i32* [[ARRAYIDX12]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK10: omp.dispatch.end:			// CHECK10: omp.dispatch.end:
	// CHECK10-NEXT: br label [[OMP_PRECOND_END]]			// CHECK10-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK10: omp.precond.end:			// CHECK10: omp.precond.end:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	▲ Show 20 Lines • Show All 1,858 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK11-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !19			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]
	// CHECK11-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]			// CHECK11-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]
	// CHECK11-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK11-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK11-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]			// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]
	// CHECK11-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !19			// CHECK11-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK11: omp.dispatch.end:			// CHECK11: omp.dispatch.end:
	// CHECK11-NEXT: br label [[OMP_PRECOND_END]]			// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK11: omp.precond.end:			// CHECK11: omp.precond.end:
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK11-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !22			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]
	// CHECK11-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]			// CHECK11-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]
	// CHECK11-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK11-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK11-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]			// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]
	// CHECK11-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !22			// CHECK11-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK11: omp.dispatch.end:			// CHECK11: omp.dispatch.end:
	// CHECK11-NEXT: br label [[OMP_PRECOND_END]]			// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK11: omp.precond.end:			// CHECK11: omp.precond.end:
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	▲ Show 20 Lines • Show All 1,863 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK11-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK11-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !25			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i32 [[TMP22]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i32 [[TMP22]]
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i32 [[TMP25]]			// CHECK11-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i32 [[TMP25]]
	// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX5]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX5]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i32 [[TMP28]]			// CHECK11-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i32 [[TMP28]]
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !25			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK11: omp.dispatch.end:			// CHECK11: omp.dispatch.end:
	// CHECK11-NEXT: br label [[OMP_PRECOND_END]]			// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK11: omp.precond.end:			// CHECK11: omp.precond.end:
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK11-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK11-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i32 [[TMP23]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i32 [[TMP23]]
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i32 [[TMP26]]			// CHECK11-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i32 [[TMP26]]
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX6]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX6]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]			// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i32 [[TMP29]]			// CHECK11-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i32 [[TMP29]]
	// CHECK11-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !28			// CHECK11-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK11: omp.dispatch.end:			// CHECK11: omp.dispatch.end:
	// CHECK11-NEXT: br label [[OMP_PRECOND_END]]			// CHECK11-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK11: omp.precond.end:			// CHECK11: omp.precond.end:
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	▲ Show 20 Lines • Show All 1,858 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK12-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !19			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP21:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP21]], i32 [[TMP22]]
	// CHECK12-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP23:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP24:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]			// CHECK12-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds double, double [[TMP24]], i32 [[TMP25]]
	// CHECK12-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP26:%.]] = load double, double [[ARRAYIDX5]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]			// CHECK12-NEXT: [[ADD6:%.*]] = fadd double [[TMP23]], [[TMP26]]
	// CHECK12-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP27:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]			// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds double, double [[TMP27]], i32 [[TMP28]]
	// CHECK12-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !19			// CHECK12-NEXT: store double [[ADD6]], double* [[ARRAYIDX7]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK12: omp.dispatch.end:			// CHECK12: omp.dispatch.end:
	// CHECK12-NEXT: br label [[OMP_PRECOND_END]]			// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK12: omp.precond.end:			// CHECK12: omp.precond.end:
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK12-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !22			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP22:%.]] = load double, double** [[TMP2]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds double, double [[TMP22]], i32 [[TMP23]]
	// CHECK12-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP25:%.]] = load double, double** [[TMP3]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]			// CHECK12-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds double, double [[TMP25]], i32 [[TMP26]]
	// CHECK12-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP27:%.]] = load double, double [[ARRAYIDX6]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]			// CHECK12-NEXT: [[ADD7:%.*]] = fadd double [[TMP24]], [[TMP27]]
	// CHECK12-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP28:%.]] = load double, double** [[TMP1]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]			// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds double, double [[TMP28]], i32 [[TMP29]]
	// CHECK12-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !22			// CHECK12-NEXT: store double [[ADD7]], double* [[ARRAYIDX8]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK12: omp.dispatch.end:			// CHECK12: omp.dispatch.end:
	// CHECK12-NEXT: br label [[OMP_PRECOND_END]]			// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK12: omp.precond.end:			// CHECK12: omp.precond.end:
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	▲ Show 20 Lines • Show All 1,863 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK12-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK12-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !25			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i32 [[TMP22]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP21]], i32 [[TMP22]]
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i32 [[TMP25]]			// CHECK12-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds i32, i32 [[TMP24]], i32 [[TMP25]]
	// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX5]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[ARRAYIDX5]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP23]], [[TMP26]]
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i32 [[TMP28]]			// CHECK12-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds i32, i32 [[TMP27]], i32 [[TMP28]]
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !25			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX7]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP29]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK12: omp.dispatch.end:			// CHECK12: omp.dispatch.end:
	// CHECK12-NEXT: br label [[OMP_PRECOND_END]]			// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK12: omp.precond.end:			// CHECK12: omp.precond.end:
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK12-NEXT: [[TMP17:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP16]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0			// CHECK12-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP17]], 0
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !28			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP2]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i32 [[TMP23]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP22]], i32 [[TMP23]]
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[ARRAYIDX]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP3]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP26:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i32 [[TMP26]]			// CHECK12-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds i32, i32 [[TMP25]], i32 [[TMP26]]
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX6]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[ARRAYIDX6]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]			// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], [[TMP27]]
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP1]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i32 [[TMP29]]			// CHECK12-NEXT: [[ARRAYIDX8:%.]] = getelementptr inbounds i32, i32 [[TMP28]], i32 [[TMP29]]
	// CHECK12-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !28			// CHECK12-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX8]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP30]], 1
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK12: omp.dispatch.end:			// CHECK12: omp.dispatch.end:
	// CHECK12-NEXT: br label [[OMP_PRECOND_END]]			// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK12: omp.precond.end:			// CHECK12: omp.precond.end:
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//

clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 542 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 548 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp

This file has a very large number of changes (4,936 lines). Show File Contents

clang/test/OpenMP/distribute_simd_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK1-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK1-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK1-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK1-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK1-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK1-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK1-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK1-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK1-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK1-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !16			// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !16			// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !16			// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK1-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK1-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !16			// CHECK1-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !17
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !16			// CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !20
	// CHECK1-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK1-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK1-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK1-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !20
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK2-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK2-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK2-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK2-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK2-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK2-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK2-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK2-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK2-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK2-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !16			// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !16			// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !16			// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK2-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK2-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !16			// CHECK2-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !17
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !16			// CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !20
	// CHECK2-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK2-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK2-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK2-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !20
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK2-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK3-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK3-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK3-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK3-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK3-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK3-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK3-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK3-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK3-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK3-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK3-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK3-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK3-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK3-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
	// CHECK3-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK3-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK3-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK3-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK4-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK4-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK4-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK4-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK4-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK4-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK4-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK4-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK4-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK4-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK4-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK4-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK4-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK4-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK4-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK4-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
	// CHECK4-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK4-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK4-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK4-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK4-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK4-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK4-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: br label [[COND_END]]			// CHECK5-NEXT: br label [[COND_END]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK5-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK5-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK5-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK5-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK5-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK5-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK5-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK5-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK5-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK5-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK5-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK5-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK5-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK5-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !14			// CHECK5-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !15
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK5-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8			// CHECK5-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8
	// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64			// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]			// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK5-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4
	// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK5-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8			// CHECK5-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64			// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]			// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK5-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4
	// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]			// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
	// CHECK5-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !14			// CHECK5-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !15
	// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64			// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]			// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]
	// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK5: .omp.final.then:			// CHECK5: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !17			// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !17			// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !17			// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK5-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !17			// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !18
	// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17			// CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK5-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK5: omp_if.then:			// CHECK5: omp_if.then:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK5-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
	// CHECK5-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK5-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK5-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK5-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK5-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !14, !llvm.access.group !20			// CHECK5-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK5: omp_if.else:			// CHECK5: omp_if.else:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK5: omp.inner.for.cond13:			// CHECK5: omp.inner.for.cond13:
	// CHECK5-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK5-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK5-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK5: omp.inner.for.body15:			// CHECK5: omp.inner.for.body15:
	// CHECK5-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK5-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK5-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK5-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK5-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK5-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK5-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK5-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK5-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK5: omp.body.continue20:			// CHECK5: omp.body.continue20:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK5: omp.inner.for.inc21:			// CHECK5: omp.inner.for.inc21:
	// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK5-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK5-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK5: omp.inner.for.end23:			// CHECK5: omp.inner.for.end23:
	// CHECK5-NEXT: br label [[OMP_IF_END]]			// CHECK5-NEXT: br label [[OMP_IF_END]]
	// CHECK5: omp_if.end:			// CHECK5: omp_if.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: br label [[COND_END]]			// CHECK6-NEXT: br label [[COND_END]]
	// CHECK6: cond.end:			// CHECK6: cond.end:
	// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK6-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK6-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK6-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK6-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK6-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK6-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK6-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK6-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK6-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK6-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK6-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK6-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK6-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK6-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK6-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK6-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK6-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK6-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !14			// CHECK6-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !15
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]
	// CHECK6-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK6-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK6-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8			// CHECK6-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8
	// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64			// CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK6-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]			// CHECK6-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]
	// CHECK6-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK6-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4
	// CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK6-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8			// CHECK6-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8
	// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64			// CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]			// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]
	// CHECK6-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK6-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4
	// CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]			// CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
	// CHECK6-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !14			// CHECK6-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !15
	// CHECK6-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK6-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64			// CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK6-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]			// CHECK6-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]
	// CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK6-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK6-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK6: .omp.final.then:			// CHECK6: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !17			// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !17			// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !17			// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK6-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK6-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK6-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK6-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !17			// CHECK6-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !18
	// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK6-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK6-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17			// CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK6-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK6: omp_if.then:			// CHECK6: omp_if.then:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK6-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK6-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
	// CHECK6-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK6-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK6-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK6-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK6-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !14, !llvm.access.group !20			// CHECK6-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK6-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK6: omp_if.else:			// CHECK6: omp_if.else:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK6: omp.inner.for.cond13:			// CHECK6: omp.inner.for.cond13:
	// CHECK6-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK6-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK6-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK6-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK6: omp.inner.for.body15:			// CHECK6: omp.inner.for.body15:
	// CHECK6-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK6-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK6-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK6-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK6-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK6-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK6-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK6-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK6-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK6-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK6: omp.body.continue20:			// CHECK6: omp.body.continue20:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK6: omp.inner.for.inc21:			// CHECK6: omp.inner.for.inc21:
	// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK6-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK6-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK6: omp.inner.for.end23:			// CHECK6: omp.inner.for.end23:
	// CHECK6-NEXT: br label [[OMP_IF_END]]			// CHECK6-NEXT: br label [[OMP_IF_END]]
	// CHECK6: omp_if.end:			// CHECK6: omp_if.end:
	// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK6: omp.loop.exit:			// CHECK6: omp.loop.exit:
	// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26
	// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK6-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK6-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: br label [[COND_END]]			// CHECK7-NEXT: br label [[COND_END]]
	// CHECK7: cond.end:			// CHECK7: cond.end:
	// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK7-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK7-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK7-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK7-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK7-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK7-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK7-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK7-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK7-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK7-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK7-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK7-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK7-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK7-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK7-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK7: omp.loop.exit:			// CHECK7: omp.loop.exit:
	// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK7-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK7-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK7: .omp.final.then:			// CHECK7: .omp.final.then:
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK7-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !15			// CHECK7-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !16
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]
	// CHECK7-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK7-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK7-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4			// CHECK7-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4
	// CHECK7-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK7-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]			// CHECK7-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]
	// CHECK7-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK7-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4
	// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK7-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4			// CHECK7-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4
	// CHECK7-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK7-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]			// CHECK7-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]
	// CHECK7-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK7-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4
	// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]			// CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
	// CHECK7-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !15			// CHECK7-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !16
	// CHECK7-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK7-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK7-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]			// CHECK7-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]
	// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK7: omp.loop.exit:			// CHECK7: omp.loop.exit:
	// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK7-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK7-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK7: .omp.final.then:			// CHECK7: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK7-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK7-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK7-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK7-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK7-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK7-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK7-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK7-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK7-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK7-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK7-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK7-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18			// CHECK7-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK7-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK7-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK7-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK7-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK7: omp_if.then:			// CHECK7: omp_if.then:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK7-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK7-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
	// CHECK7-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK7-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK7-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK7-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK7-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK7-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21			// CHECK7-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK7-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK7: omp_if.else:			// CHECK7: omp_if.else:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK7: omp.inner.for.cond13:			// CHECK7: omp.inner.for.cond13:
	// CHECK7-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK7-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK7-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK7: omp.inner.for.body15:			// CHECK7: omp.inner.for.body15:
	// CHECK7-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK7-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK7-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK7-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK7-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK7-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK7-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK7-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK7-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK7-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK7-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK7: omp.body.continue20:			// CHECK7: omp.body.continue20:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK7: omp.inner.for.inc21:			// CHECK7: omp.inner.for.inc21:
	// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK7-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK7: omp.inner.for.end23:			// CHECK7: omp.inner.for.end23:
	// CHECK7-NEXT: br label [[OMP_IF_END]]			// CHECK7-NEXT: br label [[OMP_IF_END]]
	// CHECK7: omp_if.end:			// CHECK7: omp_if.end:
	// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK7: omp.loop.exit:			// CHECK7: omp.loop.exit:
	// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK7-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK7-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK7-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK7-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK7-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK7-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: br label [[COND_END]]			// CHECK8-NEXT: br label [[COND_END]]
	// CHECK8: cond.end:			// CHECK8: cond.end:
	// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK8-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK8-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK8-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK8-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK8-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK8-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK8-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK8-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK8-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK8-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK8-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK8-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK8-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK8-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK8-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK8-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK8-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK8-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK8: omp.loop.exit:			// CHECK8: omp.loop.exit:
	// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK8-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK8-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK8-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK8-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK8: .omp.final.then:			// CHECK8: .omp.final.then:
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK8-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK8-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK8-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !15			// CHECK8-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !16
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]
	// CHECK8-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK8-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK8-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4			// CHECK8-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4
	// CHECK8-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK8-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]			// CHECK8-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]
	// CHECK8-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK8-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4
	// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK8-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4			// CHECK8-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4
	// CHECK8-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK8-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]			// CHECK8-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]
	// CHECK8-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK8-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4
	// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]			// CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
	// CHECK8-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !15			// CHECK8-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !16
	// CHECK8-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK8-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK8-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]			// CHECK8-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]
	// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK8: omp.loop.exit:			// CHECK8: omp.loop.exit:
	// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK8-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK8-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK8-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK8-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK8: .omp.final.then:			// CHECK8: .omp.final.then:
	▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK8-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK8-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK8-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK8-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK8-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK8-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK8-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK8-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK8-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK8-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK8-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK8-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK8-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK8-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK8-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18			// CHECK8-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK8-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK8-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK8-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK8-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK8-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK8: omp_if.then:			// CHECK8: omp_if.then:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK8-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK8-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK8-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
	// CHECK8-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK8-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK8-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK8-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK8-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK8-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK8-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21			// CHECK8-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK8-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK8-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK8: omp_if.else:			// CHECK8: omp_if.else:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK8: omp.inner.for.cond13:			// CHECK8: omp.inner.for.cond13:
	// CHECK8-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK8-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK8-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK8-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK8-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK8: omp.inner.for.body15:			// CHECK8: omp.inner.for.body15:
	// CHECK8-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK8-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK8-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK8-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK8-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK8-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK8-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK8-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK8-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK8-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK8: omp.body.continue20:			// CHECK8: omp.body.continue20:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK8: omp.inner.for.inc21:			// CHECK8: omp.inner.for.inc21:
	// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK8-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK8-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK8: omp.inner.for.end23:			// CHECK8: omp.inner.for.end23:
	// CHECK8-NEXT: br label [[OMP_IF_END]]			// CHECK8-NEXT: br label [[OMP_IF_END]]
	// CHECK8: omp_if.end:			// CHECK8: omp_if.end:
	// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK8-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK8: omp.loop.exit:			// CHECK8: omp.loop.exit:
	// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK8-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK8-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK8-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK8-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK8-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK8-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK8-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK8-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK8-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 2,756 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: br label [[COND_END]]			// CHECK17-NEXT: br label [[COND_END]]
	// CHECK17: cond.end:			// CHECK17: cond.end:
	// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK17-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK17-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK17-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK17-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK17-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK17-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK17-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK17-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK17-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK17-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK17-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK17-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK17-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK17-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK17-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK17-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK17-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK17-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK17-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK17-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9
	// CHECK17-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK17-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK17-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK17-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK17-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK17: omp.loop.exit:			// CHECK17: omp.loop.exit:
	// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK17-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK17: .omp.final.then:			// CHECK17: .omp.final.then:
	▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK17-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK17: omp.loop.exit:			// CHECK17: omp.loop.exit:
	// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK17-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK17-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK17: .omp.final.then:			// CHECK17: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK17-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK17-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK17-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !16			// CHECK17-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK17-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !16			// CHECK17-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK17-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK17-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK17-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK17-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK17-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK17-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !16			// CHECK17-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK17-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK17-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK17-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK17-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK17-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK17-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !16			// CHECK17-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK17-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK17-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK17-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !16			// CHECK17-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK17-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK17-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK17-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK17-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: br label [[COND_END]]			// CHECK17-NEXT: br label [[COND_END]]
	// CHECK17: cond.end:			// CHECK17: cond.end:
	// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK17-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
	// CHECK17-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK17-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK17-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK17-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK17-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK17-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK17-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK17: omp.loop.exit:			// CHECK17: omp.loop.exit:
	// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK17-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK17-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: br label [[COND_END]]			// CHECK18-NEXT: br label [[COND_END]]
	// CHECK18: cond.end:			// CHECK18: cond.end:
	// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK18-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9
	// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK18-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK18-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK18-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9
	// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK18-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK18-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK18-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK18-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK18-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK18-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK18-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK18-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9
	// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK18-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK18-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK18-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK18-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK18-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK18-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK18-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK18-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9
	// CHECK18-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK18-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK18-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK18-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK18-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK18: omp.loop.exit:			// CHECK18: omp.loop.exit:
	// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK18-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK18-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK18: .omp.final.then:			// CHECK18: .omp.final.then:
	▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK18-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK18: omp.loop.exit:			// CHECK18: omp.loop.exit:
	// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK18-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK18-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK18: .omp.final.then:			// CHECK18: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK18-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK18-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK18-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !16			// CHECK18-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK18-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !16			// CHECK18-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK18-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK18-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK18-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK18-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK18-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK18-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !16			// CHECK18-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK18-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK18-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK18-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK18-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK18-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK18-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !16			// CHECK18-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK18-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK18-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK18-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !16			// CHECK18-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK18-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16			// CHECK18-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK18-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK18-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: br label [[COND_END]]			// CHECK18-NEXT: br label [[COND_END]]
	// CHECK18: cond.end:			// CHECK18: cond.end:
	// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK18-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !21
	// CHECK18-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK18-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK18-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK18-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK18-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK18-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK18-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !21
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK18-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK18: omp.loop.exit:			// CHECK18: omp.loop.exit:
	// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK18-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK18-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: br label [[COND_END]]			// CHECK19-NEXT: br label [[COND_END]]
	// CHECK19: cond.end:			// CHECK19: cond.end:
	// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK19-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK19-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK19-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK19-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK19-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK19-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK19-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK19-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK19-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK19-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK19-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK19-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK19-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK19-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK19-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK19-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK19-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK19-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK19: omp.loop.exit:			// CHECK19: omp.loop.exit:
	// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK19-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK19: .omp.final.then:			// CHECK19: .omp.final.then:
	▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK19-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK19: omp.loop.exit:			// CHECK19: omp.loop.exit:
	// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK19-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK19-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK19: .omp.final.then:			// CHECK19: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK19-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK19-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK19-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK19-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK19-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK19-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK19-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK19-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK19-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK19-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK19-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK19-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK19-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK19-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK19-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK19-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK19-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK19-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK19-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: br label [[COND_END]]			// CHECK19-NEXT: br label [[COND_END]]
	// CHECK19: cond.end:			// CHECK19: cond.end:
	// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK19-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK19-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
	// CHECK19-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK19-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK19-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK19-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK19-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK19-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK19-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !22
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK19-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK19: omp.loop.exit:			// CHECK19: omp.loop.exit:
	// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK19-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK19-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK19-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK19-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: br label [[COND_END]]			// CHECK20-NEXT: br label [[COND_END]]
	// CHECK20: cond.end:			// CHECK20: cond.end:
	// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK20-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK20-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK20-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK20-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK20-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK20-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK20-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK20-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK20-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK20-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK20-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK20-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK20-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK20-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK20-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK20-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK20-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK20-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK20: omp.loop.exit:			// CHECK20: omp.loop.exit:
	// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK20-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK20-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK20: .omp.final.then:			// CHECK20: .omp.final.then:
	▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK20-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK20: omp.loop.exit:			// CHECK20: omp.loop.exit:
	// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK20-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK20-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK20: .omp.final.then:			// CHECK20: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK20-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK20-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK20-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK20-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK20-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK20-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK20-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK20-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK20-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK20-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK20-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK20-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK20-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK20-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK20-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK20-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK20-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK20-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK20-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: br label [[COND_END]]			// CHECK20-NEXT: br label [[COND_END]]
	// CHECK20: cond.end:			// CHECK20: cond.end:
	// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK20-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK20-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK20-NEXT: [[TMP16:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
	// CHECK20-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32			// CHECK20-NEXT: [[CONV9:%.*]] = sext i8 [[TMP16]] to i32
	// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK20-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK20-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK20-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK20-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK20-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1			// CHECK20-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !llvm.access.group !22
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK20-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK20-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK20: omp.loop.exit:			// CHECK20: omp.loop.exit:
	// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK20-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK20-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK20-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK20-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK21-NEXT: br label [[COND_END]]			// CHECK21-NEXT: br label [[COND_END]]
	// CHECK21: cond.end:			// CHECK21: cond.end:
	// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK21-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK21: omp.inner.for.cond:			// CHECK21: omp.inner.for.cond:
	// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK21: omp.inner.for.body:			// CHECK21: omp.inner.for.body:
	// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK21-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9
	// CHECK21-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK21-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK21-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK21-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9
	// CHECK21-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK21-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK21-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK21-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK21-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK21-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK21-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9
	// CHECK21-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK21-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK21-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK21-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK21-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK21-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK21-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9
	// CHECK21-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK21-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK21-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK21: omp.body.continue:			// CHECK21: omp.body.continue:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK21: omp.inner.for.inc:			// CHECK21: omp.inner.for.inc:
	// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK21-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK21: omp.inner.for.end:			// CHECK21: omp.inner.for.end:
	// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK21: omp.loop.exit:			// CHECK21: omp.loop.exit:
	// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK21-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK21-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK21-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK21-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK21: .omp.final.then:			// CHECK21: .omp.final.then:
	▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
	// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK21: omp.inner.for.body:			// CHECK21: omp.inner.for.body:
	// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK21-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK21-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK21-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !14			// CHECK21-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !16
	// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]			// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]
	// CHECK21-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK21-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK21-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8			// CHECK21-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8
	// CHECK21-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64			// CHECK21-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK21-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]			// CHECK21-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]
	// CHECK21-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK21-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4
	// CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK21-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK21-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8			// CHECK21-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8
	// CHECK21-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64			// CHECK21-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK21-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]			// CHECK21-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]
	// CHECK21-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK21-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4
	// CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]			// CHECK21-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
	// CHECK21-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !14			// CHECK21-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !16
	// CHECK21-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64			// CHECK21-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK21-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]			// CHECK21-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]
	// CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK21-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK21: omp.body.continue:			// CHECK21: omp.body.continue:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK21: omp.inner.for.inc:			// CHECK21: omp.inner.for.inc:
	// CHECK21-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK21: omp.inner.for.end:			// CHECK21: omp.inner.for.end:
	// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK21: omp.loop.exit:			// CHECK21: omp.loop.exit:
	// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK21-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK21-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK21: .omp.final.then:			// CHECK21: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK21-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK21-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK21: omp.dispatch.body:			// CHECK21: omp.dispatch.body:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK21: omp.inner.for.cond:			// CHECK21: omp.inner.for.cond:
	// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK21-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK21: omp.inner.for.body:			// CHECK21: omp.inner.for.body:
	// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK21-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK21-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK21-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !17			// CHECK21-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !19
	// CHECK21-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK21-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK21-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !17			// CHECK21-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !19
	// CHECK21-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK21-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK21-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK21-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK21-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK21-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK21-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !17			// CHECK21-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !19
	// CHECK21-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK21-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK21-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK21-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK21-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK21-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK21-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !17			// CHECK21-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !19
	// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK21-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK21-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK21-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK21-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17			// CHECK21-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK21: omp.body.continue:			// CHECK21: omp.body.continue:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK21: omp.inner.for.inc:			// CHECK21: omp.inner.for.inc:
	// CHECK21-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK21-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK21-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK21-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK21-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK21: omp.inner.for.end:			// CHECK21: omp.inner.for.end:
	// CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK21: omp.dispatch.inc:			// CHECK21: omp.dispatch.inc:
	// CHECK21-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK21-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK21-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK21-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK21-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK21-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
	// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK21-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK21-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK21: omp_if.then:			// CHECK21: omp_if.then:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK21: omp.inner.for.cond:			// CHECK21: omp.inner.for.cond:
	// CHECK21-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK21-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK21-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK21-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK21-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK21: omp.inner.for.body:			// CHECK21: omp.inner.for.body:
	// CHECK21-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK21-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
	// CHECK21-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK21-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK21-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK21-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK21-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK21-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK21-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !14, !llvm.access.group !20			// CHECK21-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK21: omp.body.continue:			// CHECK21: omp.body.continue:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK21: omp.inner.for.inc:			// CHECK21: omp.inner.for.inc:
	// CHECK21-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK21-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK21: omp.inner.for.end:			// CHECK21: omp.inner.for.end:
	// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK21: omp_if.else:			// CHECK21: omp_if.else:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK21: omp.inner.for.cond13:			// CHECK21: omp.inner.for.cond13:
	// CHECK21-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK21-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK21-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK21-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK21: omp.inner.for.body15:			// CHECK21: omp.inner.for.body15:
	// CHECK21-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK21-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK21-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK21-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK21-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK21-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK21-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK21-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK21-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK21-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK21: omp.body.continue20:			// CHECK21: omp.body.continue20:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK21: omp.inner.for.inc21:			// CHECK21: omp.inner.for.inc21:
	// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK21-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK21-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK21: omp.inner.for.end23:			// CHECK21: omp.inner.for.end23:
	// CHECK21-NEXT: br label [[OMP_IF_END]]			// CHECK21-NEXT: br label [[OMP_IF_END]]
	// CHECK21: omp_if.end:			// CHECK21: omp_if.end:
	// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK21: omp.loop.exit:			// CHECK21: omp.loop.exit:
	// CHECK21-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK21-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK21-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK21-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK21: omp.dispatch.body:			// CHECK21: omp.dispatch.body:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK21: omp.inner.for.cond:			// CHECK21: omp.inner.for.cond:
	// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25			// CHECK21-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK21: omp.inner.for.body:			// CHECK21: omp.inner.for.body:
	// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25			// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK21: omp.body.continue:			// CHECK21: omp.body.continue:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK21: omp.inner.for.inc:			// CHECK21: omp.inner.for.inc:
	// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK21-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK21-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK21: omp.inner.for.end:			// CHECK21: omp.inner.for.end:
	// CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK21: omp.dispatch.inc:			// CHECK21: omp.dispatch.inc:
	// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK21-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK21-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK21-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK21-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK21-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK22-NEXT: br label [[COND_END]]			// CHECK22-NEXT: br label [[COND_END]]
	// CHECK22: cond.end:			// CHECK22: cond.end:
	// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK22-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK22-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK22-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK22: omp.inner.for.cond:			// CHECK22: omp.inner.for.cond:
	// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK22: omp.inner.for.body:			// CHECK22: omp.inner.for.body:
	// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8			// CHECK22-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !9
	// CHECK22-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64			// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
	// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK22-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK22-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8			// CHECK22-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !9
	// CHECK22-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64			// CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK22-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]			// CHECK22-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM2]]
	// CHECK22-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK22-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK22-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8			// CHECK22-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !9
	// CHECK22-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64			// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK22-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]			// CHECK22-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM5]]
	// CHECK22-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK22-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX6]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]			// CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP21]]
	// CHECK22-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8			// CHECK22-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !9
	// CHECK22-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64			// CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP23]] to i64
	// CHECK22-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]			// CHECK22-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM8]]
	// CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK22: omp.body.continue:			// CHECK22: omp.body.continue:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK22: omp.inner.for.inc:			// CHECK22: omp.inner.for.inc:
	// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK22-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK22: omp.inner.for.end:			// CHECK22: omp.inner.for.end:
	// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK22: omp.loop.exit:			// CHECK22: omp.loop.exit:
	// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK22-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK22-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK22-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK22-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK22-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK22-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK22: .omp.final.then:			// CHECK22: .omp.final.then:
	▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
	// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK22: omp.inner.for.body:			// CHECK22: omp.inner.for.body:
	// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK22-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK22-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK22-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !14			// CHECK22-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !nontemporal !16
	// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]			// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]]
	// CHECK22-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK22-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK22-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8			// CHECK22-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8
	// CHECK22-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64			// CHECK22-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK22-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]			// CHECK22-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]]
	// CHECK22-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4			// CHECK22-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4
	// CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK22-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK22-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8			// CHECK22-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8
	// CHECK22-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64			// CHECK22-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK22-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]			// CHECK22-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]]
	// CHECK22-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4			// CHECK22-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4
	// CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]			// CHECK22-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
	// CHECK22-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !14			// CHECK22-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !nontemporal !16
	// CHECK22-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64			// CHECK22-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK22-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]			// CHECK22-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]]
	// CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4			// CHECK22-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK22: omp.body.continue:			// CHECK22: omp.body.continue:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK22: omp.inner.for.inc:			// CHECK22: omp.inner.for.inc:
	// CHECK22-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK22: omp.inner.for.end:			// CHECK22: omp.inner.for.end:
	// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK22: omp.loop.exit:			// CHECK22: omp.loop.exit:
	// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK22-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK22-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK22-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK22-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK22: .omp.final.then:			// CHECK22: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK22-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK22-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK22: omp.dispatch.body:			// CHECK22: omp.dispatch.body:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK22: omp.inner.for.cond:			// CHECK22: omp.inner.for.cond:
	// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK22-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK22: omp.inner.for.body:			// CHECK22: omp.inner.for.body:
	// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK22-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK22-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK22-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17			// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !17			// CHECK22-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !19
	// CHECK22-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64			// CHECK22-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
	// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]			// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]]
	// CHECK22-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !17			// CHECK22-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !19
	// CHECK22-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64			// CHECK22-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
	// CHECK22-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]			// CHECK22-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]]
	// CHECK22-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK22-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK22-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !17			// CHECK22-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !19
	// CHECK22-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64			// CHECK22-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
	// CHECK22-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]			// CHECK22-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]]
	// CHECK22-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]			// CHECK22-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
	// CHECK22-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !17			// CHECK22-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !19
	// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64			// CHECK22-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
	// CHECK22-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]			// CHECK22-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]]
	// CHECK22-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !17			// CHECK22-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK22: omp.body.continue:			// CHECK22: omp.body.continue:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK22: omp.inner.for.inc:			// CHECK22: omp.inner.for.inc:
	// CHECK22-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK22-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1			// CHECK22-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1
	// CHECK22-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK22-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK22: omp.inner.for.end:			// CHECK22: omp.inner.for.end:
	// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK22: omp.dispatch.inc:			// CHECK22: omp.dispatch.inc:
	// CHECK22-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK22-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK22-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK22-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK22-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4			// CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4
	// CHECK22-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
	// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK22-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK22-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK22-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK22: omp_if.then:			// CHECK22: omp_if.then:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK22: omp.inner.for.cond:			// CHECK22: omp.inner.for.cond:
	// CHECK22-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK22-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK22-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK22-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK22-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK22-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK22: omp.inner.for.body:			// CHECK22: omp.inner.for.body:
	// CHECK22-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK22-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !22
	// CHECK22-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK22-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK22-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK22-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK22-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK22-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK22-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !14, !llvm.access.group !20			// CHECK22-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !16, !llvm.access.group !22
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK22: omp.body.continue:			// CHECK22: omp.body.continue:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK22: omp.inner.for.inc:			// CHECK22: omp.inner.for.inc:
	// CHECK22-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK22-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK22-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK22: omp.inner.for.end:			// CHECK22: omp.inner.for.end:
	// CHECK22-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK22-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK22: omp_if.else:			// CHECK22: omp_if.else:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK22: omp.inner.for.cond13:			// CHECK22: omp.inner.for.cond13:
	// CHECK22-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK22-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK22-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK22-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK22-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK22: omp.inner.for.body15:			// CHECK22: omp.inner.for.body15:
	// CHECK22-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK22-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK22-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK22-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK22-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK22-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK22-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK22-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK22-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK22-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK22: omp.body.continue20:			// CHECK22: omp.body.continue20:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK22: omp.inner.for.inc21:			// CHECK22: omp.inner.for.inc21:
	// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK22-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK22-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK22: omp.inner.for.end23:			// CHECK22: omp.inner.for.end23:
	// CHECK22-NEXT: br label [[OMP_IF_END]]			// CHECK22-NEXT: br label [[OMP_IF_END]]
	// CHECK22: omp_if.end:			// CHECK22: omp_if.end:
	// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK22: omp.loop.exit:			// CHECK22: omp.loop.exit:
	// CHECK22-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK22-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK22-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK22-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK22: omp.dispatch.body:			// CHECK22: omp.dispatch.body:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK22: omp.inner.for.cond:			// CHECK22: omp.inner.for.cond:
	// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25			// CHECK22-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK22-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK22-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK22: omp.inner.for.body:			// CHECK22: omp.inner.for.body:
	// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25			// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK22: omp.body.continue:			// CHECK22: omp.body.continue:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK22: omp.inner.for.inc:			// CHECK22: omp.inner.for.inc:
	// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK22-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25			// CHECK22-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK22: omp.inner.for.end:			// CHECK22: omp.inner.for.end:
	// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK22: omp.dispatch.inc:			// CHECK22: omp.dispatch.inc:
	// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK22-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK22-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK22-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK22-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK22-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK23-NEXT: br label [[COND_END]]			// CHECK23-NEXT: br label [[COND_END]]
	// CHECK23: cond.end:			// CHECK23: cond.end:
	// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK23-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK23: omp.inner.for.cond:			// CHECK23: omp.inner.for.cond:
	// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK23: omp.inner.for.body:			// CHECK23: omp.inner.for.body:
	// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK23-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK23-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK23-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK23-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK23-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK23-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK23-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK23-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK23-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK23-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK23-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK23-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK23-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK23-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK23-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK23: omp.body.continue:			// CHECK23: omp.body.continue:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK23: omp.inner.for.inc:			// CHECK23: omp.inner.for.inc:
	// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK23: omp.inner.for.end:			// CHECK23: omp.inner.for.end:
	// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK23: omp.loop.exit:			// CHECK23: omp.loop.exit:
	// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK23-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK23-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK23-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK23-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK23: .omp.final.then:			// CHECK23: .omp.final.then:
	▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
	// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK23: omp.inner.for.body:			// CHECK23: omp.inner.for.body:
	// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK23-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK23-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK23-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !15			// CHECK23-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !17
	// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]			// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]
	// CHECK23-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK23-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK23-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4			// CHECK23-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4
	// CHECK23-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK23-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]			// CHECK23-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]
	// CHECK23-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK23-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4
	// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK23-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK23-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4			// CHECK23-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4
	// CHECK23-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK23-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]			// CHECK23-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]
	// CHECK23-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK23-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4
	// CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]			// CHECK23-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
	// CHECK23-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !15			// CHECK23-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !17
	// CHECK23-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK23-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]			// CHECK23-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]
	// CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK23-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK23: omp.body.continue:			// CHECK23: omp.body.continue:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK23: omp.inner.for.inc:			// CHECK23: omp.inner.for.inc:
	// CHECK23-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK23: omp.inner.for.end:			// CHECK23: omp.inner.for.end:
	// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK23: omp.loop.exit:			// CHECK23: omp.loop.exit:
	// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK23-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK23-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK23: .omp.final.then:			// CHECK23: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK23-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK23-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK23: omp.dispatch.body:			// CHECK23: omp.dispatch.body:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK23: omp.inner.for.cond:			// CHECK23: omp.inner.for.cond:
	// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK23-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK23: omp.inner.for.body:			// CHECK23: omp.inner.for.body:
	// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK23-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK23-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK23-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK23-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK23-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK23-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK23-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK23-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK23-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK23-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK23-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK23-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK23-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK23-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18			// CHECK23-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK23: omp.body.continue:			// CHECK23: omp.body.continue:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK23: omp.inner.for.inc:			// CHECK23: omp.inner.for.inc:
	// CHECK23-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK23-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK23-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK23-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK23-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK23: omp.inner.for.end:			// CHECK23: omp.inner.for.end:
	// CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK23: omp.dispatch.inc:			// CHECK23: omp.dispatch.inc:
	// CHECK23-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK23-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK23-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK23-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK23-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK23-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK23-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK23-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
	// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK23-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK23-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK23-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK23: omp_if.then:			// CHECK23: omp_if.then:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK23: omp.inner.for.cond:			// CHECK23: omp.inner.for.cond:
	// CHECK23-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK23-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK23-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK23-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK23-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK23: omp.inner.for.body:			// CHECK23: omp.inner.for.body:
	// CHECK23-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK23-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !23
	// CHECK23-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK23-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK23-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK23-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK23-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK23-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK23-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21			// CHECK23-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !17, !llvm.access.group !23
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK23: omp.body.continue:			// CHECK23: omp.body.continue:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK23: omp.inner.for.inc:			// CHECK23: omp.inner.for.inc:
	// CHECK23-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK23-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK23-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK23: omp.inner.for.end:			// CHECK23: omp.inner.for.end:
	// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK23: omp_if.else:			// CHECK23: omp_if.else:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK23: omp.inner.for.cond13:			// CHECK23: omp.inner.for.cond13:
	// CHECK23-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK23-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK23-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK23-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK23: omp.inner.for.body15:			// CHECK23: omp.inner.for.body15:
	// CHECK23-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK23-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK23-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK23-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK23-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK23-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK23-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK23-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK23-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK23-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK23-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK23: omp.body.continue20:			// CHECK23: omp.body.continue20:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK23: omp.inner.for.inc21:			// CHECK23: omp.inner.for.inc21:
	// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK23-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK23: omp.inner.for.end23:			// CHECK23: omp.inner.for.end23:
	// CHECK23-NEXT: br label [[OMP_IF_END]]			// CHECK23-NEXT: br label [[OMP_IF_END]]
	// CHECK23: omp_if.end:			// CHECK23: omp_if.end:
	// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK23: omp.loop.exit:			// CHECK23: omp.loop.exit:
	// CHECK23-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK23-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK23-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK23-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK23: omp.dispatch.body:			// CHECK23: omp.dispatch.body:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK23: omp.inner.for.cond:			// CHECK23: omp.inner.for.cond:
	// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK23-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK23-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK23-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK23-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK23: omp.inner.for.body:			// CHECK23: omp.inner.for.body:
	// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK23: omp.body.continue:			// CHECK23: omp.body.continue:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK23: omp.inner.for.inc:			// CHECK23: omp.inner.for.inc:
	// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK23-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK23-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK23: omp.inner.for.end:			// CHECK23: omp.inner.for.end:
	// CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK23: omp.dispatch.inc:			// CHECK23: omp.dispatch.inc:
	// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK23-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK23-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK23-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK23-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK23-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK24-NEXT: br label [[COND_END]]			// CHECK24-NEXT: br label [[COND_END]]
	// CHECK24: cond.end:			// CHECK24: cond.end:
	// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]			// CHECK24-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
	// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK24-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK24-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK24: omp.inner.for.cond:			// CHECK24: omp.inner.for.cond:
	// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK24: omp.inner.for.body:			// CHECK24: omp.inner.for.body:
	// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7			// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 7
	// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]			// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]]
	// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4			// CHECK24-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP14:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]			// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i32 [[TMP14]]
	// CHECK24-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK24-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4			// CHECK24-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]			// CHECK24-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP16]], i32 [[TMP17]]
	// CHECK24-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK24-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK24-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4			// CHECK24-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP20:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]			// CHECK24-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP19]], i32 [[TMP20]]
	// CHECK24-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK24-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]			// CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP21]]
	// CHECK24-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4			// CHECK24-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP23:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]			// CHECK24-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP22]], i32 [[TMP23]]
	// CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK24: omp.body.continue:			// CHECK24: omp.body.continue:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK24: omp.inner.for.inc:			// CHECK24: omp.inner.for.inc:
	// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK24-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK24: omp.inner.for.end:			// CHECK24: omp.inner.for.end:
	// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK24: omp.loop.exit:			// CHECK24: omp.loop.exit:
	// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])			// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
	// CHECK24-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK24-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK24-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK24-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK24-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK24-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK24: .omp.final.then:			// CHECK24: .omp.final.then:
	▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
	// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK24: omp.inner.for.body:			// CHECK24: omp.inner.for.body:
	// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7			// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
	// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]			// CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
	// CHECK24-NEXT: store i32 [[SUB]], i32* [[I]], align 4			// CHECK24-NEXT: store i32 [[SUB]], i32* [[I]], align 4
	// CHECK24-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !15			// CHECK24-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 4, !nontemporal !17
	// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4
	// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]			// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i32 [[TMP13]]
	// CHECK24-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4			// CHECK24-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4
	// CHECK24-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4			// CHECK24-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 4
	// CHECK24-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4
	// CHECK24-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]			// CHECK24-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP15]], i32 [[TMP16]]
	// CHECK24-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4			// CHECK24-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX2]], align 4
	// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]			// CHECK24-NEXT: [[MUL3:%.*]] = fmul float [[TMP14]], [[TMP17]]
	// CHECK24-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4			// CHECK24-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 4
	// CHECK24-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4
	// CHECK24-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]			// CHECK24-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP18]], i32 [[TMP19]]
	// CHECK24-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4			// CHECK24-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX4]], align 4
	// CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]			// CHECK24-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP20]]
	// CHECK24-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !15			// CHECK24-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 4, !nontemporal !17
	// CHECK24-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4
	// CHECK24-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]			// CHECK24-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP21]], i32 [[TMP22]]
	// CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4			// CHECK24-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK24: omp.body.continue:			// CHECK24: omp.body.continue:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK24: omp.inner.for.inc:			// CHECK24: omp.inner.for.inc:
	// CHECK24-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1			// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
	// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK24: omp.inner.for.end:			// CHECK24: omp.inner.for.end:
	// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK24: omp.loop.exit:			// CHECK24: omp.loop.exit:
	// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])			// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
	// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK24-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0			// CHECK24-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
	// CHECK24-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK24-NEXT: br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK24: .omp.final.then:			// CHECK24: .omp.final.then:
	▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
	// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK24-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]			// CHECK24-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
	// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK24: omp.dispatch.body:			// CHECK24: omp.dispatch.body:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK24: omp.inner.for.cond:			// CHECK24: omp.inner.for.cond:
	// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]			// CHECK24-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
	// CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK24: omp.inner.for.body:			// CHECK24: omp.inner.for.body:
	// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127			// CHECK24-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127
	// CHECK24-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]			// CHECK24-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]]
	// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18			// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]			// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i32 [[TMP15]]
	// CHECK24-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]			// CHECK24-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP17]], i32 [[TMP18]]
	// CHECK24-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX3]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]			// CHECK24-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP19]]
	// CHECK24-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]			// CHECK24-NEXT: [[ARRAYIDX5:%.]] = getelementptr inbounds float, float [[TMP20]], i32 [[TMP21]]
	// CHECK24-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX5]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]			// CHECK24-NEXT: [[MUL6:%.*]] = fmul float [[MUL4]], [[TMP22]]
	// CHECK24-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]			// CHECK24-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP23]], i32 [[TMP24]]
	// CHECK24-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !18			// CHECK24-NEXT: store float [[MUL6]], float* [[ARRAYIDX7]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK24: omp.body.continue:			// CHECK24: omp.body.continue:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK24: omp.inner.for.inc:			// CHECK24: omp.inner.for.inc:
	// CHECK24-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK24-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1			// CHECK24-NEXT: [[ADD8:%.*]] = add i32 [[TMP25]], 1
	// CHECK24-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK24-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
	// CHECK24: omp.inner.for.end:			// CHECK24: omp.inner.for.end:
	// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK24: omp.dispatch.inc:			// CHECK24: omp.dispatch.inc:
	// CHECK24-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK24-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK24-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK24-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK24-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]			// CHECK24-NEXT: [[ADD9:%.*]] = add i32 [[TMP26]], [[TMP27]]
	// CHECK24-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK24-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK24-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
	// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1			// CHECK24-NEXT: [[TMP14:%.]] = load i8, i8 [[TMP1]], align 1
	// CHECK24-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0			// CHECK24-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP14]], 0
	// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK24: omp_if.then:			// CHECK24: omp_if.then:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK24: omp.inner.for.cond:			// CHECK24: omp.inner.for.cond:
	// CHECK24-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK24-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK24-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK24-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK24-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK24-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK24: omp.inner.for.body:			// CHECK24: omp.inner.for.body:
	// CHECK24-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK24-NEXT: [[TMP17:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !23
	// CHECK24-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32			// CHECK24-NEXT: [[CONV9:%.*]] = sext i8 [[TMP17]] to i32
	// CHECK24-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK24-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]			// CHECK24-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[MUL]]
	// CHECK24-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8			// CHECK24-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD10]] to i8
	// CHECK24-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !15, !llvm.access.group !21			// CHECK24-NEXT: store i8 [[CONV11]], i8* [[I6]], align 1, !nontemporal !17, !llvm.access.group !23
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK24: omp.body.continue:			// CHECK24: omp.body.continue:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK24: omp.inner.for.inc:			// CHECK24: omp.inner.for.inc:
	// CHECK24-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK24-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK24-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK24-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK24: omp.inner.for.end:			// CHECK24: omp.inner.for.end:
	// CHECK24-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK24-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK24: omp_if.else:			// CHECK24: omp_if.else:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13:%.*]]
	// CHECK24: omp.inner.for.cond13:			// CHECK24: omp.inner.for.cond13:
	// CHECK24-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK24-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK24-NEXT: [[CMP14:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK24-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]			// CHECK24-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY15:%.]], label [[OMP_INNER_FOR_END23:%.]]
	// CHECK24: omp.inner.for.body15:			// CHECK24: omp.inner.for.body15:
	// CHECK24-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1			// CHECK24-NEXT: [[TMP22:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1
	// CHECK24-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32			// CHECK24-NEXT: [[CONV16:%.*]] = sext i8 [[TMP22]] to i32
	// CHECK24-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1			// CHECK24-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP23]], 1
	// CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]			// CHECK24-NEXT: [[ADD18:%.*]] = add nsw i32 [[CONV16]], [[MUL17]]
	// CHECK24-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8			// CHECK24-NEXT: [[CONV19:%.*]] = trunc i32 [[ADD18]] to i8
	// CHECK24-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1			// CHECK24-NEXT: store i8 [[CONV19]], i8* [[I6]], align 1
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE20:%.*]]
	// CHECK24: omp.body.continue20:			// CHECK24: omp.body.continue20:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC21:%.*]]
	// CHECK24: omp.inner.for.inc21:			// CHECK24: omp.inner.for.inc21:
	// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK24-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK24-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[ADD22]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND13]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK24: omp.inner.for.end23:			// CHECK24: omp.inner.for.end23:
	// CHECK24-NEXT: br label [[OMP_IF_END]]			// CHECK24-NEXT: br label [[OMP_IF_END]]
	// CHECK24: omp_if.end:			// CHECK24: omp_if.end:
	// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK24: omp.loop.exit:			// CHECK24: omp.loop.exit:
	// CHECK24-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK24-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK24-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK24-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
	// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK24: omp.dispatch.body:			// CHECK24: omp.dispatch.body:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK24: omp.inner.for.cond:			// CHECK24: omp.inner.for.cond:
	// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK24-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK24-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK24-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK24-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK24: omp.inner.for.body:			// CHECK24: omp.inner.for.body:
	// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK24: omp.body.continue:			// CHECK24: omp.body.continue:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK24: omp.inner.for.inc:			// CHECK24: omp.inner.for.inc:
	// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK24-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK24-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK24: omp.inner.for.end:			// CHECK24: omp.inner.for.end:
	// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK24: omp.dispatch.inc:			// CHECK24: omp.dispatch.inc:
	// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK24-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK24-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK24-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK24-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK24-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 2,691 Lines • Show Last 20 Lines

clang/test/OpenMP/for_reduction_codegen_UDR.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 508 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8			// CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[S_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[S_ADDR]], align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]])			// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]])
	// CHECK1-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[TMP0]])			// CHECK1-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[TMP0]])
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10			// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: store i32 10, i32* [[I]], align 4			// CHECK1-NEXT: store i32 10, i32* [[I]], align 4
	// CHECK1-NEXT: call void @.omp_combiner.(%struct.S* [[TMP0]], %struct.S* [[S1]])			// CHECK1-NEXT: call void @.omp_combiner.(%struct.S* [[TMP0]], %struct.S* [[S1]])
	// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR4]]			// CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR4]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_combiner.			// CHECK1-LABEL: define {{[^@]+}}@.omp_combiner.
	▲ Show 20 Lines • Show All 3,037 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[S_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load %struct.S, %struct.S** [[S_ADDR]], align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]])			// CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]])
	// CHECK2-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[TMP0]])			// CHECK2-NEXT: call void @.omp_initializer.(%struct.S* [[S1]], %struct.S* [[TMP0]])
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10			// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: store i32 10, i32* [[I]], align 4			// CHECK2-NEXT: store i32 10, i32* [[I]], align 4
	// CHECK2-NEXT: call void @.omp_combiner.(%struct.S* [[TMP0]], %struct.S* [[S1]])			// CHECK2-NEXT: call void @.omp_combiner.(%struct.S* [[TMP0]], %struct.S* [[S1]])
	// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR4]]			// CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S* nonnull align 4 dereferenceable(12) [[S1]]) #[[ATTR4]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_combiner.			// CHECK2-LABEL: define {{[^@]+}}@.omp_combiner.
	▲ Show 20 Lines • Show All 4,281 Lines • Show Last 20 Lines

clang/test/OpenMP/for_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 451 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 457 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp

	Show First 20 Lines • Show All 595 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2			// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2
	// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4			// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: .omp_outlined..9.exit:			// CHECK1: .omp_outlined..9.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 594 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2			// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2
	// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4			// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: .omp_outlined..9.exit:			// CHECK2: .omp_outlined..9.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 32 Lines
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca %struct.S, align 8
	// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
	// CHECK2-NEXT: [[THIS1:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp

	Show First 20 Lines • Show All 595 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !14			// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !15
	// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: .omp_outlined..9.exit:			// CHECK1: .omp_outlined..9.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	▲ Show 20 Lines • Show All 593 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !14			// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !15
	// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: .omp_outlined..9.exit:			// CHECK2: .omp_outlined..9.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	▲ Show 20 Lines • Show All 297 Lines • Show Last 20 Lines

clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0			// CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
	// CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]			// CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]
	// CHECK1: .execute.parallel:			// CHECK1: .execute.parallel:
	// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])			// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])
	// CHECK1-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8
	// CHECK1-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)			// CHECK1-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
	// CHECK1-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]			// CHECK1-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]
	// CHECK1: .execute.fn:			// CHECK1: .execute.fn:
	// CHECK1-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5:[0-9]+]]			// CHECK1-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
	// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]			// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]
	// CHECK1: .check.next:			// CHECK1: .check.next:
	// CHECK1-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*			// CHECK1-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*
	// CHECK1-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])			// CHECK1-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])
	// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL]]			// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL]]
	// CHECK1: .terminate.parallel:			// CHECK1: .terminate.parallel:
	// CHECK1-NEXT: call void @__kmpc_kernel_end_parallel()			// CHECK1-NEXT: call void @__kmpc_kernel_end_parallel()
	// CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]]			// CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]]
	Show All 12 Lines
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]			// CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
	// CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]			// CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
	// CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]			// CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]
	// CHECK1: .worker:			// CHECK1: .worker:
	// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker() #[[ATTR5]]			// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker() #[[ATTR2]]
	// CHECK1-NEXT: br label [[DOTEXIT:%.*]]			// CHECK1-NEXT: br label [[DOTEXIT:%.*]]
	// CHECK1: .mastercheck:			// CHECK1: .mastercheck:
	// CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1			// CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
	// CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1			// CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
	// CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1			// CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1
	// CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]			// CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
	// CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]			// CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
	// CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]			// CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
	// CHECK1: .master:			// CHECK1: .master:
	// CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]			// CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
	// CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)			// CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
	// CHECK1-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK1-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA6:![0-9]+]]			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]
	// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]			// CHECK1-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]			// CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]
	// CHECK1: .termination.notifier:			// CHECK1: .termination.notifier:
	// CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1)			// CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1)
	// CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)			// CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
	// CHECK1-NEXT: br label [[DOTEXIT]]			// CHECK1-NEXT: br label [[DOTEXIT]]
	// CHECK1: .exit:			// CHECK1: .exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca float, align 4			// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
	// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4			// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10:![0-9]+]]			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK1-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*			// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
	// CHECK1-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK1-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*			// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
	// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)			// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)
	// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*			// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*
	// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*			// CHECK1-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99			// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99
	// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK1: cond.true:			// CHECK1: cond.true:
	// CHECK1-NEXT: br label [[COND_END:%.*]]			// CHECK1-NEXT: br label [[COND_END:%.*]]
	// CHECK1: cond.false:			// CHECK1: cond.false:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR2]]
	// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA12:![0-9]+]]			// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*			// CHECK1-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR2]]
	// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA12]]			// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]
	// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR7:[0-9]+]]			// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR8:[0-9]+]]
	// CHECK1-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*			// CHECK1-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4			// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
	// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4			// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4
	// CHECK1-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK1-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*			// CHECK1-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*
	// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM_ON_STACK]] to i8*			// CHECK1-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM_ON_STACK]] to i8*
	// CHECK1-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex") @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP26]], i64 3)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex") @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP26]], i64 3)
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK1-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*			// CHECK1-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC1ERKfS2_			// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC1ERKfS2_
	// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8			// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
	// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8			// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
	// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8
	// CHECK1-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR7]]			// CHECK1-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR8]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 13 Lines
	// CHECK1-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex", align 4			// CHECK1-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex", align 4
	// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca float, align 4			// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
	// CHECK1-NEXT: [[REF_TMP6:%.*]] = alloca float, align 4			// CHECK1-NEXT: [[REF_TMP6:%.*]] = alloca float, align 4
	// CHECK1-NEXT: [[I7:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[I7:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex", align 4			// CHECK1-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex", align 4
	// CHECK1-NEXT: [[REF_TMP15:%.*]] = alloca float, align 4			// CHECK1-NEXT: [[REF_TMP15:%.*]] = alloca float, align 4
	// CHECK1-NEXT: [[REF_TMP16:%.*]] = alloca float, align 4			// CHECK1-NEXT: [[REF_TMP16:%.*]] = alloca float, align 4
	// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store %"class.std::complex"* [[PARTIAL_SUM]], %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex"* [[PARTIAL_SUM]], %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1			// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
	// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1			// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
	// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1			// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
	// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*			// CHECK1-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK1: omp.precond.then:			// CHECK1: omp.precond.then:
	// CHECK1-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR2]]
	// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA12]]			// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]
	// CHECK1-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*			// CHECK1-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR2]]
	// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA12]]			// CHECK1-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]
	// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR7]]			// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR8]]
	// CHECK1-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*			// CHECK1-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*			// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
	// CHECK1: omp.dispatch.cond:			// CHECK1: omp.dispatch.cond:
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK1: cond.true:			// CHECK1: cond.true:
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[COND_END:%.*]]			// CHECK1-NEXT: br label [[COND_END:%.*]]
	// CHECK1: cond.false:			// CHECK1: cond.false:
	// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1
	// CHECK1-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]			// CHECK1-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]
	// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]
	// CHECK1: omp.dispatch.cleanup:			// CHECK1: omp.dispatch.cleanup:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1			// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1
	// CHECK1-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]			// CHECK1-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]
	// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1
	// CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]			// CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*			// CHECK1-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP40]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP40]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP41:%.]] = bitcast float [[REF_TMP15]] to i8*			// CHECK1-NEXT: [[TMP41:%.]] = bitcast float [[REF_TMP15]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP41]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP41]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float			// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float
	// CHECK1-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA12]]			// CHECK1-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]
	// CHECK1-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*			// CHECK1-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float			// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float
	// CHECK1-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA12]]			// CHECK1-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]
	// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR7]]			// CHECK1-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR8]]
	// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR8]]
	// CHECK1-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*			// CHECK1-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*			// CHECK1-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*			// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1			// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1
	// CHECK1-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]			// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]
	// CHECK1-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]			// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]
	// CHECK1-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])
	// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0			// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8			// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
	// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*			// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
	// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)			// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)
	// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1			// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
	// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
	// CHECK1: .omp.reduction.then:			// CHECK1: .omp.reduction.then:
	// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR8]]
	// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])			// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
	// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
	// CHECK1: .omp.reduction.done:			// CHECK1: .omp.reduction.done:
	// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*			// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[OMP_PRECOND_END]]			// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK1: omp.precond.end:			// CHECK1: omp.precond.end:
	// CHECK1-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK1-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK1-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK1-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR2]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIfEpLIfEERS0_RKS_IT_E			// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIfEpLIfEERS0_RKS_IT_E
	// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR8]]
	// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA14:![0-9]+]]			// CHECK1-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]
	// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]			// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]
	// CHECK1-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK1-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR8]]
	// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA16:![0-9]+]]			// CHECK1-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]
	// CHECK1-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]			// CHECK1-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]
	// CHECK1-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK1-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK1-NEXT: ret %"class.std::complex"* [[THIS1]]			// CHECK1-NEXT: ret %"class.std::complex"* [[THIS1]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func			// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex", align 4			// CHECK1-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex", align 4
	// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA17:![0-9]+]]			// CHECK1-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA19:![0-9]+]]
	// CHECK1-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]			// CHECK1-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]
	// CHECK1-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*			// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*
	// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1			// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1
	// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*			// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*			// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*
	// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*			// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4
	// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK1-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16			// CHECK1-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
	// CHECK1-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])			// CHECK1-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])
	// CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4			// CHECK1-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1
	// CHECK1-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1			// CHECK1-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1
	// CHECK1-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*			// CHECK1-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
	// CHECK1-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0			// CHECK1-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0
	// CHECK1-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK1-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK1-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]			// CHECK1-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]
	// CHECK1-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2			// CHECK1-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2
	// CHECK1-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1			// CHECK1-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1
	// CHECK1-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0			// CHECK1-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0
	// CHECK1-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]			// CHECK1-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]
	// CHECK1-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0			// CHECK1-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0
	// CHECK1-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]			// CHECK1-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]
	// CHECK1-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]			// CHECK1-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]
	// CHECK1-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]			// CHECK1-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]
	// CHECK1-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK1-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK1: then:			// CHECK1: then:
	// CHECK1-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*			// CHECK1-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
	// CHECK1-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*			// CHECK1-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
	// CHECK1-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR5]]			// CHECK1-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[IFCONT:%.*]]			// CHECK1-NEXT: br label [[IFCONT:%.*]]
	// CHECK1: else:			// CHECK1: else:
	// CHECK1-NEXT: br label [[IFCONT]]			// CHECK1-NEXT: br label [[IFCONT]]
	// CHECK1: ifcont:			// CHECK1: ifcont:
	// CHECK1-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK1-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK1-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]			// CHECK1-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]
	// CHECK1-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK1-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK1: then4:			// CHECK1: then4:
	// CHECK1-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK1-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8			// CHECK1-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8
	// CHECK1-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK1-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*			// CHECK1-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*
	// CHECK1-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*			// CHECK1-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*
	// CHECK1-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*			// CHECK1-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*
	// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*			// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !19			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !21
	// CHECK1-NEXT: br label [[IFCONT6:%.*]]			// CHECK1-NEXT: br label [[IFCONT6:%.*]]
	// CHECK1: else5:			// CHECK1: else5:
	// CHECK1-NEXT: br label [[IFCONT6]]			// CHECK1-NEXT: br label [[IFCONT6]]
	// CHECK1: ifcont6:			// CHECK1: ifcont6:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func			// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31			// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
	// CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5			// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
	// CHECK1-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
	// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[PRECOND:%.*]]			// CHECK1-NEXT: br label [[PRECOND:%.*]]
	// CHECK1: precond:			// CHECK1: precond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2			// CHECK1-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2
	// CHECK1-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
	// CHECK1: body:			// CHECK1: body:
	// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])
	// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0			// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
	// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK1: then:			// CHECK1: then:
	// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
	// CHECK1-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]			// CHECK1-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
	// CHECK1-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4			// CHECK1-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
	// CHECK1-NEXT: br label [[IFCONT:%.*]]			// CHECK1-NEXT: br label [[IFCONT:%.*]]
	// CHECK1: else:			// CHECK1: else:
	// CHECK1-NEXT: br label [[IFCONT]]			// CHECK1-NEXT: br label [[IFCONT]]
	// CHECK1: ifcont:			// CHECK1: ifcont:
	// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]			// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
	// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK1: then4:			// CHECK1: then4:
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*			// CHECK1-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
	// CHECK1-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[IFCONT6:%.*]]			// CHECK1-NEXT: br label [[IFCONT6:%.*]]
	// CHECK1: else5:			// CHECK1: else5:
	// CHECK1-NEXT: br label [[IFCONT6]]			// CHECK1-NEXT: br label [[IFCONT6]]
	// CHECK1: ifcont6:			// CHECK1: ifcont6:
	// CHECK1-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK1-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK1-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[PRECOND]]			// CHECK1-NEXT: br label [[PRECOND]]
	// CHECK1: exit:			// CHECK1: exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
	// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			// CHECK1-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			// CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	// CHECK1-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1
	// CHECK1-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**			// CHECK1-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex"**			// CHECK1-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex"**
	// CHECK1-NEXT: [[TMP11:%.]] = load %"class.std::complex", %"class.std::complex"** [[TMP10]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP11:%.]] = load %"class.std::complex", %"class.std::complex"** [[TMP10]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex"* [[TMP11]]) #[[ATTR5]]			// CHECK1-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex"* [[TMP11]]) #[[ATTR2]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker
	// CHECK1-SAME: () #[[ATTR0]] {			// CHECK1-SAME: () #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[WORK_FN:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[WORK_FN:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1			// CHECK1-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1
	Show All 13 Lines
	// CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0			// CHECK1-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
	// CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]			// CHECK1-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]
	// CHECK1: .execute.parallel:			// CHECK1: .execute.parallel:
	// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK1-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK1-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8			// CHECK1-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8
	// CHECK1-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*)			// CHECK1-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*)
	// CHECK1-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]			// CHECK1-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]
	// CHECK1: .execute.fn:			// CHECK1: .execute.fn:
	// CHECK1-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5]]			// CHECK1-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]			// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]
	// CHECK1: .check.next:			// CHECK1: .check.next:
	// CHECK1-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*			// CHECK1-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*
	// CHECK1-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])			// CHECK1-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])
	// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL]]			// CHECK1-NEXT: br label [[DOTTERMINATE_PARALLEL]]
	// CHECK1: .terminate.parallel:			// CHECK1: .terminate.parallel:
	// CHECK1-NEXT: call void @__kmpc_kernel_end_parallel()			// CHECK1-NEXT: call void @__kmpc_kernel_end_parallel()
	// CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]]			// CHECK1-NEXT: br label [[DOTBARRIER_PARALLEL]]
	Show All 12 Lines
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK1-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]			// CHECK1-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
	// CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]			// CHECK1-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
	// CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]			// CHECK1-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]
	// CHECK1: .worker:			// CHECK1: .worker:
	// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker() #[[ATTR5]]			// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker() #[[ATTR2]]
	// CHECK1-NEXT: br label [[DOTEXIT:%.*]]			// CHECK1-NEXT: br label [[DOTEXIT:%.*]]
	// CHECK1: .mastercheck:			// CHECK1: .mastercheck:
	// CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK1-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK1-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1			// CHECK1-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
	// CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1			// CHECK1-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
	// CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1			// CHECK1-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1
	// CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]			// CHECK1-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
	// CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]			// CHECK1-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
	// CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]			// CHECK1-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
	// CHECK1: .master:			// CHECK1: .master:
	// CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK1-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK1-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]			// CHECK1-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
	// CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)			// CHECK1-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
	// CHECK1-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK1-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]			// CHECK1-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]			// CHECK1-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]
	// CHECK1: .termination.notifier:			// CHECK1: .termination.notifier:
	// CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1)			// CHECK1-NEXT: call void @__kmpc_kernel_deinit(i16 1)
	// CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)			// CHECK1-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
	// CHECK1-NEXT: br label [[DOTEXIT]]			// CHECK1-NEXT: br label [[DOTEXIT]]
	// CHECK1: .exit:			// CHECK1: .exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[IB:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca double, align 8			// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
	// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8			// CHECK1-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8
	// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK1-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*			// CHECK1-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
	// CHECK1-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK1-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*			// CHECK1-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
	// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)			// CHECK1-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)
	// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*			// CHECK1-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*
	// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*			// CHECK1-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99			// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99
	// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK1: cond.true:			// CHECK1: cond.true:
	// CHECK1-NEXT: br label [[COND_END:%.*]]			// CHECK1-NEXT: br label [[COND_END:%.*]]
	// CHECK1: cond.false:			// CHECK1: cond.false:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR2]]
	// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA20:![0-9]+]]			// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*			// CHECK1-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR2]]
	// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA20]]			// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]
	// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR7]]			// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR8]]
	// CHECK1-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*			// CHECK1-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4			// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
	// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4			// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4
	// CHECK1-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK1-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*			// CHECK1-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*
	// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM_ON_STACK]] to i8*			// CHECK1-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM_ON_STACK]] to i8*
	// CHECK1-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK1-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex.0") @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP26]], i64 3)			// CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex.0") @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP26]], i64 3)
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK1-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*			// CHECK1-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR2]]
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])
	// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])			// CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC1ERKdS2_			// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC1ERKdS2_
	// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8			// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
	// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8			// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
	// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8			// CHECK1-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8
	// CHECK1-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR7]]			// CHECK1-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR8]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 13 Lines
	// CHECK1-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca double, align 8			// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
	// CHECK1-NEXT: [[REF_TMP6:%.*]] = alloca double, align 8			// CHECK1-NEXT: [[REF_TMP6:%.*]] = alloca double, align 8
	// CHECK1-NEXT: [[I7:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[I7:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: [[REF_TMP15:%.*]] = alloca double, align 8			// CHECK1-NEXT: [[REF_TMP15:%.*]] = alloca double, align 8
	// CHECK1-NEXT: [[REF_TMP16:%.*]] = alloca double, align 8			// CHECK1-NEXT: [[REF_TMP16:%.*]] = alloca double, align 8
	// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store %"class.std::complex.0"* [[PARTIAL_SUM]], %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex.0"* [[PARTIAL_SUM]], %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK1-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1			// CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
	// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1			// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
	// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1			// CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
	// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*			// CHECK1-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK1: omp.precond.then:			// CHECK1: omp.precond.then:
	// CHECK1-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR2]]
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR2]]
	// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA20]]			// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]
	// CHECK1-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*			// CHECK1-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR2]]
	// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA20]]			// CHECK1-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]
	// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR7]]			// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR8]]
	// CHECK1-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*			// CHECK1-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK1-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*			// CHECK1-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
	// CHECK1: omp.dispatch.cond:			// CHECK1: omp.dispatch.cond:
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]			// CHECK1-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]
	// CHECK1-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK1-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK1: cond.true:			// CHECK1: cond.true:
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[COND_END:%.*]]			// CHECK1-NEXT: br label [[COND_END:%.*]]
	// CHECK1: cond.false:			// CHECK1: cond.false:
	// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1
	// CHECK1-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]			// CHECK1-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]
	// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]
	// CHECK1: omp.dispatch.cleanup:			// CHECK1: omp.dispatch.cleanup:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1			// CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1
	// CHECK1-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]			// CHECK1-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]
	// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK1: omp.inner.for.cond.cleanup:			// CHECK1: omp.inner.for.cond.cleanup:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1
	// CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]			// CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*			// CHECK1-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP40]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP40]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP41:%.]] = bitcast double [[REF_TMP15]] to i8*			// CHECK1-NEXT: [[TMP41:%.]] = bitcast double [[REF_TMP15]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP41]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP41]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double			// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double
	// CHECK1-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA20]]			// CHECK1-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]
	// CHECK1-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*			// CHECK1-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double			// CHECK1-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double
	// CHECK1-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA20]]			// CHECK1-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]
	// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR7]]			// CHECK1-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR8]]
	// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR8]]
	// CHECK1-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*			// CHECK1-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*			// CHECK1-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*			// CHECK1-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1			// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1
	// CHECK1-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]			// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]
	// CHECK1-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]			// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]
	// CHECK1-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])
	// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0			// CHECK1-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK1-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8			// CHECK1-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
	// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*			// CHECK1-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
	// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)			// CHECK1-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)
	// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1			// CHECK1-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
	// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
	// CHECK1: .omp.reduction.then:			// CHECK1: .omp.reduction.then:
	// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR8]]
	// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])			// CHECK1-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
	// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]			// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
	// CHECK1: .omp.reduction.done:			// CHECK1: .omp.reduction.done:
	// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*			// CHECK1-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK1-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK1-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK1-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK1-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK1-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[OMP_PRECOND_END]]			// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK1: omp.precond.end:			// CHECK1: omp.precond.end:
	// CHECK1-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK1-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK1-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK1-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK1-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR5]]			// CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR2]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIdEpLIdEERS0_RKS_IT_E			// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIdEpLIdEERS0_RKS_IT_E
	// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR8]]
	// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA22:![0-9]+]]			// CHECK1-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]
	// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]			// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]
	// CHECK1-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK1-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR7]]			// CHECK1-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR8]]
	// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA24:![0-9]+]]			// CHECK1-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]
	// CHECK1-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]			// CHECK1-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]
	// CHECK1-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK1-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK1-NEXT: ret %"class.std::complex.0"* [[THIS1]]			// CHECK1-NEXT: ret %"class.std::complex.0"* [[THIS1]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5			// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5
	// CHECK1-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8			// CHECK1-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK1-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]			// CHECK1-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]
	// CHECK1-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK1-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*			// CHECK1-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*
	// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1			// CHECK1-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1
	// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*			// CHECK1-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*			// CHECK1-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*
	// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*			// CHECK1-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
	Show All 14 Lines
	// CHECK1-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16			// CHECK1-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
	// CHECK1-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])			// CHECK1-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])
	// CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8			// CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1			// CHECK1-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1
	// CHECK1-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1			// CHECK1-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1
	// CHECK1-NEXT: br label [[DOTSHUFFLE_PRE_COND]]			// CHECK1-NEXT: br label [[DOTSHUFFLE_PRE_COND]]
	// CHECK1: .shuffle.exit:			// CHECK1: .shuffle.exit:
	// CHECK1-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*			// CHECK1-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
	// CHECK1-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0			// CHECK1-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0
	// CHECK1-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK1-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK1-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]			// CHECK1-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]
	// CHECK1-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2			// CHECK1-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2
	// CHECK1-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1			// CHECK1-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1
	// CHECK1-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0			// CHECK1-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0
	// CHECK1-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]			// CHECK1-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]
	// CHECK1-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0			// CHECK1-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0
	// CHECK1-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]			// CHECK1-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]
	// CHECK1-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]			// CHECK1-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]
	// CHECK1-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]			// CHECK1-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]
	// CHECK1-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK1-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK1: then:			// CHECK1: then:
	// CHECK1-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*			// CHECK1-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
	// CHECK1-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*			// CHECK1-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
	// CHECK1-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR5]]			// CHECK1-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR2]]
	// CHECK1-NEXT: br label [[IFCONT:%.*]]			// CHECK1-NEXT: br label [[IFCONT:%.*]]
	// CHECK1: else:			// CHECK1: else:
	// CHECK1-NEXT: br label [[IFCONT]]			// CHECK1-NEXT: br label [[IFCONT]]
	// CHECK1: ifcont:			// CHECK1: ifcont:
	// CHECK1-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK1-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK1-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]			// CHECK1-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]
	// CHECK1-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK1-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK1: then4:			// CHECK1: then4:
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8			// CHECK1-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
	// CHECK1-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK1-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8			// CHECK1-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8
	// CHECK1-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*			// CHECK1-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*
	// CHECK1-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*			// CHECK1-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*
	// CHECK1-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*			// CHECK1-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*
	// CHECK1-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*			// CHECK1-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !25			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !27
	// CHECK1-NEXT: br label [[IFCONT6:%.*]]			// CHECK1-NEXT: br label [[IFCONT6:%.*]]
	// CHECK1: else5:			// CHECK1: else5:
	// CHECK1-NEXT: br label [[IFCONT6]]			// CHECK1-NEXT: br label [[IFCONT6]]
	// CHECK1: ifcont6:			// CHECK1: ifcont6:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6			// CHECK1-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6
	// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK1-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31			// CHECK1-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
	// CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK1-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5			// CHECK1-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
	// CHECK1-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
	// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[PRECOND:%.*]]			// CHECK1-NEXT: br label [[PRECOND:%.*]]
	// CHECK1: precond:			// CHECK1: precond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4			// CHECK1-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4
	// CHECK1-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
	// CHECK1: body:			// CHECK1: body:
	// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0			// CHECK1-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
	// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK1-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK1: then:			// CHECK1: then:
	// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK1-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
	// CHECK1-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]			// CHECK1-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
	// CHECK1-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4			// CHECK1-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
	// CHECK1-NEXT: br label [[IFCONT:%.*]]			// CHECK1-NEXT: br label [[IFCONT:%.*]]
	// CHECK1: else:			// CHECK1: else:
	// CHECK1-NEXT: br label [[IFCONT]]			// CHECK1-NEXT: br label [[IFCONT]]
	// CHECK1: ifcont:			// CHECK1: ifcont:
	// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]			// CHECK1-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
	// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK1-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK1: then4:			// CHECK1: then4:
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
	// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK1-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*			// CHECK1-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
	// CHECK1-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[IFCONT6:%.*]]			// CHECK1-NEXT: br label [[IFCONT6:%.*]]
	// CHECK1: else5:			// CHECK1: else5:
	// CHECK1-NEXT: br label [[IFCONT6]]			// CHECK1-NEXT: br label [[IFCONT6]]
	// CHECK1: ifcont6:			// CHECK1: ifcont6:
	// CHECK1-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK1-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK1-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: br label [[PRECOND]]			// CHECK1-NEXT: br label [[PRECOND]]
	// CHECK1: exit:			// CHECK1: exit:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			// CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK1-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK1-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			// CHECK1-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA17]]			// CHECK1-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA19]]
	// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			// CHECK1-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	// CHECK1-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			// CHECK1-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0			// CHECK1-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0
	// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**			// CHECK1-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1
	// CHECK1-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**			// CHECK1-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex.0"**			// CHECK1-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex.0"**
	// CHECK1-NEXT: [[TMP11:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[TMP10]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP11:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[TMP10]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex.0"* [[TMP11]]) #[[ATTR5]]			// CHECK1-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex.0"* [[TMP11]]) #[[ATTR2]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC2ERKfS2_			// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC2ERKfS2_
	// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8			// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
	// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8			// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
	// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP1:%.]] = load float, float [[TMP0]], align 4, !tbaa [[TBAA12]]			// CHECK1-NEXT: [[TMP1:%.]] = load float, float [[TMP0]], align 4, !tbaa [[TBAA14]]
	// CHECK1-NEXT: store float [[TMP1]], float* [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK1-NEXT: store float [[TMP1]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP2:%.]] = load float, float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP2:%.]] = load float, float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP3:%.]] = load float, float [[TMP2]], align 4, !tbaa [[TBAA12]]			// CHECK1-NEXT: [[TMP3:%.]] = load float, float [[TMP2]], align 4, !tbaa [[TBAA14]]
	// CHECK1-NEXT: store float [[TMP3]], float* [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK1-NEXT: store float [[TMP3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4realEv			// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4realEv
	// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP0:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK1-NEXT: [[TMP0:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK1-NEXT: ret float [[TMP0]]			// CHECK1-NEXT: ret float [[TMP0]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4imagEv			// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4imagEv
	// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP0:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK1-NEXT: [[TMP0:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK1-NEXT: ret float [[TMP0]]			// CHECK1-NEXT: ret float [[TMP0]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC2ERKdS2_			// CHECK1-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC2ERKdS2_
	// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8			// CHECK1-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
	// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8			// CHECK1-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
	// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP1:%.]] = load double, double [[TMP0]], align 8, !tbaa [[TBAA20]]			// CHECK1-NEXT: [[TMP1:%.]] = load double, double [[TMP0]], align 8, !tbaa [[TBAA22]]
	// CHECK1-NEXT: store double [[TMP1]], double* [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK1-NEXT: store double [[TMP1]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP2:%.]] = load double, double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: [[TMP2:%.]] = load double, double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[TMP3:%.]] = load double, double [[TMP2]], align 8, !tbaa [[TBAA20]]			// CHECK1-NEXT: [[TMP3:%.]] = load double, double [[TMP2]], align 8, !tbaa [[TBAA22]]
	// CHECK1-NEXT: store double [[TMP3]], double* [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK1-NEXT: store double [[TMP3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4realEv			// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4realEv
	// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK1-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP0:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK1-NEXT: [[TMP0:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK1-NEXT: ret double [[TMP0]]			// CHECK1-NEXT: ret double [[TMP0]]
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4imagEv			// CHECK1-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4imagEv
	// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK1-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK1-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK1-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK1-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP0:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK1-NEXT: [[TMP0:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK1-NEXT: ret double [[TMP0]]			// CHECK1-NEXT: ret double [[TMP0]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker
	// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[WORK_FN:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[WORK_FN:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1			// CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1
	Show All 13 Lines
	// CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0			// CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
	// CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]			// CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]
	// CHECK2: .execute.parallel:			// CHECK2: .execute.parallel:
	// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])			// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])
	// CHECK2-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8
	// CHECK2-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)			// CHECK2-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
	// CHECK2-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]			// CHECK2-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]
	// CHECK2: .execute.fn:			// CHECK2: .execute.fn:
	// CHECK2-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5:[0-9]+]]			// CHECK2-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
	// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]			// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]
	// CHECK2: .check.next:			// CHECK2: .check.next:
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*
	// CHECK2-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])			// CHECK2-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])
	// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL]]			// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL]]
	// CHECK2: .terminate.parallel:			// CHECK2: .terminate.parallel:
	// CHECK2-NEXT: call void @__kmpc_kernel_end_parallel()			// CHECK2-NEXT: call void @__kmpc_kernel_end_parallel()
	// CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]]			// CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]]
	Show All 12 Lines
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]			// CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
	// CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]			// CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
	// CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]			// CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]
	// CHECK2: .worker:			// CHECK2: .worker:
	// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker() #[[ATTR5]]			// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker() #[[ATTR2]]
	// CHECK2-NEXT: br label [[DOTEXIT:%.*]]			// CHECK2-NEXT: br label [[DOTEXIT:%.*]]
	// CHECK2: .mastercheck:			// CHECK2: .mastercheck:
	// CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1			// CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
	// CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1			// CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
	// CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1			// CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1
	// CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]			// CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
	// CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]			// CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
	// CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]			// CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
	// CHECK2: .master:			// CHECK2: .master:
	// CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]			// CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
	// CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)			// CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
	// CHECK2-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK2-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA6:![0-9]+]]			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]
	// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]			// CHECK2-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]			// CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]
	// CHECK2: .termination.notifier:			// CHECK2: .termination.notifier:
	// CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1)			// CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1)
	// CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)			// CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
	// CHECK2-NEXT: br label [[DOTEXIT]]			// CHECK2-NEXT: br label [[DOTEXIT]]
	// CHECK2: .exit:			// CHECK2: .exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca float, align 4			// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
	// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4			// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10:![0-9]+]]			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK2-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*			// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
	// CHECK2-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK2-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*			// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
	// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)			// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)
	// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*			// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*
	// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*			// CHECK2-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99			// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99
	// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK2: cond.true:			// CHECK2: cond.true:
	// CHECK2-NEXT: br label [[COND_END:%.*]]			// CHECK2-NEXT: br label [[COND_END:%.*]]
	// CHECK2: cond.false:			// CHECK2: cond.false:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR2]]
	// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA12:![0-9]+]]			// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*			// CHECK2-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR2]]
	// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA12]]			// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]
	// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR7:[0-9]+]]			// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR8:[0-9]+]]
	// CHECK2-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*			// CHECK2-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4			// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
	// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4			// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4
	// CHECK2-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK2-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*			// CHECK2-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*
	// CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM_ON_STACK]] to i8*			// CHECK2-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM_ON_STACK]] to i8*
	// CHECK2-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex") @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP26]], i64 3)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex") @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP26]], i64 3)
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK2-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*			// CHECK2-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC1ERKfS2_			// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC1ERKfS2_
	// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8			// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
	// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8			// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
	// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8
	// CHECK2-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR7]]			// CHECK2-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR8]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 13 Lines
	// CHECK2-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex", align 4			// CHECK2-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex", align 4
	// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca float, align 4			// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
	// CHECK2-NEXT: [[REF_TMP6:%.*]] = alloca float, align 4			// CHECK2-NEXT: [[REF_TMP6:%.*]] = alloca float, align 4
	// CHECK2-NEXT: [[I7:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[I7:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex", align 4			// CHECK2-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex", align 4
	// CHECK2-NEXT: [[REF_TMP15:%.*]] = alloca float, align 4			// CHECK2-NEXT: [[REF_TMP15:%.*]] = alloca float, align 4
	// CHECK2-NEXT: [[REF_TMP16:%.*]] = alloca float, align 4			// CHECK2-NEXT: [[REF_TMP16:%.*]] = alloca float, align 4
	// CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8			// CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store %"class.std::complex"* [[PARTIAL_SUM]], %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex"* [[PARTIAL_SUM]], %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1			// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
	// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1			// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
	// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1			// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
	// CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*			// CHECK2-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK2: omp.precond.then:			// CHECK2: omp.precond.then:
	// CHECK2-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR2]]
	// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA12]]			// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]
	// CHECK2-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*			// CHECK2-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR2]]
	// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA12]]			// CHECK2-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]
	// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR7]]			// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR8]]
	// CHECK2-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*			// CHECK2-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*			// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
	// CHECK2: omp.dispatch.cond:			// CHECK2: omp.dispatch.cond:
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK2: cond.true:			// CHECK2: cond.true:
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[COND_END:%.*]]			// CHECK2-NEXT: br label [[COND_END:%.*]]
	// CHECK2: cond.false:			// CHECK2: cond.false:
	// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1			// CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1
	// CHECK2-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]			// CHECK2-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]
	// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]
	// CHECK2: omp.dispatch.cleanup:			// CHECK2: omp.dispatch.cleanup:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1			// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1
	// CHECK2-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]			// CHECK2-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]
	// CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1
	// CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]			// CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*			// CHECK2-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP40]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP40]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP41:%.]] = bitcast float [[REF_TMP15]] to i8*			// CHECK2-NEXT: [[TMP41:%.]] = bitcast float [[REF_TMP15]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP41]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP41]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float			// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float
	// CHECK2-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA12]]			// CHECK2-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]
	// CHECK2-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*			// CHECK2-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float			// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float
	// CHECK2-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA12]]			// CHECK2-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]
	// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR7]]			// CHECK2-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR8]]
	// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR8]]
	// CHECK2-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*			// CHECK2-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*			// CHECK2-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*			// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1			// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1
	// CHECK2-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]			// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]
	// CHECK2-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]			// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]
	// CHECK2-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])
	// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0			// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8			// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
	// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*			// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
	// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)			// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)
	// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1			// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
	// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
	// CHECK2: .omp.reduction.then:			// CHECK2: .omp.reduction.then:
	// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR8]]
	// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])			// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
	// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
	// CHECK2: .omp.reduction.done:			// CHECK2: .omp.reduction.done:
	// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*			// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[OMP_PRECOND_END]]			// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK2: omp.precond.end:			// CHECK2: omp.precond.end:
	// CHECK2-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK2-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK2-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK2-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR2]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIfEpLIfEERS0_RKS_IT_E			// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIfEpLIfEERS0_RKS_IT_E
	// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR8]]
	// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA14:![0-9]+]]			// CHECK2-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]
	// CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]			// CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]
	// CHECK2-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK2-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR8]]
	// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA16:![0-9]+]]			// CHECK2-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]
	// CHECK2-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]			// CHECK2-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]
	// CHECK2-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK2-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK2-NEXT: ret %"class.std::complex"* [[THIS1]]			// CHECK2-NEXT: ret %"class.std::complex"* [[THIS1]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func			// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8			// CHECK2-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK2-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex", align 4			// CHECK2-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex", align 4
	// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA17:![0-9]+]]			// CHECK2-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA19:![0-9]+]]
	// CHECK2-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]			// CHECK2-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]
	// CHECK2-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK2-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*			// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*
	// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1			// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1
	// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*			// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*			// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*
	// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*			// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4
	// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK2-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16			// CHECK2-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
	// CHECK2-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])			// CHECK2-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])
	// CHECK2-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4			// CHECK2-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1
	// CHECK2-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*			// CHECK2-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
	// CHECK2-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0			// CHECK2-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0
	// CHECK2-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK2-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK2-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]			// CHECK2-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]
	// CHECK2-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2			// CHECK2-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2
	// CHECK2-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1			// CHECK2-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1
	// CHECK2-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0			// CHECK2-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0
	// CHECK2-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]			// CHECK2-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]
	// CHECK2-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0			// CHECK2-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0
	// CHECK2-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]			// CHECK2-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]
	// CHECK2-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]			// CHECK2-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]
	// CHECK2-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]			// CHECK2-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]
	// CHECK2-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK2-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK2: then:			// CHECK2: then:
	// CHECK2-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*			// CHECK2-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
	// CHECK2-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*			// CHECK2-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
	// CHECK2-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR5]]			// CHECK2-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[IFCONT:%.*]]			// CHECK2-NEXT: br label [[IFCONT:%.*]]
	// CHECK2: else:			// CHECK2: else:
	// CHECK2-NEXT: br label [[IFCONT]]			// CHECK2-NEXT: br label [[IFCONT]]
	// CHECK2: ifcont:			// CHECK2: ifcont:
	// CHECK2-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK2-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK2-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]			// CHECK2-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]
	// CHECK2-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK2-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK2: then4:			// CHECK2: then4:
	// CHECK2-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK2-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8			// CHECK2-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8
	// CHECK2-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK2-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*			// CHECK2-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*
	// CHECK2-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*			// CHECK2-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*
	// CHECK2-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*			// CHECK2-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*
	// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*			// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !19			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !21
	// CHECK2-NEXT: br label [[IFCONT6:%.*]]			// CHECK2-NEXT: br label [[IFCONT6:%.*]]
	// CHECK2: else5:			// CHECK2: else5:
	// CHECK2-NEXT: br label [[IFCONT6]]			// CHECK2-NEXT: br label [[IFCONT6]]
	// CHECK2: ifcont6:			// CHECK2: ifcont6:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func			// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31			// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
	// CHECK2-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5			// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
	// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
	// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[PRECOND:%.*]]			// CHECK2-NEXT: br label [[PRECOND:%.*]]
	// CHECK2: precond:			// CHECK2: precond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2			// CHECK2-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2
	// CHECK2-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
	// CHECK2: body:			// CHECK2: body:
	// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])
	// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0			// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
	// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK2: then:			// CHECK2: then:
	// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
	// CHECK2-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]			// CHECK2-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
	// CHECK2-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4			// CHECK2-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
	// CHECK2-NEXT: br label [[IFCONT:%.*]]			// CHECK2-NEXT: br label [[IFCONT:%.*]]
	// CHECK2: else:			// CHECK2: else:
	// CHECK2-NEXT: br label [[IFCONT]]			// CHECK2-NEXT: br label [[IFCONT]]
	// CHECK2: ifcont:			// CHECK2: ifcont:
	// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]			// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
	// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK2: then4:			// CHECK2: then4:
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
	// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*			// CHECK2-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
	// CHECK2-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[IFCONT6:%.*]]			// CHECK2-NEXT: br label [[IFCONT6:%.*]]
	// CHECK2: else5:			// CHECK2: else5:
	// CHECK2-NEXT: br label [[IFCONT6]]			// CHECK2-NEXT: br label [[IFCONT6]]
	// CHECK2: ifcont6:			// CHECK2: ifcont6:
	// CHECK2-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK2-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK2-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[PRECOND]]			// CHECK2-NEXT: br label [[PRECOND]]
	// CHECK2: exit:			// CHECK2: exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
	// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			// CHECK2-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			// CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0			// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1
	// CHECK2-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**			// CHECK2-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex"**			// CHECK2-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex"**
	// CHECK2-NEXT: [[TMP11:%.]] = load %"class.std::complex", %"class.std::complex"** [[TMP10]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP11:%.]] = load %"class.std::complex", %"class.std::complex"** [[TMP10]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex"* [[TMP11]]) #[[ATTR5]]			// CHECK2-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex"* [[TMP11]]) #[[ATTR2]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker
	// CHECK2-SAME: () #[[ATTR0]] {			// CHECK2-SAME: () #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[WORK_FN:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[WORK_FN:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1			// CHECK2-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1
	Show All 13 Lines
	// CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0			// CHECK2-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
	// CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]			// CHECK2-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]
	// CHECK2: .execute.parallel:			// CHECK2: .execute.parallel:
	// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK2-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK2-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8			// CHECK2-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8
	// CHECK2-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*)			// CHECK2-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*)
	// CHECK2-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]			// CHECK2-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]
	// CHECK2: .execute.fn:			// CHECK2: .execute.fn:
	// CHECK2-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5]]			// CHECK2-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]			// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]
	// CHECK2: .check.next:			// CHECK2: .check.next:
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*
	// CHECK2-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])			// CHECK2-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])
	// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL]]			// CHECK2-NEXT: br label [[DOTTERMINATE_PARALLEL]]
	// CHECK2: .terminate.parallel:			// CHECK2: .terminate.parallel:
	// CHECK2-NEXT: call void @__kmpc_kernel_end_parallel()			// CHECK2-NEXT: call void @__kmpc_kernel_end_parallel()
	// CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]]			// CHECK2-NEXT: br label [[DOTBARRIER_PARALLEL]]
	Show All 12 Lines
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK2-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]			// CHECK2-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
	// CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]			// CHECK2-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
	// CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]			// CHECK2-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]
	// CHECK2: .worker:			// CHECK2: .worker:
	// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker() #[[ATTR5]]			// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker() #[[ATTR2]]
	// CHECK2-NEXT: br label [[DOTEXIT:%.*]]			// CHECK2-NEXT: br label [[DOTEXIT:%.*]]
	// CHECK2: .mastercheck:			// CHECK2: .mastercheck:
	// CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK2-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK2-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1			// CHECK2-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
	// CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1			// CHECK2-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
	// CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1			// CHECK2-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1
	// CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]			// CHECK2-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
	// CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]			// CHECK2-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
	// CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]			// CHECK2-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
	// CHECK2: .master:			// CHECK2: .master:
	// CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK2-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK2-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]			// CHECK2-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
	// CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)			// CHECK2-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
	// CHECK2-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK2-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]			// CHECK2-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]			// CHECK2-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]
	// CHECK2: .termination.notifier:			// CHECK2: .termination.notifier:
	// CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1)			// CHECK2-NEXT: call void @__kmpc_kernel_deinit(i16 1)
	// CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)			// CHECK2-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
	// CHECK2-NEXT: br label [[DOTEXIT]]			// CHECK2-NEXT: br label [[DOTEXIT]]
	// CHECK2: .exit:			// CHECK2: .exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[IB:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca double, align 8			// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
	// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8			// CHECK2-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8
	// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK2-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*			// CHECK2-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
	// CHECK2-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK2-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*			// CHECK2-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
	// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)			// CHECK2-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)
	// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*			// CHECK2-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*
	// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*			// CHECK2-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99			// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99
	// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK2: cond.true:			// CHECK2: cond.true:
	// CHECK2-NEXT: br label [[COND_END:%.*]]			// CHECK2-NEXT: br label [[COND_END:%.*]]
	// CHECK2: cond.false:			// CHECK2: cond.false:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR2]]
	// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA20:![0-9]+]]			// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*			// CHECK2-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR2]]
	// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA20]]			// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]
	// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR7]]			// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR8]]
	// CHECK2-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*			// CHECK2-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4			// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
	// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4			// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4
	// CHECK2-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK2-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*			// CHECK2-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*
	// CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM_ON_STACK]] to i8*			// CHECK2-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM_ON_STACK]] to i8*
	// CHECK2-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK2-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex.0") @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP26]], i64 3)			// CHECK2-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex.0") @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP26]], i64 3)
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK2-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*			// CHECK2-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR2]]
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])
	// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])			// CHECK2-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC1ERKdS2_			// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC1ERKdS2_
	// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8			// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
	// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8			// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
	// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8			// CHECK2-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8
	// CHECK2-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR7]]			// CHECK2-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR8]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 13 Lines
	// CHECK2-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca double, align 8			// CHECK2-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
	// CHECK2-NEXT: [[REF_TMP6:%.*]] = alloca double, align 8			// CHECK2-NEXT: [[REF_TMP6:%.*]] = alloca double, align 8
	// CHECK2-NEXT: [[I7:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[I7:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: [[REF_TMP15:%.*]] = alloca double, align 8			// CHECK2-NEXT: [[REF_TMP15:%.*]] = alloca double, align 8
	// CHECK2-NEXT: [[REF_TMP16:%.*]] = alloca double, align 8			// CHECK2-NEXT: [[REF_TMP16:%.*]] = alloca double, align 8
	// CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8			// CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store %"class.std::complex.0"* [[PARTIAL_SUM]], %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex.0"* [[PARTIAL_SUM]], %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK2-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1			// CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
	// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1			// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
	// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1			// CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
	// CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*			// CHECK2-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK2: omp.precond.then:			// CHECK2: omp.precond.then:
	// CHECK2-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR2]]
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR2]]
	// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA20]]			// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]
	// CHECK2-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*			// CHECK2-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR2]]
	// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA20]]			// CHECK2-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]
	// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR7]]			// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR8]]
	// CHECK2-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*			// CHECK2-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK2-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*			// CHECK2-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
	// CHECK2: omp.dispatch.cond:			// CHECK2: omp.dispatch.cond:
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]			// CHECK2-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]
	// CHECK2-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK2-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK2: cond.true:			// CHECK2: cond.true:
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[COND_END:%.*]]			// CHECK2-NEXT: br label [[COND_END:%.*]]
	// CHECK2: cond.false:			// CHECK2: cond.false:
	// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1			// CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1
	// CHECK2-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]			// CHECK2-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]
	// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]
	// CHECK2: omp.dispatch.cleanup:			// CHECK2: omp.dispatch.cleanup:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1			// CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1
	// CHECK2-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]			// CHECK2-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]
	// CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK2: omp.inner.for.cond.cleanup:			// CHECK2: omp.inner.for.cond.cleanup:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1
	// CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]			// CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*			// CHECK2-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP40]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP40]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP41:%.]] = bitcast double [[REF_TMP15]] to i8*			// CHECK2-NEXT: [[TMP41:%.]] = bitcast double [[REF_TMP15]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP41]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP41]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double			// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double
	// CHECK2-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA20]]			// CHECK2-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]
	// CHECK2-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*			// CHECK2-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double			// CHECK2-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double
	// CHECK2-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA20]]			// CHECK2-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]
	// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR7]]			// CHECK2-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR8]]
	// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR8]]
	// CHECK2-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*			// CHECK2-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*			// CHECK2-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*			// CHECK2-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1			// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1
	// CHECK2-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]			// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]
	// CHECK2-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]			// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]
	// CHECK2-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])
	// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0			// CHECK2-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK2-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8			// CHECK2-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
	// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*			// CHECK2-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
	// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)			// CHECK2-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)
	// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1			// CHECK2-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
	// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
	// CHECK2: .omp.reduction.then:			// CHECK2: .omp.reduction.then:
	// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR8]]
	// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])			// CHECK2-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
	// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]			// CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
	// CHECK2: .omp.reduction.done:			// CHECK2: .omp.reduction.done:
	// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*			// CHECK2-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK2-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK2-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK2-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK2-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK2-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[OMP_PRECOND_END]]			// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK2: omp.precond.end:			// CHECK2: omp.precond.end:
	// CHECK2-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK2-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK2-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK2-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK2-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR5]]			// CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR2]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIdEpLIdEERS0_RKS_IT_E			// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIdEpLIdEERS0_RKS_IT_E
	// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR8]]
	// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA22:![0-9]+]]			// CHECK2-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]
	// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]			// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]
	// CHECK2-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK2-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR7]]			// CHECK2-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR8]]
	// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA24:![0-9]+]]			// CHECK2-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]
	// CHECK2-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]			// CHECK2-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]
	// CHECK2-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK2-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK2-NEXT: ret %"class.std::complex.0"* [[THIS1]]			// CHECK2-NEXT: ret %"class.std::complex.0"* [[THIS1]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5			// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5
	// CHECK2-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8			// CHECK2-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK2-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]			// CHECK2-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]
	// CHECK2-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK2-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*			// CHECK2-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*
	// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1			// CHECK2-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1
	// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*			// CHECK2-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*			// CHECK2-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*
	// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*			// CHECK2-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
	Show All 14 Lines
	// CHECK2-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16			// CHECK2-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
	// CHECK2-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])			// CHECK2-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])
	// CHECK2-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8			// CHECK2-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1			// CHECK2-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1
	// CHECK2-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1			// CHECK2-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1
	// CHECK2-NEXT: br label [[DOTSHUFFLE_PRE_COND]]			// CHECK2-NEXT: br label [[DOTSHUFFLE_PRE_COND]]
	// CHECK2: .shuffle.exit:			// CHECK2: .shuffle.exit:
	// CHECK2-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*			// CHECK2-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
	// CHECK2-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0			// CHECK2-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0
	// CHECK2-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK2-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK2-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]			// CHECK2-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]
	// CHECK2-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2			// CHECK2-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2
	// CHECK2-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1			// CHECK2-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1
	// CHECK2-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0			// CHECK2-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0
	// CHECK2-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]			// CHECK2-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]
	// CHECK2-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0			// CHECK2-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0
	// CHECK2-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]			// CHECK2-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]
	// CHECK2-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]			// CHECK2-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]
	// CHECK2-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]			// CHECK2-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]
	// CHECK2-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK2-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK2: then:			// CHECK2: then:
	// CHECK2-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*			// CHECK2-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
	// CHECK2-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*			// CHECK2-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
	// CHECK2-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR5]]			// CHECK2-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR2]]
	// CHECK2-NEXT: br label [[IFCONT:%.*]]			// CHECK2-NEXT: br label [[IFCONT:%.*]]
	// CHECK2: else:			// CHECK2: else:
	// CHECK2-NEXT: br label [[IFCONT]]			// CHECK2-NEXT: br label [[IFCONT]]
	// CHECK2: ifcont:			// CHECK2: ifcont:
	// CHECK2-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK2-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK2-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]			// CHECK2-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]
	// CHECK2-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK2-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK2: then4:			// CHECK2: then4:
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8			// CHECK2-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
	// CHECK2-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK2-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8			// CHECK2-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8
	// CHECK2-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*			// CHECK2-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*
	// CHECK2-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*			// CHECK2-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*
	// CHECK2-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*			// CHECK2-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*
	// CHECK2-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*			// CHECK2-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !25			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !27
	// CHECK2-NEXT: br label [[IFCONT6:%.*]]			// CHECK2-NEXT: br label [[IFCONT6:%.*]]
	// CHECK2: else5:			// CHECK2: else5:
	// CHECK2-NEXT: br label [[IFCONT6]]			// CHECK2-NEXT: br label [[IFCONT6]]
	// CHECK2: ifcont6:			// CHECK2: ifcont6:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6			// CHECK2-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6
	// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK2-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31			// CHECK2-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
	// CHECK2-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK2-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5			// CHECK2-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
	// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
	// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[PRECOND:%.*]]			// CHECK2-NEXT: br label [[PRECOND:%.*]]
	// CHECK2: precond:			// CHECK2: precond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4			// CHECK2-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4
	// CHECK2-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
	// CHECK2: body:			// CHECK2: body:
	// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0			// CHECK2-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
	// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK2-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK2: then:			// CHECK2: then:
	// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK2-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
	// CHECK2-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]			// CHECK2-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
	// CHECK2-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4			// CHECK2-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
	// CHECK2-NEXT: br label [[IFCONT:%.*]]			// CHECK2-NEXT: br label [[IFCONT:%.*]]
	// CHECK2: else:			// CHECK2: else:
	// CHECK2-NEXT: br label [[IFCONT]]			// CHECK2-NEXT: br label [[IFCONT]]
	// CHECK2: ifcont:			// CHECK2: ifcont:
	// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]			// CHECK2-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
	// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK2-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK2: then4:			// CHECK2: then4:
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
	// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK2-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*			// CHECK2-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
	// CHECK2-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[IFCONT6:%.*]]			// CHECK2-NEXT: br label [[IFCONT6:%.*]]
	// CHECK2: else5:			// CHECK2: else5:
	// CHECK2-NEXT: br label [[IFCONT6]]			// CHECK2-NEXT: br label [[IFCONT6]]
	// CHECK2: ifcont6:			// CHECK2: ifcont6:
	// CHECK2-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK2-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK2-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: br label [[PRECOND]]			// CHECK2-NEXT: br label [[PRECOND]]
	// CHECK2: exit:			// CHECK2: exit:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			// CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK2-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK2-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			// CHECK2-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA17]]			// CHECK2-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA19]]
	// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			// CHECK2-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			// CHECK2-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0			// CHECK2-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0
	// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**			// CHECK2-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1
	// CHECK2-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**			// CHECK2-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex.0"**			// CHECK2-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex.0"**
	// CHECK2-NEXT: [[TMP11:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[TMP10]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP11:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[TMP10]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex.0"* [[TMP11]]) #[[ATTR5]]			// CHECK2-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex.0"* [[TMP11]]) #[[ATTR2]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC2ERKfS2_			// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC2ERKfS2_
	// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8			// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
	// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8			// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
	// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP1:%.]] = load float, float [[TMP0]], align 4, !tbaa [[TBAA12]]			// CHECK2-NEXT: [[TMP1:%.]] = load float, float [[TMP0]], align 4, !tbaa [[TBAA14]]
	// CHECK2-NEXT: store float [[TMP1]], float* [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK2-NEXT: store float [[TMP1]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP2:%.]] = load float, float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP2:%.]] = load float, float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP3:%.]] = load float, float [[TMP2]], align 4, !tbaa [[TBAA12]]			// CHECK2-NEXT: [[TMP3:%.]] = load float, float [[TMP2]], align 4, !tbaa [[TBAA14]]
	// CHECK2-NEXT: store float [[TMP3]], float* [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK2-NEXT: store float [[TMP3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4realEv			// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4realEv
	// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP0:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK2-NEXT: [[TMP0:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK2-NEXT: ret float [[TMP0]]			// CHECK2-NEXT: ret float [[TMP0]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4imagEv			// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4imagEv
	// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP0:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK2-NEXT: [[TMP0:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK2-NEXT: ret float [[TMP0]]			// CHECK2-NEXT: ret float [[TMP0]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC2ERKdS2_			// CHECK2-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC2ERKdS2_
	// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8			// CHECK2-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
	// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8			// CHECK2-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
	// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP1:%.]] = load double, double [[TMP0]], align 8, !tbaa [[TBAA20]]			// CHECK2-NEXT: [[TMP1:%.]] = load double, double [[TMP0]], align 8, !tbaa [[TBAA22]]
	// CHECK2-NEXT: store double [[TMP1]], double* [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK2-NEXT: store double [[TMP1]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP2:%.]] = load double, double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: [[TMP2:%.]] = load double, double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[TMP3:%.]] = load double, double [[TMP2]], align 8, !tbaa [[TBAA20]]			// CHECK2-NEXT: [[TMP3:%.]] = load double, double [[TMP2]], align 8, !tbaa [[TBAA22]]
	// CHECK2-NEXT: store double [[TMP3]], double* [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK2-NEXT: store double [[TMP3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4realEv			// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4realEv
	// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK2-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP0:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK2-NEXT: [[TMP0:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK2-NEXT: ret double [[TMP0]]			// CHECK2-NEXT: ret double [[TMP0]]
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4imagEv			// CHECK2-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4imagEv
	// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK2-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK2-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK2-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP0:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK2-NEXT: [[TMP0:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK2-NEXT: ret double [[TMP0]]			// CHECK2-NEXT: ret double [[TMP0]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker
	// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[WORK_FN:%.]] = alloca i8, align 8			// CHECK3-NEXT: [[WORK_FN:%.]] = alloca i8, align 8
	// CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1			// CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1
	Show All 13 Lines
	// CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0			// CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
	// CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]			// CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]
	// CHECK3: .execute.parallel:			// CHECK3: .execute.parallel:
	// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])			// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3:[0-9]+]])
	// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8			// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8
	// CHECK3-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)			// CHECK3-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
	// CHECK3-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]			// CHECK3-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]
	// CHECK3: .execute.fn:			// CHECK3: .execute.fn:
	// CHECK3-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5:[0-9]+]]			// CHECK3-NEXT: call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
	// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]			// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]
	// CHECK3: .check.next:			// CHECK3: .check.next:
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*
	// CHECK3-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])			// CHECK3-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])
	// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL]]			// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL]]
	// CHECK3: .terminate.parallel:			// CHECK3: .terminate.parallel:
	// CHECK3-NEXT: call void @__kmpc_kernel_end_parallel()			// CHECK3-NEXT: call void @__kmpc_kernel_end_parallel()
	// CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]]			// CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]]
	Show All 12 Lines
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]			// CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
	// CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]			// CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
	// CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]			// CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]
	// CHECK3: .worker:			// CHECK3: .worker:
	// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker() #[[ATTR5]]			// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIfEvv_l19_worker() #[[ATTR2]]
	// CHECK3-NEXT: br label [[DOTEXIT:%.*]]			// CHECK3-NEXT: br label [[DOTEXIT:%.*]]
	// CHECK3: .mastercheck:			// CHECK3: .mastercheck:
	// CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1			// CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
	// CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1			// CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
	// CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1			// CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1
	// CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]			// CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
	// CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]			// CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
	// CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]			// CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
	// CHECK3: .master:			// CHECK3: .master:
	// CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]			// CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
	// CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)			// CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
	// CHECK3-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK3-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA6:![0-9]+]]			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8:![0-9]+]]
	// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]			// CHECK3-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]			// CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]
	// CHECK3: .termination.notifier:			// CHECK3: .termination.notifier:
	// CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1)			// CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1)
	// CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)			// CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
	// CHECK3-NEXT: br label [[DOTEXIT]]			// CHECK3-NEXT: br label [[DOTEXIT]]
	// CHECK3: .exit:			// CHECK3: .exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca float, align 4			// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
	// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4			// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca float, align 4
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10:![0-9]+]]			// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12:![0-9]+]]
	// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK3-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*			// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
	// CHECK3-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK3-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*			// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
	// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)			// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 8)
	// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*			// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex"*
	// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*			// CHECK3-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99			// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99
	// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK3: cond.true:			// CHECK3: cond.true:
	// CHECK3-NEXT: br label [[COND_END:%.*]]			// CHECK3-NEXT: br label [[COND_END:%.*]]
	// CHECK3: cond.false:			// CHECK3: cond.false:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK3: omp.inner.for.cond.cleanup:			// CHECK3: omp.inner.for.cond.cleanup:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP14:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP14]]) #[[ATTR2]]
	// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA12:![0-9]+]]			// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14:![0-9]+]]
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*			// CHECK3-NEXT: [[TMP15:%.]] = bitcast float [[REF_TMP2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP15]]) #[[ATTR2]]
	// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA12]]			// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP2]], align 4, !tbaa [[TBAA14]]
	// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR7:[0-9]+]]			// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM_ON_STACK]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP2]]) #[[ATTR8:[0-9]+]]
	// CHECK3-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*			// CHECK3-NEXT: [[TMP16:%.]] = bitcast float [[REF_TMP2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP17:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4			// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
	// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4			// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4
	// CHECK3-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*			// CHECK3-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*
	// CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK3-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*			// CHECK3-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*
	// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM_ON_STACK]] to i8*			// CHECK3-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM_ON_STACK]] to i8*
	// CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex") @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP26]], i64 3)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex") @__omp_outlined__1 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8), i8* [[TMP26]], i64 3)
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK3-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*			// CHECK3-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC1ERKfS2_			// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC1ERKfS2_
	// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8			// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
	// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8			// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
	// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8
	// CHECK3-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load float, float** [[__IM_ADDR]], align 8
	// CHECK3-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR7]]			// CHECK3-NEXT: call void @_ZNSt7complexIfEC2ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS1]], float* nonnull align 4 dereferenceable(4) [[TMP0]], float* nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR8]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 13 Lines
	// CHECK3-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex", align 4			// CHECK3-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex", align 4
	// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca float, align 4			// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca float, align 4
	// CHECK3-NEXT: [[REF_TMP6:%.*]] = alloca float, align 4			// CHECK3-NEXT: [[REF_TMP6:%.*]] = alloca float, align 4
	// CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex", align 4			// CHECK3-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex", align 4
	// CHECK3-NEXT: [[REF_TMP15:%.*]] = alloca float, align 4			// CHECK3-NEXT: [[REF_TMP15:%.*]] = alloca float, align 4
	// CHECK3-NEXT: [[REF_TMP16:%.*]] = alloca float, align 4			// CHECK3-NEXT: [[REF_TMP16:%.*]] = alloca float, align 4
	// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8			// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store %"class.std::complex"* [[PARTIAL_SUM]], %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex"* [[PARTIAL_SUM]], %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1			// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
	// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1			// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
	// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1			// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
	// CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*			// CHECK3-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK3: omp.precond.then:			// CHECK3: omp.precond.then:
	// CHECK3-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP21]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP22:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP22]]) #[[ATTR2]]
	// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA12]]			// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP]], align 4, !tbaa [[TBAA14]]
	// CHECK3-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*			// CHECK3-NEXT: [[TMP23:%.]] = bitcast float [[REF_TMP6]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP23]]) #[[ATTR2]]
	// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA12]]			// CHECK3-NEXT: store float 0.000000e+00, float* [[REF_TMP6]], align 4, !tbaa [[TBAA14]]
	// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR7]]			// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], float* nonnull align 4 dereferenceable(4) [[REF_TMP]], float* nonnull align 4 dereferenceable(4) [[REF_TMP6]]) #[[ATTR8]]
	// CHECK3-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*			// CHECK3-NEXT: [[TMP24:%.]] = bitcast float [[REF_TMP6]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP24]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP25:%.]] = bitcast float [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP25]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*			// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
	// CHECK3: omp.dispatch.cond:			// CHECK3: omp.dispatch.cond:
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK3: cond.true:			// CHECK3: cond.true:
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[COND_END:%.*]]			// CHECK3-NEXT: br label [[COND_END:%.*]]
	// CHECK3: cond.false:			// CHECK3: cond.false:
	// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1			// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1
	// CHECK3-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]			// CHECK3-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]
	// CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]			// CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]
	// CHECK3: omp.dispatch.cleanup:			// CHECK3: omp.dispatch.cleanup:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_END:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_END:%.*]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1			// CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1
	// CHECK3-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]			// CHECK3-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]
	// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK3: omp.inner.for.cond.cleanup:			// CHECK3: omp.inner.for.cond.cleanup:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1
	// CHECK3-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]			// CHECK3-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*			// CHECK3-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP40]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP40]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP41:%.]] = bitcast float [[REF_TMP15]] to i8*			// CHECK3-NEXT: [[TMP41:%.]] = bitcast float [[REF_TMP15]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP41]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP41]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float			// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to float
	// CHECK3-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA12]]			// CHECK3-NEXT: store float [[CONV]], float* [[REF_TMP15]], align 4, !tbaa [[TBAA14]]
	// CHECK3-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*			// CHECK3-NEXT: [[TMP43:%.]] = bitcast float [[REF_TMP16]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP43]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float			// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to float
	// CHECK3-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA12]]			// CHECK3-NEXT: store float [[CONV17]], float* [[REF_TMP16]], align 4, !tbaa [[TBAA14]]
	// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR7]]			// CHECK3-NEXT: call void @_ZNSt7complexIfEC1ERKfS2_(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]], float* nonnull align 4 dereferenceable(4) [[REF_TMP15]], float* nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR8]]
	// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[REF_TMP14]]) #[[ATTR8]]
	// CHECK3-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*			// CHECK3-NEXT: [[TMP45:%.]] = bitcast float [[REF_TMP16]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP45]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*			// CHECK3-NEXT: [[TMP46:%.]] = bitcast float [[REF_TMP15]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP46]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*			// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[REF_TMP14]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP47]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1			// CHECK3-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1
	// CHECK3-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]			// CHECK3-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]
	// CHECK3-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]			// CHECK3-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]
	// CHECK3-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])
	// CHECK3-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0			// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8			// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
	// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*			// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
	// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)			// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func, void (i8, i32) @_omp_reduction_inter_warp_copy_func)
	// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1			// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
	// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
	// CHECK3: .omp.reduction.then:			// CHECK3: .omp.reduction.then:
	// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 4 dereferenceable(8) %"class.std::complex" @_ZNSt7complexIfEpLIfEERS0_RKS_IT_E(%"class.std::complex"* nonnull align 4 dereferenceable(8) [[TMP2]], %"class.std::complex"* nonnull align 4 dereferenceable(8) [[PARTIAL_SUM5]]) #[[ATTR8]]
	// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])			// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
	// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]			// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
	// CHECK3: .omp.reduction.done:			// CHECK3: .omp.reduction.done:
	// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*			// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*			// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex" [[PARTIAL_SUM5]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP63]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[OMP_PRECOND_END]]			// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK3: omp.precond.end:			// CHECK3: omp.precond.end:
	// CHECK3-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK3-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK3-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK3-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR2]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIfEpLIfEERS0_RKS_IT_E			// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIfEpLIfEERS0_RKS_IT_E
	// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR4:[0-9]+]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], %"class.std::complex" nonnull align 4 dereferenceable(8) [[__C:%.*]]) #[[ATTR5:[0-9]+]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex"* [[__C]], %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL:%.]] = call float @_ZNKSt7complexIfE4realEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP0]]) #[[ATTR8]]
	// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA14:![0-9]+]]			// CHECK3-NEXT: [[TMP1:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16:![0-9]+]]
	// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]			// CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CALL]]
	// CHECK3-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK3-NEXT: store float [[ADD]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex", %"class.std::complex"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL2:%.]] = call float @_ZNKSt7complexIfE4imagEv(%"class.std::complex" nonnull align 4 dereferenceable(8) [[TMP2]]) #[[ATTR8]]
	// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA16:![0-9]+]]			// CHECK3-NEXT: [[TMP3:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18:![0-9]+]]
	// CHECK3-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]			// CHECK3-NEXT: [[ADD3:%.*]] = fadd float [[TMP3]], [[CALL2]]
	// CHECK3-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK3-NEXT: store float [[ADD3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK3-NEXT: ret %"class.std::complex"* [[THIS1]]			// CHECK3-NEXT: ret %"class.std::complex"* [[THIS1]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func			// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func
	// CHECK3-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8			// CHECK3-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK3-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex", align 4			// CHECK3-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex", align 4
	// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA17:![0-9]+]]			// CHECK3-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA19:![0-9]+]]
	// CHECK3-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]			// CHECK3-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]
	// CHECK3-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK3-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*			// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex"*
	// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1			// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex", %"class.std::complex" [[TMP12]], i64 1
	// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*			// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex" [[TMP13]] to i8*
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*			// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex" [[TMP12]] to i64*
	// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*			// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
	// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP15]], align 4
	// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK3-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16			// CHECK3-NEXT: [[TMP18:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
	// CHECK3-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])			// CHECK3-NEXT: [[TMP19:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP17]], i16 [[TMP7]], i16 [[TMP18]])
	// CHECK3-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4			// CHECK3-NEXT: store i64 [[TMP19]], i64* [[TMP16]], align 4
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr i64, i64 [[TMP15]], i64 1
	// CHECK3-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1			// CHECK3-NEXT: [[TMP21:%.]] = getelementptr i64, i64 [[TMP16]], i64 1
	// CHECK3-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*			// CHECK3-NEXT: [[TMP22:%.]] = bitcast %"class.std::complex" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
	// CHECK3-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP22]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0			// CHECK3-NEXT: [[TMP23:%.*]] = icmp eq i16 [[TMP8]], 0
	// CHECK3-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK3-NEXT: [[TMP24:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK3-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[TMP25:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]			// CHECK3-NEXT: [[TMP26:%.*]] = and i1 [[TMP24]], [[TMP25]]
	// CHECK3-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2			// CHECK3-NEXT: [[TMP27:%.*]] = icmp eq i16 [[TMP8]], 2
	// CHECK3-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1			// CHECK3-NEXT: [[TMP28:%.*]] = and i16 [[TMP6]], 1
	// CHECK3-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0			// CHECK3-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP28]], 0
	// CHECK3-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]			// CHECK3-NEXT: [[TMP30:%.*]] = and i1 [[TMP27]], [[TMP29]]
	// CHECK3-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0			// CHECK3-NEXT: [[TMP31:%.*]] = icmp sgt i16 [[TMP7]], 0
	// CHECK3-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]			// CHECK3-NEXT: [[TMP32:%.*]] = and i1 [[TMP30]], [[TMP31]]
	// CHECK3-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]			// CHECK3-NEXT: [[TMP33:%.*]] = or i1 [[TMP23]], [[TMP26]]
	// CHECK3-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]			// CHECK3-NEXT: [[TMP34:%.*]] = or i1 [[TMP33]], [[TMP32]]
	// CHECK3-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK3-NEXT: br i1 [[TMP34]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK3: then:			// CHECK3: then:
	// CHECK3-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*			// CHECK3-NEXT: [[TMP35:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
	// CHECK3-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*			// CHECK3-NEXT: [[TMP36:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
	// CHECK3-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR5]]			// CHECK3-NEXT: call void @"_omp$reduction$reduction_func"(i8* [[TMP35]], i8* [[TMP36]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[IFCONT:%.*]]			// CHECK3-NEXT: br label [[IFCONT:%.*]]
	// CHECK3: else:			// CHECK3: else:
	// CHECK3-NEXT: br label [[IFCONT]]			// CHECK3-NEXT: br label [[IFCONT]]
	// CHECK3: ifcont:			// CHECK3: ifcont:
	// CHECK3-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK3-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK3-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]			// CHECK3-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]]
	// CHECK3-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK3-NEXT: br i1 [[TMP39]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK3: then4:			// CHECK3: then4:
	// CHECK3-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK3-NEXT: [[TMP40:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8			// CHECK3-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP40]], align 8
	// CHECK3-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK3-NEXT: [[TMP42:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK3-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK3-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*			// CHECK3-NEXT: [[TMP44:%.]] = bitcast i8 [[TMP41]] to %"class.std::complex"*
	// CHECK3-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*			// CHECK3-NEXT: [[TMP45:%.]] = bitcast i8 [[TMP43]] to %"class.std::complex"*
	// CHECK3-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*			// CHECK3-NEXT: [[TMP46:%.]] = bitcast %"class.std::complex" [[TMP45]] to i8*
	// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*			// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex" [[TMP44]] to i8*
	// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !19			// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 8, i1 false), !tbaa.struct !21
	// CHECK3-NEXT: br label [[IFCONT6:%.*]]			// CHECK3-NEXT: br label [[IFCONT6:%.*]]
	// CHECK3: else5:			// CHECK3: else5:
	// CHECK3-NEXT: br label [[IFCONT6]]			// CHECK3-NEXT: br label [[IFCONT6]]
	// CHECK3: ifcont6:			// CHECK3: ifcont6:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func			// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func
	// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31			// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
	// CHECK3-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5			// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
	// CHECK3-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
	// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[PRECOND:%.*]]			// CHECK3-NEXT: br label [[PRECOND:%.*]]
	// CHECK3: precond:			// CHECK3: precond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2			// CHECK3-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 2
	// CHECK3-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
	// CHECK3: body:			// CHECK3: body:
	// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 [[TMP2]])
	// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0			// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
	// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK3: then:			// CHECK3: then:
	// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
	// CHECK3-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]			// CHECK3-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
	// CHECK3-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4			// CHECK3-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
	// CHECK3-NEXT: br label [[IFCONT:%.*]]			// CHECK3-NEXT: br label [[IFCONT:%.*]]
	// CHECK3: else:			// CHECK3: else:
	// CHECK3-NEXT: br label [[IFCONT]]			// CHECK3-NEXT: br label [[IFCONT]]
	// CHECK3: ifcont:			// CHECK3: ifcont:
	// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]			// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
	// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK3: then4:			// CHECK3: then4:
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
	// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*			// CHECK3-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
	// CHECK3-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[IFCONT6:%.*]]			// CHECK3-NEXT: br label [[IFCONT6:%.*]]
	// CHECK3: else5:			// CHECK3: else5:
	// CHECK3-NEXT: br label [[IFCONT6]]			// CHECK3-NEXT: br label [[IFCONT6]]
	// CHECK3: ifcont6:			// CHECK3: ifcont6:
	// CHECK3-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK3-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK3-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[PRECOND]]			// CHECK3-NEXT: br label [[PRECOND]]
	// CHECK3: exit:			// CHECK3: exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
	// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			// CHECK3-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0			// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1
	// CHECK3-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**			// CHECK3-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex"**			// CHECK3-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex"**
	// CHECK3-NEXT: [[TMP11:%.]] = load %"class.std::complex", %"class.std::complex"** [[TMP10]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP11:%.]] = load %"class.std::complex", %"class.std::complex"** [[TMP10]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex"* [[TMP11]]) #[[ATTR5]]			// CHECK3-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex"* [[TMP11]]) #[[ATTR2]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker
	// CHECK3-SAME: () #[[ATTR0]] {			// CHECK3-SAME: () #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[WORK_FN:%.]] = alloca i8, align 8			// CHECK3-NEXT: [[WORK_FN:%.]] = alloca i8, align 8
	// CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1			// CHECK3-NEXT: [[EXEC_STATUS:%.*]] = alloca i8, align 1
	Show All 13 Lines
	// CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0			// CHECK3-NEXT: [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
	// CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]			// CHECK3-NEXT: br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.]], label [[DOTBARRIER_PARALLEL:%.]]
	// CHECK3: .execute.parallel:			// CHECK3: .execute.parallel:
	// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8			// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8** [[WORK_FN]], align 8
	// CHECK3-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*)			// CHECK3-NEXT: [[WORK_MATCH:%.]] = icmp eq i8 [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8*)
	// CHECK3-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]			// CHECK3-NEXT: br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.]], label [[DOTCHECK_NEXT:%.]]
	// CHECK3: .execute.fn:			// CHECK3: .execute.fn:
	// CHECK3-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR5]]			// CHECK3-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]			// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL:%.*]]
	// CHECK3: .check.next:			// CHECK3: .check.next:
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast i8 [[TMP2]] to void (i16, i32)*
	// CHECK3-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])			// CHECK3-NEXT: call void [[TMP6]](i16 0, i32 [[TMP4]])
	// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL]]			// CHECK3-NEXT: br label [[DOTTERMINATE_PARALLEL]]
	// CHECK3: .terminate.parallel:			// CHECK3: .terminate.parallel:
	// CHECK3-NEXT: call void @__kmpc_kernel_end_parallel()			// CHECK3-NEXT: call void @__kmpc_kernel_end_parallel()
	// CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]]			// CHECK3-NEXT: br label [[DOTBARRIER_PARALLEL]]
	Show All 12 Lines
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK3-NEXT: [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]			// CHECK3-NEXT: [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
	// CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]			// CHECK3-NEXT: [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
	// CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]			// CHECK3-NEXT: br i1 [[TMP0]], label [[DOTWORKER:%.]], label [[DOTMASTERCHECK:%.]]
	// CHECK3: .worker:			// CHECK3: .worker:
	// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker() #[[ATTR5]]			// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z17complex_reductionIdEvv_l19_worker() #[[ATTR2]]
	// CHECK3-NEXT: br label [[DOTEXIT:%.*]]			// CHECK3-NEXT: br label [[DOTEXIT:%.*]]
	// CHECK3: .mastercheck:			// CHECK3: .mastercheck:
	// CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK3-NEXT: [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK3-NEXT: [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1			// CHECK3-NEXT: [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
	// CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1			// CHECK3-NEXT: [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
	// CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1			// CHECK3-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], -1
	// CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]			// CHECK3-NEXT: [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
	// CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]			// CHECK3-NEXT: [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
	// CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]			// CHECK3-NEXT: br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
	// CHECK3: .master:			// CHECK3: .master:
	// CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()			// CHECK3-NEXT: [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()			// CHECK3-NEXT: [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
	// CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]			// CHECK3-NEXT: [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
	// CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)			// CHECK3-NEXT: call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
	// CHECK3-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK3-NEXT: [[TMP5:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5]]			// CHECK3-NEXT: call void @__omp_outlined__2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]			// CHECK3-NEXT: br label [[DOTTERMINATION_NOTIFIER:%.*]]
	// CHECK3: .termination.notifier:			// CHECK3: .termination.notifier:
	// CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1)			// CHECK3-NEXT: call void @__kmpc_kernel_deinit(i16 1)
	// CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)			// CHECK3-NEXT: call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
	// CHECK3-NEXT: br label [[DOTEXIT]]			// CHECK3-NEXT: br label [[DOTEXIT]]
	// CHECK3: .exit:			// CHECK3: .exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__2
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[IB:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca double, align 8			// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
	// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8			// CHECK3-NEXT: [[REF_TMP2:%.*]] = alloca double, align 8
	// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8			// CHECK3-NEXT: [[CAPTURED_VARS_ADDRS:%.]] = alloca [3 x i8], align 8
	// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK3-NEXT: [[ISTART:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*			// CHECK3-NEXT: [[ISTART_ON_STACK:%.]] = bitcast i8 [[ISTART]] to i32*
	// CHECK3-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)			// CHECK3-NEXT: [[IEND:%.]] = call i8 @__kmpc_alloc_shared(i64 4)
	// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*			// CHECK3-NEXT: [[IEND_ON_STACK:%.]] = bitcast i8 [[IEND]] to i32*
	// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)			// CHECK3-NEXT: [[PARTIAL_SUM:%.]] = call i8 @__kmpc_alloc_shared(i64 16)
	// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*			// CHECK3-NEXT: [[PARTIAL_SUM_ON_STACK:%.]] = bitcast i8 [[PARTIAL_SUM]] to %"class.std::complex.0"*
	// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP0:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP1:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP1]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP2:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP2]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 99, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*			// CHECK3-NEXT: [[TMP5:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP5]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP6]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99			// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 99
	// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK3: cond.true:			// CHECK3: cond.true:
	// CHECK3-NEXT: br label [[COND_END:%.*]]			// CHECK3-NEXT: br label [[COND_END:%.*]]
	// CHECK3: cond.false:			// CHECK3: cond.false:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK3: omp.inner.for.cond.cleanup:			// CHECK3: omp.inner.for.cond.cleanup:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD]], i32* [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP14:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP14]]) #[[ATTR2]]
	// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA20:![0-9]+]]			// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22:![0-9]+]]
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*			// CHECK3-NEXT: [[TMP15:%.]] = bitcast double [[REF_TMP2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP15]]) #[[ATTR2]]
	// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA20]]			// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP2]], align 8, !tbaa [[TBAA22]]
	// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR7]]			// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM_ON_STACK]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP2]]) #[[ATTR8]]
	// CHECK3-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*			// CHECK3-NEXT: [[TMP16:%.]] = bitcast double [[REF_TMP2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP17:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4			// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP18]], 4
	// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[MUL3]], i32* [[ISTART_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[IB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4			// CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[ADD4]], 4
	// CHECK3-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[MUL5]], i32* [[IEND_ON_STACK]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*			// CHECK3-NEXT: [[TMP21:%.]] = bitcast i32 [[ISTART_ON_STACK]] to i8*
	// CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP21]], i8** [[TMP20]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1			// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
	// CHECK3-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*			// CHECK3-NEXT: [[TMP23:%.]] = bitcast i32 [[IEND_ON_STACK]] to i8*
	// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP23]], i8** [[TMP22]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2			// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM_ON_STACK]] to i8*			// CHECK3-NEXT: [[TMP25:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM_ON_STACK]] to i8*
	// CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP25]], i8** [[TMP24]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**			// CHECK3-NEXT: [[TMP26:%.]] = bitcast [3 x i8]* [[CAPTURED_VARS_ADDRS]] to i8**
	// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex.0") @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP26]], i64 3)			// CHECK3-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32, i32, i32, i32, %"class.std::complex.0") @__omp_outlined__3 to i8), i8 bitcast (void (i16, i32)* @__omp_outlined__3_wrapper to i8), i8* [[TMP26]], i64 3)
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP7]])
	// CHECK3-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*			// CHECK3-NEXT: [[TMP28:%.]] = bitcast i32 [[IB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP28]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP29:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP29]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP30:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP30]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP31:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP31]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP32:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP32]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP33:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP33]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[PARTIAL_SUM]])
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[IEND]])
	// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])			// CHECK3-NEXT: call void @__kmpc_free_shared(i8* [[ISTART]])
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC1ERKdS2_			// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC1ERKdS2_
	// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8			// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
	// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8			// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
	// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8			// CHECK3-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8
	// CHECK3-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8			// CHECK3-NEXT: [[TMP1:%.]] = load double, double** [[__IM_ADDR]], align 8
	// CHECK3-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR7]]			// CHECK3-NEXT: call void @_ZNSt7complexIdEC2ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS1]], double* nonnull align 8 dereferenceable(8) [[TMP0]], double* nonnull align 8 dereferenceable(8) [[TMP1]]) #[[ATTR8]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ISTART:%.]], i32 nonnull align 4 dereferenceable(4) [[IEND:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[PARTIAL_SUM:%.*]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	Show All 13 Lines
	// CHECK3-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[PARTIAL_SUM5:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca double, align 8			// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca double, align 8
	// CHECK3-NEXT: [[REF_TMP6:%.*]] = alloca double, align 8			// CHECK3-NEXT: [[REF_TMP6:%.*]] = alloca double, align 8
	// CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[I7:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[REF_TMP14:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: [[REF_TMP15:%.*]] = alloca double, align 8			// CHECK3-NEXT: [[REF_TMP15:%.*]] = alloca double, align 8
	// CHECK3-NEXT: [[REF_TMP16:%.*]] = alloca double, align 8			// CHECK3-NEXT: [[REF_TMP16:%.*]] = alloca double, align 8
	// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8			// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[ISTART]], i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i32* [[IEND]], i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store %"class.std::complex.0"* [[PARTIAL_SUM]], %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex.0"* [[PARTIAL_SUM]], %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP0:%.]] = load i32, i32** [[ISTART_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[IEND_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[PARTIAL_SUM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP3:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP3]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK3-NEXT: [[TMP6:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP6]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[TMP1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP8]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1			// CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
	// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1			// CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
	// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1			// CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
	// CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast i32 [[I]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP11]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP12]], i32* [[I]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*			// CHECK3-NEXT: [[TMP13:%.]] = bitcast i32 [[I]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP13]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP14]], [[TMP15]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]]
	// CHECK3: omp.precond.then:			// CHECK3: omp.precond.then:
	// CHECK3-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP16:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP16]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP17:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP17]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP19:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP19]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP20:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP20]]) #[[ATTR2]]
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK3-NEXT: [[TMP21:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP21]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP22:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP22]]) #[[ATTR2]]
	// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA20]]			// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP]], align 8, !tbaa [[TBAA22]]
	// CHECK3-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*			// CHECK3-NEXT: [[TMP23:%.]] = bitcast double [[REF_TMP6]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP23]]) #[[ATTR2]]
	// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA20]]			// CHECK3-NEXT: store double 0.000000e+00, double* [[REF_TMP6]], align 8, !tbaa [[TBAA22]]
	// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR7]]			// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], double* nonnull align 8 dereferenceable(8) [[REF_TMP]], double* nonnull align 8 dereferenceable(8) [[REF_TMP6]]) #[[ATTR8]]
	// CHECK3-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*			// CHECK3-NEXT: [[TMP24:%.]] = bitcast double [[REF_TMP6]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP24]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*			// CHECK3-NEXT: [[TMP25:%.]] = bitcast double [[REF_TMP]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP25]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*			// CHECK3-NEXT: [[TMP26:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP26]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[TMP27]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB2]], i32 [[TMP28]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
	// CHECK3: omp.dispatch.cond:			// CHECK3: omp.dispatch.cond:
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[TMP29]], [[TMP30]]
	// CHECK3-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]			// CHECK3-NEXT: br i1 [[CMP8]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]]
	// CHECK3: cond.true:			// CHECK3: cond.true:
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[COND_END:%.*]]			// CHECK3-NEXT: br label [[COND_END:%.*]]
	// CHECK3: cond.false:			// CHECK3: cond.false:
	// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP31]], [[COND_TRUE]] ], [ [[TMP32]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1			// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP35]], 1
	// CHECK3-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]			// CHECK3-NEXT: [[CMP10:%.*]] = icmp ult i32 [[TMP34]], [[ADD9]]
	// CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]			// CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]]
	// CHECK3: omp.dispatch.cleanup:			// CHECK3: omp.dispatch.cleanup:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_END:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_END:%.*]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1			// CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP37]], 1
	// CHECK3-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]			// CHECK3-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP36]], [[ADD11]]
	// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]			// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]]
	// CHECK3: omp.inner.for.cond.cleanup:			// CHECK3: omp.inner.for.cond.cleanup:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP39]], 1
	// CHECK3-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]			// CHECK3-NEXT: [[ADD13:%.*]] = add i32 [[TMP38]], [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD13]], i32* [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*			// CHECK3-NEXT: [[TMP40:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP40]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP40]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP41:%.]] = bitcast double [[REF_TMP15]] to i8*			// CHECK3-NEXT: [[TMP41:%.]] = bitcast double [[REF_TMP15]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP41]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP41]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double			// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP42]] to double
	// CHECK3-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA20]]			// CHECK3-NEXT: store double [[CONV]], double* [[REF_TMP15]], align 8, !tbaa [[TBAA22]]
	// CHECK3-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*			// CHECK3-NEXT: [[TMP43:%.]] = bitcast double [[REF_TMP16]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[TMP43]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[I7]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double			// CHECK3-NEXT: [[CONV17:%.*]] = sitofp i32 [[TMP44]] to double
	// CHECK3-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA20]]			// CHECK3-NEXT: store double [[CONV17]], double* [[REF_TMP16]], align 8, !tbaa [[TBAA22]]
	// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR7]]			// CHECK3-NEXT: call void @_ZNSt7complexIdEC1ERKdS2_(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]], double* nonnull align 8 dereferenceable(8) [[REF_TMP15]], double* nonnull align 8 dereferenceable(8) [[REF_TMP16]]) #[[ATTR8]]
	// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[REF_TMP14]]) #[[ATTR8]]
	// CHECK3-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*			// CHECK3-NEXT: [[TMP45:%.]] = bitcast double [[REF_TMP16]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP45]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*			// CHECK3-NEXT: [[TMP46:%.]] = bitcast double [[REF_TMP15]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* [[TMP46]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*			// CHECK3-NEXT: [[TMP47:%.]] = bitcast %"class.std::complex.0" [[REF_TMP14]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP47]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1			// CHECK3-NEXT: [[ADD18:%.*]] = add i32 [[TMP48]], 1
	// CHECK3-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]			// CHECK3-NEXT: [[ADD19:%.*]] = add i32 [[TMP49]], [[TMP50]]
	// CHECK3-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD19]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]			// CHECK3-NEXT: [[ADD20:%.*]] = add i32 [[TMP51]], [[TMP52]]
	// CHECK3-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP53:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP54:%.]] = load i32, i32 [[TMP53]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP54]])
	// CHECK3-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP55:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP56:%.]] = load i32, i32 [[TMP55]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0			// CHECK3-NEXT: [[TMP57:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK3-NEXT: [[TMP58:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8			// CHECK3-NEXT: store i8* [[TMP58]], i8** [[TMP57]], align 8
	// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*			// CHECK3-NEXT: [[TMP59:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_RED_LIST]] to i8*
	// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)			// CHECK3-NEXT: [[TMP60:%.]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(%struct.ident_t @[[GLOB3]], i32 [[TMP56]], i32 1, i64 8, i8* [[TMP59]], void (i8, i16, i16, i16) @_omp_reduction_shuffle_and_reduce_func5, void (i8, i32) @_omp_reduction_inter_warp_copy_func6)
	// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1			// CHECK3-NEXT: [[TMP61:%.*]] = icmp eq i32 [[TMP60]], 1
	// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP61]], label [[DOTOMP_REDUCTION_THEN:%.]], label [[DOTOMP_REDUCTION_DONE:%.]]
	// CHECK3: .omp.reduction.then:			// CHECK3: .omp.reduction.then:
	// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL21:%.]] = call nonnull align 8 dereferenceable(16) %"class.std::complex.0" @_ZNSt7complexIdEpLIdEERS0_RKS_IT_E(%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[TMP2]], %"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[PARTIAL_SUM5]]) #[[ATTR8]]
	// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])			// CHECK3-NEXT: call void @__kmpc_nvptx_end_reduce_nowait(i32 [[TMP56]])
	// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]			// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DONE]]
	// CHECK3: .omp.reduction.done:			// CHECK3: .omp.reduction.done:
	// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*			// CHECK3-NEXT: [[TMP62:%.]] = bitcast i32 [[I7]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP62]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*			// CHECK3-NEXT: [[TMP63:%.]] = bitcast %"class.std::complex.0" [[PARTIAL_SUM5]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP63]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*			// CHECK3-NEXT: [[TMP64:%.]] = bitcast i32 [[DOTOMP_IS_LAST]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP64]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*			// CHECK3-NEXT: [[TMP65:%.]] = bitcast i32 [[DOTOMP_STRIDE]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP65]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*			// CHECK3-NEXT: [[TMP66:%.]] = bitcast i32 [[DOTOMP_UB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP66]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*			// CHECK3-NEXT: [[TMP67:%.]] = bitcast i32 [[DOTOMP_LB]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP67]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[OMP_PRECOND_END]]			// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK3: omp.precond.end:			// CHECK3: omp.precond.end:
	// CHECK3-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*			// CHECK3-NEXT: [[TMP68:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_2]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP68]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*			// CHECK3-NEXT: [[TMP69:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_1]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP69]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*			// CHECK3-NEXT: [[TMP70:%.]] = bitcast i32 [[DOTCAPTURE_EXPR_]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP70]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*			// CHECK3-NEXT: [[TMP71:%.]] = bitcast i32 [[DOTOMP_IV]] to i8*
	// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR5]]			// CHECK3-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP71]]) #[[ATTR2]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIdEpLIdEERS0_RKS_IT_E			// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIdEpLIdEERS0_RKS_IT_E
	// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], %"class.std::complex.0" nonnull align 8 dereferenceable(16) [[__C:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[__C_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex.0"* [[__C]], %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP0:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL:%.]] = call double @_ZNKSt7complexIdE4realEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP0]]) #[[ATTR8]]
	// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA22:![0-9]+]]			// CHECK3-NEXT: [[TMP1:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24:![0-9]+]]
	// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]			// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[CALL]]
	// CHECK3-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK3-NEXT: store double [[ADD]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP2:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[__C_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR7]]			// CHECK3-NEXT: [[CALL2:%.]] = call double @_ZNKSt7complexIdE4imagEv(%"class.std::complex.0" nonnull align 8 dereferenceable(16) [[TMP2]]) #[[ATTR8]]
	// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA24:![0-9]+]]			// CHECK3-NEXT: [[TMP3:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26:![0-9]+]]
	// CHECK3-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]			// CHECK3-NEXT: [[ADD3:%.*]] = fadd double [[TMP3]], [[CALL2]]
	// CHECK3-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK3-NEXT: store double [[ADD3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK3-NEXT: ret %"class.std::complex.0"* [[THIS1]]			// CHECK3-NEXT: ret %"class.std::complex.0"* [[THIS1]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5			// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func5
	// CHECK3-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i8* [[TMP0:%.]], i16 signext [[TMP1:%.]], i16 signext [[TMP2:%.]], i16 signext [[TMP3:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8			// CHECK3-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.]] = alloca [1 x i8], align 8
	// CHECK3-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: store i16 [[TMP1]], i16* [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: store i16 [[TMP2]], i16* [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: store i16 [[TMP3]], i16* [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP4:%.]] = load i8, i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]			// CHECK3-NEXT: [[TMP5:%.]] = bitcast i8 [[TMP4]] to [1 x i8]
	// CHECK3-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: [[TMP6:%.]] = load i16, i16 [[DOTADDR1]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: [[TMP7:%.]] = load i16, i16 [[DOTADDR2]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: [[TMP8:%.]] = load i16, i16 [[DOTADDR3]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8			// CHECK3-NEXT: [[TMP10:%.]] = load i8, i8** [[TMP9]], align 8
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*			// CHECK3-NEXT: [[TMP12:%.]] = bitcast i8 [[TMP10]] to %"class.std::complex.0"*
	// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1			// CHECK3-NEXT: [[TMP13:%.]] = getelementptr %"class.std::complex.0", %"class.std::complex.0" [[TMP12]], i64 1
	// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*			// CHECK3-NEXT: [[TMP14:%.]] = bitcast %"class.std::complex.0" [[TMP13]] to i8*
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*			// CHECK3-NEXT: [[TMP15:%.]] = bitcast %"class.std::complex.0" [[TMP12]] to i64*
	// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*			// CHECK3-NEXT: [[TMP16:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i64*
	Show All 14 Lines
	// CHECK3-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16			// CHECK3-NEXT: [[TMP26:%.*]] = trunc i32 [[NVPTX_WARP_SIZE]] to i16
	// CHECK3-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])			// CHECK3-NEXT: [[TMP27:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP25]], i16 [[TMP7]], i16 [[TMP26]])
	// CHECK3-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8			// CHECK3-NEXT: store i64 [[TMP27]], i64* [[TMP18]], align 8
	// CHECK3-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1			// CHECK3-NEXT: [[TMP28]] = getelementptr i64, i64* [[TMP17]], i64 1
	// CHECK3-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1			// CHECK3-NEXT: [[TMP29]] = getelementptr i64, i64* [[TMP18]], i64 1
	// CHECK3-NEXT: br label [[DOTSHUFFLE_PRE_COND]]			// CHECK3-NEXT: br label [[DOTSHUFFLE_PRE_COND]]
	// CHECK3: .shuffle.exit:			// CHECK3: .shuffle.exit:
	// CHECK3-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*			// CHECK3-NEXT: [[TMP30:%.]] = bitcast %"class.std::complex.0" [[DOTOMP_REDUCTION_ELEMENT]] to i8*
	// CHECK3-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP30]], i8** [[TMP11]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0			// CHECK3-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP8]], 0
	// CHECK3-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK3-NEXT: [[TMP32:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK3-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[TMP33:%.*]] = icmp ult i16 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]			// CHECK3-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]]
	// CHECK3-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2			// CHECK3-NEXT: [[TMP35:%.*]] = icmp eq i16 [[TMP8]], 2
	// CHECK3-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1			// CHECK3-NEXT: [[TMP36:%.*]] = and i16 [[TMP6]], 1
	// CHECK3-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0			// CHECK3-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP36]], 0
	// CHECK3-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]			// CHECK3-NEXT: [[TMP38:%.*]] = and i1 [[TMP35]], [[TMP37]]
	// CHECK3-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0			// CHECK3-NEXT: [[TMP39:%.*]] = icmp sgt i16 [[TMP7]], 0
	// CHECK3-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]			// CHECK3-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]]
	// CHECK3-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]			// CHECK3-NEXT: [[TMP41:%.*]] = or i1 [[TMP31]], [[TMP34]]
	// CHECK3-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]			// CHECK3-NEXT: [[TMP42:%.*]] = or i1 [[TMP41]], [[TMP40]]
	// CHECK3-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK3-NEXT: br i1 [[TMP42]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK3: then:			// CHECK3: then:
	// CHECK3-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*			// CHECK3-NEXT: [[TMP43:%.]] = bitcast [1 x i8]* [[TMP5]] to i8*
	// CHECK3-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*			// CHECK3-NEXT: [[TMP44:%.]] = bitcast [1 x i8]* [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to i8*
	// CHECK3-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR5]]			// CHECK3-NEXT: call void @"_omp$reduction$reduction_func4"(i8* [[TMP43]], i8* [[TMP44]]) #[[ATTR2]]
	// CHECK3-NEXT: br label [[IFCONT:%.*]]			// CHECK3-NEXT: br label [[IFCONT:%.*]]
	// CHECK3: else:			// CHECK3: else:
	// CHECK3-NEXT: br label [[IFCONT]]			// CHECK3-NEXT: br label [[IFCONT]]
	// CHECK3: ifcont:			// CHECK3: ifcont:
	// CHECK3-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1			// CHECK3-NEXT: [[TMP45:%.*]] = icmp eq i16 [[TMP8]], 1
	// CHECK3-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[TMP46:%.*]] = icmp uge i16 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]			// CHECK3-NEXT: [[TMP47:%.*]] = and i1 [[TMP45]], [[TMP46]]
	// CHECK3-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK3-NEXT: br i1 [[TMP47]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK3: then4:			// CHECK3: then4:
	// CHECK3-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0			// CHECK3-NEXT: [[TMP48:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8			// CHECK3-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
	// CHECK3-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0			// CHECK3-NEXT: [[TMP50:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP5]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8			// CHECK3-NEXT: [[TMP51:%.]] = load i8, i8** [[TMP50]], align 8
	// CHECK3-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*			// CHECK3-NEXT: [[TMP52:%.]] = bitcast i8 [[TMP49]] to %"class.std::complex.0"*
	// CHECK3-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*			// CHECK3-NEXT: [[TMP53:%.]] = bitcast i8 [[TMP51]] to %"class.std::complex.0"*
	// CHECK3-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*			// CHECK3-NEXT: [[TMP54:%.]] = bitcast %"class.std::complex.0" [[TMP53]] to i8*
	// CHECK3-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*			// CHECK3-NEXT: [[TMP55:%.]] = bitcast %"class.std::complex.0" [[TMP52]] to i8*
	// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !25			// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 16, i1 false), !tbaa.struct !27
	// CHECK3-NEXT: br label [[IFCONT6:%.*]]			// CHECK3-NEXT: br label [[IFCONT6:%.*]]
	// CHECK3: else5:			// CHECK3: else5:
	// CHECK3-NEXT: br label [[IFCONT6]]			// CHECK3-NEXT: br label [[IFCONT6]]
	// CHECK3: ifcont6:			// CHECK3: ifcont6:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6			// CHECK3-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func6
	// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i8* [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK3-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])			// CHECK3-NEXT: [[TMP2:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB3]])
	// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31			// CHECK3-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[NVPTX_TID2]], 31
	// CHECK3-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()			// CHECK3-NEXT: [[NVPTX_TID3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
	// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5			// CHECK3-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[NVPTX_TID3]], 5
	// CHECK3-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load i8, i8** [[DOTADDR]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8 [[TMP3]] to [1 x i8]
	// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 0, i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[PRECOND:%.*]]			// CHECK3-NEXT: br label [[PRECOND:%.*]]
	// CHECK3: precond:			// CHECK3: precond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4			// CHECK3-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], 4
	// CHECK3-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP6]], label [[BODY:%.]], label [[EXIT:%.]]
	// CHECK3: body:			// CHECK3: body:
	// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0			// CHECK3-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0
	// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]			// CHECK3-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.]], label [[ELSE:%.]]
	// CHECK3: then:			// CHECK3: then:
	// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK3-NEXT: [[TMP7:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP8:%.]] = load i8, i8** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast i8 [[TMP8]] to i32*
	// CHECK3-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]			// CHECK3-NEXT: [[TMP10:%.]] = getelementptr i32, i32 [[TMP9]], i32 [[TMP5]]
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]]
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP10]], align 4
	// CHECK3-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4			// CHECK3-NEXT: store volatile i32 [[TMP12]], i32 addrspace(3)* [[TMP11]], align 4
	// CHECK3-NEXT: br label [[IFCONT:%.*]]			// CHECK3-NEXT: br label [[IFCONT:%.*]]
	// CHECK3: else:			// CHECK3: else:
	// CHECK3-NEXT: br label [[IFCONT]]			// CHECK3-NEXT: br label [[IFCONT]]
	// CHECK3: ifcont:			// CHECK3: ifcont:
	// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB4]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]			// CHECK3-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[NVPTX_TID]], [[TMP13]]
	// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]			// CHECK3-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN4:%.]], label [[ELSE5:%.]]
	// CHECK3: then4:			// CHECK3: then4:
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [32 x i32], [32 x i32] addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_TID]]
	// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0			// CHECK3-NEXT: [[TMP15:%.]] = getelementptr inbounds [1 x i8], [1 x i8] [[TMP4]], i64 0, i64 0
	// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP16:%.]] = load i8, i8** [[TMP15]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*			// CHECK3-NEXT: [[TMP17:%.]] = bitcast i8 [[TMP16]] to i32*
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr i32, i32 [[TMP17]], i32 [[TMP5]]
	// CHECK3-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: [[TMP19:%.]] = load volatile i32, i32 addrspace(3) [[TMP14]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP19]], i32* [[TMP18]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[IFCONT6:%.*]]			// CHECK3-NEXT: br label [[IFCONT6:%.*]]
	// CHECK3: else5:			// CHECK3: else5:
	// CHECK3-NEXT: br label [[IFCONT6]]			// CHECK3-NEXT: br label [[IFCONT6]]
	// CHECK3: ifcont6:			// CHECK3: ifcont6:
	// CHECK3-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1			// CHECK3-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP5]], 1
	// CHECK3-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP20]], i32* [[DOTCNT_ADDR]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: br label [[PRECOND]]			// CHECK3-NEXT: br label [[PRECOND]]
	// CHECK3: exit:			// CHECK3: exit:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			// CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			// CHECK3-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	// CHECK3-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			// CHECK3-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA17]]			// CHECK3-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2, !tbaa [[TBAA19]]
	// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA6]]			// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA8]]
	// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			// CHECK3-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			// CHECK3-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0			// CHECK3-NEXT: [[TMP3:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 0
	// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**			// CHECK3-NEXT: [[TMP4:%.]] = bitcast i8* [[TMP3]] to i32**
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32** [[TMP4]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 1
	// CHECK3-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**			// CHECK3-NEXT: [[TMP7:%.]] = bitcast i8* [[TMP6]] to i32**
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32** [[TMP7]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds i8, i8** [[TMP2]], i64 2
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex.0"**			// CHECK3-NEXT: [[TMP10:%.]] = bitcast i8* [[TMP9]] to %"class.std::complex.0"**
	// CHECK3-NEXT: [[TMP11:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[TMP10]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP11:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[TMP10]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex.0"* [[TMP11]]) #[[ATTR5]]			// CHECK3-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]], i32* [[TMP8]], %"class.std::complex.0"* [[TMP11]]) #[[ATTR2]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC2ERKfS2_			// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIfEC2ERKfS2_
	// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.]], float nonnull align 4 dereferenceable(4) [[__RE:%.]], float nonnull align 4 dereferenceable(4) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8			// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca float, align 8
	// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8			// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca float, align 8
	// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store float* [[__RE]], float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store float* [[__IM]], float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP0:%.]] = load float, float** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP1:%.]] = load float, float [[TMP0]], align 4, !tbaa [[TBAA12]]			// CHECK3-NEXT: [[TMP1:%.]] = load float, float [[TMP0]], align 4, !tbaa [[TBAA14]]
	// CHECK3-NEXT: store float [[TMP1]], float* [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK3-NEXT: store float [[TMP1]], float* [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP2:%.]] = load float, float** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP2:%.]] = load float, float** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP3:%.]] = load float, float [[TMP2]], align 4, !tbaa [[TBAA12]]			// CHECK3-NEXT: [[TMP3:%.]] = load float, float [[TMP2]], align 4, !tbaa [[TBAA14]]
	// CHECK3-NEXT: store float [[TMP3]], float* [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK3-NEXT: store float [[TMP3]], float* [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4realEv			// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4realEv
	// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0			// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP0:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA14]]			// CHECK3-NEXT: [[TMP0:%.]] = load float, float [[__RE_]], align 4, !tbaa [[TBAA16]]
	// CHECK3-NEXT: ret float [[TMP0]]			// CHECK3-NEXT: ret float [[TMP0]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4imagEv			// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIfE4imagEv
	// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex"* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex", align 8
	// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex"* [[THIS]], %"class.std::complex"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex", %"class.std::complex"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1			// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex", %"class.std::complex" [[THIS1]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP0:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA16]]			// CHECK3-NEXT: [[TMP0:%.]] = load float, float [[__IM_]], align 4, !tbaa [[TBAA18]]
	// CHECK3-NEXT: ret float [[TMP0]]			// CHECK3-NEXT: ret float [[TMP0]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC2ERKdS2_			// CHECK3-LABEL: define {{[^@]+}}@_ZNSt7complexIdEC2ERKdS2_
	// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.]], double nonnull align 8 dereferenceable(8) [[__RE:%.]], double nonnull align 8 dereferenceable(8) [[__IM:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8			// CHECK3-NEXT: [[__RE_ADDR:%.]] = alloca double, align 8
	// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8			// CHECK3-NEXT: [[__IM_ADDR:%.]] = alloca double, align 8
	// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store double* [[__RE]], double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store double* [[__IM]], double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP0:%.]] = load double, double** [[__RE_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP1:%.]] = load double, double [[TMP0]], align 8, !tbaa [[TBAA20]]			// CHECK3-NEXT: [[TMP1:%.]] = load double, double [[TMP0]], align 8, !tbaa [[TBAA22]]
	// CHECK3-NEXT: store double [[TMP1]], double* [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK3-NEXT: store double [[TMP1]], double* [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP2:%.]] = load double, double** [[__IM_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: [[TMP2:%.]] = load double, double** [[__IM_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[TMP3:%.]] = load double, double [[TMP2]], align 8, !tbaa [[TBAA20]]			// CHECK3-NEXT: [[TMP3:%.]] = load double, double [[TMP2]], align 8, !tbaa [[TBAA22]]
	// CHECK3-NEXT: store double [[TMP3]], double* [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK3-NEXT: store double [[TMP3]], double* [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4realEv			// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4realEv
	// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0			// CHECK3-NEXT: [[__RE_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP0:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA22]]			// CHECK3-NEXT: [[TMP0:%.]] = load double, double [[__RE_]], align 8, !tbaa [[TBAA24]]
	// CHECK3-NEXT: ret double [[TMP0]]			// CHECK3-NEXT: ret double [[TMP0]]
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4imagEv			// CHECK3-LABEL: define {{[^@]+}}@_ZNKSt7complexIdE4imagEv
	// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR4]] comdat align 2 {			// CHECK3-SAME: (%"class.std::complex.0"* nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR5]] comdat align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8			// CHECK3-NEXT: [[THIS_ADDR:%.]] = alloca %"class.std::complex.0", align 8
	// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA10]]			// CHECK3-NEXT: store %"class.std::complex.0"* [[THIS]], %"class.std::complex.0"** [[THIS_ADDR]], align 8, !tbaa [[TBAA12]]
	// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8			// CHECK3-NEXT: [[THIS1:%.]] = load %"class.std::complex.0", %"class.std::complex.0"** [[THIS_ADDR]], align 8
	// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1			// CHECK3-NEXT: [[__IM_:%.]] = getelementptr inbounds %"class.std::complex.0", %"class.std::complex.0" [[THIS1]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP0:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA24]]			// CHECK3-NEXT: [[TMP0:%.]] = load double, double [[__IM_]], align 8, !tbaa [[TBAA26]]
	// CHECK3-NEXT: ret double [[TMP0]]			// CHECK3-NEXT: ret double [[TMP0]]
	//			//

clang/test/OpenMP/ordered_codegen.cpp

	Show First 20 Lines • Show All 554 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]
	// CHECK1: simd.if.then:			// CHECK1: simd.if.then:
	// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1			// CHECK1-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1
	// CHECK1-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]			// CHECK1-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1
	// CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]			// CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2			// CHECK1-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2			// CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2			// CHECK1-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]			// CHECK1-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
	// CHECK1-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1			// CHECK1-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1
	// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1			// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1
	// CHECK1-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1			// CHECK1-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
	Show All 33 Lines
	// CHECK1-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4			// CHECK1-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]
	// CHECK1: omp.inner.for.cond29:			// CHECK1: omp.inner.for.cond29:
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1			// CHECK1-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1
	// CHECK1-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]			// CHECK1-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
	// CHECK1-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]			// CHECK1-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]
	// CHECK1: omp.inner.for.body32:			// CHECK1: omp.inner.for.body32:
	// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4			// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1			// CHECK1-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1
	// CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]			// CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
	// CHECK1-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4			// CHECK1-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4			// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64			// CHECK1-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK1-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]			// CHECK1-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]
	// CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4			// CHECK1-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: call void @__captured_stmt.1(i32* [[I28]])			// CHECK1-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]
	// CHECK1: omp.body.continue37:			// CHECK1: omp.body.continue37:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]
	// CHECK1: omp.inner.for.inc38:			// CHECK1: omp.inner.for.inc38:
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1			// CHECK1-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1
	// CHECK1-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4			// CHECK1-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK1-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			// CHECK1-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK1: omp.inner.for.end40:			// CHECK1: omp.inner.for.end40:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
	// CHECK1-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	▲ Show 20 Lines • Show All 483 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]
	// CHECK2: simd.if.then:			// CHECK2: simd.if.then:
	// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1			// CHECK2-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1
	// CHECK2-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]			// CHECK2-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1
	// CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]			// CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2			// CHECK2-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2			// CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2			// CHECK2-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]			// CHECK2-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
	// CHECK2-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1			// CHECK2-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1
	// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1			// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1
	// CHECK2-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1			// CHECK2-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
	Show All 33 Lines
	// CHECK2-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4			// CHECK2-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]
	// CHECK2: omp.inner.for.cond29:			// CHECK2: omp.inner.for.cond29:
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1			// CHECK2-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1
	// CHECK2-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]			// CHECK2-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
	// CHECK2-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]			// CHECK2-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]
	// CHECK2: omp.inner.for.body32:			// CHECK2: omp.inner.for.body32:
	// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4			// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1			// CHECK2-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1
	// CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]			// CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
	// CHECK2-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4			// CHECK2-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4			// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64			// CHECK2-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK2-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]			// CHECK2-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]
	// CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4			// CHECK2-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: call void @__captured_stmt.1(i32* [[I28]])			// CHECK2-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]
	// CHECK2: omp.body.continue37:			// CHECK2: omp.body.continue37:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]
	// CHECK2: omp.inner.for.inc38:			// CHECK2: omp.inner.for.inc38:
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1			// CHECK2-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1
	// CHECK2-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4			// CHECK2-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK2-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			// CHECK2-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK2: omp.inner.for.end40:			// CHECK2: omp.inner.for.end40:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK2-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
	// CHECK2-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	▲ Show 20 Lines • Show All 483 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]
	// CHECK3: simd.if.then:			// CHECK3: simd.if.then:
	// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1			// CHECK3-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1
	// CHECK3-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]			// CHECK3-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
	// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1
	// CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]			// CHECK3-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2			// CHECK3-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !2			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]
	// CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2			// CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2			// CHECK3-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK3-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]			// CHECK3-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
	// CHECK3-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1			// CHECK3-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1
	// CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1			// CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1
	// CHECK3-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1			// CHECK3-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
	Show All 33 Lines
	// CHECK3-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4			// CHECK3-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]
	// CHECK3: omp.inner.for.cond29:			// CHECK3: omp.inner.for.cond29:
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1			// CHECK3-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1
	// CHECK3-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]			// CHECK3-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
	// CHECK3-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]			// CHECK3-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]
	// CHECK3: omp.inner.for.body32:			// CHECK3: omp.inner.for.body32:
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1			// CHECK3-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1
	// CHECK3-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]			// CHECK3-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
	// CHECK3-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4			// CHECK3-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4			// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64			// CHECK3-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK3-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]			// CHECK3-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]
	// CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4			// CHECK3-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: call void @__captured_stmt.1(i32* [[I28]])			// CHECK3-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]
	// CHECK3: omp.body.continue37:			// CHECK3: omp.body.continue37:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]
	// CHECK3: omp.inner.for.inc38:			// CHECK3: omp.inner.for.inc38:
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1			// CHECK3-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1
	// CHECK3-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4			// CHECK3-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			// CHECK3-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK3: omp.inner.for.end40:			// CHECK3: omp.inner.for.end40:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
	// CHECK3-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	▲ Show 20 Lines • Show All 483 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[SIMD_IF_THEN:%.]], label [[SIMD_IF_END:%.]]
	// CHECK4: simd.if.then:			// CHECK4: simd.if.then:
	// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1			// CHECK4-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1
	// CHECK4-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]			// CHECK4-NEXT: [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
	// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !2			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP11]], 1
	// CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]			// CHECK4-NEXT: [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !2			// CHECK4-NEXT: store i32 [[ADD8]], i32* [[I5]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !2			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM]]
	// CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !2			// CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !2			// CHECK4-NEXT: call void @__captured_stmt(i32* [[I5]]), !llvm.access.group !3
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2			// CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_1]], align 4
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_]], align 4
	// CHECK4-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]			// CHECK4-NEXT: [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
	// CHECK4-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1			// CHECK4-NEXT: [[SUB11:%.*]] = sub i32 [[SUB10]], 1
	// CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1			// CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[SUB11]], 1
	// CHECK4-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1			// CHECK4-NEXT: [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
	Show All 33 Lines
	// CHECK4-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP26:%.]] = call i32 @__kmpc_dispatch_next_4u(%struct.ident_t @[[GLOB1]], i32 [[TMP0]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4			// CHECK4-NEXT: store i32 [[TMP27]], i32* [[DOTOMP_IV16]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]]
	// CHECK4: omp.inner.for.cond29:			// CHECK4: omp.inner.for.cond29:
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1			// CHECK4-NEXT: [[ADD30:%.*]] = add i32 [[TMP29]], 1
	// CHECK4-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]			// CHECK4-NEXT: [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
	// CHECK4-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]			// CHECK4-NEXT: br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.]], label [[OMP_INNER_FOR_END40:%.]]
	// CHECK4: omp.inner.for.body32:			// CHECK4: omp.inner.for.body32:
	// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4			// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1			// CHECK4-NEXT: [[MUL33:%.*]] = mul i32 [[TMP31]], 1
	// CHECK4-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]			// CHECK4-NEXT: [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
	// CHECK4-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4			// CHECK4-NEXT: store i32 [[ADD34]], i32* [[I28]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4			// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[I28]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64			// CHECK4-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK4-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]			// CHECK4-NEXT: [[ARRAYIDX36:%.]] = getelementptr inbounds [10 x float], [10 x float] @f, i64 0, i64 [[IDXPROM35]]
	// CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4			// CHECK4-NEXT: store float 0.000000e+00, float* [[ARRAYIDX36]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: call void @__captured_stmt.1(i32* [[I28]])			// CHECK4-NEXT: call void @__captured_stmt.1(i32* [[I28]]), !llvm.access.group !7
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]]
	// CHECK4: omp.body.continue37:			// CHECK4: omp.body.continue37:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC38:%.*]]
	// CHECK4: omp.inner.for.inc38:			// CHECK4: omp.inner.for.inc38:
	// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4			// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1			// CHECK4-NEXT: [[ADD39:%.*]] = add i32 [[TMP33]], 1
	// CHECK4-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4			// CHECK4-NEXT: store i32 [[ADD39]], i32* [[DOTOMP_IV16]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])			// CHECK4-NEXT: call void @__kmpc_dispatch_fini_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group !7
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK4: omp.inner.for.end40:			// CHECK4: omp.inner.for.end40:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK4-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
	// CHECK4-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	▲ Show 20 Lines • Show All 828 Lines • Show Last 20 Lines

clang/test/OpenMP/parallel_for_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 763 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4			// CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK1-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !4			// CHECK1-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK1-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !4			// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !4			// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4			// CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK1-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7			// CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK1-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK1-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK1-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK1-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7			// CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK1-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK1-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK1-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8			// CHECK1-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]			// CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
	// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11
	// CHECK1-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64			// CHECK1-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
	// CHECK1-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11			// CHECK1-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
	// CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1			// CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
	// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]			// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
	// CHECK1-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8			// CHECK1-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
	// CHECK1-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10			// CHECK1-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11			// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
	// CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11			// CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
	// CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]			// CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
	// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1			// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
	// CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]			// CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
	// CHECK1-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32			// CHECK1-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
	// CHECK1-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10			// CHECK1-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK1-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK1-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64			// CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
	// CHECK1-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]			// CHECK1-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]
	// CHECK1-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !10			// CHECK1-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]			// CHECK1-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
	// CHECK1-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK1-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK1-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64			// CHECK1-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
	// CHECK1-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]			// CHECK1-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]
	// CHECK1-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !10			// CHECK1-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]			// CHECK1-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
	// CHECK1-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK1-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK1-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64			// CHECK1-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
	// CHECK1-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]			// CHECK1-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]
	// CHECK1-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10			// CHECK1-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK1-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1			// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
	// CHECK1-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK1-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: br label [[OMP_PRECOND_END]]			// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK1: omp.precond.end:			// CHECK1: omp.precond.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20			// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
	// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8			// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
	// CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13			// CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20			// CHECK1-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
	// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20			// CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
	// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !13			// CHECK1-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK1-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !13			// CHECK1-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK1-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64			// CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
	// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]			// CHECK1-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]
	// CHECK1-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK1-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !13			// CHECK1-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK1-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64			// CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
	// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]			// CHECK1-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]
	// CHECK1-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]			// CHECK1-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
	// CHECK1-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !13			// CHECK1-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !14
	// CHECK1-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK1-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK1-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64			// CHECK1-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
	// CHECK1-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]			// CHECK1-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]
	// CHECK1-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13			// CHECK1-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 684 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4			// CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK2-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !4			// CHECK2-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK2-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !4			// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !4			// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4			// CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK2-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7			// CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK2-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK2-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK2-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK2-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7			// CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK2-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK2-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK2-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8			// CHECK2-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]			// CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
	// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11
	// CHECK2-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64			// CHECK2-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
	// CHECK2-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11			// CHECK2-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
	// CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1			// CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
	// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]			// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
	// CHECK2-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8			// CHECK2-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
	// CHECK2-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10			// CHECK2-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11			// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
	// CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11			// CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
	// CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]			// CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
	// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1			// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
	// CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]			// CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
	// CHECK2-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32			// CHECK2-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
	// CHECK2-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10			// CHECK2-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK2-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK2-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK2-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64			// CHECK2-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
	// CHECK2-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]			// CHECK2-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]
	// CHECK2-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !10			// CHECK2-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]			// CHECK2-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
	// CHECK2-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK2-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK2-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64			// CHECK2-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
	// CHECK2-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]			// CHECK2-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]
	// CHECK2-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !10			// CHECK2-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]			// CHECK2-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
	// CHECK2-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK2-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK2-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64			// CHECK2-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
	// CHECK2-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]			// CHECK2-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]
	// CHECK2-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10			// CHECK2-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK2-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1			// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
	// CHECK2-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK2-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: br label [[OMP_PRECOND_END]]			// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK2: omp.precond.end:			// CHECK2: omp.precond.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20			// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
	// CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8			// CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
	// CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13			// CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20			// CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
	// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20			// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
	// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !13			// CHECK2-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK2-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !13			// CHECK2-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK2-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64			// CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
	// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]			// CHECK2-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]
	// CHECK2-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK2-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !13			// CHECK2-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK2-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64			// CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
	// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]			// CHECK2-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]
	// CHECK2-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]			// CHECK2-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
	// CHECK2-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !13			// CHECK2-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !14
	// CHECK2-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK2-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK2-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64			// CHECK2-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
	// CHECK2-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]			// CHECK2-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]
	// CHECK2-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13			// CHECK2-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 684 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK3-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK3-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4			// CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK3-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !4			// CHECK3-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK3-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !4			// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK3-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !4			// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4			// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK3-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK3-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK3-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7			// CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK3-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK3-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK3-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !7			// CHECK3-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !8
	// CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK3-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !7			// CHECK3-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !8
	// CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK3-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7			// CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK3-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK3-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK3-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8			// CHECK3-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]			// CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
	// CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10			// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11
	// CHECK3-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64			// CHECK3-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
	// CHECK3-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11			// CHECK3-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
	// CHECK3-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1			// CHECK3-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
	// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]			// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
	// CHECK3-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8			// CHECK3-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
	// CHECK3-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10			// CHECK3-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11			// CHECK3-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
	// CHECK3-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11			// CHECK3-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
	// CHECK3-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]			// CHECK3-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
	// CHECK3-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1			// CHECK3-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
	// CHECK3-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]			// CHECK3-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
	// CHECK3-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32			// CHECK3-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
	// CHECK3-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64			// CHECK3-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]
	// CHECK3-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK3-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK3-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64			// CHECK3-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
	// CHECK3-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]			// CHECK3-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]
	// CHECK3-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]			// CHECK3-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
	// CHECK3-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK3-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK3-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64			// CHECK3-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
	// CHECK3-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]			// CHECK3-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]
	// CHECK3-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]			// CHECK3-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
	// CHECK3-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK3-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK3-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64			// CHECK3-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
	// CHECK3-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]			// CHECK3-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]
	// CHECK3-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK3-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1			// CHECK3-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
	// CHECK3-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK3-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: br label [[OMP_PRECOND_END]]			// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK3: omp.precond.end:			// CHECK3: omp.precond.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20			// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
	// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8			// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
	// CHECK3-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13			// CHECK3-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20			// CHECK3-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
	// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20			// CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
	// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]			// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
	// CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]			// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
	// CHECK3-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !13			// CHECK3-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK3-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64			// CHECK3-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK3-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !13			// CHECK3-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK3-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK3-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64			// CHECK3-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
	// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]			// CHECK3-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]
	// CHECK3-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK3-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK3-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !13			// CHECK3-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK3-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK3-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64			// CHECK3-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
	// CHECK3-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]			// CHECK3-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]
	// CHECK3-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]			// CHECK3-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
	// CHECK3-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !13			// CHECK3-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK3-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK3-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64			// CHECK3-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
	// CHECK3-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]			// CHECK3-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]
	// CHECK3-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 684 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4			// CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK4-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !4			// CHECK4-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !4			// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK4-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !4			// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4			// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK4-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7			// CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK4-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK4-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK4-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !7			// CHECK4-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !8
	// CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK4-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !7			// CHECK4-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !8
	// CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK4-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7			// CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK4-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK4-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK4-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8			// CHECK4-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]			// CHECK4-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
	// CHECK4-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10			// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11
	// CHECK4-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64			// CHECK4-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
	// CHECK4-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11			// CHECK4-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
	// CHECK4-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1			// CHECK4-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
	// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]			// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
	// CHECK4-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8			// CHECK4-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
	// CHECK4-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10			// CHECK4-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11			// CHECK4-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
	// CHECK4-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11			// CHECK4-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
	// CHECK4-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]			// CHECK4-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
	// CHECK4-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1			// CHECK4-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
	// CHECK4-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]			// CHECK4-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
	// CHECK4-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32			// CHECK4-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
	// CHECK4-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64			// CHECK4-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]
	// CHECK4-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK4-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK4-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64			// CHECK4-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
	// CHECK4-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]			// CHECK4-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]
	// CHECK4-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]			// CHECK4-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
	// CHECK4-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK4-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK4-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64			// CHECK4-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
	// CHECK4-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]			// CHECK4-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]
	// CHECK4-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]			// CHECK4-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
	// CHECK4-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK4-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK4-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64			// CHECK4-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
	// CHECK4-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]			// CHECK4-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]
	// CHECK4-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK4-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1			// CHECK4-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
	// CHECK4-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK4-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: br label [[OMP_PRECOND_END]]			// CHECK4-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK4: omp.precond.end:			// CHECK4: omp.precond.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20			// CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
	// CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8			// CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
	// CHECK4-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13			// CHECK4-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20			// CHECK4-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
	// CHECK4-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20			// CHECK4-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
	// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]			// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
	// CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]			// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
	// CHECK4-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !13			// CHECK4-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK4-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64			// CHECK4-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK4-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !13			// CHECK4-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK4-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK4-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64			// CHECK4-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
	// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]			// CHECK4-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]
	// CHECK4-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK4-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK4-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !13			// CHECK4-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK4-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK4-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64			// CHECK4-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
	// CHECK4-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]			// CHECK4-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]
	// CHECK4-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]			// CHECK4-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
	// CHECK4-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !13			// CHECK4-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK4-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK4-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64			// CHECK4-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
	// CHECK4-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]			// CHECK4-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]
	// CHECK4-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines
	// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat {			// CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat {
	// CHECK4-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]]			// CHECK4-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]]
	// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]			// CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]
	// CHECK4-NEXT: unreachable			// CHECK4-NEXT: unreachable
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev			// CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev
	// CHECK5-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {			// CHECK5-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG7:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A:%.*]] = alloca double, align 8			// CHECK5-NEXT: [[A:%.*]] = alloca double, align 8
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1			// CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG9:![0-9]+]]			// CHECK5-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG10:![0-9]+]]
	// CHECK5-NEXT: [[TMP0:%.]] = load double, double [[A]], align 8, !dbg [[DBG10:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load double, double [[A]], align 8, !dbg [[DBG11:![0-9]+]]
	// CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG10]]			// CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG11]]
	// CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG10]]			// CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]]
	// CHECK5-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG10]]			// CHECK5-NEXT: [[TMP1:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]]
	// CHECK5-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*, !dbg [[DBG10]]			// CHECK5-NEXT: [[CONV1:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*, !dbg [[DBG11]]
	// CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1, !dbg [[DBG10]]			// CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1, !dbg [[DBG11]]
	// CHECK5-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !dbg [[DBG10]]			// CHECK5-NEXT: [[TMP2:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !dbg [[DBG11]]
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP2]]), !dbg [[DBG10]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32, i32, ...)* bitcast (void (i32, i32, i64)* @.omp_outlined. to void (i32, i32, ...)*), i64 [[TMP2]]), !dbg [[DBG11]]
	// CHECK5-NEXT: ret void, !dbg [[DBG11:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG12:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1:[0-9]+]] !dbg [[DBG12:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1:[0-9]+]] !dbg [[DBG13:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8			// CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8
	// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[A:%.*]] = alloca double, align 8			// CHECK5-NEXT: [[A:%.*]] = alloca double, align 8
	// CHECK5-NEXT: [[I5:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[I5:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8			// CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
	// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG13:![0-9]+]]			// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG14:![0-9]+]]
	// CHECK5-NEXT: [[TMP0:%.]] = load double, double undef, align 8, !dbg [[DBG14:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load double, double undef, align 8, !dbg [[DBG15:![0-9]+]]
	// CHECK5-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]], !dbg [[DBG14]]			// CHECK5-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]], !dbg [[DBG15]]
	// CHECK5-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP1:%.]] = load double, double [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP1:%.]] = load double, double [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00, !dbg [[DBG14]]			// CHECK5-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00, !dbg [[DBG15]]
	// CHECK5-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00, !dbg [[DBG14]]			// CHECK5-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00, !dbg [[DBG15]]
	// CHECK5-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64, !dbg [[DBG14]]			// CHECK5-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64, !dbg [[DBG15]]
	// CHECK5-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1, !dbg [[DBG14]]			// CHECK5-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1, !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP2:%.]] = load double, double [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP2:%.]] = load double, double [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG14]]			// CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG15]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]], !dbg [[DBG13]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]], !dbg [[DBG14]]
	// CHECK5: omp.precond.then:			// CHECK5: omp.precond.then:
	// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP3:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP3:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG14]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV]], align 8, !dbg [[DBG13]]			// CHECK5-NEXT: [[TMP4:%.]] = load i8, i8 [[CONV]], align 8, !dbg [[DBG14]]
	// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG13]]			// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG14]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG13]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]]
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[TMP5]], align 4, !dbg [[DBG13]]			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[TMP5]], align 4, !dbg [[DBG14]]
	// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]), !dbg [[DBG13]]			// CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]), !dbg [[DBG14]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG13]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG14]]
	// CHECK5: omp.dispatch.cond:			// CHECK5: omp.dispatch.cond:
	// CHECK5-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]], !dbg [[DBG14]]			// CHECK5-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]], !dbg [[DBG15]]
	// CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG14]]			// CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG15]]
	// CHECK5: cond.true:			// CHECK5: cond.true:
	// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG14]]			// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG15]]
	// CHECK5: cond.false:			// CHECK5: cond.false:
	// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG14]]			// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG15]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ], !dbg [[DBG14]]			// CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ], !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP11:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP11:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1, !dbg [[DBG14]]			// CHECK5-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1, !dbg [[DBG15]]
	// CHECK5-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]], !dbg [[DBG14]]			// CHECK5-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]], !dbg [[DBG15]]
	// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG13]]			// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG14]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG13]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG14]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP14:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP14:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1, !dbg [[DBG14]]			// CHECK5-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1, !dbg [[DBG15]]
	// CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]], !dbg [[DBG14]]			// CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]], !dbg [[DBG15]]
	// CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG13]]			// CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG14]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1, !dbg [[DBG14]]			// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1, !dbg [[DBG15]]
	// CHECK5-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]], !dbg [[DBG14]]			// CHECK5-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]], !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG15:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG16:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG13]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG14]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1, !dbg [[DBG14]]			// CHECK5-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1, !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG13]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG14]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG13]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG14]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP19:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]], !dbg [[DBG14]]			// CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]], !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]], !dbg [[DBG14]]			// CHECK5-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]], !dbg [[DBG15]]
	// CHECK5-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]]			// CHECK5-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG13]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG14]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG13]]			// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]]
	// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4, !dbg [[DBG13]]			// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4, !dbg [[DBG14]]
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP23]]), !dbg [[DBG13]]			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP23]]), !dbg [[DBG14]]
	// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG13]]			// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG14]]
	// CHECK5: omp.precond.end:			// CHECK5: omp.precond.end:
	// CHECK5-NEXT: ret void, !dbg [[DBG15]]			// CHECK5-NEXT: ret void, !dbg [[DBG16]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_			// CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
	// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG20:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG21:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8			// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
	// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8			// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
	// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8			// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..1 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG21:![0-9]+]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..1 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG22:![0-9]+]]
	// CHECK5-NEXT: ret void, !dbg [[DBG22:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG23:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG23:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG24:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8			// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8
	// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8			// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8
	// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8			// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG24:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG25:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG24]]			// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG25]]
	// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG24]]			// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG25]]
	// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG24]]			// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG25]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG25:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG26:![0-9]+]]
	// CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG24]]			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG24]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG25]]
	// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG24]]			// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG25]]
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG25]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG26]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG25]]			// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG26]]
	// CHECK5: cond.true:			// CHECK5: cond.true:
	// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG25]]			// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG26]]
	// CHECK5: cond.false:			// CHECK5: cond.false:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG25]]			// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG26]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG25]]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG26]]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG24]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG25]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG25]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG26]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG24]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG25]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG25]]			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG26]]
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG25]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG26]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG26:![0-9]+]]			// CHECK5-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG27:![0-9]+]]
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG26]]			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG27]]
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG26]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG26]]			// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG27]]
	// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG26]]			// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG26]]			// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG26]]			// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG27]]
	// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG26]]			// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG26]]			// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG27]]
	// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG26]]			// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG27]]
	// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG26]]			// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG27]]
	// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG26]]			// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG27]]
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG27:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG28:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG24]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG25]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG25]]			// CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG26]]
	// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG25]]			// CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG24]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG24]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG25]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB8:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG24]]			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB8:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG25]]
	// CHECK5-NEXT: ret void, !dbg [[DBG27]]			// CHECK5-NEXT: ret void, !dbg [[DBG28]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_			// CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
	// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG29:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8			// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
	// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8			// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
	// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8			// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB14:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..2 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG30:![0-9]+]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB14:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..2 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG31:![0-9]+]]
	// CHECK5-NEXT: ret void, !dbg [[DBG31:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG32:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG32:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8			// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8
	// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8			// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8
	// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8			// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG33:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG33]]			// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG34]]
	// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG33]]			// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG34]]
	// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG33]]			// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG34]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG34:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG35:![0-9]+]]
	// CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG33]]			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG34]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG33]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG34]]
	// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG33]]			// CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG34]]
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG34]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG35]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG34]]			// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG35]]
	// CHECK5: cond.true:			// CHECK5: cond.true:
	// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG34]]			// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG35]]
	// CHECK5: cond.false:			// CHECK5: cond.false:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG34]]			// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG35]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG34]]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG35]]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG33]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG34]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG34]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG35]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG33]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG34]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG34]]			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG35]]
	// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG34]]			// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG35]]
	// CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG35:![0-9]+]]			// CHECK5-NEXT: [[TMP12:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG36:![0-9]+]]
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG35]]			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG36]]
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG35]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP15:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP16:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG35]]			// CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG36]]
	// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG35]]			// CHECK5-NEXT: [[ARRAYIDX3:%.]] = getelementptr inbounds float, float [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP17:%.]] = load float, float [[ARRAYIDX3]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG35]]			// CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP18:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG35]]			// CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG36]]
	// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG35]]			// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX6]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG35]]			// CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP21:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG36]]
	// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG35]]			// CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG36]]
	// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG35]]			// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG36]]
	// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG35]]			// CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG36]]
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG36:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG37:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG33]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG34]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG34]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG35]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG34]]			// CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG33]], !llvm.loop [[LOOP37:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG34]], !llvm.loop [[LOOP38:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG33]]			// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG34]]
	// CHECK5: omp.loop.exit:			// CHECK5: omp.loop.exit:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG33]]			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG34]]
	// CHECK5-NEXT: ret void, !dbg [[DBG36]]			// CHECK5-NEXT: ret void, !dbg [[DBG37]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_			// CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
	// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG38:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8			// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
	// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8			// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
	// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8			// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB19:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..3 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG39:![0-9]+]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB19:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..3 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG40:![0-9]+]]
	// CHECK5-NEXT: ret void, !dbg [[DBG40:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG41:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG41:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8			// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8
	// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8			// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8
	// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8			// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG42:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG43:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG42]]			// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG43]]
	// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG42]]			// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG43]]
	// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG42]]			// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG43]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG43:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44:![0-9]+]]
	// CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG42]]			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG43]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG42]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG43]]
	// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG42]]			// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG43]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG42]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG43]]
	// CHECK5: omp.dispatch.cond:			// CHECK5: omp.dispatch.cond:
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG43]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG44]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG43]]			// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG44]]
	// CHECK5: cond.true:			// CHECK5: cond.true:
	// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG43]]			// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG44]]
	// CHECK5: cond.false:			// CHECK5: cond.false:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG43]]			// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG44]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG43]]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG43]]			// CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG44]]
	// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG42]]			// CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG43]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG42]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG43]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG43]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG44]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG42]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG43]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG43]]			// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG44]]
	// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG43]]			// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG44:![0-9]+]]			// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG45:![0-9]+]]
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG44]]			// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG45]]
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG44]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP18:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG44]]			// CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG45]]
	// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG44]]			// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG44]]			// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG44]]			// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG45]]
	// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG44]]			// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP22:%.]] = load float, float [[ARRAYIDX7]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG44]]			// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG45]]
	// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG44]]			// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG45]]
	// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG44]]			// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG45]]
	// CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG44]]			// CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG45]]
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG45:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG46:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG42]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG43]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG43]]			// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG42]], !llvm.loop [[LOOP46:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG42]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG43]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG43]]			// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG43]]			// CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG44]]
	// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]]			// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG42]], !llvm.loop [[LOOP47:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP48:![0-9]+]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG42]]			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG43]]
	// CHECK5-NEXT: ret void, !dbg [[DBG45]]			// CHECK5-NEXT: ret void, !dbg [[DBG46]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_			// CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
	// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG48:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8			// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
	// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8			// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
	// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8			// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB21:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..4 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG49:![0-9]+]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB21:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..4 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG50:![0-9]+]]
	// CHECK5-NEXT: ret void, !dbg [[DBG50:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG51:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG51:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8			// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8
	// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8			// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8
	// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8			// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG52:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG53:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG52]]			// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG53]]
	// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG52]]			// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG53]]
	// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG52]]			// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG53]]
	// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG53:![0-9]+]]			// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG54:![0-9]+]]
	// CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG53]]			// CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG54]]
	// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG53]]			// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG54]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG53]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG54]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG52]]			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG53]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG52]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG53]]
	// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG52]]			// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG53]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG52]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG53]]
	// CHECK5: omp.dispatch.cond:			// CHECK5: omp.dispatch.cond:
	// CHECK5-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB21]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG52]]			// CHECK5-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB21]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG53]]
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG52]]			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG53]]
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG52]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG53]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG53]]			// CHECK5-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG54]]
	// CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG53]]			// CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG52]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG53]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55
	// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG53]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG54]], !llvm.access.group !55
	// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG53]]			// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG54]]
	// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG53]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG54]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG52]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG53]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55
	// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG53]]			// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG54]]
	// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG53]]			// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG54]]
	// CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG53]], !llvm.access.group !54			// CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG54]], !llvm.access.group !55
	// CHECK5-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG55:![0-9]+]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG56:![0-9]+]], !llvm.access.group !55
	// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]], !dbg [[DBG55]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]], !dbg [[DBG56]]
	// CHECK5-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]], !dbg [[DBG55]]			// CHECK5-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]], !dbg [[DBG56]]
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG55]]			// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG56]]
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]], !dbg [[DBG55]]			// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]], !dbg [[DBG56]]
	// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG55]]			// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG56]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]], !dbg [[DBG55]]			// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]], !dbg [[DBG56]]
	// CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG55]], !llvm.access.group !54			// CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG56]], !llvm.access.group !55
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG56:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG57:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG52]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG53]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54			// CHECK5-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55
	// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG53]]			// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG54]]
	// CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54			// CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG52]], !llvm.loop [[LOOP57:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP58:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG52]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG53]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG52]], !llvm.loop [[LOOP59:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP60:![0-9]+]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: ret void, !dbg [[DBG56]]			// CHECK5-NEXT: ret void, !dbg [[DBG57]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_			// CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_
	// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG60:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8			// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
	// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8			// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
	// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8			// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB23:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..5 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG61:![0-9]+]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB23:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..5 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG62:![0-9]+]]
	// CHECK5-NEXT: ret void, !dbg [[DBG62:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG63:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG63:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8			// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8
	// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8			// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8
	// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8			// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG64:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG65:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG64]]			// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG65]]
	// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG64]]			// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG65]]
	// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG64]]			// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG65]]
	// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG65:![0-9]+]]			// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG66:![0-9]+]]
	// CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG65]]			// CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG66]]
	// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG65]]			// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG66]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG65]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG66]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG64]]			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG64]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG65]]
	// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG64]]			// CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG65]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG64]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]]
	// CHECK5: omp.dispatch.cond:			// CHECK5: omp.dispatch.cond:
	// CHECK5-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB23]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG64]]			// CHECK5-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB23]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG65]]
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG64]]			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG65]]
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG64]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG65]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG65]]			// CHECK5-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG66]]
	// CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG65]]			// CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG64]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67
	// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG65]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG66]], !llvm.access.group !67
	// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG65]]			// CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG66]]
	// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG65]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG66]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG64]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG65]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67
	// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG65]]			// CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG66]]
	// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG65]]			// CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG66]]
	// CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG65]], !llvm.access.group !66			// CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG66]], !llvm.access.group !67
	// CHECK5-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG67:![0-9]+]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG68:![0-9]+]], !llvm.access.group !67
	// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]], !dbg [[DBG67]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]], !dbg [[DBG68]]
	// CHECK5-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]], !dbg [[DBG67]]			// CHECK5-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]], !dbg [[DBG68]]
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG67]]			// CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG68]]
	// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]], !dbg [[DBG67]]			// CHECK5-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]], !dbg [[DBG68]]
	// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG67]]			// CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG68]]
	// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]], !dbg [[DBG67]]			// CHECK5-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]], !dbg [[DBG68]]
	// CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG67]], !llvm.access.group !66			// CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG68]], !llvm.access.group !67
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG68:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG69:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG64]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG65]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66			// CHECK5-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67
	// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG65]]			// CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG66]]
	// CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66			// CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG64]], !llvm.loop [[LOOP69:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP70:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG64]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG65]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG64]], !llvm.loop [[LOOP71:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP72:![0-9]+]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: ret void, !dbg [[DBG68]]			// CHECK5-NEXT: ret void, !dbg [[DBG69]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_			// CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
	// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG72:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8			// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
	// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8			// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
	// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8			// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
	// CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG73:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG74:![0-9]+]]
	// CHECK5-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG74:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG75:![0-9]+]]
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB25:[0-9]+]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i32, float, float, float, float) @.omp_outlined..6 to void (i32, i32, ...)), i32 [[Y]], float [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float [[D_ADDR]]), !dbg [[DBG75:![0-9]+]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB25:[0-9]+]], i32 5, void (i32, i32, ...)* bitcast (void (i32, i32, i32, float, float, float, float) @.omp_outlined..6 to void (i32, i32, ...)), i32 [[Y]], float [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float [[D_ADDR]]), !dbg [[DBG76:![0-9]+]]
	// CHECK5-NEXT: ret void, !dbg [[DBG76:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG77:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[Y:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG77:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[Y:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[Y_ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[Y_ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8
	Show All 12 Lines
	// CHECK5-NEXT: [[X8:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[X8:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8			// CHECK5-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8			// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8
	// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8			// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8
	// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8			// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[Y_ADDR]], align 8, !dbg [[DBG78:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32** [[Y_ADDR]], align 8, !dbg [[DBG79:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG79]]
	// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG79]]
	// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG79]]
	// CHECK5-NEXT: [[TMP4:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP4:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG79]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !dbg [[DBG79:![0-9]+]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP0]], align 4, !dbg [[DBG80:![0-9]+]]
	// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG79]]			// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG80]]
	// CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]]			// CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
	// CHECK5-NEXT: [[TMP6:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]]			// CHECK5-NEXT: [[TMP6:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
	// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG79]]			// CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG80]]
	// CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG79]]			// CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG80]]
	// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG79]]			// CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG80]]
	// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG79]]			// CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG80]]
	// CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG79]]			// CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG80]]
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG80:![0-9]+]]			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG81:![0-9]+]]
	// CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG80]]			// CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG81]]
	// CHECK5-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG79]]			// CHECK5-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]]
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]]			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
	// CHECK5-NEXT: store i8 [[TMP7]], i8* [[I]], align 1, !dbg [[DBG79]]			// CHECK5-NEXT: store i8 [[TMP7]], i8* [[I]], align 1, !dbg [[DBG80]]
	// CHECK5-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG80]]			// CHECK5-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG81]]
	// CHECK5-NEXT: [[TMP8:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]]			// CHECK5-NEXT: [[TMP8:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
	// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG79]]			// CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG80]]
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG79]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG80]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]], !dbg [[DBG78]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.]], label [[OMP_PRECOND_END:%.]], !dbg [[DBG79]]
	// CHECK5: omp.precond.then:			// CHECK5: omp.precond.then:
	// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG79]]			// CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG80]]
	// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]]			// CHECK5-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]
	// CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG79]]			// CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG80]]
	// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG79]]			// CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG80]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG79]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG80]]
	// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]]			// CHECK5-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4, !dbg [[DBG79]]
	// CHECK5-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG78]]			// CHECK5-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG79]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG78]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG79]]
	// CHECK5: omp.dispatch.cond:			// CHECK5: omp.dispatch.cond:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]
	// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4, !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP14:%.]] = load i32, i32 [[TMP13]], align 4, !dbg [[DBG79]]
	// CHECK5-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB25]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG78]]			// CHECK5-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB25]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG79]]
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG78]]			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG79]]
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG78]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG79]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG79]]			// CHECK5-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8, !dbg [[DBG80]]
	// CHECK5-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]]			// CHECK5-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG78]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG79]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG79]]			// CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG80]]
	// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG78]]			// CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG79]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG79]]			// CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG80]]
	// CHECK5-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG79]]			// CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG80]]
	// CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG79]]			// CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG80]]
	// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG79]]			// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG80]]
	// CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG79]]			// CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG80]]
	// CHECK5-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG79]]			// CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG80]]
	// CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG79]]			// CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG80]]
	// CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG79]]			// CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG80]]
	// CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG80]]			// CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG81]]
	// CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG80]]			// CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG81]]
	// CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG80]]			// CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG81]]
	// CHECK5-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !dbg [[DBG80]], !llvm.access.group !81			// CHECK5-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !dbg [[DBG81]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG82:![0-9]+]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG83:![0-9]+]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG82]]			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG83]]
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG82]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG83]]
	// CHECK5-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG82]]			// CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG83]]
	// CHECK5-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG82]]			// CHECK5-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG83]]
	// CHECK5-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG82]]			// CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG83]]
	// CHECK5-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG82]]			// CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG83]]
	// CHECK5-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG82]]			// CHECK5-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG83]]
	// CHECK5-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG82]]			// CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG83]]
	// CHECK5-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG82]]			// CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG83]]
	// CHECK5-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG82]]			// CHECK5-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG83]]
	// CHECK5-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !dbg [[DBG82]], !llvm.access.group !81			// CHECK5-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !dbg [[DBG83]], !llvm.access.group !82
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG83:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG84:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG78]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG79]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG79]]			// CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG80]]
	// CHECK5-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81			// CHECK5-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG78]], !llvm.loop [[LOOP84:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP85:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG78]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG79]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG78]], !llvm.loop [[LOOP86:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP87:![0-9]+]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG78]]			// CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG79]]
	// CHECK5: omp.precond.end:			// CHECK5: omp.precond.end:
	// CHECK5-NEXT: ret void, !dbg [[DBG83]]			// CHECK5-NEXT: ret void, !dbg [[DBG84]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_			// CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
	// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG87:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], float [[B:%.]], float [[C:%.]], float [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8			// CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8
	// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8			// CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8
	// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8			// CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8
	// CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG88:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG89:![0-9]+]]
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB27:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..7 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG89:![0-9]+]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB27:[0-9]+]], i32 4, void (i32, i32, ...)* bitcast (void (i32, i32, float, float, float, float)* @.omp_outlined..7 to void (i32, i32, ...)), float* [[A_ADDR]], float [[B_ADDR]], float [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG90:![0-9]+]]
	// CHECK5-NEXT: ret void, !dbg [[DBG90:![0-9]+]]			// CHECK5-NEXT: ret void, !dbg [[DBG91:![0-9]+]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG91:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], float* nonnull align 8 dereferenceable(8) [[B:%.]], float* nonnull align 8 dereferenceable(8) [[C:%.]], float* nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[B_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[C_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[D_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1			// CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1
	// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1			// CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1
	// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8			// CHECK5-NEXT: store float [[B]], float* [[B_ADDR]], align 8
	// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8			// CHECK5-NEXT: store float [[C]], float* [[C_ADDR]], align 8
	// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8			// CHECK5-NEXT: store float [[D]], float* [[D_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG92:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG93:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG92]]			// CHECK5-NEXT: [[TMP1:%.]] = load float, float** [[B_ADDR]], align 8, !dbg [[DBG93]]
	// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG92]]			// CHECK5-NEXT: [[TMP2:%.]] = load float, float** [[C_ADDR]], align 8, !dbg [[DBG93]]
	// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG92]]			// CHECK5-NEXT: [[TMP3:%.]] = load float, float** [[D_ADDR]], align 8, !dbg [[DBG93]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG93:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG94:![0-9]+]]
	// CHECK5-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG93]]			// CHECK5-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG94]]
	// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG93]]			// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG94]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG93]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG94]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG92]]			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG92]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[TMP4]], align 4, !dbg [[DBG93]]
	// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG92]]			// CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG93]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG92]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG93]]
	// CHECK5: omp.dispatch.cond:			// CHECK5: omp.dispatch.cond:
	// CHECK5-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB27]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]), !dbg [[DBG92]]			// CHECK5-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB27]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]), !dbg [[DBG93]]
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG92]]			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG93]]
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG92]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]], !dbg [[DBG93]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG93]]			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG94]]
	// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]]			// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG92]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG93]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG93]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG94]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG92]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]], !dbg [[DBG93]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG93]]			// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG94]]
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG93]]			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG94]]
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG93]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG94]]
	// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG93]]			// CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG94]]
	// CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG93]]			// CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG94]]
	// CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG93]]			// CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG94]]
	// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG93]]			// CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG94]]
	// CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG95:![0-9]+]]			// CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG96:![0-9]+]]
	// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG95]]			// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG96]]
	// CHECK5-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !dbg [[DBG95]], !llvm.access.group !94			// CHECK5-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !dbg [[DBG96]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG96:![0-9]+]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !dbg [[DBG97:![0-9]+]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG96]]			// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG97]]
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG96]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG97]]
	// CHECK5-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG96]]			// CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG97]]
	// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG96]]			// CHECK5-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG97]]
	// CHECK5-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG96]]			// CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG97]]
	// CHECK5-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG96]]			// CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG97]]
	// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG96]]			// CHECK5-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG97]]
	// CHECK5-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG96]]			// CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG97]]
	// CHECK5-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG96]]			// CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG97]]
	// CHECK5-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG96]]			// CHECK5-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG97]]
	// CHECK5-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !dbg [[DBG96]], !llvm.access.group !94			// CHECK5-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !dbg [[DBG97]], !llvm.access.group !95
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG97:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG98:![0-9]+]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG92]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG93]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG93]]			// CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG94]]
	// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94			// CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP98:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP99:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG92]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG93]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP100:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP101:![0-9]+]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: ret void, !dbg [[DBG97]]			// CHECK5-NEXT: ret void, !dbg [[DBG98]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z3foov			// CHECK5-LABEL: define {{[^@]+}}@_Z3foov
	// CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG101:![0-9]+]] {			// CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG102:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG102:![0-9]+]]			// CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG103:![0-9]+]]
	// CHECK5-NEXT: ret i32 0, !dbg [[DBG102]]			// CHECK5-NEXT: ret i32 0, !dbg [[DBG103]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi			// CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi
	// CHECK5-SAME: (float* [[A:%.]], i32 [[N:%.]]) #[[ATTR0]] !dbg [[DBG103:![0-9]+]] {			// CHECK5-SAME: (float* [[A:%.]], i32 [[N:%.]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float, align 8
	// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8			// CHECK5-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8
	// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8			// CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
	// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4			// CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
	// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32 [[N_ADDR]], align 4, !dbg [[DBG104:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load i32, i32 [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG104]]			// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]]
	// CHECK5-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG104]]			// CHECK5-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG105]]
	// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG104]]			// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG105]]
	// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG104]]			// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]]
	// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG104]]			// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG105]]
	// CHECK5-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]]			// CHECK5-NEXT: [[TMP3:%.]] = load i32, i32 [[N_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
	// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[N_CASTED]] to i32*, !dbg [[DBG105]]			// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[N_CASTED]] to i32*, !dbg [[DBG106]]
	// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4, !dbg [[DBG105]]			// CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4, !dbg [[DBG106]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8, !dbg [[DBG105]]			// CHECK5-NEXT: [[TMP4:%.]] = load i64, i64 [[N_CASTED]], align 8, !dbg [[DBG106]]
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB32:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, float*, i64, i64) @.omp_outlined..8 to void (i32, i32, ...)), float* [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG105]]			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB32:[0-9]+]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, float*, i64, i64) @.omp_outlined..8 to void (i32, i32, ...)), float* [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG106]]
	// CHECK5-NEXT: [[TMP5:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG106:![0-9]+]]			// CHECK5-NEXT: [[TMP5:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG107:![0-9]+]]
	// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]), !dbg [[DBG106]]			// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]), !dbg [[DBG107]]
	// CHECK5-NEXT: ret void, !dbg [[DBG106]]			// CHECK5-NEXT: ret void, !dbg [[DBG107]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8			// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8
	// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], i64 [[VLA:%.]], i64 [[N:%.]]) #[[ATTR1]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG107:![0-9]+]] {			// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], float* nonnull align 8 dereferenceable(8) [[A:%.]], i64 [[VLA:%.]], i64 [[N:%.]]) #[[ATTR1]] personality i8 bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG108:![0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8			// CHECK5-NEXT: [[A_ADDR:%.]] = alloca float*, align 8
	// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8			// CHECK5-NEXT: [[SAVED_STACK:%.]] = alloca i8, align 8
	// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8			// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
	// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
	// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8			// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
	// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8			// CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 8
	// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8			// CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
	// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8			// CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8
	// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG108:![0-9]+]]			// CHECK5-NEXT: [[TMP0:%.]] = load float, float** [[A_ADDR]], align 8, !dbg [[DBG109:![0-9]+]]
	// CHECK5-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG108]]			// CHECK5-NEXT: [[TMP1:%.]] = load i64, i64 [[VLA_ADDR]], align 8, !dbg [[DBG109]]
	// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*, !dbg [[DBG108]]			// CHECK5-NEXT: [[CONV:%.]] = bitcast i64 [[N_ADDR]] to i32*, !dbg [[DBG109]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG109:![0-9]+]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG110:![0-9]+]]
	// CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG108]]			// CHECK5-NEXT: [[TMP2:%.]] = call i8 @llvm.stacksave(), !dbg [[DBG109]]
	// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG108]]			// CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG109]]
	// CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG108]]			// CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG109]]
	// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG108]]			// CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG109]]
	// CHECK5-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG108]]			// CHECK5-NEXT: [[TMP3:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG109]]
	// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4, !dbg [[DBG108]]			// CHECK5-NEXT: [[TMP4:%.]] = load i32, i32 [[TMP3]], align 4, !dbg [[DBG109]]
	// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG108]]			// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG109]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG108]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG109]]
	// CHECK5: omp.dispatch.cond:			// CHECK5: omp.dispatch.cond:
	// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG109]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG110]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG109]]			// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.]], label [[COND_FALSE:%.]], !dbg [[DBG110]]
	// CHECK5: cond.true:			// CHECK5: cond.true:
	// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG109]]			// CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG110]]
	// CHECK5: cond.false:			// CHECK5: cond.false:
	// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG109]]			// CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG110]]
	// CHECK5: cond.end:			// CHECK5: cond.end:
	// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG109]]			// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG109]]			// CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG110]]
	// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]], !dbg [[DBG108]]			// CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_CLEANUP:%.]], !dbg [[DBG109]]
	// CHECK5: omp.dispatch.cleanup:			// CHECK5: omp.dispatch.cleanup:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG108]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG109]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG108]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG109]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG109]]			// CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG110]]
	// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]], !dbg [[DBG108]]			// CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_COND_CLEANUP:%.]], !dbg [[DBG109]]
	// CHECK5: omp.inner.for.cond.cleanup:			// CHECK5: omp.inner.for.cond.cleanup:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG108]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG109]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG109]]			// CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG110]]
	// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG109]]			// CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov()			// CHECK5-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov()
	// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG110:![0-9]+]]			// CHECK5-NEXT: to label [[INVOKE_CONT:%.]] unwind label [[TERMINATE_LPAD:%.]], !dbg [[DBG111:![0-9]+]]
	// CHECK5: invoke.cont:			// CHECK5: invoke.cont:
	// CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG110]]			// CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]]
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG110]]			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG111]]
	// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG110]]			// CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG111]]
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG110]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]]
	// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG110]]			// CHECK5-NEXT: [[TMP14:%.]] = load float, float [[ARRAYIDX]], align 4, !dbg [[DBG111]]
	// CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]], !dbg [[DBG110]]			// CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]], !dbg [[DBG111]]
	// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[CONV]], align 8, !dbg [[DBG110]]			// CHECK5-NEXT: [[TMP15:%.]] = load i32, i32 [[CONV]], align 8, !dbg [[DBG111]]
	// CHECK5-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG110]]			// CHECK5-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]]
	// CHECK5-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]], !dbg [[DBG110]]			// CHECK5-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]], !dbg [[DBG111]]
	// CHECK5-NEXT: [[TMP16:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG110]]			// CHECK5-NEXT: [[TMP16:%.]] = load float, float** [[TMP0]], align 8, !dbg [[DBG111]]
	// CHECK5-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG110]]			// CHECK5-NEXT: [[TMP17:%.]] = load i32, i32 [[I]], align 4, !dbg [[DBG111]]
	// CHECK5-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG110]]			// CHECK5-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG111]]
	// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM8]], !dbg [[DBG110]]			// CHECK5-NEXT: [[ARRAYIDX9:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM8]], !dbg [[DBG111]]
	// CHECK5-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX9]], align 4, !dbg [[DBG110]]			// CHECK5-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX9]], align 4, !dbg [[DBG111]]
	// CHECK5-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]], !dbg [[DBG110]]			// CHECK5-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]], !dbg [[DBG111]]
	// CHECK5-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG110]]			// CHECK5-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG111]]
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG110]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG111]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG108]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG109]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG109]]			// CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG108]], !llvm.loop [[LOOP111:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP112:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG108]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG109]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG109]]			// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG109]]			// CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG110]]
	// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]]			// CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG108]], !llvm.loop [[LOOP112:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP113:![0-9]+]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG108]]			// CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG109]]
	// CHECK5-NEXT: [[TMP24:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG108]]			// CHECK5-NEXT: [[TMP24:%.]] = load i8, i8** [[SAVED_STACK]], align 8, !dbg [[DBG109]]
	// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]), !dbg [[DBG108]]			// CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]), !dbg [[DBG109]]
	// CHECK5-NEXT: ret void, !dbg [[DBG110]]			// CHECK5-NEXT: ret void, !dbg [[DBG111]]
	// CHECK5: terminate.lpad:			// CHECK5: terminate.lpad:
	// CHECK5-NEXT: [[TMP25:%.]] = landingpad { i8, i32 }			// CHECK5-NEXT: [[TMP25:%.]] = landingpad { i8, i32 }
	// CHECK5-NEXT: catch i8* null, !dbg [[DBG110]]			// CHECK5-NEXT: catch i8* null, !dbg [[DBG111]]
	// CHECK5-NEXT: [[TMP26:%.]] = extractvalue { i8, i32 } [[TMP25]], 0, !dbg [[DBG110]]			// CHECK5-NEXT: [[TMP26:%.]] = extractvalue { i8, i32 } [[TMP25]], 0, !dbg [[DBG111]]
	// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG110]]			// CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG111]]
	// CHECK5-NEXT: unreachable, !dbg [[DBG110]]			// CHECK5-NEXT: unreachable, !dbg [[DBG111]]
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate			// CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate
	// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] {			// CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] {
	// CHECK5-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]]			// CHECK5-NEXT: [[TMP2:%.]] = call i8 @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]]
	// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]			// CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]]
	// CHECK5-NEXT: unreachable			// CHECK5-NEXT: unreachable
	//			//
	▲ Show 20 Lines • Show All 522 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK6-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK6-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4			// CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK6-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK6-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !5
	// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !4			// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !5
	// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4			// CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK6-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4			// CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK6-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8			// CHECK6-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1			// CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1
	// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]			// CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
	// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP10:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127			// CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127
	// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]			// CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]]
	// CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7			// CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP11:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP12:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP11]], i64 [[TMP12]]
	// CHECK6-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK6-NEXT: [[TMP13:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP14:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]			// CHECK6-NEXT: [[ARRAYIDX2:%.]] = getelementptr inbounds float, float [[TMP14]], i64 [[TMP15]]
	// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !7			// CHECK6-NEXT: [[TMP16:%.]] = load float, float [[ARRAYIDX2]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]			// CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
	// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP17:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP18:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]			// CHECK6-NEXT: [[ARRAYIDX4:%.]] = getelementptr inbounds float, float [[TMP17]], i64 [[TMP18]]
	// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !7			// CHECK6-NEXT: [[TMP19:%.]] = load float, float [[ARRAYIDX4]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]			// CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
	// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP20:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP21:%.]] = load i64, i64 [[I]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]			// CHECK6-NEXT: [[ARRAYIDX6:%.]] = getelementptr inbounds float, float [[TMP20]], i64 [[TMP21]]
	// CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7			// CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK6-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1			// CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1
	// CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7			// CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8			// CHECK6-NEXT: [[TMP16:%.]] = load i64, i64 [[DOTOMP_LB]], align 8
	// CHECK6-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8			// CHECK6-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP17:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP18:%.]] = load i64, i64 [[DOTOMP_UB]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]			// CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
	// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10			// CHECK6-NEXT: [[TMP19:%.]] = load i8, i8 [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11
	// CHECK6-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64			// CHECK6-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
	// CHECK6-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP20:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11			// CHECK6-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
	// CHECK6-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1			// CHECK6-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
	// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]			// CHECK6-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
	// CHECK6-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8			// CHECK6-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
	// CHECK6-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10			// CHECK6-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP22:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11			// CHECK6-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
	// CHECK6-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11			// CHECK6-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
	// CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]			// CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
	// CHECK6-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1			// CHECK6-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
	// CHECK6-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]			// CHECK6-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
	// CHECK6-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32			// CHECK6-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
	// CHECK6-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10			// CHECK6-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP23:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK6-NEXT: [[TMP24:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP23]], i64 [[IDXPROM]]
	// CHECK6-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK6-NEXT: [[TMP25:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP26:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK6-NEXT: [[TMP27:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK6-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64			// CHECK6-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
	// CHECK6-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]			// CHECK6-NEXT: [[ARRAYIDX22:%.]] = getelementptr inbounds float, float [[TMP26]], i64 [[IDXPROM21]]
	// CHECK6-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !10			// CHECK6-NEXT: [[TMP28:%.]] = load float, float [[ARRAYIDX22]], align 4, !llvm.access.group !11
	// CHECK6-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]			// CHECK6-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
	// CHECK6-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP29:%.]] = load float, float** [[TMP4]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK6-NEXT: [[TMP30:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK6-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64			// CHECK6-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
	// CHECK6-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]			// CHECK6-NEXT: [[ARRAYIDX25:%.]] = getelementptr inbounds float, float [[TMP29]], i64 [[IDXPROM24]]
	// CHECK6-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !10			// CHECK6-NEXT: [[TMP31:%.]] = load float, float [[ARRAYIDX25]], align 4, !llvm.access.group !11
	// CHECK6-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]			// CHECK6-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
	// CHECK6-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP32:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !10			// CHECK6-NEXT: [[TMP33:%.]] = load i8, i8 [[I7]], align 1, !llvm.access.group !11
	// CHECK6-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64			// CHECK6-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
	// CHECK6-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]			// CHECK6-NEXT: [[ARRAYIDX28:%.]] = getelementptr inbounds float, float [[TMP32]], i64 [[IDXPROM27]]
	// CHECK6-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10			// CHECK6-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK6-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1			// CHECK6-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
	// CHECK6-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10			// CHECK6-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: br label [[OMP_PRECOND_END]]			// CHECK6-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK6: omp.precond.end:			// CHECK6: omp.precond.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP6:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20			// CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]]
	// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8			// CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8
	// CHECK6-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13			// CHECK6-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20			// CHECK6-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
	// CHECK6-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20			// CHECK6-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
	// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]			// CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
	// CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1			// CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
	// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]			// CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
	// CHECK6-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13			// CHECK6-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !13			// CHECK6-NEXT: [[TMP13:%.]] = load float, float** [[TMP1]], align 8, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK6-NEXT: [[TMP14:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds float, float [[TMP13]], i64 [[IDXPROM]]
	// CHECK6-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP15:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !13			// CHECK6-NEXT: [[TMP16:%.]] = load float, float** [[TMP2]], align 8, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK6-NEXT: [[TMP17:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64			// CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
	// CHECK6-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]			// CHECK6-NEXT: [[ARRAYIDX7:%.]] = getelementptr inbounds float, float [[TMP16]], i64 [[IDXPROM6]]
	// CHECK6-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP18:%.]] = load float, float [[ARRAYIDX7]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]			// CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
	// CHECK6-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !13			// CHECK6-NEXT: [[TMP19:%.]] = load float, float** [[TMP3]], align 8, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK6-NEXT: [[TMP20:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64			// CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
	// CHECK6-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]			// CHECK6-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP19]], i64 [[IDXPROM9]]
	// CHECK6-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]			// CHECK6-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
	// CHECK6-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !13			// CHECK6-NEXT: [[TMP22:%.]] = load float, float** [[TMP0]], align 8, !llvm.access.group !14
	// CHECK6-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !13			// CHECK6-NEXT: [[TMP23:%.]] = load i8, i8 [[I]], align 1, !llvm.access.group !14
	// CHECK6-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64			// CHECK6-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
	// CHECK6-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]			// CHECK6-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds float, float [[TMP22]], i64 [[IDXPROM12]]
	// CHECK6-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13			// CHECK6-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK6-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 997 Lines • ▼ Show 20 Lines
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP45:%.]] = load i32, i32 [[TMP44]], align 4			// CHECK12-NEXT: [[TMP45:%.]] = load i32, i32 [[TMP44]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]])
	// CHECK12-NEXT: br label [[OMP_PRECOND_END]]			// CHECK12-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK12: omp.precond.end:			// CHECK12: omp.precond.end:
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 446 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 401 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 408 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_master_taskloop_codegen.cpp

	Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: .omp_outlined..1.exit:			// CHECK1: .omp_outlined..1.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !28
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !28
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !28
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: .omp_outlined..3.exit:			// CHECK1: .omp_outlined..3.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !40
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !40
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP20]], i32 0, i32 0			// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP20]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP21]], align 8			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP21]], align 8
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK1-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK1-NEXT: store i32 [[TMP26]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[TMP26]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1			// CHECK1-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[TMP27]], align 8			// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[TMP27]], align 8
	// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP29]], i64 [[IDXPROM_I]]			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP29]], i64 [[IDXPROM_I]]
	// CHECK1-NEXT: [[TMP33:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8			// CHECK1-NEXT: [[TMP33:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8
	// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP34]], align 8			// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP34]], align 8
	// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[TMP35]], align 4			// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[TMP35]], align 4
	// CHECK1-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP36]] to i64			// CHECK1-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP36]] to i64
	// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP33]], i64 [[IDXPROM4_I]]			// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP33]], i64 [[IDXPROM4_I]]
	// CHECK1-NEXT: [[TMP37:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1			// CHECK1-NEXT: [[TMP37:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1
	// CHECK1-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP37]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP37]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !40
	// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP38]] to i64			// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP38]] to i64
	// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP40:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP40:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP39]], [[TMP40]]			// CHECK1-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP39]], [[TMP40]]
	// CHECK1-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1			// CHECK1-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
	// CHECK1-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64			// CHECK1-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
	// CHECK1-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]			// CHECK1-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
	// CHECK1-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1			// CHECK1-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
	// CHECK1-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !39			// CHECK1-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: store i32 [[TMP41]], i32* [[J_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[TMP41]], i32* [[J_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP42:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !40
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP42]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP42]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]
	// CHECK1: land.lhs.true.i:			// CHECK1: land.lhs.true.i:
	// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP43]], [[TMP44]]			// CHECK1-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP43]], [[TMP44]]
	// CHECK1-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK1-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK1: taskloop.if.then.i:			// CHECK1: taskloop.if.then.i:
	// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: store i64 [[TMP45]], i64* [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK1-NEXT: store i64 [[TMP45]], i64* [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[TMP46:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK1-NEXT: [[TMP46:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP47:%.]] = load i32, i32** [[TMP46]], align 8			// CHECK1-NEXT: [[TMP47:%.]] = load i32, i32** [[TMP46]], align 8
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8			// CHECK1-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP50:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP50:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[TMP51:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP51:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP50]], [[TMP51]]			// CHECK1-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP50]], [[TMP51]]
	// CHECK1-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP52:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP52:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP53]], [[TMP54]]			// CHECK1-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP53]], [[TMP54]]
	// CHECK1-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1			// CHECK1-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
	// CHECK1-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64			// CHECK1-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
	// CHECK1-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP52]], [[CONV22_I]]			// CHECK1-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP52]], [[CONV22_I]]
	// CHECK1-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32			// CHECK1-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
	// CHECK1-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP55]] to i64			// CHECK1-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP55]] to i64
	// CHECK1-NEXT: [[TMP56:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP56:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[TMP57:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP57:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP59:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP59:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP58]], [[TMP59]]			// CHECK1-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP58]], [[TMP59]]
	// CHECK1-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1			// CHECK1-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
	// CHECK1-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64			// CHECK1-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
	// CHECK1-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP57]], [[CONV33_I]]			// CHECK1-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP57]], [[CONV33_I]]
	// CHECK1-NEXT: [[TMP60:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP60:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK1-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP60]], [[TMP61]]			// CHECK1-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP60]], [[TMP61]]
	// CHECK1-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1			// CHECK1-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
	// CHECK1-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64			// CHECK1-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
	// CHECK1-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]			// CHECK1-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
	// CHECK1-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP56]], [[MUL41_I]]			// CHECK1-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP56]], [[MUL41_I]]
	// CHECK1-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]			// CHECK1-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
	// CHECK1-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32			// CHECK1-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
	// CHECK1-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !39			// CHECK1-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !40
	// CHECK1-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK1-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK1-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP62]], 1			// CHECK1-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP62]], 1
	// CHECK1-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK1-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK1: .omp_outlined..6.exit:			// CHECK1: .omp_outlined..6.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8
	▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !52
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !52
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK1-NEXT: [[TMP26:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP25]], i32 4) #[[ATTR2]]			// CHECK1-NEXT: [[TMP26:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP25]], i32 4) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK1-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK1-NEXT: br i1 [[TMP27]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK1-NEXT: br i1 [[TMP27]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK1: .cancel.exit.i:			// CHECK1: .cancel.exit.i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT:%.*]]
	// CHECK1: .cancel.continue.i:			// CHECK1: .cancel.continue.i:
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK1-NEXT: [[TMP29:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i32 4) #[[ATTR2]]			// CHECK1-NEXT: [[TMP29:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i32 4) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
	// CHECK1-NEXT: br i1 [[TMP30]], label [[DOTCANCEL_EXIT2_I:%.]], label [[DOTCANCEL_CONTINUE3_I:%.]]			// CHECK1-NEXT: br i1 [[TMP30]], label [[DOTCANCEL_EXIT2_I:%.]], label [[DOTCANCEL_CONTINUE3_I:%.]]
	// CHECK1: .cancel.exit2.i:			// CHECK1: .cancel.exit2.i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK1: .cancel.continue3.i:			// CHECK1: .cancel.continue3.i:
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK1-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP31]], 1			// CHECK1-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP31]], 1
	// CHECK1-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK1: .omp_outlined..9.exit:			// CHECK1: .omp_outlined..9.exit:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init			// CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
	// CHECK1-SAME: () #[[ATTR7:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {			// CHECK1-SAME: () #[[ATTR7:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1)			// CHECK1-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !63			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !64
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_6:%.]], %struct.anon.6* [[TMP20]], i32 0, i32 0			// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_6:%.]], %struct.anon.6* [[TMP20]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8
	// CHECK1-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !63			// CHECK1-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK1-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK1-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK1-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1			// CHECK1-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1
	// CHECK1-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !63			// CHECK1-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !64
	// CHECK1-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !63			// CHECK1-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !63			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i32 0, i32* [[TMP27]], align 4			// CHECK1-NEXT: store i32 0, i32* [[TMP27]], align 4
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__12_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__12_EXIT:%.]]
	// CHECK1: taskloop.if.then.i:			// CHECK1: taskloop.if.then.i:
	// CHECK1-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !63			// CHECK1-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK1-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]			// CHECK1-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]
	// CHECK1-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !63			// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4			// CHECK1-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4
	// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK1-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1			// CHECK1-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1
	// CHECK1-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK1-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__12_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__12_EXIT]]
	// CHECK1: .omp_outlined..12.exit:			// CHECK1: .omp_outlined..12.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp			// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: .omp_outlined..1.exit:			// CHECK2: .omp_outlined..1.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !28
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !28
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !28
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: .omp_outlined..3.exit:			// CHECK2: .omp_outlined..3.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !40
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !40
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP20]], i32 0, i32 0			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP20]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP21]], align 8			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP21]], align 8
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK2-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[TMP23]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK2-NEXT: store i32 [[TMP26]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[TMP26]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1			// CHECK2-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[TMP27]], align 8			// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[TMP27]], align 8
	// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP29]], i64 [[IDXPROM_I]]			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP29]], i64 [[IDXPROM_I]]
	// CHECK2-NEXT: [[TMP33:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8			// CHECK2-NEXT: [[TMP33:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8
	// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP34]], align 8			// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP34]], align 8
	// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[TMP35]], align 4			// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[TMP35]], align 4
	// CHECK2-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP36]] to i64			// CHECK2-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP36]] to i64
	// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP33]], i64 [[IDXPROM4_I]]			// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP33]], i64 [[IDXPROM4_I]]
	// CHECK2-NEXT: [[TMP37:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1			// CHECK2-NEXT: [[TMP37:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1
	// CHECK2-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP37]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP37]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !40
	// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP38]] to i64			// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP38]] to i64
	// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP40:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP40:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP39]], [[TMP40]]			// CHECK2-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP39]], [[TMP40]]
	// CHECK2-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1			// CHECK2-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
	// CHECK2-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64			// CHECK2-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
	// CHECK2-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]			// CHECK2-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
	// CHECK2-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1			// CHECK2-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
	// CHECK2-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !39			// CHECK2-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: store i32 [[TMP41]], i32* [[J_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[TMP41]], i32* [[J_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP42:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !40
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP42]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP42]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]
	// CHECK2: land.lhs.true.i:			// CHECK2: land.lhs.true.i:
	// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP43]], [[TMP44]]			// CHECK2-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP43]], [[TMP44]]
	// CHECK2-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK2-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK2: taskloop.if.then.i:			// CHECK2: taskloop.if.then.i:
	// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: store i64 [[TMP45]], i64* [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK2-NEXT: store i64 [[TMP45]], i64* [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[TMP46:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0			// CHECK2-NEXT: [[TMP46:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP47:%.]] = load i32, i32** [[TMP46]], align 8			// CHECK2-NEXT: [[TMP47:%.]] = load i32, i32** [[TMP46]], align 8
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP20]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8			// CHECK2-NEXT: [[TMP49:%.]] = load i8, i8** [[TMP48]], align 8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP50:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP50:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[TMP51:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP51:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP50]], [[TMP51]]			// CHECK2-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP50]], [[TMP51]]
	// CHECK2-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP52:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP52:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP53]], [[TMP54]]			// CHECK2-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP53]], [[TMP54]]
	// CHECK2-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1			// CHECK2-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
	// CHECK2-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64			// CHECK2-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
	// CHECK2-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP52]], [[CONV22_I]]			// CHECK2-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP52]], [[CONV22_I]]
	// CHECK2-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32			// CHECK2-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
	// CHECK2-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP55]] to i64			// CHECK2-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP55]] to i64
	// CHECK2-NEXT: [[TMP56:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP56:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[TMP57:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP57:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP59:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP59:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP58]], [[TMP59]]			// CHECK2-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP58]], [[TMP59]]
	// CHECK2-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1			// CHECK2-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
	// CHECK2-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64			// CHECK2-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
	// CHECK2-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP57]], [[CONV33_I]]			// CHECK2-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP57]], [[CONV33_I]]
	// CHECK2-NEXT: [[TMP60:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP60:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !39			// CHECK2-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP60]], [[TMP61]]			// CHECK2-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP60]], [[TMP61]]
	// CHECK2-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1			// CHECK2-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
	// CHECK2-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64			// CHECK2-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
	// CHECK2-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]			// CHECK2-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
	// CHECK2-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP56]], [[MUL41_I]]			// CHECK2-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP56]], [[MUL41_I]]
	// CHECK2-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]			// CHECK2-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
	// CHECK2-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32			// CHECK2-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
	// CHECK2-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !39			// CHECK2-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !40
	// CHECK2-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK2-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK2-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP62]], 1			// CHECK2-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP62]], 1
	// CHECK2-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !39			// CHECK2-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !40
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK2: .omp_outlined..6.exit:			// CHECK2: .omp_outlined..6.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8
	▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !52
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !52
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK2-NEXT: [[TMP26:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP25]], i32 4) #[[ATTR2]]			// CHECK2-NEXT: [[TMP26:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP25]], i32 4) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0			// CHECK2-NEXT: [[TMP27:%.*]] = icmp ne i32 [[TMP26]], 0
	// CHECK2-NEXT: br i1 [[TMP27]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]			// CHECK2-NEXT: br i1 [[TMP27]], label [[DOTCANCEL_EXIT_I:%.]], label [[DOTCANCEL_CONTINUE_I:%.]]
	// CHECK2: .cancel.exit.i:			// CHECK2: .cancel.exit.i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT:%.*]]
	// CHECK2: .cancel.continue.i:			// CHECK2: .cancel.continue.i:
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK2-NEXT: [[TMP29:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i32 4) #[[ATTR2]]			// CHECK2-NEXT: [[TMP29:%.]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i32 4) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0			// CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
	// CHECK2-NEXT: br i1 [[TMP30]], label [[DOTCANCEL_EXIT2_I:%.]], label [[DOTCANCEL_CONTINUE3_I:%.]]			// CHECK2-NEXT: br i1 [[TMP30]], label [[DOTCANCEL_EXIT2_I:%.]], label [[DOTCANCEL_CONTINUE3_I:%.]]
	// CHECK2: .cancel.exit2.i:			// CHECK2: .cancel.exit2.i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK2: .cancel.continue3.i:			// CHECK2: .cancel.continue3.i:
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK2-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP31]], 1			// CHECK2-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP31]], 1
	// CHECK2-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK2: .omp_outlined..9.exit:			// CHECK2: .omp_outlined..9.exit:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init			// CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
	// CHECK2-SAME: () #[[ATTR7:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {			// CHECK2-SAME: () #[[ATTR7:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1)			// CHECK2-NEXT: call void @_ZN1SC1Ei(%struct.S* nonnull align 4 dereferenceable(4) @s, i32 1)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !63			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !64
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_6:%.]], %struct.anon.6* [[TMP20]], i32 0, i32 0			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_6:%.]], %struct.anon.6* [[TMP20]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8
	// CHECK2-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !63			// CHECK2-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK2-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK2-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK2-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1			// CHECK2-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1
	// CHECK2-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !63			// CHECK2-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !64
	// CHECK2-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !63			// CHECK2-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !63			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i32 0, i32* [[TMP27]], align 4			// CHECK2-NEXT: store i32 0, i32* [[TMP27]], align 4
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__12_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__12_EXIT:%.]]
	// CHECK2: taskloop.if.then.i:			// CHECK2: taskloop.if.then.i:
	// CHECK2-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !63			// CHECK2-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6 [[TMP20]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK2-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]			// CHECK2-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]
	// CHECK2-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !63			// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4			// CHECK2-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4
	// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK2-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1			// CHECK2-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1
	// CHECK2-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK2-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__12_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__12_EXIT]]
	// CHECK2: .omp_outlined..12.exit:			// CHECK2: .omp_outlined..12.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp			// CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_codegen.cpp
	// CHECK2-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" {			// CHECK2-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__cxx_global_var_init()			// CHECK2-NEXT: call void @__cxx_global_var_init()
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//

clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp

	Show First 20 Lines • Show All 414 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)			// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)
	// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8
	// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8			// CHECK1-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8
	// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8			// CHECK1-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4			// CHECK1-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4
	// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK1-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0
	// CHECK1-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4			// CHECK1-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4
	// CHECK1-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*			// CHECK1-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*
	// CHECK1-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK1-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]]			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]]
	// CHECK1-NEXT: store i32 33, i32* [[TMP44]], align 4			// CHECK1-NEXT: store i32 33, i32* [[TMP44]], align 4
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0			// CHECK1-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
	// CHECK1-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK1: .omp.lastprivate.then.i:			// CHECK1: .omp.lastprivate.then.i:
	// CHECK1-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK1-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK1-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK1-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4			// CHECK1-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4
	// CHECK1-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4			// CHECK1-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4
	▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !28
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !28
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)			// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)
	// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8			// CHECK1-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8
	// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8			// CHECK1-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64			// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK1-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !28
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0
	// CHECK1-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4			// CHECK1-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4
	// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*			// CHECK1-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*
	// CHECK1-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*			// CHECK1-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]]			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1			// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1
	// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !27			// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !28
	// CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0			// CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
	// CHECK1-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK1: .omp.lastprivate.then.i:			// CHECK1: .omp.lastprivate.then.i:
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128
	// CHECK1-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128			// CHECK1-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128
	// CHECK1-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*			// CHECK1-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*
	// CHECK1-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*			// CHECK1-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]
	▲ Show 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)			// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)
	// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8
	// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8			// CHECK2-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8
	// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8			// CHECK2-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4			// CHECK2-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4
	// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK2-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0
	// CHECK2-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4			// CHECK2-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4
	// CHECK2-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*			// CHECK2-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*
	// CHECK2-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK2-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]]			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]]
	// CHECK2-NEXT: store i32 33, i32* [[TMP44]], align 4			// CHECK2-NEXT: store i32 33, i32* [[TMP44]], align 4
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0			// CHECK2-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
	// CHECK2-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK2: .omp.lastprivate.then.i:			// CHECK2: .omp.lastprivate.then.i:
	// CHECK2-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK2-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK2-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK2-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4			// CHECK2-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4
	// CHECK2-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4			// CHECK2-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4
	▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !28
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !28
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)			// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)
	// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8			// CHECK2-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8
	// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8			// CHECK2-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64			// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !27			// CHECK2-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !28
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !28
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0
	// CHECK2-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4			// CHECK2-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4
	// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*			// CHECK2-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*
	// CHECK2-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*			// CHECK2-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]]			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1			// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1
	// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !27			// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !27			// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !28
	// CHECK2-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0			// CHECK2-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
	// CHECK2-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK2: .omp.lastprivate.then.i:			// CHECK2: .omp.lastprivate.then.i:
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128
	// CHECK2-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128			// CHECK2-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128
	// CHECK2-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*			// CHECK2-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*
	// CHECK2-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*			// CHECK2-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]
	▲ Show 20 Lines • Show All 235 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK3-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK3-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)			// CHECK3-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)
	// CHECK3-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]			// CHECK3-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]
	// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0			// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8			// CHECK3-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8
	// CHECK3-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK3-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK3-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32			// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32
	// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK3: omp.inner.for.cond.i:			// CHECK3: omp.inner.for.cond.i:
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64			// CHECK3-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64
	// CHECK3-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]			// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]
	// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK3: omp.inner.for.body.i:			// CHECK3: omp.inner.for.body.i:
	// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !14
	// CHECK3-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8			// CHECK3-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8
	// CHECK3-NEXT: store i32 11, i32* [[TMP31]], align 4			// CHECK3-NEXT: store i32 11, i32* [[TMP31]], align 4
	// CHECK3-NEXT: [[TMP36:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 0			// CHECK3-NEXT: [[TMP36:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[TMP30]], double** [[TMP36]], align 8, !noalias !13			// CHECK3-NEXT: store double* [[TMP30]], double** [[TMP36]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP37:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 1			// CHECK3-NEXT: [[TMP37:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 1
	// CHECK3-NEXT: store i32* [[TMP31]], i32** [[TMP37]], align 8, !noalias !13			// CHECK3-NEXT: store i32* [[TMP31]], i32** [[TMP37]], align 8, !noalias !14
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) #[[ATTR3]]			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1			// CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1
	// CHECK3-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK3: omp.inner.for.end.i:			// CHECK3: omp.inner.for.end.i:
	// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0			// CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
	// CHECK3-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK3: .omp.lastprivate.then.i:			// CHECK3: .omp.lastprivate.then.i:
	// CHECK3-NEXT: [[TMP41:%.]] = load double, double [[TMP30]], align 8			// CHECK3-NEXT: [[TMP41:%.]] = load double, double [[TMP30]], align 8
	// CHECK3-NEXT: store volatile double [[TMP41]], double* [[TMP27]], align 8			// CHECK3-NEXT: store volatile double [[TMP41]], double* [[TMP27]], align 8
	// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP29]], align 4			// CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP29]], align 4
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK4-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK4-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)			// CHECK4-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)
	// CHECK4-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]			// CHECK4-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]
	// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0			// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8			// CHECK4-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8
	// CHECK4-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK4-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK4-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32			// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32
	// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK4: omp.inner.for.cond.i:			// CHECK4: omp.inner.for.cond.i:
	// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64			// CHECK4-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64
	// CHECK4-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]			// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]
	// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK4: omp.inner.for.body.i:			// CHECK4: omp.inner.for.body.i:
	// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !14
	// CHECK4-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8			// CHECK4-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8
	// CHECK4-NEXT: store i32 11, i32* [[TMP31]], align 4			// CHECK4-NEXT: store i32 11, i32* [[TMP31]], align 4
	// CHECK4-NEXT: [[BLOCK_ISA_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 0			// CHECK4-NEXT: [[BLOCK_ISA_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 0
	// CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8), i8* [[BLOCK_ISA_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8), i8* [[BLOCK_ISA_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[BLOCK_FLAGS_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 1			// CHECK4-NEXT: [[BLOCK_FLAGS_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 1
	// CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !13			// CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[BLOCK_RESERVED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 2			// CHECK4-NEXT: [[BLOCK_RESERVED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 2
	// CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[BLOCK_INVOKE_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 3			// CHECK4-NEXT: [[BLOCK_INVOKE_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 3
	// CHECK4-NEXT: store i8* bitcast (void (i8) @_block_invoke to i8), i8* [[BLOCK_INVOKE_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* bitcast (void (i8) @_block_invoke to i8), i8* [[BLOCK_INVOKE_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[BLOCK_DESCRIPTOR_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 4			// CHECK4-NEXT: [[BLOCK_DESCRIPTOR_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 4
	// CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8, i8 }* @__block_descriptor_tmp.2 to %struct.__block_descriptor), %struct.__block_descriptor* [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !13			// CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8, i8 }* @__block_descriptor_tmp.2 to %struct.__block_descriptor), %struct.__block_descriptor* [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[BLOCK_CAPTURED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 5			// CHECK4-NEXT: [[BLOCK_CAPTURED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 5
	// CHECK4-NEXT: [[TMP36:%.]] = load volatile double, double [[TMP30]], align 8			// CHECK4-NEXT: [[TMP36:%.]] = load volatile double, double [[TMP30]], align 8
	// CHECK4-NEXT: store volatile double [[TMP36]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !13			// CHECK4-NEXT: store volatile double [[TMP36]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[BLOCK_CAPTURED3_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 6			// CHECK4-NEXT: [[BLOCK_CAPTURED3_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK4-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK4-NEXT: store i32 [[TMP37]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !13			// CHECK4-NEXT: store i32 [[TMP37]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP38:%.]] = bitcast <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_I]] to void ()*			// CHECK4-NEXT: [[TMP38:%.]] = bitcast <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_I]] to void ()*
	// CHECK4-NEXT: [[BLOCK_LITERAL_I:%.]] = bitcast void () [[TMP38]] to %struct.__block_literal_generic*			// CHECK4-NEXT: [[BLOCK_LITERAL_I:%.]] = bitcast void () [[TMP38]] to %struct.__block_literal_generic*
	// CHECK4-NEXT: [[TMP39:%.]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3			// CHECK4-NEXT: [[TMP39:%.]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3
	// CHECK4-NEXT: [[TMP40:%.]] = bitcast %struct.__block_literal_generic [[BLOCK_LITERAL_I]] to i8*			// CHECK4-NEXT: [[TMP40:%.]] = bitcast %struct.__block_literal_generic [[BLOCK_LITERAL_I]] to i8*
	// CHECK4-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP39]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP39]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP42:%.]] = bitcast i8 [[TMP41]] to void (i8)			// CHECK4-NEXT: [[TMP42:%.]] = bitcast i8 [[TMP41]] to void (i8)
	// CHECK4-NEXT: call void [[TMP42]](i8* [[TMP40]]) #[[ATTR4]]			// CHECK4-NEXT: call void [[TMP42]](i8* [[TMP40]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], 1			// CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], 1
	// CHECK4-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK4: omp.inner.for.end.i:			// CHECK4: omp.inner.for.end.i:
	// CHECK4-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0			// CHECK4-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
	// CHECK4-NEXT: br i1 [[TMP45]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK4-NEXT: br i1 [[TMP45]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK4: .omp.lastprivate.then.i:			// CHECK4: .omp.lastprivate.then.i:
	// CHECK4-NEXT: [[TMP46:%.]] = load double, double [[TMP30]], align 8			// CHECK4-NEXT: [[TMP46:%.]] = load double, double [[TMP30]], align 8
	// CHECK4-NEXT: store volatile double [[TMP46]], double* [[TMP27]], align 8			// CHECK4-NEXT: store volatile double [[TMP46]], double* [[TMP27]], align 8
	// CHECK4-NEXT: [[TMP47:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK4-NEXT: [[TMP47:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK4-NEXT: store i32 [[TMP47]], i32* [[TMP29]], align 4			// CHECK4-NEXT: store i32 [[TMP47]], i32* [[TMP29]], align 4
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK5-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK5-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK5-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK5-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK5-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK5-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK5-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK5-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK5-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, float, %struct.St) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, float, %struct.St) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK5-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0			// CHECK5-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK5-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK5-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, float, %struct.St)			// CHECK5-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, float, %struct.St)
	// CHECK5-NEXT: call void [[TMP27]](i8* [[TMP26]], float* [[DOTLASTPRIV_PTR_ADDR_I]], %struct.St* [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]			// CHECK5-NEXT: call void [[TMP27]](i8* [[TMP26]], float* [[DOTLASTPRIV_PTR_ADDR_I]], %struct.St* [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]
	// CHECK5-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK5-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK5-NEXT: [[TMP29:%.]] = load float, float** [[TMP28]], align 8			// CHECK5-NEXT: [[TMP29:%.]] = load float, float** [[TMP28]], align 8
	// CHECK5-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK5-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP31:%.]] = load %struct.St, %struct.St** [[TMP30]], align 8			// CHECK5-NEXT: [[TMP31:%.]] = load %struct.St, %struct.St** [[TMP30]], align 8
	// CHECK5-NEXT: [[TMP32:%.]] = load float, float** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP32:%.]] = load float, float** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP33:%.]] = load %struct.St, %struct.St** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP33:%.]] = load %struct.St, %struct.St** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP34]] to i32			// CHECK5-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP34]] to i32
	// CHECK5-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK5: omp.inner.for.cond.i:			// CHECK5: omp.inner.for.cond.i:
	// CHECK5-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK5-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK5-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP35]] to i64			// CHECK5-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP35]] to i64
	// CHECK5-NEXT: [[TMP36:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP36:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP36]]			// CHECK5-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP36]]
	// CHECK5-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK5-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK5: omp.inner.for.body.i:			// CHECK5: omp.inner.for.body.i:
	// CHECK5-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK5-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK5-NEXT: store i32 [[TMP37]], i32* [[I_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[TMP37]], i32* [[I_I]], align 4, !noalias !14
	// CHECK5-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK5-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK5-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1			// CHECK5-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1
	// CHECK5-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK5: omp.inner.for.end.i:			// CHECK5: omp.inner.for.end.i:
	// CHECK5-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK5-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK5-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0			// CHECK5-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
	// CHECK5-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK5-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK5: .omp.lastprivate.then.i:			// CHECK5: .omp.lastprivate.then.i:
	// CHECK5-NEXT: [[TMP41:%.]] = load float, float** [[TMP32]], align 8			// CHECK5-NEXT: [[TMP41:%.]] = load float, float** [[TMP32]], align 8
	// CHECK5-NEXT: store float* [[TMP41]], float** [[TMP29]], align 8			// CHECK5-NEXT: store float* [[TMP41]], float** [[TMP29]], align 8
	// CHECK5-NEXT: [[TMP42:%.]] = load %struct.St, %struct.St** [[TMP33]], align 8			// CHECK5-NEXT: [[TMP42:%.]] = load %struct.St, %struct.St** [[TMP33]], align 8
	// CHECK5-NEXT: store %struct.St* [[TMP42]], %struct.St** [[TMP31]], align 8			// CHECK5-NEXT: store %struct.St* [[TMP42]], %struct.St** [[TMP31]], align 8
	// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK6-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK6-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK6-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK6-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK6-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK6-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK6-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK6-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK6-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK6-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK6-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK6-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK6-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)			// CHECK6-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)
	// CHECK6-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2:[0-9]+]]			// CHECK6-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2:[0-9]+]]
	// CHECK6-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0			// CHECK6-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK6-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK6-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK6-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK6: omp.inner.for.cond.i:			// CHECK6: omp.inner.for.cond.i:
	// CHECK6-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK6-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP30]] to i64			// CHECK6-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP30]] to i64
	// CHECK6-NEXT: [[TMP31:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP31:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP31]]			// CHECK6-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP31]]
	// CHECK6-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK6-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK6: omp.inner.for.body.i:			// CHECK6: omp.inner.for.body.i:
	// CHECK6-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK6-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK6-NEXT: store i32 [[TMP32]], i32* [[I_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[TMP32]], i32* [[I_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK6-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP33]], 1			// CHECK6-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP33]], 1
	// CHECK6-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK6: omp.inner.for.end.i:			// CHECK6: omp.inner.for.end.i:
	// CHECK6-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK6-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0			// CHECK6-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
	// CHECK6-NEXT: br i1 [[TMP35]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK6-NEXT: br i1 [[TMP35]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK6: .omp.lastprivate.then.i:			// CHECK6: .omp.lastprivate.then.i:
	// CHECK6-NEXT: store i32 10, i32* [[I_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 10, i32* [[I_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[TMP36:%.]] = load i32, i32 [[I_I]], align 4, !noalias !13			// CHECK6-NEXT: [[TMP36:%.]] = load i32, i32 [[I_I]], align 4, !noalias !14
	// CHECK6-NEXT: store i32 [[TMP36]], i32* [[TMP27]], align 4			// CHECK6-NEXT: store i32 [[TMP36]], i32* [[TMP27]], align 4
	// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK6: .omp_outlined..1.exit:			// CHECK6: .omp_outlined..1.exit:
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_dup.			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_dup.
	// CHECK6-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.]], %struct.kmp_task_t_with_privates [[TMP1:%.]], i32 [[TMP2:%.]]) #[[ATTR5]] {			// CHECK6-SAME: (%struct.kmp_task_t_with_privates* [[TMP0:%.]], %struct.kmp_task_t_with_privates [[TMP1:%.]], i32 [[TMP2:%.]]) #[[ATTR5]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTADDR:%.]] = alloca %struct.kmp_task_t_with_privates, align 8			// CHECK6-NEXT: [[DOTADDR:%.]] = alloca %struct.kmp_task_t_with_privates, align 8
	// CHECK6-NEXT: [[DOTADDR1:%.]] = alloca %struct.kmp_task_t_with_privates, align 8			// CHECK6-NEXT: [[DOTADDR1:%.]] = alloca %struct.kmp_task_t_with_privates, align 8
	// CHECK6-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
	// CHECK6-NEXT: store %struct.kmp_task_t_with_privates* [[TMP0]], %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8			// CHECK6-NEXT: store %struct.kmp_task_t_with_privates* [[TMP0]], %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8
	// CHECK6-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK6-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
	// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTADDR2]], align 4			// CHECK6-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTADDR2]], align 4
	// CHECK6-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8			// CHECK6-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8
	// CHECK6-NEXT: [[TMP7:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK6-NEXT: [[TMP7:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 198 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK1: .omp_outlined..1.exit:			// CHECK1: .omp_outlined..1.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !30			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !30			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !31
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK1-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK1-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !30, !llvm.access.group !31			// CHECK1-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !31, !llvm.access.group !32
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK1-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK1-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK1-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK1: .omp_outlined..3.exit:			// CHECK1: .omp_outlined..3.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
	// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {			// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !46			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !47
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)			// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)
	// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]			// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8			// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK1-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK1-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8
	// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK1-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK1-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8			// CHECK1-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8
	// CHECK1-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK1-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4			// CHECK1-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4
	// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64			// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]
	// CHECK1-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8			// CHECK1-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8
	// CHECK1-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4			// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4
	// CHECK1-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64			// CHECK1-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64
	// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]			// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]
	// CHECK1-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1			// CHECK1-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1
	// CHECK1-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK1-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]			// CHECK1-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]
	// CHECK1-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1			// CHECK1-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
	// CHECK1-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64			// CHECK1-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
	// CHECK1-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]			// CHECK1-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
	// CHECK1-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1			// CHECK1-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
	// CHECK1-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !46			// CHECK1-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !46			// CHECK1-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK1-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !46			// CHECK1-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]
	// CHECK1: land.lhs.true.i:			// CHECK1: land.lhs.true.i:
	// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]			// CHECK1-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]
	// CHECK1-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]			// CHECK1-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]
	// CHECK1: taskloop.if.then.i:			// CHECK1: taskloop.if.then.i:
	// CHECK1-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK1-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK1-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK1-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK1-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8			// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8
	// CHECK1-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8			// CHECK1-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP58:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP58:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP59:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP59:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP58]], [[TMP59]]			// CHECK1-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP58]], [[TMP59]]
	// CHECK1-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP62:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP62:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]			// CHECK1-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]
	// CHECK1-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1			// CHECK1-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
	// CHECK1-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64			// CHECK1-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
	// CHECK1-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP60]], [[CONV22_I]]			// CHECK1-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP60]], [[CONV22_I]]
	// CHECK1-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32			// CHECK1-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
	// CHECK1-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP63]] to i64			// CHECK1-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP63]] to i64
	// CHECK1-NEXT: [[TMP64:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP64:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP65:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP65:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP66:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP66:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP67:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP67:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP66]], [[TMP67]]			// CHECK1-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP66]], [[TMP67]]
	// CHECK1-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1			// CHECK1-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
	// CHECK1-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64			// CHECK1-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
	// CHECK1-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP65]], [[CONV33_I]]			// CHECK1-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP65]], [[CONV33_I]]
	// CHECK1-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]			// CHECK1-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]
	// CHECK1-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1			// CHECK1-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
	// CHECK1-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64			// CHECK1-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
	// CHECK1-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]			// CHECK1-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
	// CHECK1-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP64]], [[MUL41_I]]			// CHECK1-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP64]], [[MUL41_I]]
	// CHECK1-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]			// CHECK1-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
	// CHECK1-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32			// CHECK1-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
	// CHECK1-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP70:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: [[TMP70:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP70]], 1			// CHECK1-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP70]], 1
	// CHECK1-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK1-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP48:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: br label [[TASKLOOP_IF_END_I]]			// CHECK1-NEXT: br label [[TASKLOOP_IF_END_I]]
	// CHECK1: taskloop.if.end.i:			// CHECK1: taskloop.if.end.i:
	// CHECK1-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK1-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK1-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0			// CHECK1-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0
	// CHECK1-NEXT: br i1 [[TMP72]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP72]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]
	// CHECK1: .omp.lastprivate.then.i:			// CHECK1: .omp.lastprivate.then.i:
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK1: .omp_outlined..6.exit:			// CHECK1: .omp_outlined..6.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !61			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !62
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !61			// CHECK1-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !62
	// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0			// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8
	// CHECK1-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !61			// CHECK1-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !62
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK1-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !61			// CHECK1-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !62
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !61			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !62
	// CHECK1-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1			// CHECK1-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1
	// CHECK1-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !61			// CHECK1-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !62
	// CHECK1-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !61			// CHECK1-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !62
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !61			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i32 0, i32* [[TMP27]], align 4			// CHECK1-NEXT: store i32 0, i32* [[TMP27]], align 4
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !61			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !62
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK1: taskloop.if.then.i:			// CHECK1: taskloop.if.then.i:
	// CHECK1-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !61			// CHECK1-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !62
	// CHECK1-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !61			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !62
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK1-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK1-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK1-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !61, !llvm.access.group !62			// CHECK1-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !62, !llvm.access.group !63
	// CHECK1-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]			// CHECK1-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]
	// CHECK1-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK1-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !61, !llvm.access.group !62			// CHECK1-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !62, !llvm.access.group !63
	// CHECK1-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !62			// CHECK1-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !63
	// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK1-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK1-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1			// CHECK1-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1
	// CHECK1-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK1-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP63:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP64:![0-9]+]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK1: .omp_outlined..9.exit:			// CHECK1: .omp_outlined..9.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp			// CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
	// CHECK1-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {			// CHECK1-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
	▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK2: .omp_outlined..1.exit:			// CHECK2: .omp_outlined..1.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !30			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !30			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !31
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK2-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK2-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !30, !llvm.access.group !31			// CHECK2-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !31, !llvm.access.group !32
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK2-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK2-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK2-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK2: .omp_outlined..3.exit:			// CHECK2: .omp_outlined..3.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
	// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {			// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !46			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !47
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)			// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)
	// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]			// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8			// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK2-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK2-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8
	// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK2-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK2-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8			// CHECK2-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8
	// CHECK2-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK2-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4			// CHECK2-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4
	// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64			// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]
	// CHECK2-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8			// CHECK2-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8
	// CHECK2-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4			// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4
	// CHECK2-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64			// CHECK2-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64
	// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]			// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]
	// CHECK2-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1			// CHECK2-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1
	// CHECK2-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK2-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]			// CHECK2-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]
	// CHECK2-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1			// CHECK2-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
	// CHECK2-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64			// CHECK2-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
	// CHECK2-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]			// CHECK2-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
	// CHECK2-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1			// CHECK2-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
	// CHECK2-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !46			// CHECK2-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !46			// CHECK2-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK2-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !46			// CHECK2-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]
	// CHECK2: land.lhs.true.i:			// CHECK2: land.lhs.true.i:
	// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]			// CHECK2-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]
	// CHECK2-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]			// CHECK2-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]
	// CHECK2: taskloop.if.then.i:			// CHECK2: taskloop.if.then.i:
	// CHECK2-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK2-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK2-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK2-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK2-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8			// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8
	// CHECK2-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8			// CHECK2-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP58:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP58:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP59:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP59:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP58]], [[TMP59]]			// CHECK2-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP58]], [[TMP59]]
	// CHECK2-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP61:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP62:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP62:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]			// CHECK2-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]
	// CHECK2-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1			// CHECK2-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
	// CHECK2-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64			// CHECK2-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
	// CHECK2-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP60]], [[CONV22_I]]			// CHECK2-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP60]], [[CONV22_I]]
	// CHECK2-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32			// CHECK2-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
	// CHECK2-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP63]] to i64			// CHECK2-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP63]] to i64
	// CHECK2-NEXT: [[TMP64:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP64:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP65:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP65:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP66:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP66:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP67:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP67:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP66]], [[TMP67]]			// CHECK2-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP66]], [[TMP67]]
	// CHECK2-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1			// CHECK2-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
	// CHECK2-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64			// CHECK2-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
	// CHECK2-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP65]], [[CONV33_I]]			// CHECK2-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP65]], [[CONV33_I]]
	// CHECK2-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]			// CHECK2-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]
	// CHECK2-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1			// CHECK2-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
	// CHECK2-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64			// CHECK2-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
	// CHECK2-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]			// CHECK2-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
	// CHECK2-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP64]], [[MUL41_I]]			// CHECK2-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP64]], [[MUL41_I]]
	// CHECK2-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]			// CHECK2-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
	// CHECK2-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32			// CHECK2-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
	// CHECK2-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP70:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: [[TMP70:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP70]], 1			// CHECK2-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP70]], 1
	// CHECK2-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK2-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP48:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: br label [[TASKLOOP_IF_END_I]]			// CHECK2-NEXT: br label [[TASKLOOP_IF_END_I]]
	// CHECK2: taskloop.if.end.i:			// CHECK2: taskloop.if.end.i:
	// CHECK2-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK2-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK2-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0			// CHECK2-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0
	// CHECK2-NEXT: br i1 [[TMP72]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP72]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]
	// CHECK2: .omp.lastprivate.then.i:			// CHECK2: .omp.lastprivate.then.i:
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK2: .omp_outlined..6.exit:			// CHECK2: .omp_outlined..6.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !61			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !62
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !61			// CHECK2-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !62
	// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8
	// CHECK2-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !61			// CHECK2-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !62
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK2-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !61			// CHECK2-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !62
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !61			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !62
	// CHECK2-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1			// CHECK2-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1
	// CHECK2-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !61			// CHECK2-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !62
	// CHECK2-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !61			// CHECK2-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !62
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !61			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i32 0, i32* [[TMP27]], align 4			// CHECK2-NEXT: store i32 0, i32* [[TMP27]], align 4
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !61			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !62
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK2: taskloop.if.then.i:			// CHECK2: taskloop.if.then.i:
	// CHECK2-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !61			// CHECK2-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !62
	// CHECK2-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !61			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !62
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK2-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK2-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK2-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !61, !llvm.access.group !62			// CHECK2-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !62, !llvm.access.group !63
	// CHECK2-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]			// CHECK2-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]
	// CHECK2-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK2-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !61, !llvm.access.group !62			// CHECK2-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !62, !llvm.access.group !63
	// CHECK2-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !62			// CHECK2-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !63
	// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK2-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK2-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1			// CHECK2-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1
	// CHECK2-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !61, !llvm.access.group !62			// CHECK2-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !62, !llvm.access.group !63
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP63:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP64:![0-9]+]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK2: .omp_outlined..9.exit:			// CHECK2: .omp_outlined..9.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ei			// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ei
	// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.]], i32 [[C:%.]]) unnamed_addr #[[ATTR8]] align 2 {			// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.]], i32 [[C:%.]]) unnamed_addr #[[ATTR8]] align 2 {
	▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK3: omp.inner.for.cond.i:			// CHECK3: omp.inner.for.cond.i:
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK3-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK3-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK3: omp.inner.for.body.i:			// CHECK3: omp.inner.for.body.i:
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !14
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK3-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK3-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK3: .omp_outlined..1.exit:			// CHECK3: .omp_outlined..1.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !30			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !30			// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !31
	// CHECK3-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK3-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30			// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK3: omp.inner.for.cond.i:			// CHECK3: omp.inner.for.cond.i:
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK3-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK3-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK3-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !30, !llvm.access.group !31			// CHECK3-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !31, !llvm.access.group !32
	// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK3: omp.inner.for.body.i:			// CHECK3: omp.inner.for.body.i:
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK3-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK3-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK3-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK3-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK3-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK3-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK3: .omp_outlined..3.exit:			// CHECK3: .omp_outlined..3.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5
	// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {			// CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK3-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK3-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !47
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK3-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)			// CHECK3-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)
	// CHECK3-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]			// CHECK3-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
	// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0			// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK3-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK3-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK3-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK3-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8			// CHECK3-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8
	// CHECK3-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8			// CHECK3-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8
	// CHECK3-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK3-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK3-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4			// CHECK3-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4
	// CHECK3-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64			// CHECK3-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64
	// CHECK3-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]			// CHECK3-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]
	// CHECK3-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8			// CHECK3-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8
	// CHECK3-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK3-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8			// CHECK3-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8
	// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4			// CHECK3-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4
	// CHECK3-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64			// CHECK3-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64
	// CHECK3-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]			// CHECK3-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]
	// CHECK3-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1			// CHECK3-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1
	// CHECK3-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32			// CHECK3-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32
	// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK3-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK3-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK3-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]			// CHECK3-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]
	// CHECK3-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1			// CHECK3-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
	// CHECK3-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64			// CHECK3-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
	// CHECK3-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]			// CHECK3-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
	// CHECK3-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1			// CHECK3-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
	// CHECK3-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !46			// CHECK3-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK3-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]			// CHECK3-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]
	// CHECK3-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]			// CHECK3-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]
	// CHECK3: land.lhs.true.i:			// CHECK3: land.lhs.true.i:
	// CHECK3-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]			// CHECK3-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]
	// CHECK3-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]			// CHECK3-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]
	// CHECK3: taskloop.if.then.i:			// CHECK3: taskloop.if.then.i:
	// CHECK3-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK3-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK3-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8			// CHECK3-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8
	// CHECK3-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK3-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8			// CHECK3-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8
	// CHECK3-NEXT: [[TMP58:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 3			// CHECK3-NEXT: [[TMP58:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 3
	// CHECK3-NEXT: [[TMP59:%.]] = load i8, i8 [[TMP58]], align 1			// CHECK3-NEXT: [[TMP59:%.]] = load i8, i8 [[TMP58]], align 1
	// CHECK3-NEXT: [[TOBOOL_I:%.*]] = trunc i8 [[TMP59]] to i1			// CHECK3-NEXT: [[TOBOOL_I:%.*]] = trunc i8 [[TMP59]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL_I]], label [[OMP_IF_THEN_I:%.]], label [[OMP_IF_ELSE_I:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL_I]], label [[OMP_IF_THEN_I:%.]], label [[OMP_IF_ELSE_I:%.]]
	// CHECK3: omp_if.then.i:			// CHECK3: omp_if.then.i:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK3: omp.inner.for.cond.i:			// CHECK3: omp.inner.for.cond.i:
	// CHECK3-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP61:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP61:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP60]], [[TMP61]]			// CHECK3-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP60]], [[TMP61]]
	// CHECK3-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK3-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK3: omp.inner.for.body.i:			// CHECK3: omp.inner.for.body.i:
	// CHECK3-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP64:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP64:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]			// CHECK3-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]
	// CHECK3-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1			// CHECK3-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
	// CHECK3-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64			// CHECK3-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
	// CHECK3-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP62]], [[CONV22_I]]			// CHECK3-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP62]], [[CONV22_I]]
	// CHECK3-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32			// CHECK3-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
	// CHECK3-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP65:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP65:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP65]] to i64			// CHECK3-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP65]] to i64
	// CHECK3-NEXT: [[TMP66:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP66:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP67:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP67:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]			// CHECK3-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]
	// CHECK3-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1			// CHECK3-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
	// CHECK3-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64			// CHECK3-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
	// CHECK3-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP67]], [[CONV33_I]]			// CHECK3-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP67]], [[CONV33_I]]
	// CHECK3-NEXT: [[TMP70:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP70:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP70]], [[TMP71]]			// CHECK3-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP70]], [[TMP71]]
	// CHECK3-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1			// CHECK3-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
	// CHECK3-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64			// CHECK3-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
	// CHECK3-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]			// CHECK3-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
	// CHECK3-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP66]], [[MUL41_I]]			// CHECK3-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP66]], [[MUL41_I]]
	// CHECK3-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]			// CHECK3-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
	// CHECK3-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32			// CHECK3-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
	// CHECK3-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[TMP72:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: [[TMP72:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP72]], 1			// CHECK3-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP72]], 1
	// CHECK3-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK3-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP48:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK3: omp.inner.for.end.i:			// CHECK3: omp.inner.for.end.i:
	// CHECK3-NEXT: br label [[OMP_IF_END_I:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END_I:%.*]]
	// CHECK3: omp_if.else.i:			// CHECK3: omp_if.else.i:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND47_I:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND47_I:%.*]]
	// CHECK3: omp.inner.for.cond47.i:			// CHECK3: omp.inner.for.cond47.i:
	// CHECK3-NEXT: [[TMP73:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP73:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP74:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP74:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[CMP48_I:%.*]] = icmp ule i64 [[TMP73]], [[TMP74]]			// CHECK3-NEXT: [[CMP48_I:%.*]] = icmp ule i64 [[TMP73]], [[TMP74]]
	// CHECK3-NEXT: br i1 [[CMP48_I]], label [[OMP_INNER_FOR_BODY49_I:%.]], label [[OMP_INNER_FOR_END82_I:%.]]			// CHECK3-NEXT: br i1 [[CMP48_I]], label [[OMP_INNER_FOR_BODY49_I:%.]], label [[OMP_INNER_FOR_END82_I:%.]]
	// CHECK3: omp.inner.for.body49.i:			// CHECK3: omp.inner.for.body49.i:
	// CHECK3-NEXT: [[TMP75:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP75:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP76:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP76:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP77:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP77:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[SUB50_I:%.*]] = sub i32 [[TMP76]], [[TMP77]]			// CHECK3-NEXT: [[SUB50_I:%.*]] = sub i32 [[TMP76]], [[TMP77]]
	// CHECK3-NEXT: [[SUB51_I:%.*]] = sub i32 [[SUB50_I]], 1			// CHECK3-NEXT: [[SUB51_I:%.*]] = sub i32 [[SUB50_I]], 1
	// CHECK3-NEXT: [[CONV55_I:%.*]] = zext i32 [[SUB50_I]] to i64			// CHECK3-NEXT: [[CONV55_I:%.*]] = zext i32 [[SUB50_I]] to i64
	// CHECK3-NEXT: [[DIV56_I:%.*]] = sdiv i64 [[TMP75]], [[CONV55_I]]			// CHECK3-NEXT: [[DIV56_I:%.*]] = sdiv i64 [[TMP75]], [[CONV55_I]]
	// CHECK3-NEXT: [[CONV59_I:%.*]] = trunc i64 [[DIV56_I]] to i32			// CHECK3-NEXT: [[CONV59_I:%.*]] = trunc i64 [[DIV56_I]] to i32
	// CHECK3-NEXT: store i32 [[CONV59_I]], i32* [[I14_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[CONV59_I]], i32* [[I14_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP78:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP78:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[CONV60_I:%.*]] = sext i32 [[TMP78]] to i64			// CHECK3-NEXT: [[CONV60_I:%.*]] = sext i32 [[TMP78]] to i64
	// CHECK3-NEXT: [[TMP79:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP79:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP80:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP80:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[TMP81:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP81:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP82:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP82:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[SUB61_I:%.*]] = sub i32 [[TMP81]], [[TMP82]]			// CHECK3-NEXT: [[SUB61_I:%.*]] = sub i32 [[TMP81]], [[TMP82]]
	// CHECK3-NEXT: [[SUB62_I:%.*]] = sub i32 [[SUB61_I]], 1			// CHECK3-NEXT: [[SUB62_I:%.*]] = sub i32 [[SUB61_I]], 1
	// CHECK3-NEXT: [[CONV66_I:%.*]] = zext i32 [[SUB61_I]] to i64			// CHECK3-NEXT: [[CONV66_I:%.*]] = zext i32 [[SUB61_I]] to i64
	// CHECK3-NEXT: [[DIV67_I:%.*]] = sdiv i64 [[TMP80]], [[CONV66_I]]			// CHECK3-NEXT: [[DIV67_I:%.*]] = sdiv i64 [[TMP80]], [[CONV66_I]]
	// CHECK3-NEXT: [[TMP83:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP83:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP84:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP84:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[SUB68_I:%.*]] = sub i32 [[TMP83]], [[TMP84]]			// CHECK3-NEXT: [[SUB68_I:%.*]] = sub i32 [[TMP83]], [[TMP84]]
	// CHECK3-NEXT: [[SUB69_I:%.*]] = sub i32 [[SUB68_I]], 1			// CHECK3-NEXT: [[SUB69_I:%.*]] = sub i32 [[SUB68_I]], 1
	// CHECK3-NEXT: [[CONV73_I:%.*]] = zext i32 [[SUB68_I]] to i64			// CHECK3-NEXT: [[CONV73_I:%.*]] = zext i32 [[SUB68_I]] to i64
	// CHECK3-NEXT: [[MUL74_I:%.*]] = mul nsw i64 [[DIV67_I]], [[CONV73_I]]			// CHECK3-NEXT: [[MUL74_I:%.*]] = mul nsw i64 [[DIV67_I]], [[CONV73_I]]
	// CHECK3-NEXT: [[SUB75_I:%.*]] = sub nsw i64 [[TMP79]], [[MUL74_I]]			// CHECK3-NEXT: [[SUB75_I:%.*]] = sub nsw i64 [[TMP79]], [[MUL74_I]]
	// CHECK3-NEXT: [[ADD77_I:%.*]] = add nsw i64 [[CONV60_I]], [[SUB75_I]]			// CHECK3-NEXT: [[ADD77_I:%.*]] = add nsw i64 [[CONV60_I]], [[SUB75_I]]
	// CHECK3-NEXT: [[CONV78_I:%.*]] = trunc i64 [[ADD77_I]] to i32			// CHECK3-NEXT: [[CONV78_I:%.*]] = trunc i64 [[ADD77_I]] to i32
	// CHECK3-NEXT: store i32 [[CONV78_I]], i32* [[J15_I]], align 4, !noalias !46			// CHECK3-NEXT: store i32 [[CONV78_I]], i32* [[J15_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP85:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK3-NEXT: [[TMP85:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK3-NEXT: [[ADD81_I:%.*]] = add nsw i64 [[TMP85]], 1			// CHECK3-NEXT: [[ADD81_I:%.*]] = add nsw i64 [[TMP85]], 1
	// CHECK3-NEXT: store i64 [[ADD81_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK3-NEXT: store i64 [[ADD81_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND47_I]], !llvm.loop [[LOOP50:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND47_I]], !llvm.loop [[LOOP51:![0-9]+]]
	// CHECK3: omp.inner.for.end82.i:			// CHECK3: omp.inner.for.end82.i:
	// CHECK3-NEXT: br label [[OMP_IF_END_I]]			// CHECK3-NEXT: br label [[OMP_IF_END_I]]
	// CHECK3: omp_if.end.i:			// CHECK3: omp_if.end.i:
	// CHECK3-NEXT: br label [[TASKLOOP_IF_END_I]]			// CHECK3-NEXT: br label [[TASKLOOP_IF_END_I]]
	// CHECK3: taskloop.if.end.i:			// CHECK3: taskloop.if.end.i:
	// CHECK3-NEXT: [[TMP86:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK3-NEXT: [[TMP86:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK3-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0			// CHECK3-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0
	// CHECK3-NEXT: br i1 [[TMP87]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP87]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]
	// CHECK3: .omp.lastprivate.then.i:			// CHECK3: .omp.lastprivate.then.i:
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK3: .omp_outlined..6.exit:			// CHECK3: .omp_outlined..6.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK3-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !63			// CHECK3-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !64
	// CHECK3-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0			// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8			// CHECK3-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8
	// CHECK3-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !63			// CHECK3-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !64
	// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8			// CHECK3-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK3-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK3-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK3-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1			// CHECK3-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1
	// CHECK3-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !63			// CHECK3-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !64
	// CHECK3-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !63			// CHECK3-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !63			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK3-NEXT: store i32 0, i32* [[TMP27]], align 4			// CHECK3-NEXT: store i32 0, i32* [[TMP27]], align 4
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK3-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]			// CHECK3-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]
	// CHECK3-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK3-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK3: taskloop.if.then.i:			// CHECK3: taskloop.if.then.i:
	// CHECK3-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !63			// CHECK3-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !64
	// CHECK3-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK3-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK3-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK3-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK3: omp.inner.for.cond.i:			// CHECK3: omp.inner.for.cond.i:
	// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK3-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK3-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK3-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !63, !llvm.access.group !64			// CHECK3-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !64, !llvm.access.group !65
	// CHECK3-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]			// CHECK3-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]
	// CHECK3-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK3-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK3: omp.inner.for.body.i:			// CHECK3: omp.inner.for.body.i:
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !63, !llvm.access.group !64			// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !64, !llvm.access.group !65
	// CHECK3-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !64			// CHECK3-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !65
	// CHECK3-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK3-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK3-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1			// CHECK3-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1
	// CHECK3-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK3-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP65:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP66:![0-9]+]]
	// CHECK3: omp.inner.for.end.i:			// CHECK3: omp.inner.for.end.i:
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK3: .omp_outlined..9.exit:			// CHECK3: .omp_outlined..9.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp			// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
	// CHECK3-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {			// CHECK3-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
	▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK4: omp.inner.for.cond.i:			// CHECK4: omp.inner.for.cond.i:
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK4-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK4-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK4: omp.inner.for.body.i:			// CHECK4: omp.inner.for.body.i:
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK4-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK4-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK4: .omp_outlined..1.exit:			// CHECK4: .omp_outlined..1.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2			// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i64 [[DOTCAPTURE_EXPR_:%.]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !30			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !30			// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !31
	// CHECK4-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: [[TMP20:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !30			// CHECK4-NEXT: [[TMP21:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !31
	// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32			// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP21]] to i32
	// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30			// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK4: omp.inner.for.cond.i:			// CHECK4: omp.inner.for.cond.i:
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK4-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64			// CHECK4-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP22]] to i64
	// CHECK4-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !30, !llvm.access.group !31			// CHECK4-NEXT: [[TMP23:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !31, !llvm.access.group !32
	// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]			// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP23]]
	// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK4: omp.inner.for.body.i:			// CHECK4: omp.inner.for.body.i:
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK4-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK4-NEXT: store i32 [[TMP24]], i32* [[I_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK4-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1			// CHECK4-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP25]], 1
	// CHECK4-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !30, !llvm.access.group !31			// CHECK4-NEXT: store i32 [[ADD2_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK4: .omp_outlined..3.exit:			// CHECK4: .omp_outlined..3.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5			// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5
	// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {			// CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.]], i32 noalias [[DOTBOUND_TID_:%.]], i32 nonnull align 4 dereferenceable(4) [[I:%.]], i32 nonnull align 4 dereferenceable(4) [[ARGC:%.]], i8** nonnull align 8 dereferenceable(8) [[ARGV:%.]], i64 [[DOTCAPTURE_EXPR_:%.]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK4-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK4-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !47
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK4-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP22:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)			// CHECK4-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32)
	// CHECK4-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]			// CHECK4-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
	// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0			// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_2:%.]], %struct.anon.2* [[TMP22]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK4-NEXT: [[TMP29:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8			// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32** [[TMP29]], align 8
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP30]], align 4
	// CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK4-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8			// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32** [[TMP32]], align 8
	// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4			// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[TMP33]], align 4
	// CHECK4-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[TMP34]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK4-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8			// CHECK4-NEXT: [[TMP36:%.]] = load i8, i8** [[TMP35]], align 8
	// CHECK4-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8			// CHECK4-NEXT: [[TMP37:%.]] = load i8, i8** [[TMP36]], align 8
	// CHECK4-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK4-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK4-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK4-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4			// CHECK4-NEXT: [[TMP40:%.]] = load i32, i32 [[TMP39]], align 4
	// CHECK4-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64			// CHECK4-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP40]] to i64
	// CHECK4-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]			// CHECK4-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i8, i8** [[TMP37]], i64 [[IDXPROM_I]]
	// CHECK4-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8			// CHECK4-NEXT: [[TMP41:%.]] = load i8, i8** [[ARRAYIDX_I]], align 8
	// CHECK4-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK4-NEXT: [[TMP42:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8			// CHECK4-NEXT: [[TMP43:%.]] = load i32, i32** [[TMP42]], align 8
	// CHECK4-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4			// CHECK4-NEXT: [[TMP44:%.]] = load i32, i32 [[TMP43]], align 4
	// CHECK4-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64			// CHECK4-NEXT: [[IDXPROM4_I:%.*]] = sext i32 [[TMP44]] to i64
	// CHECK4-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]			// CHECK4-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds i8, i8 [[TMP41]], i64 [[IDXPROM4_I]]
	// CHECK4-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1			// CHECK4-NEXT: [[TMP45:%.]] = load i8, i8 [[ARRAYIDX5_I]], align 1
	// CHECK4-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32			// CHECK4-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP45]] to i32
	// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK4-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK4-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK4-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]			// CHECK4-NEXT: [[SUB8_I:%.*]] = sub i32 [[TMP47]], [[TMP48]]
	// CHECK4-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1			// CHECK4-NEXT: [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
	// CHECK4-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64			// CHECK4-NEXT: [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
	// CHECK4-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]			// CHECK4-NEXT: [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
	// CHECK4-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1			// CHECK4-NEXT: [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
	// CHECK4-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !46			// CHECK4-NEXT: store i64 [[SUB12_I]], i64* [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 0, i32* [[I_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[TMP49]], i32* [[J_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !47
	// CHECK4-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]			// CHECK4-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP50]]
	// CHECK4-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]			// CHECK4-NEXT: br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.]], label [[TASKLOOP_IF_END_I:%.]]
	// CHECK4: land.lhs.true.i:			// CHECK4: land.lhs.true.i:
	// CHECK4-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP51:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]			// CHECK4-NEXT: [[CMP13_I:%.*]] = icmp slt i32 [[TMP51]], [[TMP52]]
	// CHECK4-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]			// CHECK4-NEXT: br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]
	// CHECK4: taskloop.if.then.i:			// CHECK4: taskloop.if.then.i:
	// CHECK4-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP53:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK4-NEXT: store i64 [[TMP53]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1			// CHECK4-NEXT: [[TMP54:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8			// CHECK4-NEXT: [[TMP55:%.]] = load i32, i32** [[TMP54]], align 8
	// CHECK4-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2			// CHECK4-NEXT: [[TMP56:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8			// CHECK4-NEXT: [[TMP57:%.]] = load i8, i8** [[TMP56]], align 8
	// CHECK4-NEXT: [[TMP58:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 3			// CHECK4-NEXT: [[TMP58:%.]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2 [[TMP22]], i32 0, i32 3
	// CHECK4-NEXT: [[TMP59:%.]] = load i8, i8 [[TMP58]], align 1			// CHECK4-NEXT: [[TMP59:%.]] = load i8, i8 [[TMP58]], align 1
	// CHECK4-NEXT: [[TOBOOL_I:%.*]] = trunc i8 [[TMP59]] to i1			// CHECK4-NEXT: [[TOBOOL_I:%.*]] = trunc i8 [[TMP59]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL_I]], label [[OMP_IF_THEN_I:%.]], label [[OMP_IF_ELSE_I:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL_I]], label [[OMP_IF_THEN_I:%.]], label [[OMP_IF_ELSE_I:%.]]
	// CHECK4: omp_if.then.i:			// CHECK4: omp_if.then.i:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK4: omp.inner.for.cond.i:			// CHECK4: omp.inner.for.cond.i:
	// CHECK4-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP60:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP61:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP61:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP60]], [[TMP61]]			// CHECK4-NEXT: [[CMP16_I:%.*]] = icmp ule i64 [[TMP60]], [[TMP61]]
	// CHECK4-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK4-NEXT: br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK4: omp.inner.for.body.i:			// CHECK4: omp.inner.for.body.i:
	// CHECK4-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP62:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP63:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP64:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP64:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]			// CHECK4-NEXT: [[SUB17_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]
	// CHECK4-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1			// CHECK4-NEXT: [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
	// CHECK4-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64			// CHECK4-NEXT: [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
	// CHECK4-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP62]], [[CONV22_I]]			// CHECK4-NEXT: [[DIV23_I:%.*]] = sdiv i64 [[TMP62]], [[CONV22_I]]
	// CHECK4-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32			// CHECK4-NEXT: [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
	// CHECK4-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: store i32 [[CONV26_I]], i32* [[I14_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP65:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP65:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP65]] to i64			// CHECK4-NEXT: [[CONV27_I:%.*]] = sext i32 [[TMP65]] to i64
	// CHECK4-NEXT: [[TMP66:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP66:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP67:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP67:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP68:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP69:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]			// CHECK4-NEXT: [[SUB28_I:%.*]] = sub i32 [[TMP68]], [[TMP69]]
	// CHECK4-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1			// CHECK4-NEXT: [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
	// CHECK4-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64			// CHECK4-NEXT: [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
	// CHECK4-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP67]], [[CONV33_I]]			// CHECK4-NEXT: [[DIV34_I:%.*]] = sdiv i64 [[TMP67]], [[CONV33_I]]
	// CHECK4-NEXT: [[TMP70:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP70:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP71:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP70]], [[TMP71]]			// CHECK4-NEXT: [[SUB35_I:%.*]] = sub i32 [[TMP70]], [[TMP71]]
	// CHECK4-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1			// CHECK4-NEXT: [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
	// CHECK4-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64			// CHECK4-NEXT: [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
	// CHECK4-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]			// CHECK4-NEXT: [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
	// CHECK4-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP66]], [[MUL41_I]]			// CHECK4-NEXT: [[SUB42_I:%.*]] = sub nsw i64 [[TMP66]], [[MUL41_I]]
	// CHECK4-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]			// CHECK4-NEXT: [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
	// CHECK4-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32			// CHECK4-NEXT: [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
	// CHECK4-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: store i32 [[CONV45_I]], i32* [[J15_I]], align 4, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[TMP72:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: [[TMP72:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP72]], 1			// CHECK4-NEXT: [[ADD46_I:%.*]] = add nsw i64 [[TMP72]], 1
	// CHECK4-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46, !llvm.access.group !47			// CHECK4-NEXT: store i64 [[ADD46_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47, !llvm.access.group !48
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP48:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK4: omp.inner.for.end.i:			// CHECK4: omp.inner.for.end.i:
	// CHECK4-NEXT: br label [[OMP_IF_END_I:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END_I:%.*]]
	// CHECK4: omp_if.else.i:			// CHECK4: omp_if.else.i:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND47_I:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND47_I:%.*]]
	// CHECK4: omp.inner.for.cond47.i:			// CHECK4: omp.inner.for.cond47.i:
	// CHECK4-NEXT: [[TMP73:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP73:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP74:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP74:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[CMP48_I:%.*]] = icmp ule i64 [[TMP73]], [[TMP74]]			// CHECK4-NEXT: [[CMP48_I:%.*]] = icmp ule i64 [[TMP73]], [[TMP74]]
	// CHECK4-NEXT: br i1 [[CMP48_I]], label [[OMP_INNER_FOR_BODY49_I:%.]], label [[OMP_INNER_FOR_END82_I:%.]]			// CHECK4-NEXT: br i1 [[CMP48_I]], label [[OMP_INNER_FOR_BODY49_I:%.]], label [[OMP_INNER_FOR_END82_I:%.]]
	// CHECK4: omp.inner.for.body49.i:			// CHECK4: omp.inner.for.body49.i:
	// CHECK4-NEXT: [[TMP75:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP75:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP76:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP76:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP77:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP77:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[SUB50_I:%.*]] = sub i32 [[TMP76]], [[TMP77]]			// CHECK4-NEXT: [[SUB50_I:%.*]] = sub i32 [[TMP76]], [[TMP77]]
	// CHECK4-NEXT: [[SUB51_I:%.*]] = sub i32 [[SUB50_I]], 1			// CHECK4-NEXT: [[SUB51_I:%.*]] = sub i32 [[SUB50_I]], 1
	// CHECK4-NEXT: [[CONV55_I:%.*]] = zext i32 [[SUB50_I]] to i64			// CHECK4-NEXT: [[CONV55_I:%.*]] = zext i32 [[SUB50_I]] to i64
	// CHECK4-NEXT: [[DIV56_I:%.*]] = sdiv i64 [[TMP75]], [[CONV55_I]]			// CHECK4-NEXT: [[DIV56_I:%.*]] = sdiv i64 [[TMP75]], [[CONV55_I]]
	// CHECK4-NEXT: [[CONV59_I:%.*]] = trunc i64 [[DIV56_I]] to i32			// CHECK4-NEXT: [[CONV59_I:%.*]] = trunc i64 [[DIV56_I]] to i32
	// CHECK4-NEXT: store i32 [[CONV59_I]], i32* [[I14_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[CONV59_I]], i32* [[I14_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP78:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP78:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[CONV60_I:%.*]] = sext i32 [[TMP78]] to i64			// CHECK4-NEXT: [[CONV60_I:%.*]] = sext i32 [[TMP78]] to i64
	// CHECK4-NEXT: [[TMP79:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP79:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP80:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP80:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[TMP81:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP81:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP82:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP82:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[SUB61_I:%.*]] = sub i32 [[TMP81]], [[TMP82]]			// CHECK4-NEXT: [[SUB61_I:%.*]] = sub i32 [[TMP81]], [[TMP82]]
	// CHECK4-NEXT: [[SUB62_I:%.*]] = sub i32 [[SUB61_I]], 1			// CHECK4-NEXT: [[SUB62_I:%.*]] = sub i32 [[SUB61_I]], 1
	// CHECK4-NEXT: [[CONV66_I:%.*]] = zext i32 [[SUB61_I]] to i64			// CHECK4-NEXT: [[CONV66_I:%.*]] = zext i32 [[SUB61_I]] to i64
	// CHECK4-NEXT: [[DIV67_I:%.*]] = sdiv i64 [[TMP80]], [[CONV66_I]]			// CHECK4-NEXT: [[DIV67_I:%.*]] = sdiv i64 [[TMP80]], [[CONV66_I]]
	// CHECK4-NEXT: [[TMP83:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP83:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP84:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP84:%.]] = load i32, i32 [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[SUB68_I:%.*]] = sub i32 [[TMP83]], [[TMP84]]			// CHECK4-NEXT: [[SUB68_I:%.*]] = sub i32 [[TMP83]], [[TMP84]]
	// CHECK4-NEXT: [[SUB69_I:%.*]] = sub i32 [[SUB68_I]], 1			// CHECK4-NEXT: [[SUB69_I:%.*]] = sub i32 [[SUB68_I]], 1
	// CHECK4-NEXT: [[CONV73_I:%.*]] = zext i32 [[SUB68_I]] to i64			// CHECK4-NEXT: [[CONV73_I:%.*]] = zext i32 [[SUB68_I]] to i64
	// CHECK4-NEXT: [[MUL74_I:%.*]] = mul nsw i64 [[DIV67_I]], [[CONV73_I]]			// CHECK4-NEXT: [[MUL74_I:%.*]] = mul nsw i64 [[DIV67_I]], [[CONV73_I]]
	// CHECK4-NEXT: [[SUB75_I:%.*]] = sub nsw i64 [[TMP79]], [[MUL74_I]]			// CHECK4-NEXT: [[SUB75_I:%.*]] = sub nsw i64 [[TMP79]], [[MUL74_I]]
	// CHECK4-NEXT: [[ADD77_I:%.*]] = add nsw i64 [[CONV60_I]], [[SUB75_I]]			// CHECK4-NEXT: [[ADD77_I:%.*]] = add nsw i64 [[CONV60_I]], [[SUB75_I]]
	// CHECK4-NEXT: [[CONV78_I:%.*]] = trunc i64 [[ADD77_I]] to i32			// CHECK4-NEXT: [[CONV78_I:%.*]] = trunc i64 [[ADD77_I]] to i32
	// CHECK4-NEXT: store i32 [[CONV78_I]], i32* [[J15_I]], align 4, !noalias !46			// CHECK4-NEXT: store i32 [[CONV78_I]], i32* [[J15_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP85:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK4-NEXT: [[TMP85:%.]] = load i64, i64 [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK4-NEXT: [[ADD81_I:%.*]] = add nsw i64 [[TMP85]], 1			// CHECK4-NEXT: [[ADD81_I:%.*]] = add nsw i64 [[TMP85]], 1
	// CHECK4-NEXT: store i64 [[ADD81_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !46			// CHECK4-NEXT: store i64 [[ADD81_I]], i64* [[DOTOMP_IV_I]], align 8, !noalias !47
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND47_I]], !llvm.loop [[LOOP50:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND47_I]], !llvm.loop [[LOOP51:![0-9]+]]
	// CHECK4: omp.inner.for.end82.i:			// CHECK4: omp.inner.for.end82.i:
	// CHECK4-NEXT: br label [[OMP_IF_END_I]]			// CHECK4-NEXT: br label [[OMP_IF_END_I]]
	// CHECK4: omp_if.end.i:			// CHECK4: omp_if.end.i:
	// CHECK4-NEXT: br label [[TASKLOOP_IF_END_I]]			// CHECK4-NEXT: br label [[TASKLOOP_IF_END_I]]
	// CHECK4: taskloop.if.end.i:			// CHECK4: taskloop.if.end.i:
	// CHECK4-NEXT: [[TMP86:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !46			// CHECK4-NEXT: [[TMP86:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !47
	// CHECK4-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0			// CHECK4-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0
	// CHECK4-NEXT: br i1 [[TMP87]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]			// CHECK4-NEXT: br i1 [[TMP87]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__6_EXIT:%.]]
	// CHECK4: .omp.lastprivate.then.i:			// CHECK4: .omp.lastprivate.then.i:
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__6_EXIT]]
	// CHECK4: .omp_outlined..6.exit:			// CHECK4: .omp_outlined..6.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK4-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !63			// CHECK4-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !64
	// CHECK4-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: [[TMP20:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0			// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON_4:%.]], %struct.anon.4* [[TMP20]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8			// CHECK4-NEXT: [[TMP22:%.]] = load %struct.S, %struct.S** [[TMP21]], align 8
	// CHECK4-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !63			// CHECK4-NEXT: store i32* [[TMP_I]], i32** [[TMP1_I]], align 8, !noalias !64
	// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8			// CHECK4-NEXT: [[TMP24:%.]] = load i32, i32** [[TMP23]], align 8
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK4-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK4-NEXT: store i32 [[TMP25]], i32* [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK4-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1			// CHECK4-NEXT: [[SUB3_I:%.*]] = sub nsw i32 [[TMP26]], 1
	// CHECK4-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !63			// CHECK4-NEXT: store i32 [[SUB3_I]], i32* [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias !64
	// CHECK4-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !63			// CHECK4-NEXT: store i32* [[A_I]], i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !63			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP4_I]], align 8, !noalias !64
	// CHECK4-NEXT: store i32 0, i32* [[TMP27]], align 4			// CHECK4-NEXT: store i32 0, i32* [[TMP27]], align 4
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !63			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__I]], align 4, !noalias !64
	// CHECK4-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]			// CHECK4-NEXT: [[CMP_I:%.*]] = icmp slt i32 0, [[TMP28]]
	// CHECK4-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK4-NEXT: br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK4: taskloop.if.then.i:			// CHECK4: taskloop.if.then.i:
	// CHECK4-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !63			// CHECK4-NEXT: store i32* [[A5_I]], i32** [[TMP6_I]], align 8, !noalias !64
	// CHECK4-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !63			// CHECK4-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !64
	// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63			// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64
	// CHECK4-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1			// CHECK4-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4 [[TMP20]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK4: omp.inner.for.cond.i:			// CHECK4: omp.inner.for.cond.i:
	// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK4-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64			// CHECK4-NEXT: [[CONV7_I:%.*]] = sext i32 [[TMP32]] to i64
	// CHECK4-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !63, !llvm.access.group !64			// CHECK4-NEXT: [[TMP33:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !64, !llvm.access.group !65
	// CHECK4-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]			// CHECK4-NEXT: [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP33]]
	// CHECK4-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK4-NEXT: br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK4: omp.inner.for.body.i:			// CHECK4: omp.inner.for.body.i:
	// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !63, !llvm.access.group !64			// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32** [[TMP6_I]], align 8, !noalias !64, !llvm.access.group !65
	// CHECK4-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !64			// CHECK4-NEXT: store i32 [[TMP34]], i32* [[TMP35]], align 4, !llvm.access.group !65
	// CHECK4-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK4-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK4-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1			// CHECK4-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP36]], 1
	// CHECK4-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !63, !llvm.access.group !64			// CHECK4-NEXT: store i32 [[ADD9_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !64, !llvm.access.group !65
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP65:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP66:![0-9]+]]
	// CHECK4: omp.inner.for.end.i:			// CHECK4: omp.inner.for.end.i:
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__9_EXIT]]
	// CHECK4: .omp_outlined..9.exit:			// CHECK4: .omp_outlined..9.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp			// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
	// CHECK4-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {			// CHECK4-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
	▲ Show 20 Lines • Show All 1,490 Lines • Show Last 20 Lines

clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 414 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)			// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)
	// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8
	// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8			// CHECK1-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8
	// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8			// CHECK1-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4			// CHECK1-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4
	// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK1-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK1-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0
	// CHECK1-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*			// CHECK1-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*
	// CHECK1-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK1-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]], !llvm.access.group !14			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]], !llvm.access.group !15
	// CHECK1-NEXT: store i32 33, i32* [[TMP44]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 33, i32* [[TMP44]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0			// CHECK1-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
	// CHECK1-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK1: .omp.lastprivate.then.i:			// CHECK1: .omp.lastprivate.then.i:
	// CHECK1-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK1-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK1-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK1-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4			// CHECK1-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4
	// CHECK1-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4			// CHECK1-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4
	▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !31			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !32
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)			// CHECK1-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)
	// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8			// CHECK1-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8
	// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8			// CHECK1-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32
	// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31			// CHECK1-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK1-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64			// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !31, !llvm.access.group !32			// CHECK1-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !32, !llvm.access.group !33
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK1-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK1-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK1-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128, !llvm.access.group !32			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128, !llvm.access.group !33
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0
	// CHECK1-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !32			// CHECK1-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0			// CHECK1-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*			// CHECK1-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*
	// CHECK1-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*			// CHECK1-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]], !llvm.access.group !32			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]], !llvm.access.group !33
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1			// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1
	// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK1: omp.inner.for.end.i:			// CHECK1: omp.inner.for.end.i:
	// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !31			// CHECK1-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !32
	// CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0			// CHECK1-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
	// CHECK1-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK1: .omp.lastprivate.then.i:			// CHECK1: .omp.lastprivate.then.i:
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128
	// CHECK1-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128			// CHECK1-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128
	// CHECK1-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*			// CHECK1-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*
	// CHECK1-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*			// CHECK1-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]
	▲ Show 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, %struct.S, i32, [2 x %struct.S], [2 x i32], i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)			// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, %struct.S, i32, [2 x %struct.S], [2 x i32], i32)
	// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S] [[DOTLASTPRIV_PTR_ADDR2_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR3_I]], i32** [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load %struct.S, %struct.S** [[TMP26]], align 8
	// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8			// CHECK2-NEXT: [[TMP33:%.]] = load [2 x i32], [2 x i32]** [[TMP32]], align 8
	// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8			// CHECK2-NEXT: [[TMP35:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP34]], align 8
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S, %struct.S** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4			// CHECK2-NEXT: [[TMP38:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 4
	// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8			// CHECK2-NEXT: [[TMP39:%.]] = load i32, i32** [[TMP38]], align 8
	// CHECK2-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP40:%.]] = load %struct.S, %struct.S** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP42:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP43:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP47]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[TMP41]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP43]], i64 0, i64 0
	// CHECK2-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[TMP49]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX6_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP42]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*			// CHECK2-NEXT: [[TMP50:%.]] = bitcast %struct.S [[ARRAYIDX6_I]] to i8*
	// CHECK2-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK2-NEXT: [[TMP51:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]], !llvm.access.group !14			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP50]], i8* align 8 [[TMP51]], i64 8, i1 false) #[[ATTR4]], !llvm.access.group !15
	// CHECK2-NEXT: store i32 33, i32* [[TMP44]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 33, i32* [[TMP44]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP53:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0			// CHECK2-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0
	// CHECK2-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP54]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK2: .omp.lastprivate.then.i:			// CHECK2: .omp.lastprivate.then.i:
	// CHECK2-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*			// CHECK2-NEXT: [[TMP55:%.]] = bitcast %struct.S [[TMP27]] to i8*
	// CHECK2-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*			// CHECK2-NEXT: [[TMP56:%.]] = bitcast %struct.S [[TMP40]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP55]], i8* align 8 [[TMP56]], i64 8, i1 false) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4			// CHECK2-NEXT: [[TMP57:%.]] = load i32, i32 [[TMP41]], align 4
	// CHECK2-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4			// CHECK2-NEXT: store i32 [[TMP57]], i32* [[TMP29]], align 4
	▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 16
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 64
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.3, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0) @.omp_task_privates_map..4 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !31			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !32
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)			// CHECK2-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, i32, [2 x i32], [2 x %struct.S.0], %struct.S.0)
	// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void [[TMP25]](i8* [[TMP24]], i32 [[DOTLASTPRIV_PTR_ADDR_I]], [2 x i32] [[DOTLASTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0] [[DOTLASTPRIV_PTR_ADDR2_I]], %struct.S.0 [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP29:%.]] = load [2 x i32], [2 x i32]** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP32:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8			// CHECK2-NEXT: [[TMP33:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[TMP32]], align 8
	// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8			// CHECK2-NEXT: [[TMP35:%.]] = load %struct.S.0, %struct.S.0** [[TMP34]], align 8
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1 [[TMP22]], i32 0, i32 3
	// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load %struct.S.0, %struct.S.0** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP39:%.]] = load [2 x i32], [2 x i32]** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP40:%.]] = load [2 x %struct.S.0], [2 x %struct.S.0]** [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP41:%.]] = load %struct.S.0, %struct.S.0** [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP42:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP42]] to i32
	// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31			// CHECK2-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK2-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64			// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !31, !llvm.access.group !32			// CHECK2-NEXT: [[TMP44:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !32, !llvm.access.group !33
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP44]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK2-NEXT: [[TMP45:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK2-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK2-NEXT: store i32 [[TMP45]], i32* [[I_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128, !llvm.access.group !32			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[TMP38]], align 128, !llvm.access.group !33
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x i32], [2 x i32] [[TMP39]], i64 0, i64 0
	// CHECK2-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !32			// CHECK2-NEXT: store i32 [[TMP46]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0			// CHECK2-NEXT: [[ARRAYIDX5_I:%.]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0] [[TMP40]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*			// CHECK2-NEXT: [[TMP47:%.]] = bitcast %struct.S.0 [[ARRAYIDX5_I]] to i8*
	// CHECK2-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*			// CHECK2-NEXT: [[TMP48:%.]] = bitcast %struct.S.0 [[TMP41]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]], !llvm.access.group !32			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i64 4, i1 false) #[[ATTR4]], !llvm.access.group !33
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1			// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP49]], 1
	// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !31, !llvm.access.group !32			// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group !33
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK2: omp.inner.for.end.i:			// CHECK2: omp.inner.for.end.i:
	// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !31			// CHECK2-NEXT: [[TMP50:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !32
	// CHECK2-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0			// CHECK2-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
	// CHECK2-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP51]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK2: .omp.lastprivate.then.i:			// CHECK2: .omp.lastprivate.then.i:
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[TMP38]], align 128
	// CHECK2-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128			// CHECK2-NEXT: store i32 [[TMP52]], i32* [[TMP27]], align 128
	// CHECK2-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*			// CHECK2-NEXT: [[TMP53:%.]] = bitcast [2 x i32] [[TMP29]] to i8*
	// CHECK2-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*			// CHECK2-NEXT: [[TMP54:%.]] = bitcast [2 x i32] [[TMP39]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP53]], i8* align 4 [[TMP54]], i64 8, i1 false) #[[ATTR4]]
	▲ Show 20 Lines • Show All 235 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK3-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK3-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK3-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK3-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK3-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)			// CHECK3-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)
	// CHECK3-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]			// CHECK3-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]
	// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0			// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8			// CHECK3-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8
	// CHECK3-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK3-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK3-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK3-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32			// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32
	// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK3-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK3: omp.inner.for.cond.i:			// CHECK3: omp.inner.for.cond.i:
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64			// CHECK3-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64
	// CHECK3-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]			// CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]
	// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK3: omp.inner.for.body.i:			// CHECK3: omp.inner.for.body.i:
	// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8, !llvm.access.group !14			// CHECK3-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8, !llvm.access.group !15
	// CHECK3-NEXT: store i32 11, i32* [[TMP31]], align 4, !llvm.access.group !14			// CHECK3-NEXT: store i32 11, i32* [[TMP31]], align 4, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP36:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 0			// CHECK3-NEXT: [[TMP36:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 0
	// CHECK3-NEXT: store double* [[TMP30]], double** [[TMP36]], align 8, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: store double* [[TMP30]], double** [[TMP36]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: [[TMP37:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 1			// CHECK3-NEXT: [[TMP37:%.]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0 [[REF_TMP_I]], i32 0, i32 1
	// CHECK3-NEXT: store i32* [[TMP31]], i32** [[TMP37]], align 8, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: store i32* [[TMP31]], i32** [[TMP37]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) #[[ATTR3]], !llvm.access.group !14			// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) #[[ATTR3]], !llvm.access.group !15
	// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1			// CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1
	// CHECK3-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK3-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK3: omp.inner.for.end.i:			// CHECK3: omp.inner.for.end.i:
	// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK3-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0			// CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
	// CHECK3-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK3: .omp.lastprivate.then.i:			// CHECK3: .omp.lastprivate.then.i:
	// CHECK3-NEXT: [[TMP41:%.]] = load double, double [[TMP30]], align 8			// CHECK3-NEXT: [[TMP41:%.]] = load double, double [[TMP30]], align 8
	// CHECK3-NEXT: store volatile double [[TMP41]], double* [[TMP27]], align 8			// CHECK3-NEXT: store volatile double [[TMP41]], double* [[TMP27]], align 8
	// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK3-NEXT: [[TMP42:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP29]], align 4			// CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP29]], align 4
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK4-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK4-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK4-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK4-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK4-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, double, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP23:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)			// CHECK4-NEXT: [[TMP25:%.]] = bitcast void (i8, ...)* [[TMP23]] to void (i8, double, i32)
	// CHECK4-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]			// CHECK4-NEXT: call void [[TMP25]](i8* [[TMP24]], double [[DOTLASTPRIV_PTR_ADDR_I]], i32 [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]
	// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0			// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8			// CHECK4-NEXT: [[TMP27:%.]] = load double, double** [[TMP26]], align 8
	// CHECK4-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK4-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32** [[TMP28]], align 8
	// CHECK4-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP30:%.]] = load double, double** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK4-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32			// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP32]] to i32
	// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK4-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK4: omp.inner.for.cond.i:			// CHECK4: omp.inner.for.cond.i:
	// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64			// CHECK4-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP33]] to i64
	// CHECK4-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]			// CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP34]]
	// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK4: omp.inner.for.body.i:			// CHECK4: omp.inner.for.body.i:
	// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store i32 [[TMP35]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8, !llvm.access.group !14			// CHECK4-NEXT: store double 1.000000e+00, double* [[TMP30]], align 8, !llvm.access.group !15
	// CHECK4-NEXT: store i32 11, i32* [[TMP31]], align 4, !llvm.access.group !14			// CHECK4-NEXT: store i32 11, i32* [[TMP31]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: [[BLOCK_ISA_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 0			// CHECK4-NEXT: [[BLOCK_ISA_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 0
	// CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8), i8* [[BLOCK_ISA_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8), i8* [[BLOCK_ISA_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[BLOCK_FLAGS_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 1			// CHECK4-NEXT: [[BLOCK_FLAGS_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 1
	// CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[BLOCK_RESERVED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 2			// CHECK4-NEXT: [[BLOCK_RESERVED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 2
	// CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[BLOCK_INVOKE_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 3			// CHECK4-NEXT: [[BLOCK_INVOKE_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 3
	// CHECK4-NEXT: store i8* bitcast (void (i8) @_block_invoke to i8), i8* [[BLOCK_INVOKE_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store i8* bitcast (void (i8) @_block_invoke to i8), i8* [[BLOCK_INVOKE_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[BLOCK_DESCRIPTOR_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 4			// CHECK4-NEXT: [[BLOCK_DESCRIPTOR_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 4
	// CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8, i8 }* @__block_descriptor_tmp.2 to %struct.__block_descriptor), %struct.__block_descriptor* [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8, i8 }* @__block_descriptor_tmp.2 to %struct.__block_descriptor), %struct.__block_descriptor* [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[BLOCK_CAPTURED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 5			// CHECK4-NEXT: [[BLOCK_CAPTURED_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 5
	// CHECK4-NEXT: [[TMP36:%.]] = load volatile double, double [[TMP30]], align 8, !llvm.access.group !14			// CHECK4-NEXT: [[TMP36:%.]] = load volatile double, double [[TMP30]], align 8, !llvm.access.group !15
	// CHECK4-NEXT: store volatile double [[TMP36]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store volatile double [[TMP36]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[BLOCK_CAPTURED3_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 6			// CHECK4-NEXT: [[BLOCK_CAPTURED3_I:%.]] = getelementptr inbounds <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>, <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }> [[BLOCK_I]], i32 0, i32 6
	// CHECK4-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP31]], align 4, !llvm.access.group !14			// CHECK4-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP31]], align 4, !llvm.access.group !15
	// CHECK4-NEXT: store i32 [[TMP37]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store i32 [[TMP37]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP38:%.]] = bitcast <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_I]] to void ()*			// CHECK4-NEXT: [[TMP38:%.]] = bitcast <{ i8, i32, i32, i8, %struct.__block_descriptor, double, i32 }>* [[BLOCK_I]] to void ()*
	// CHECK4-NEXT: [[BLOCK_LITERAL_I:%.]] = bitcast void () [[TMP38]] to %struct.__block_literal_generic*			// CHECK4-NEXT: [[BLOCK_LITERAL_I:%.]] = bitcast void () [[TMP38]] to %struct.__block_literal_generic*
	// CHECK4-NEXT: [[TMP39:%.]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3			// CHECK4-NEXT: [[TMP39:%.]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3
	// CHECK4-NEXT: [[TMP40:%.]] = bitcast %struct.__block_literal_generic [[BLOCK_LITERAL_I]] to i8*			// CHECK4-NEXT: [[TMP40:%.]] = bitcast %struct.__block_literal_generic [[BLOCK_LITERAL_I]] to i8*
	// CHECK4-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP39]], align 8, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: [[TMP41:%.]] = load i8, i8** [[TMP39]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[TMP42:%.]] = bitcast i8 [[TMP41]] to void (i8)			// CHECK4-NEXT: [[TMP42:%.]] = bitcast i8 [[TMP41]] to void (i8)
	// CHECK4-NEXT: call void [[TMP42]](i8* [[TMP40]]) #[[ATTR4]], !llvm.access.group !14			// CHECK4-NEXT: call void [[TMP42]](i8* [[TMP40]]) #[[ATTR4]], !llvm.access.group !15
	// CHECK4-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: [[TMP43:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], 1			// CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], 1
	// CHECK4-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK4-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK4: omp.inner.for.end.i:			// CHECK4: omp.inner.for.end.i:
	// CHECK4-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK4-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK4-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0			// CHECK4-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
	// CHECK4-NEXT: br i1 [[TMP45]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK4-NEXT: br i1 [[TMP45]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK4: .omp.lastprivate.then.i:			// CHECK4: .omp.lastprivate.then.i:
	// CHECK4-NEXT: [[TMP46:%.]] = load double, double [[TMP30]], align 8			// CHECK4-NEXT: [[TMP46:%.]] = load double, double [[TMP30]], align 8
	// CHECK4-NEXT: store volatile double [[TMP46]], double* [[TMP27]], align 8			// CHECK4-NEXT: store volatile double [[TMP46]], double* [[TMP27]], align 8
	// CHECK4-NEXT: [[TMP47:%.]] = load i32, i32 [[TMP31]], align 4			// CHECK4-NEXT: [[TMP47:%.]] = load i32, i32 [[TMP31]], align 4
	// CHECK4-NEXT: store i32 [[TMP47]], i32* [[TMP29]], align 4			// CHECK4-NEXT: store i32 [[TMP47]], i32* [[TMP29]], align 4
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK5-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK5-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK5-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK5-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK5-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK5-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK5-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK5-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK5-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK5-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK5-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK5-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, float, %struct.St) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, float, %struct.St) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK5-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0			// CHECK5-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK5-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK5-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, float, %struct.St)			// CHECK5-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, float, %struct.St)
	// CHECK5-NEXT: call void [[TMP27]](i8* [[TMP26]], float* [[DOTLASTPRIV_PTR_ADDR_I]], %struct.St* [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]			// CHECK5-NEXT: call void [[TMP27]](i8* [[TMP26]], float* [[DOTLASTPRIV_PTR_ADDR_I]], %struct.St* [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]
	// CHECK5-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1			// CHECK5-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 1
	// CHECK5-NEXT: [[TMP29:%.]] = load float, float** [[TMP28]], align 8			// CHECK5-NEXT: [[TMP29:%.]] = load float, float** [[TMP28]], align 8
	// CHECK5-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK5-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP31:%.]] = load %struct.St, %struct.St** [[TMP30]], align 8			// CHECK5-NEXT: [[TMP31:%.]] = load %struct.St, %struct.St** [[TMP30]], align 8
	// CHECK5-NEXT: [[TMP32:%.]] = load float, float** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP32:%.]] = load float, float** [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP33:%.]] = load %struct.St, %struct.St** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP33:%.]] = load %struct.St, %struct.St** [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK5-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK5-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP34]] to i32			// CHECK5-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP34]] to i32
	// CHECK5-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK5-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK5: omp.inner.for.cond.i:			// CHECK5: omp.inner.for.cond.i:
	// CHECK5-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK5-NEXT: [[TMP35:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK5-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP35]] to i64			// CHECK5-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP35]] to i64
	// CHECK5-NEXT: [[TMP36:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK5-NEXT: [[TMP36:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK5-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP36]]			// CHECK5-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP36]]
	// CHECK5-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK5-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK5: omp.inner.for.body.i:			// CHECK5: omp.inner.for.body.i:
	// CHECK5-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK5-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK5-NEXT: store i32 [[TMP37]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK5-NEXT: store i32 [[TMP37]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK5-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK5-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK5-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1			// CHECK5-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP38]], 1
	// CHECK5-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK5-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK5: omp.inner.for.end.i:			// CHECK5: omp.inner.for.end.i:
	// CHECK5-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK5-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK5-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0			// CHECK5-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
	// CHECK5-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK5-NEXT: br i1 [[TMP40]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK5: .omp.lastprivate.then.i:			// CHECK5: .omp.lastprivate.then.i:
	// CHECK5-NEXT: [[TMP41:%.]] = load float, float** [[TMP32]], align 8			// CHECK5-NEXT: [[TMP41:%.]] = load float, float** [[TMP32]], align 8
	// CHECK5-NEXT: store float* [[TMP41]], float** [[TMP29]], align 8			// CHECK5-NEXT: store float* [[TMP41]], float** [[TMP29]], align 8
	// CHECK5-NEXT: [[TMP42:%.]] = load %struct.St, %struct.St** [[TMP33]], align 8			// CHECK5-NEXT: [[TMP42:%.]] = load %struct.St, %struct.St** [[TMP33]], align 8
	// CHECK5-NEXT: store %struct.St* [[TMP42]], %struct.St** [[TMP31]], align 8			// CHECK5-NEXT: store %struct.St* [[TMP42]], %struct.St** [[TMP31]], align 8
	// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK6-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK6-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8			// CHECK6-NEXT: [[TMP13:%.]] = load i64, i64 [[TMP12]], align 8
	// CHECK6-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK6-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK6-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK6-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK6-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK6-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8			// CHECK6-NEXT: [[TMP17:%.]] = load i32, i32 [[TMP16]], align 8
	// CHECK6-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK6-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK6-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK6-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i64 [[TMP11]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i64 [[TMP13]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i64 [[TMP15]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[TMP17]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK6-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store i8* [[TMP19]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP20:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP20]], i32 0, i32 0			// CHECK6-NEXT: [[TMP21:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP20]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP21]], align 8			// CHECK6-NEXT: [[TMP22:%.]] = load i32, i32** [[TMP21]], align 8
	// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4			// CHECK6-NEXT: [[TMP23:%.]] = load i32, i32 [[TMP22]], align 4
	// CHECK6-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP20]], i32 0, i32 1			// CHECK6-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP20]], i32 0, i32 1
	// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP24]], align 8			// CHECK6-NEXT: [[TMP25:%.]] = load i32, i32** [[TMP24]], align 8
	// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK6-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK6-NEXT: store i32 [[TMP26]], i32* [[DOTLINEAR_START1_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[TMP26]], i32* [[DOTLINEAR_START1_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP20]], i32 0, i32 0			// CHECK6-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP20]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP27]], align 8			// CHECK6-NEXT: [[TMP28:%.]] = load i32, i32** [[TMP27]], align 8
	// CHECK6-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK6-NEXT: [[TMP29:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK6-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32			// CHECK6-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
	// CHECK6-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK6: omp.inner.for.cond.i:			// CHECK6: omp.inner.for.cond.i:
	// CHECK6-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[CONV3_I:%.*]] = sext i32 [[TMP30]] to i64			// CHECK6-NEXT: [[CONV3_I:%.*]] = sext i32 [[TMP30]] to i64
	// CHECK6-NEXT: [[TMP31:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: [[TMP31:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV3_I]], [[TMP31]]			// CHECK6-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV3_I]], [[TMP31]]
	// CHECK6-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]			// CHECK6-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[OMP_INNER_FOR_END_I:%.]]
	// CHECK6: omp.inner.for.body.i:			// CHECK6: omp.inner.for.body.i:
	// CHECK6-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: store i32 [[TMP32]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: store i32 [[TMP32]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTLINEAR_START1_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTLINEAR_START1_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]			// CHECK6-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
	// CHECK6-NEXT: store i32 [[ADD5_I]], i32* [[J_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: store i32 [[ADD5_I]], i32* [[J_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[TMP35:%.]] = load i32, i32 [[J_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: [[TMP35:%.]] = load i32, i32 [[J_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP35]], 1			// CHECK6-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP35]], 1
	// CHECK6-NEXT: store i32 [[INC_I]], i32* [[J_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: store i32 [[INC_I]], i32* [[J_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: [[TMP36:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP36]], 1			// CHECK6-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP36]], 1
	// CHECK6-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK6-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK6: omp.inner.for.end.i:			// CHECK6: omp.inner.for.end.i:
	// CHECK6-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK6-NEXT: [[TMP37:%.]] = load i32, i32 [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0			// CHECK6-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0
	// CHECK6-NEXT: br i1 [[TMP38]], label [[DOTOMP_LINEAR_PU_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK6-NEXT: br i1 [[TMP38]], label [[DOTOMP_LINEAR_PU_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK6: .omp.linear.pu.i:			// CHECK6: .omp.linear.pu.i:
	// CHECK6-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLINEAR_START1_I]], align 4, !noalias !13			// CHECK6-NEXT: [[TMP39:%.]] = load i32, i32 [[DOTLINEAR_START1_I]], align 4, !noalias !14
	// CHECK6-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP39]], 10			// CHECK6-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP39]], 10
	// CHECK6-NEXT: store i32 [[ADD7_I]], i32* [[J_I]], align 4, !noalias !13			// CHECK6-NEXT: store i32 [[ADD7_I]], i32* [[J_I]], align 4, !noalias !14
	// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK6: .omp_outlined..1.exit:			// CHECK6: .omp_outlined..1.exit:
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK7-LABEL: define {{[^@]+}}@main			// CHECK7-LABEL: define {{[^@]+}}@main
	// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK7-NEXT: entry:			// CHECK7-NEXT: entry:
	▲ Show 20 Lines • Show All 1,014 Lines • Show Last 20 Lines

clang/test/OpenMP/parallel_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 392 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 399 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 434 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 441 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/sections_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 439 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 445 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5:[0-9]+]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_parallel_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 560 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK1-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK1: omp_offload.failed.i:			// CHECK1: omp_offload.failed.i:
	// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK1: .omp_outlined..1.exit:			// CHECK1: .omp_outlined..1.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK1: .cancel.exit:			// CHECK1: .cancel.exit:
	// CHECK1-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK1-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK1: .cancel.continue:			// CHECK1: .cancel.continue:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK1-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK1-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 644 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK1-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK1-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK1-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z3fooi			// CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
	// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 264 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK2-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK2: omp_offload.failed.i:			// CHECK2: omp_offload.failed.i:
	// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK2: .omp_outlined..1.exit:			// CHECK2: .omp_outlined..1.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK2-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK2-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK2: .cancel.exit:			// CHECK2: .cancel.exit:
	// CHECK2-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK2-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK2-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK2-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK2: .cancel.continue:			// CHECK2: .cancel.continue:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK2-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK2-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 644 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2
	// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK2-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK2-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi			// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
	// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK3-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK3: omp_offload.failed.i:			// CHECK3: omp_offload.failed.i:
	// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK3: .omp_outlined..1.exit:			// CHECK3: .omp_outlined..1.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK3-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK3-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK3: .cancel.exit:			// CHECK3: .cancel.exit:
	// CHECK3-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK3-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK3: .cancel.continue:			// CHECK3: .cancel.continue:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK3-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK3-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 626 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK3-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK3-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK3-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_Z3fooi			// CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
	// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK4-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK4: omp_offload.failed.i:			// CHECK4: omp_offload.failed.i:
	// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK4: .omp_outlined..1.exit:			// CHECK4: .omp_outlined..1.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK4-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK4-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK4-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK4-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK4: .cancel.exit:			// CHECK4: .cancel.exit:
	// CHECK4-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK4-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK4-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK4-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK4: .cancel.continue:			// CHECK4: .cancel.continue:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK4-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK4-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	▲ Show 20 Lines • Show All 626 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK4-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK4-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK4-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
	// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK9-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK9-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK9-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK9: .cancel.exit:			// CHECK9: .cancel.exit:
	// CHECK9-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK9-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK9: .cancel.continue:			// CHECK9: .cancel.continue:
	// CHECK9-NEXT: ret void			// CHECK9-NEXT: ret void
	//			//
	//			//
	// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK9-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {			// CHECK9-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {
	// CHECK9-NEXT: entry:			// CHECK9-NEXT: entry:
	▲ Show 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK10-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK10-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK10-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK10-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK10-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK10: .cancel.exit:			// CHECK10: .cancel.exit:
	// CHECK10-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK10-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK10-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK10-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK10: .cancel.continue:			// CHECK10: .cancel.continue:
	// CHECK10-NEXT: ret void			// CHECK10-NEXT: ret void
	//			//
	//			//
	// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK10-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {			// CHECK10-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {
	// CHECK10-NEXT: entry:			// CHECK10-NEXT: entry:
	▲ Show 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK11-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK11-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK11-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK11-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK11: .cancel.exit:			// CHECK11: .cancel.exit:
	// CHECK11-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK11-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK11: .cancel.continue:			// CHECK11: .cancel.continue:
	// CHECK11-NEXT: ret void			// CHECK11-NEXT: ret void
	//			//
	//			//
	// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK11-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK11-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK11-NEXT: entry:			// CHECK11-NEXT: entry:
	▲ Show 20 Lines • Show All 382 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK12-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK12-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK12-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK12-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK12-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK12-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK12: .cancel.exit:			// CHECK12: .cancel.exit:
	// CHECK12-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK12-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK12-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK12-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK12: .cancel.continue:			// CHECK12: .cancel.continue:
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK12-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK12-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	▲ Show 20 Lines • Show All 604 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK17-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK17-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK17-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK17-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK17-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK17-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK17: omp_offload.failed.i:			// CHECK17: omp_offload.failed.i:
	// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK17: .omp_outlined..1.exit:			// CHECK17: .omp_outlined..1.exit:
	// CHECK17-NEXT: ret i32 0			// CHECK17-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK17-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK17-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK17-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK17-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK17-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK17-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK17: .cancel.exit:			// CHECK17: .cancel.exit:
	// CHECK17-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK17-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK17: .cancel.continue:			// CHECK17: .cancel.continue:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK17-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK17-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	// CHECK17-NEXT: entry:			// CHECK17-NEXT: entry:
	▲ Show 20 Lines • Show All 644 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2
	// CHECK17-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK17-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4			// CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK17-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK17-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK17-NEXT: entry:			// CHECK17-NEXT: entry:
	// CHECK17-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi			// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi
	// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK18-NEXT: entry:			// CHECK18-NEXT: entry:
	▲ Show 20 Lines • Show All 264 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK18-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK18-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK18-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK18-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK18-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK18-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK18: omp_offload.failed.i:			// CHECK18: omp_offload.failed.i:
	// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK18: .omp_outlined..1.exit:			// CHECK18: .omp_outlined..1.exit:
	// CHECK18-NEXT: ret i32 0			// CHECK18-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK18-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK18-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK18-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK18-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK18-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK18-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK18: .cancel.exit:			// CHECK18: .cancel.exit:
	// CHECK18-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK18-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK18: .cancel.continue:			// CHECK18: .cancel.continue:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	//			//
	//			//
	// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK18-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK18-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	// CHECK18-NEXT: entry:			// CHECK18-NEXT: entry:
	▲ Show 20 Lines • Show All 644 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 2
	// CHECK18-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK18-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4			// CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	//			//
	//			//
	// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK18-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK18-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK18-NEXT: entry:			// CHECK18-NEXT: entry:
	// CHECK18-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	//			//
	//			//
	// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi			// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
	// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK19-NEXT: entry:			// CHECK19-NEXT: entry:
	▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK19-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK19-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4			// CHECK19-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
	// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK19-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK19-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK19-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK19: omp_offload.failed.i:			// CHECK19: omp_offload.failed.i:
	// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK19: .omp_outlined..1.exit:			// CHECK19: .omp_outlined..1.exit:
	// CHECK19-NEXT: ret i32 0			// CHECK19-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK19-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK19-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK19-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK19-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK19-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK19-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK19: .cancel.exit:			// CHECK19: .cancel.exit:
	// CHECK19-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK19-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK19: .cancel.continue:			// CHECK19: .cancel.continue:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	//			//
	//			//
	// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK19-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK19-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	// CHECK19-NEXT: entry:			// CHECK19-NEXT: entry:
	▲ Show 20 Lines • Show All 626 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK19-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	//			//
	//			//
	// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK19-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK19-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK19-NEXT: entry:			// CHECK19-NEXT: entry:
	// CHECK19-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi			// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi
	// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {			// CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
	// CHECK20-NEXT: entry:			// CHECK20-NEXT: entry:
	▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK20-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK20-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4			// CHECK20-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
	// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK20-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK20-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK20-NEXT: [[TMP11:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8 null, i8 null, i64* null, i64* null, i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK20: omp_offload.failed.i:			// CHECK20: omp_offload.failed.i:
	// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]			// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
	// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK20: .omp_outlined..1.exit:			// CHECK20: .omp_outlined..1.exit:
	// CHECK20-NEXT: ret i32 0			// CHECK20-NEXT: ret i32 0
	▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK20-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK20-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK20-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK20-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK20-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK20-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK20: .cancel.exit:			// CHECK20: .cancel.exit:
	// CHECK20-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK20-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK20: .cancel.continue:			// CHECK20: .cancel.continue:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK20-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK20-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	// CHECK20-NEXT: entry:			// CHECK20-NEXT: entry:
	▲ Show 20 Lines • Show All 626 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK20-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK20-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK20-SAME: () #[[ATTR6:[0-9]+]] {
	// CHECK20-NEXT: entry:			// CHECK20-NEXT: entry:
	// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//			//
	// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100			// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
	// CHECK25-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK25-NEXT: entry:			// CHECK25-NEXT: entry:
	▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
	// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK25-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK25-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK25-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK25-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK25-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK25-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK25: .cancel.exit:			// CHECK25: .cancel.exit:
	// CHECK25-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK25-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK25: .cancel.continue:			// CHECK25: .cancel.continue:
	// CHECK25-NEXT: ret void			// CHECK25-NEXT: ret void
	//			//
	//			//
	// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK25-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {			// CHECK25-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {
	// CHECK25-NEXT: entry:			// CHECK25-NEXT: entry:
	▲ Show 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
	// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8			// CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 8
	// CHECK26-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK26-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK26-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK26-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK26-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK26-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK26: .cancel.exit:			// CHECK26: .cancel.exit:
	// CHECK26-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK26-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK26: .cancel.continue:			// CHECK26: .cancel.continue:
	// CHECK26-NEXT: ret void			// CHECK26-NEXT: ret void
	//			//
	//			//
	// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK26-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {			// CHECK26-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR0]] {
	// CHECK26-NEXT: entry:			// CHECK26-NEXT: entry:
	▲ Show 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
	// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK27-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK27-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK27-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK27-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK27-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK27-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK27: .cancel.exit:			// CHECK27: .cancel.exit:
	// CHECK27-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK27-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK27: .cancel.continue:			// CHECK27: .cancel.continue:
	// CHECK27-NEXT: ret void			// CHECK27-NEXT: ret void
	//			//
	//			//
	// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK27-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK27-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK27-NEXT: entry:			// CHECK27-NEXT: entry:
	▲ Show 20 Lines • Show All 382 Lines • ▼ Show 20 Lines
	// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16			// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
	// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4			// CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 4
	// CHECK28-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK28-NEXT: [[TMP1:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK28-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4			// CHECK28-NEXT: [[TMP2:%.]] = load i32, i32 [[TMP1]], align 4
	// CHECK28-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)			// CHECK28-NEXT: [[TMP3:%.]] = call i32 @__kmpc_cancel(%struct.ident_t @[[GLOB1]], i32 [[TMP2]], i32 1)
	// CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]			// CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.]], label [[DOTCANCEL_CONTINUE:%.]]
	// CHECK28: .cancel.exit:			// CHECK28: .cancel.exit:
	// CHECK28-NEXT: [[TMP10:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])			// CHECK28-NEXT: [[TMP5:%.]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t @[[GLOB2:[0-9]+]], i32 [[TMP2]])
	// CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]]			// CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]]
	// CHECK28: .cancel.continue:			// CHECK28: .cancel.continue:
	// CHECK28-NEXT: ret void			// CHECK28-NEXT: ret void
	//			//
	//			//
	// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119			// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
	// CHECK28-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {			// CHECK28-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR0]] {
	// CHECK28-NEXT: entry:			// CHECK28-NEXT: entry:
	▲ Show 20 Lines • Show All 328 Lines • ▼ Show 20 Lines
	// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16			// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
	// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4			// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
	// CHECK28-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK28-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK28-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK28-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK28-NEXT: ret void			// CHECK28-NEXT: ret void
	//			//
	//

clang/test/OpenMP/target_parallel_for_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 781 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3			// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
	// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64			// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
	// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11			// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK1-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK1: omp_offload.failed.i:			// CHECK1: omp_offload.failed.i:
	// CHECK1-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK1-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK1-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK1-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK1-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK1-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*			// CHECK1-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*
	// CHECK1-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK1-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK1-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*			// CHECK1-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*
	// CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
	// CHECK1-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !24
	// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]			// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK1: .omp_outlined..3.exit:			// CHECK1: .omp_outlined..3.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK1-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK1-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,338 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3			// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
	// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64			// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
	// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11			// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK2-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK2-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK2: omp_offload.failed.i:			// CHECK2: omp_offload.failed.i:
	// CHECK2-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK2-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK2-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK2-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK2-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK2-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*			// CHECK2-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*
	// CHECK2-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK2-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK2-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*			// CHECK2-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*
	// CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
	// CHECK2-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !24
	// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]			// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK2: .omp_outlined..3.exit:			// CHECK2: .omp_outlined..3.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK2-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK2-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,323 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12			// CHECK3-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3			// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
	// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64			// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
	// CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12			// CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK3-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK3: omp_offload.failed.i:			// CHECK3: omp_offload.failed.i:
	// CHECK3-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK3-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK3-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK3-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK3-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK3-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK3-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK3-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]			// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK3: .omp_outlined..3.exit:			// CHECK3: .omp_outlined..3.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK3-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK3-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,302 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12			// CHECK4-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3			// CHECK4-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
	// CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64			// CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
	// CHECK4-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12			// CHECK4-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK4-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK4-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK4-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK4-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK4: omp_offload.failed.i:			// CHECK4: omp_offload.failed.i:
	// CHECK4-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK4-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK4-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK4-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK4-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK4-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK4-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK4-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]			// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK4: .omp_outlined..3.exit:			// CHECK4: .omp_outlined..3.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK4-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK4-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 4,525 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK17-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK17-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK17-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK17-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !11			// CHECK17-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3			// CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
	// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64			// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
	// CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11			// CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !12
	// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK17-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK17-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK17-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK17-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK17-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK17-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK17-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK17-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK17-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK17-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK17-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK17-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK17-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK17-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK17-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK17: omp_offload.failed.i:			// CHECK17: omp_offload.failed.i:
	// CHECK17-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK17-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK17-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK17-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK17-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK17-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK17-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK17-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK17-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*			// CHECK17-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*
	// CHECK17-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK17-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK17-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK17-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK17-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*			// CHECK17-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*
	// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23			// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
	// CHECK17-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !24
	// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]			// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
	// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK17: .omp_outlined..3.exit:			// CHECK17: .omp_outlined..3.exit:
	// CHECK17-NEXT: ret i32 0			// CHECK17-NEXT: ret i32 0
	//			//
	//			//
	// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK17-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK17-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,338 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP3:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK18-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK18-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK18-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
	// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK18-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !11			// CHECK18-NEXT: [[TMP8:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3			// CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
	// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64			// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
	// CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !11			// CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !12
	// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 8, !llvm.access.group !12
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK18-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK18-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK18-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK18-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK18-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK18-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK18-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK18-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK18-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK18-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK18-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK18-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK18-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK18-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK18-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK18: omp_offload.failed.i:			// CHECK18: omp_offload.failed.i:
	// CHECK18-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK18-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK18-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK18-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK18-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK18-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK18-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP28:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK18-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK18-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*			// CHECK18-NEXT: [[CONV4_I:%.]] = bitcast i64 [[LIN_CASTED_I]] to i32*
	// CHECK18-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK18-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK18-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP30:%.]] = load i64, i64 [[LIN_CASTED_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK18-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK18-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*			// CHECK18-NEXT: [[CONV5_I:%.]] = bitcast i64 [[A_CASTED_I]] to i32*
	// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !23			// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
	// CHECK18-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP32:%.]] = load i64, i64 [[A_CASTED_I]], align 8, !noalias !24
	// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]			// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR3]]
	// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK18: .omp_outlined..3.exit:			// CHECK18: .omp_outlined..3.exit:
	// CHECK18-NEXT: ret i32 0			// CHECK18-NEXT: ret i32 0
	//			//
	//			//
	// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK18-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {			// CHECK18-SAME: (i64 [[A:%.]], i64 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,323 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK19-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12			// CHECK19-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !13
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3			// CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
	// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64			// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
	// CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12			// CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK19-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK19-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK19-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK19-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK19-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK19-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK19-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK19-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK19-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK19-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK19-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK19-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK19-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK19-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK19: omp_offload.failed.i:			// CHECK19: omp_offload.failed.i:
	// CHECK19-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK19-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK19-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK19-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK19-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK19-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK19-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK19-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK19-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK19-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]			// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
	// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK19: .omp_outlined..3.exit:			// CHECK19: .omp_outlined..3.exit:
	// CHECK19-NEXT: ret i32 0			// CHECK19-NEXT: ret i32 0
	//			//
	//			//
	// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK19-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK19-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,302 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP4:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK20-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]			// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
	// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !12			// CHECK20-NEXT: [[TMP9:%.]] = load i64, i64 [[DOTLINEAR_START]], align 8, !llvm.access.group !13
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3			// CHECK20-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
	// CHECK20-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64			// CHECK20-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
	// CHECK20-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12			// CHECK20-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]			// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.]], label [[DOTOMP_LINEAR_PU_DONE:%.]]
	▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK20-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK20-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK20-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK20-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK20-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK20-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK20-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK20-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK20-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK20-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK20-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]			// CHECK20-NEXT: [[TMP25:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 1, i32 0) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0			// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
	// CHECK20-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]			// CHECK20-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__3_EXIT:%.]]
	// CHECK20: omp_offload.failed.i:			// CHECK20: omp_offload.failed.i:
	// CHECK20-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK20-NEXT: [[TMP27:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK20-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK20-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK20-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK20-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK20-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK20-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[LIN_CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK20-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK20-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP32:%.]] = load i32, i32 [[A_CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]			// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR3]]
	// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK20: .omp_outlined..3.exit:			// CHECK20: .omp_outlined..3.exit:
	// CHECK20-NEXT: ret i32 0			// CHECK20-NEXT: ret i32 0
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146			// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
	// CHECK20-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {			// CHECK20-SAME: (i32 [[A:%.]], i32 [[AA:%.]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 4,053 Lines • ▼ Show 20 Lines
	// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8			// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
	// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK28: omp.inner.for.end:			// CHECK28: omp.inner.for.end:
	// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK28: omp.loop.exit:			// CHECK28: omp.loop.exit:
	// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK28-NEXT: ret void			// CHECK28-NEXT: ret void
	//			//
	//

clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 459 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 466 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_parallel_for_simd_codegen.cpp

This file has a very large number of changes (2,960 lines). Show File Contents

clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 405 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 412 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	Show All 35 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_teams_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 761 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK1-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK1: omp_offload.failed.i:			// CHECK1: omp_offload.failed.i:
	// CHECK1-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK1-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK1-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK1-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK1-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK1-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK1-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK1-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
	// CHECK1-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
	// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK1: .omp_outlined..1.exit:			// CHECK1: .omp_outlined..1.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,325 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK2-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK2: omp_offload.failed.i:			// CHECK2: omp_offload.failed.i:
	// CHECK2-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK2-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK2-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK2-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK2-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK2-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK2-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK2-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK2-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK2-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK2-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
	// CHECK2-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
	// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK2: .omp_outlined..1.exit:			// CHECK2: .omp_outlined..1.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,316 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK3-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK3-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK3: omp_offload.failed.i:			// CHECK3: omp_offload.failed.i:
	// CHECK3-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK3-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK3-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK3-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK3: .omp_outlined..1.exit:			// CHECK3: .omp_outlined..1.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,286 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK4-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK4-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK4-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK4: omp_offload.failed.i:			// CHECK4: omp_offload.failed.i:
	// CHECK4-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK4-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK4-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK4-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK4-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK4-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK4: .omp_outlined..1.exit:			// CHECK4: .omp_outlined..1.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 3,401 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK17-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK17-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK17-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK17-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK17-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK17-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK17-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK17-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK17-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK17-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK17-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK17-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK17-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK17: omp_offload.failed.i:			// CHECK17: omp_offload.failed.i:
	// CHECK17-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK17-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK17-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK17-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK17-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK17-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK17-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK17-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK17-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
	// CHECK17-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK17-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK17-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK17-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23			// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
	// CHECK17-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23			// CHECK17-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
	// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK17: .omp_outlined..1.exit:			// CHECK17: .omp_outlined..1.exit:
	// CHECK17-NEXT: ret i32 0			// CHECK17-NEXT: ret i32 0
	//			//
	//			//
	// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,325 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK18-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK18-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK18-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK18-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK18-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK18-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK18-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK18-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK18-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK18-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK18-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK18-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK18-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK18: omp_offload.failed.i:			// CHECK18: omp_offload.failed.i:
	// CHECK18-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK18-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK18-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK18-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !23			// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24
	// CHECK18-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK18-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK18-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK18-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !23			// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24
	// CHECK18-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24
	// CHECK18-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK18-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK18-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK18-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !23			// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24
	// CHECK18-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !23			// CHECK18-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24
	// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK18: .omp_outlined..1.exit:			// CHECK18: .omp_outlined..1.exit:
	// CHECK18-NEXT: ret i32 0			// CHECK18-NEXT: ret i32 0
	//			//
	//			//
	// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,316 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK19-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK19-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK19-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK19-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK19-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK19-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK19-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK19-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK19-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK19-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK19-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK19-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK19-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK19: omp_offload.failed.i:			// CHECK19: omp_offload.failed.i:
	// CHECK19-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK19-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK19-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK19-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK19-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK19-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK19-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK19-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK19: .omp_outlined..1.exit:			// CHECK19: .omp_outlined..1.exit:
	// CHECK19-NEXT: ret i32 0			// CHECK19-NEXT: ret i32 0
	//			//
	//			//
	// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 1,286 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK20-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK20-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK20-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK20-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK20-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK20-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK20-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK20-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK20-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK20-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK20-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK20-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK20-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK20: omp_offload.failed.i:			// CHECK20: omp_offload.failed.i:
	// CHECK20-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK20-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK20-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK20-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24			// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25
	// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK20-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK20-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK20-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !24			// CHECK20-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
	// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK20: .omp_outlined..1.exit:			// CHECK20: .omp_outlined..1.exit:
	// CHECK20-NEXT: ret i32 0			// CHECK20-NEXT: ret i32 0
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105			// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
	// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 2,935 Lines • ▼ Show 20 Lines
	// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16			// CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
	// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4			// CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 4
	// CHECK28-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2			// CHECK28-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 2
	// CHECK28-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4			// CHECK28-NEXT: [[TMP3:%.]] = load i32, i32 [[ARRAYIDX]], align 4
	// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1			// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
	// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4			// CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
	// CHECK28-NEXT: ret void			// CHECK28-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_teams_distribute_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 775 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK1-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK1-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK1-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK1: omp_offload.failed.i:			// CHECK1: omp_offload.failed.i:
	// CHECK1-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK1-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20			// CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
	// CHECK1-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK1-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK1-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20			// CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !21
	// CHECK1-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK1-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK1-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20			// CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !21
	// CHECK1-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20			// CHECK1-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !21
	// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK1: .omp_outlined..1.exit:			// CHECK1: .omp_outlined..1.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !21			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK1-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21			// CHECK1-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK1-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK1-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK1-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK1-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK1-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK1-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK1-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK1-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK1-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK1-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK1-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK1-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK1-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK1-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK1-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK1-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !21			// CHECK1-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21			// CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK1-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !21			// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21			// CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !22
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,220 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK2-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK2-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK2-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK2: omp_offload.failed.i:			// CHECK2: omp_offload.failed.i:
	// CHECK2-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK2-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK2-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20			// CHECK2-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
	// CHECK2-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK2-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK2-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20			// CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !21
	// CHECK2-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK2-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK2-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK2-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20			// CHECK2-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !21
	// CHECK2-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20			// CHECK2-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !21
	// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK2: .omp_outlined..1.exit:			// CHECK2: .omp_outlined..1.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !21			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK2-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21			// CHECK2-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK2-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK2-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK2-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK2-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK2-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK2-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK2-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK2-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK2-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK2-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK2-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK2-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK2-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK2-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK2-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK2-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK2-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK2-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK2-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK2-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK2-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK2-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK2-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK2-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK2-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK2-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK2-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK2-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK2-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !21			// CHECK2-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK2-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK2-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21			// CHECK2-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK2-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !21			// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK2-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK2-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK2-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK2-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK2-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK2-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21			// CHECK2-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !22
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK2-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK2-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,212 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK3-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK3-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK3-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK3-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK3-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK3-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK3-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK3-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK3: omp_offload.failed.i:			// CHECK3: omp_offload.failed.i:
	// CHECK3-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK3-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK3-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK3-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21			// CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !22
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK3-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK3-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK3: .omp_outlined..1.exit:			// CHECK3: .omp_outlined..1.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 360 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK3-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK3-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK3-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK3-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK3-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK3-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK3-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK3-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK3-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK3-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK3-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK3-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK3-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK3-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK3-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK3-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22			// CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK3-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22			// CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK3-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,196 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK4-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK4-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK4-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK4-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK4-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK4-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK4-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK4-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK4: omp_offload.failed.i:			// CHECK4: omp_offload.failed.i:
	// CHECK4-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK4-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK4-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK4-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK4-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21			// CHECK4-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !22
	// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK4-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK4-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK4: .omp_outlined..1.exit:			// CHECK4: .omp_outlined..1.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 360 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK4-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK4-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK4-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK4-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK4-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK4-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK4-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK4-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK4-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK4-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK4-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK4-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK4-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK4-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK4-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK4-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK4-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK4-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK4-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK4-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK4-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK4-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK4-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK4-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK4-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK4-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK4-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK4-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK4-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK4-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK4-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK4-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK4-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22			// CHECK4-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK4-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK4-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK4-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK4-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK4-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK4-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK4-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22			// CHECK4-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK4-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK4-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK4-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK4-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK4-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK4-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,106 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK9-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK9-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK9-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK9-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK9-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK9-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK9-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK9-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK9-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK9-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK9-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK9-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK9-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK9-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK9-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK9-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK9-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK9-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK9-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !11			// CHECK9-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11			// CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK9-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK9-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !11			// CHECK9-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11			// CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK9-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 779 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK10-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK10-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK10-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK10-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK10-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK10-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK10-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK10-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK10-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK10-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK10-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK10-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK10-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK10-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK10-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK10-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK10-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK10-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK10-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !11			// CHECK10-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11			// CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK10-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK10-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !11			// CHECK10-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11			// CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK10-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK10-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK10-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 768 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK11-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK11-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK11-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK11-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK11-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK11-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK11-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK11-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK11-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK11-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK11-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK11-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK11-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK11-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK11-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK11-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK11-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK11-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12			// CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK11-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK11-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12			// CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK11-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 756 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK12-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK12-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK12-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK12-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK12-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK12-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK12-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK12-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK12-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK12-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK12-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK12-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK12-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK12-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK12-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK12-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK12-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK12-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12			// CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK12-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK12-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12			// CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK12-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 865 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK17-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK17-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK17-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK17-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK17-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK17-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK17-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK17-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK17-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK17-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK17-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK17-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK17-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK17-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK17-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK17-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK17-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK17-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK17-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK17-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK17-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK17: omp_offload.failed.i:			// CHECK17: omp_offload.failed.i:
	// CHECK17-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK17-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK17-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK17-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20			// CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
	// CHECK17-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK17-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK17-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK17-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20			// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !21
	// CHECK17-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21
	// CHECK17-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK17-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK17-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK17-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20			// CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !21
	// CHECK17-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20			// CHECK17-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !21
	// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK17: .omp_outlined..1.exit:			// CHECK17: .omp_outlined..1.exit:
	// CHECK17-NEXT: ret i32 0			// CHECK17-NEXT: ret i32 0
	//			//
	//			//
	// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !21			// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21			// CHECK17-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK17-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK17-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK17-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK17-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK17-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK17-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK17-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK17-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK17-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK17-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK17-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK17-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK17-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK17-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK17-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK17-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK17-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !21			// CHECK17-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21			// CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK17-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !21			// CHECK17-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21			// CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !22
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK17-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK17-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,220 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK18-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK18-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK18-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK18-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK18-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK18-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK18-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK18-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK18-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK18-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
	// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])			// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
	// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20			// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
	// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK18-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0			// CHECK18-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0			// CHECK18-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0			// CHECK18-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i64 0, i64 0
	// CHECK18-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK18-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK18-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK18-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK18-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK18-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK18-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK18: omp_offload.failed.i:			// CHECK18: omp_offload.failed.i:
	// CHECK18-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK18-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK18-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*			// CHECK18-NEXT: [[CONV_I:%.]] = bitcast i64 [[AA_CASTED_I]] to i16*
	// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !20			// CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21
	// CHECK18-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP30:%.]] = load i64, i64 [[AA_CASTED_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK18-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK18-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*			// CHECK18-NEXT: [[CONV4_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED_I]] to i32*
	// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !20			// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !21
	// CHECK18-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP32:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21
	// CHECK18-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK18-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK18-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*			// CHECK18-NEXT: [[CONV6_I:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED5_I]] to i32*
	// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !20			// CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !21
	// CHECK18-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !20			// CHECK18-NEXT: [[TMP34:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !21
	// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]			// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]]
	// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK18: .omp_outlined..1.exit:			// CHECK18: .omp_outlined..1.exit:
	// CHECK18-NEXT: ret i32 0			// CHECK18-NEXT: ret i32 0
	//			//
	//			//
	// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {			// CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !21			// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !21			// CHECK18-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK18-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK18-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK18-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK18-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK18-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !21			// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK18-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK18-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK18-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK18-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK18-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !21			// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK18-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK18-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK18-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK18-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK18-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK18-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !21			// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK18-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !21			// CHECK18-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !21			// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK18-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !21			// CHECK18-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !21			// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !22
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK18-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK18-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,212 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK19-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK19-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK19-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK19-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK19-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK19-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK19-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK19-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK19-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK19-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK19-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK19-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK19-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK19-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK19-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK19-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK19-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK19-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK19-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK19-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK19: omp_offload.failed.i:			// CHECK19: omp_offload.failed.i:
	// CHECK19-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK19-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK19-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK19-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21			// CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !22
	// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK19-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK19-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK19-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK19-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK19: .omp_outlined..1.exit:			// CHECK19: .omp_outlined..1.exit:
	// CHECK19-NEXT: ret i32 0			// CHECK19-NEXT: ret i32 0
	//			//
	//			//
	// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 360 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK19-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK19-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK19-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK19-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK19-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK19-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK19-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK19-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK19-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK19-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK19-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK19-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK19-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK19-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK19-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK19-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK19-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22			// CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK19-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22			// CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK19-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK19-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,196 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK20-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK20-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK20-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4			// CHECK20-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 4
	// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK20-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK20-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK20-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK20-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK20-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK20-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i16, [3 x i8]*, [3 x i8], [3 x i64])* @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*			// CHECK20-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i16, [3 x i8]*, [3 x i8], [3 x i64])*
	// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]			// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8]* [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP16:%.]] = load i16, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP17:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP18:%.]] = load [3 x i8], [3 x i8]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP19:%.]] = load [3 x i64], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0			// CHECK20-NEXT: [[TMP20:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP17]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0			// CHECK20-NEXT: [[TMP21:%.]] = getelementptr inbounds [3 x i8], [3 x i8] [[TMP18]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0			// CHECK20-NEXT: [[TMP22:%.]] = getelementptr inbounds [3 x i64], [3 x i64] [[TMP19]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK20-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK20-NEXT: [[TMP24:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK20-NEXT: [[TMP25:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK20-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]			// CHECK20-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 10) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]			// CHECK20-NEXT: [[TMP27:%.]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 3, i8 [[TMP20]], i8 [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8 null, i8 null, i32 [[TMP25]], i32 [[TMP26]]) #[[ATTR3]]
	// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0			// CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
	// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]			// CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.]], label [[DOTOMP_OUTLINED__1_EXIT:%.]]
	// CHECK20: omp_offload.failed.i:			// CHECK20: omp_offload.failed.i:
	// CHECK20-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2			// CHECK20-NEXT: [[TMP29:%.]] = load i16, i16 [[TMP16]], align 2
	// CHECK20-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*			// CHECK20-NEXT: [[CONV_I:%.]] = bitcast i32 [[AA_CASTED_I]] to i16*
	// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !21			// CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !22
	// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[AA_CASTED_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4			// CHECK20-NEXT: [[TMP31:%.]] = load i32, i32 [[TMP23]], align 4
	// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP32:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4			// CHECK20-NEXT: [[TMP33:%.]] = load i32, i32 [[TMP24]], align 4
	// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK20-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21			// CHECK20-NEXT: [[TMP34:%.]] = load i32, i32 [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
	// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]			// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]]
	// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]			// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
	// CHECK20: .omp_outlined..1.exit:			// CHECK20: .omp_outlined..1.exit:
	// CHECK20-NEXT: ret i32 0			// CHECK20-NEXT: ret i32 0
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107			// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
	// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {			// CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
	▲ Show 20 Lines • Show All 360 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK20-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !22			// CHECK20-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !22			// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK20-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK20-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !22			// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK20-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK20-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK20-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK20-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK20-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !22			// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !23
	// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK20-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK20-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK20-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK20-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK20-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK20-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !22			// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !23
	// CHECK20-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK20-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !22			// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK20-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !22			// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK20-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22			// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK20-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,106 Lines • ▼ Show 20 Lines
	// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK25-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK25-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK25-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK25-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK25: omp.dispatch.body:			// CHECK25: omp.dispatch.body:
	// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK25: omp.inner.for.cond:			// CHECK25: omp.inner.for.cond:
	// CHECK25-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK25-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK25-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK25: omp.inner.for.body:			// CHECK25: omp.inner.for.body:
	// CHECK25-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK25-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK25-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK25-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK25-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK25-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK25-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK25-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK25-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK25-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK25-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK25-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK25-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK25-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK25-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK25-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK25-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK25-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK25-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK25-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK25-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK25-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK25-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !11			// CHECK25-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11			// CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK25-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK25-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !11			// CHECK25-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11			// CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13
	// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK25: omp.body.continue:			// CHECK25: omp.body.continue:
	// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK25: omp.inner.for.inc:			// CHECK25: omp.inner.for.inc:
	// CHECK25-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK25-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK25: omp.inner.for.end:			// CHECK25: omp.inner.for.end:
	// CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK25: omp.dispatch.inc:			// CHECK25: omp.dispatch.inc:
	// CHECK25-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK25-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK25-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK25-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK25-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK25-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 779 Lines • ▼ Show 20 Lines
	// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK26-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK26-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK26-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK26-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK26: omp.dispatch.body:			// CHECK26: omp.dispatch.body:
	// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK26: omp.inner.for.cond:			// CHECK26: omp.inner.for.cond:
	// CHECK26-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK26-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK26-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK26: omp.inner.for.body:			// CHECK26: omp.inner.for.body:
	// CHECK26-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK26-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11			// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !11			// CHECK26-NEXT: [[TMP19:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !11			// CHECK26-NEXT: store i32 [[ADD8]], i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2			// CHECK26-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i64 0, i64 2
	// CHECK26-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK26-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double			// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
	// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00			// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
	// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float			// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
	// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3			// CHECK26-NEXT: [[ARRAYIDX12:%.]] = getelementptr inbounds float, float [[TMP2]], i64 3
	// CHECK26-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK26-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double			// CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
	// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00			// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
	// CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float			// CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
	// CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !11			// CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1			// CHECK26-NEXT: [[ARRAYIDX16:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i64 0, i64 1
	// CHECK26-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2			// CHECK26-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX16]], i64 0, i64 2
	// CHECK26-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK26-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !11			// CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]			// CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
	// CHECK26-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]			// CHECK26-NEXT: [[ARRAYIDX19:%.]] = getelementptr inbounds double, double [[TMP6]], i64 [[TMP23]]
	// CHECK26-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3			// CHECK26-NEXT: [[ARRAYIDX20:%.]] = getelementptr inbounds double, double [[ARRAYIDX19]], i64 3
	// CHECK26-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK26-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !11			// CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK26-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK26-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !11			// CHECK26-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !11			// CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK26-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK26-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !11			// CHECK26-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32			// CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1			// CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
	// CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8			// CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
	// CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !11			// CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !13
	// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK26: omp.body.continue:			// CHECK26: omp.body.continue:
	// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK26: omp.inner.for.inc:			// CHECK26: omp.inner.for.inc:
	// CHECK26-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK26-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK26: omp.inner.for.end:			// CHECK26: omp.inner.for.end:
	// CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK26: omp.dispatch.inc:			// CHECK26: omp.dispatch.inc:
	// CHECK26-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK26-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK26-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK26-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4			// CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
	// CHECK26-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK26-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 768 Lines • ▼ Show 20 Lines
	// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK27-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK27-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK27-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK27-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK27: omp.dispatch.body:			// CHECK27: omp.dispatch.body:
	// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK27: omp.inner.for.cond:			// CHECK27: omp.inner.for.cond:
	// CHECK27-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK27: omp.inner.for.body:			// CHECK27: omp.inner.for.body:
	// CHECK27-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK27-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK27-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK27-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK27-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK27-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK27-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK27-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK27-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK27-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK27-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK27-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK27-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK27-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK27-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK27-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK27-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK27-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK27-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK27-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK27-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12			// CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK27-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK27-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12			// CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK27: omp.body.continue:			// CHECK27: omp.body.continue:
	// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK27: omp.inner.for.inc:			// CHECK27: omp.inner.for.inc:
	// CHECK27-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK27-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK27: omp.inner.for.end:			// CHECK27: omp.inner.for.end:
	// CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK27: omp.dispatch.inc:			// CHECK27: omp.dispatch.inc:
	// CHECK27-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK27-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK27-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK27-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK27-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK27-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 756 Lines • ▼ Show 20 Lines
	// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK28-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK28-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK28-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK28-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK28: omp.dispatch.body:			// CHECK28: omp.dispatch.body:
	// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK28: omp.inner.for.cond:			// CHECK28: omp.inner.for.cond:
	// CHECK28-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK28: omp.inner.for.body:			// CHECK28: omp.inner.for.body:
	// CHECK28-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP19:%.]] = load i32, i32 [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK28-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !12			// CHECK28-NEXT: store i32 [[ADD7]], i32* [[A_ADDR]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2			// CHECK28-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x float], [10 x float] [[TMP0]], i32 0, i32 2
	// CHECK28-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP20:%.]] = load float, float [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double			// CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
	// CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00			// CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
	// CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float			// CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
	// CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3			// CHECK28-NEXT: [[ARRAYIDX10:%.]] = getelementptr inbounds float, float [[TMP2]], i32 3
	// CHECK28-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP21:%.]] = load float, float [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double			// CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
	// CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00			// CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
	// CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float			// CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
	// CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !12			// CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1			// CHECK28-NEXT: [[ARRAYIDX14:%.]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]] [[TMP3]], i32 0, i32 1
	// CHECK28-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2			// CHECK28-NEXT: [[ARRAYIDX15:%.]] = getelementptr inbounds [10 x double], [10 x double] [[ARRAYIDX14]], i32 0, i32 2
	// CHECK28-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK28-NEXT: [[TMP22:%.]] = load double, double [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00			// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
	// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !12			// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !14
	// CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]			// CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
	// CHECK28-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]			// CHECK28-NEXT: [[ARRAYIDX17:%.]] = getelementptr inbounds double, double [[TMP6]], i32 [[TMP23]]
	// CHECK28-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3			// CHECK28-NEXT: [[ARRAYIDX18:%.]] = getelementptr inbounds double, double [[ARRAYIDX17]], i32 3
	// CHECK28-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK28-NEXT: [[TMP24:%.]] = load double, double [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00			// CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
	// CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !12			// CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !14
	// CHECK28-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0			// CHECK28-NEXT: [[X:%.]] = getelementptr inbounds [[STRUCT_TT:%.]], %struct.TT* [[TMP7]], i32 0, i32 0
	// CHECK28-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP25:%.]] = load i64, i64 [[X]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1			// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
	// CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !12			// CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1			// CHECK28-NEXT: [[Y:%.]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT [[TMP7]], i32 0, i32 1
	// CHECK28-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP26:%.]] = load i8, i8 [[Y]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32			// CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
	// CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1			// CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
	// CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8			// CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
	// CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !12			// CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK28: omp.body.continue:			// CHECK28: omp.body.continue:
	// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK28: omp.inner.for.inc:			// CHECK28: omp.inner.for.inc:
	// CHECK28-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK28-NEXT: [[TMP27:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1			// CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
	// CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK28: omp.inner.for.end:			// CHECK28: omp.inner.for.end:
	// CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK28: omp.dispatch.inc:			// CHECK28: omp.dispatch.inc:
	// CHECK28-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK28-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK28-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK28-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4			// CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
	// CHECK28-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK28-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 377 Lines • ▼ Show 20 Lines
	// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
	// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]			// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
	// CHECK28: omp.inner.for.end:			// CHECK28: omp.inner.for.end:
	// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK28: omp.loop.exit:			// CHECK28: omp.loop.exit:
	// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK28-NEXT: ret void			// CHECK28-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 417 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 307 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 307 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !10			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 581 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !10			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 565 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 565 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]			// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
	// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK12: omp.dispatch.end:			// CHECK12: omp.dispatch.end:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp

	Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !3			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !3			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK2-SAME: () #[[ATTR3:[0-9]+]] section ".text.startup" {			// CHECK2-SAME: () #[[ATTR3:[0-9]+]] section ".text.startup" {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 805 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 861 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 917 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK7: omp.dispatch.end:			// CHECK7: omp.dispatch.end:
	// CHECK7-NEXT: ret void			// CHECK7-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK7: omp.dispatch.end:			// CHECK7: omp.dispatch.end:
	// CHECK7-NEXT: ret void			// CHECK7-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK8: omp.dispatch.end:			// CHECK8: omp.dispatch.end:
	// CHECK8-NEXT: ret void			// CHECK8-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK8: omp.dispatch.end:			// CHECK8: omp.dispatch.end:
	// CHECK8-NEXT: ret void			// CHECK8-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,282 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK13-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: br label [[OMP_PRECOND_END]]			// CHECK13-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK13: omp.precond.end:			// CHECK13: omp.precond.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK13-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: br label [[OMP_PRECOND_END]]			// CHECK13-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK13: omp.precond.end:			// CHECK13: omp.precond.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	▲ Show 20 Lines • Show All 758 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,282 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK14-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK14-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: br label [[OMP_PRECOND_END]]			// CHECK14-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK14: omp.precond.end:			// CHECK14: omp.precond.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK14-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK14-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK14-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: br label [[OMP_PRECOND_END]]			// CHECK14-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK14: omp.precond.end:			// CHECK14: omp.precond.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	▲ Show 20 Lines • Show All 758 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK14-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,235 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK15-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK15-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: br label [[OMP_PRECOND_END]]			// CHECK15-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK15: omp.precond.end:			// CHECK15: omp.precond.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: br label [[OMP_PRECOND_END]]			// CHECK15-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK15: omp.precond.end:			// CHECK15: omp.precond.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	▲ Show 20 Lines • Show All 729 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,235 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK16-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK16-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: br label [[OMP_PRECOND_END]]			// CHECK16-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK16: omp.precond.end:			// CHECK16: omp.precond.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: br label [[OMP_PRECOND_END]]			// CHECK16-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK16: omp.precond.end:			// CHECK16: omp.precond.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	▲ Show 20 Lines • Show All 729 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,282 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: br label [[OMP_PRECOND_END]]			// CHECK17-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK17: omp.precond.end:			// CHECK17: omp.precond.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK17-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: br label [[OMP_PRECOND_END]]			// CHECK17-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK17: omp.precond.end:			// CHECK17: omp.precond.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	▲ Show 20 Lines • Show All 758 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,282 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !14			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: br label [[OMP_PRECOND_END]]			// CHECK18-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK18: omp.precond.end:			// CHECK18: omp.precond.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK18-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !17			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I7]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[I7]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: br label [[OMP_PRECOND_END]]			// CHECK18-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK18: omp.precond.end:			// CHECK18: omp.precond.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	▲ Show 20 Lines • Show All 758 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,235 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK19-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: br label [[OMP_PRECOND_END]]			// CHECK19-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK19: omp.precond.end:			// CHECK19: omp.precond.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: br label [[OMP_PRECOND_END]]			// CHECK19-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK19: omp.precond.end:			// CHECK19: omp.precond.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	▲ Show 20 Lines • Show All 729 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,235 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP14:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP13]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP15]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK20-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: br label [[OMP_PRECOND_END]]			// CHECK20-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK20: omp.precond.end:			// CHECK20: omp.precond.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP20]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: br label [[OMP_PRECOND_END]]			// CHECK20-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK20: omp.precond.end:			// CHECK20: omp.precond.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	▲ Show 20 Lines • Show All 729 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK20-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK20-SAME: () #[[ATTR5:[0-9]+]] {
	// CHECK20-NEXT: entry:			// CHECK20-NEXT: entry:
	// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK1-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK1-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: store i32 0, i32* [[CONV]], align 8			// CHECK1-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !18
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !18
	// CHECK1-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK1-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !18
	// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: call void @_Z9gtid_testv()			// CHECK1-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: call void @_Z3fn4v()			// CHECK1-NEXT: call void @_Z3fn4v(), !llvm.access.group !27
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !30
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !30
	// CHECK1-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK1-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !30
	// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !30
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: call void @_Z3fn5v()			// CHECK1-NEXT: call void @_Z3fn5v(), !llvm.access.group !33
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !36
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK1: omp_if.then:			// CHECK1: omp_if.then:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK1: omp_if.else:			// CHECK1: omp_if.else:
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36
	// CHECK1-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK1-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !36
	// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
	// CHECK1-NEXT: br label [[OMP_IF_END]]			// CHECK1-NEXT: br label [[OMP_IF_END]]
	// CHECK1: omp_if.end:			// CHECK1: omp_if.end:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: call void @_Z3fn6v()			// CHECK1-NEXT: call void @_Z3fn6v(), !llvm.access.group !39
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: call void @_Z3fn1v()			// CHECK1-NEXT: call void @_Z3fn1v(), !llvm.access.group !45
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !48
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !48
	// CHECK1-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK1-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !48
	// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !48
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !48
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !48
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !51
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !51
	// CHECK1-NEXT: call void @_Z3fn2v()			// CHECK1-NEXT: call void @_Z3fn2v(), !llvm.access.group !51
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK1-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK1: omp_if.then:			// CHECK1: omp_if.then:
	// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK1-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK1: omp_if.else:			// CHECK1: omp_if.else:
	// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
	// CHECK1-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK1-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54
	// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK1-NEXT: br label [[OMP_IF_END]]			// CHECK1-NEXT: br label [[OMP_IF_END]]
	// CHECK1: omp_if.end:			// CHECK1: omp_if.end:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !57
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57
	// CHECK1-NEXT: call void @_Z3fn3v()			// CHECK1-NEXT: call void @_Z3fn3v(), !llvm.access.group !57
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK2-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK2-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: store i32 0, i32* [[CONV]], align 8			// CHECK2-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !18
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !18
	// CHECK2-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK2-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !18
	// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: call void @_Z9gtid_testv()			// CHECK2-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: call void @_Z3fn4v()			// CHECK2-NEXT: call void @_Z3fn4v(), !llvm.access.group !27
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !30
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !30
	// CHECK2-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK2-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !30
	// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !30
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !30
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: call void @_Z3fn5v()			// CHECK2-NEXT: call void @_Z3fn5v(), !llvm.access.group !33
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !36
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK2: omp_if.then:			// CHECK2: omp_if.then:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !36
	// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK2: omp_if.else:			// CHECK2: omp_if.else:
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !36
	// CHECK2-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK2-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !36
	// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !36
	// CHECK2-NEXT: br label [[OMP_IF_END]]			// CHECK2-NEXT: br label [[OMP_IF_END]]
	// CHECK2: omp_if.end:			// CHECK2: omp_if.end:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: call void @_Z3fn6v()			// CHECK2-NEXT: call void @_Z3fn6v(), !llvm.access.group !39
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !39
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !42
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: call void @_Z3fn1v()			// CHECK2-NEXT: call void @_Z3fn1v(), !llvm.access.group !45
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !45
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !48
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !48
	// CHECK2-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK2-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !48
	// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !48
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !48
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !48
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !48
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !51
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !51
	// CHECK2-NEXT: call void @_Z3fn2v()			// CHECK2-NEXT: call void @_Z3fn2v(), !llvm.access.group !51
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !51
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK2-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK2: omp_if.then:			// CHECK2: omp_if.then:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK2: omp_if.else:			// CHECK2: omp_if.else:
	// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
	// CHECK2-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK2-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54
	// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK2-NEXT: br label [[OMP_IF_END]]			// CHECK2-NEXT: br label [[OMP_IF_END]]
	// CHECK2: omp_if.end:			// CHECK2: omp_if.end:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK2-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !57
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57
	// CHECK2-NEXT: call void @_Z3fn3v()			// CHECK2-NEXT: call void @_Z3fn3v(), !llvm.access.group !57
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !9, !llvm.access.group !8			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9
	// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK3-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK3-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK3-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !9, !llvm.access.group !13			// CHECK3-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !19
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !19
	// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK3-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !19
	// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !19
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK3-NEXT: call void @_Z9gtid_testv()			// CHECK3-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !22
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !25
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK3-NEXT: call void @_Z3fn4v()			// CHECK3-NEXT: call void @_Z3fn4v(), !llvm.access.group !28
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK3-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: call void @_Z3fn5v()			// CHECK3-NEXT: call void @_Z3fn5v()
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8			// CHECK3-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK3-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK3-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK3-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK3-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1			// CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK3-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK3-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then5:			// CHECK3: omp_if.then5:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
	// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]]			// CHECK3-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !34
	// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK3-NEXT: br label [[OMP_IF_END]]			// CHECK3-NEXT: br label [[OMP_IF_END]]
	// CHECK3: omp_if.end:			// CHECK3: omp_if.end:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_IF_END22:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END22:%.*]]
	// CHECK3: omp_if.else6:			// CHECK3: omp_if.else6:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]
	// CHECK3: omp.inner.for.cond7:			// CHECK3: omp.inner.for.cond7:
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	Show All 23 Lines
	// CHECK3-NEXT: br label [[OMP_IF_END18]]			// CHECK3-NEXT: br label [[OMP_IF_END18]]
	// CHECK3: omp_if.end18:			// CHECK3: omp_if.end18:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]
	// CHECK3: omp.inner.for.inc19:			// CHECK3: omp.inner.for.inc19:
	// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK3-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK3: omp.inner.for.end21:			// CHECK3: omp.inner.for.end21:
	// CHECK3-NEXT: br label [[OMP_IF_END22]]			// CHECK3-NEXT: br label [[OMP_IF_END22]]
	// CHECK3: omp_if.end22:			// CHECK3: omp_if.end22:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0			// CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
	▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !38
	// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
	// CHECK3-NEXT: call void @_Z3fn6v()			// CHECK3-NEXT: call void @_Z3fn6v(), !llvm.access.group !38
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK3-NEXT: call void @_Z3fn6v()			// CHECK3-NEXT: call void @_Z3fn6v()
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK3: omp.body.continue15:			// CHECK3: omp.body.continue15:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK3: omp.inner.for.inc16:			// CHECK3: omp.inner.for.inc16:
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK3-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK3-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK3: omp.inner.for.end18:			// CHECK3: omp.inner.for.end18:
	// CHECK3-NEXT: br label [[OMP_IF_END]]			// CHECK3-NEXT: br label [[OMP_IF_END]]
	// CHECK3: omp_if.end:			// CHECK3: omp_if.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !42
	// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !42
	// CHECK3-NEXT: call void @_Z3fn6v()			// CHECK3-NEXT: call void @_Z3fn6v(), !llvm.access.group !42
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK3-NEXT: call void @_Z3fn6v()			// CHECK3-NEXT: call void @_Z3fn6v()
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK3: omp.body.continue15:			// CHECK3: omp.body.continue15:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK3: omp.inner.for.inc16:			// CHECK3: omp.inner.for.inc16:
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK3-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK3-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP45:![0-9]+]]
	// CHECK3: omp.inner.for.end18:			// CHECK3: omp.inner.for.end18:
	// CHECK3-NEXT: br label [[OMP_IF_END]]			// CHECK3-NEXT: br label [[OMP_IF_END]]
	// CHECK3: omp_if.end:			// CHECK3: omp_if.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK3-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !46
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK3-NEXT: call void @_Z3fn1v()			// CHECK3-NEXT: call void @_Z3fn1v(), !llvm.access.group !49
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK3-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: call void @_Z3fn2v()			// CHECK3-NEXT: call void @_Z3fn2v()
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK3-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK3-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK3-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK3: omp_if.then:			// CHECK3: omp_if.then:
	// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK3-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK3: omp_if.else:			// CHECK3: omp_if.else:
	// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
	// CHECK3-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK3-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54
	// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK3-NEXT: br label [[OMP_IF_END]]			// CHECK3-NEXT: br label [[OMP_IF_END]]
	// CHECK3: omp_if.end:			// CHECK3: omp_if.end:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !57
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57
	// CHECK3-NEXT: call void @_Z3fn3v()			// CHECK3-NEXT: call void @_Z3fn3v(), !llvm.access.group !57
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !9, !llvm.access.group !8			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !10, !llvm.access.group !9
	// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK4-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK4-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK4-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !9
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK4-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !9, !llvm.access.group !13			// CHECK4-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !10, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !19
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !19
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !19
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !19
	// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK4-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !19
	// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !19
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !19
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK4-NEXT: call void @_Z9gtid_testv()			// CHECK4-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !22
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !25
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !25
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !25
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !25
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK4-NEXT: call void @_Z3fn4v()			// CHECK4-NEXT: call void @_Z3fn4v(), !llvm.access.group !28
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK4-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: call void @_Z3fn5v()			// CHECK4-NEXT: call void @_Z3fn5v()
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8			// CHECK4-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK4-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK4-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK4-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK4-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1			// CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK4-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !34
	// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK4-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then5:			// CHECK4: omp_if.then5:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !34
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
	// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]]			// CHECK4-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !34
	// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK4-NEXT: br label [[OMP_IF_END]]			// CHECK4-NEXT: br label [[OMP_IF_END]]
	// CHECK4: omp_if.end:			// CHECK4: omp_if.end:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_IF_END22:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END22:%.*]]
	// CHECK4: omp_if.else6:			// CHECK4: omp_if.else6:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]
	// CHECK4: omp.inner.for.cond7:			// CHECK4: omp.inner.for.cond7:
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	Show All 23 Lines
	// CHECK4-NEXT: br label [[OMP_IF_END18]]			// CHECK4-NEXT: br label [[OMP_IF_END18]]
	// CHECK4: omp_if.end18:			// CHECK4: omp_if.end18:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]
	// CHECK4: omp.inner.for.inc19:			// CHECK4: omp.inner.for.inc19:
	// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK4-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK4: omp.inner.for.end21:			// CHECK4: omp.inner.for.end21:
	// CHECK4-NEXT: br label [[OMP_IF_END22]]			// CHECK4-NEXT: br label [[OMP_IF_END22]]
	// CHECK4: omp_if.end22:			// CHECK4: omp_if.end22:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0			// CHECK4-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
	▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !38
	// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !38
	// CHECK4-NEXT: call void @_Z3fn6v()			// CHECK4-NEXT: call void @_Z3fn6v(), !llvm.access.group !38
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK4-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK4-NEXT: call void @_Z3fn6v()			// CHECK4-NEXT: call void @_Z3fn6v()
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK4: omp.body.continue15:			// CHECK4: omp.body.continue15:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK4: omp.inner.for.inc16:			// CHECK4: omp.inner.for.inc16:
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK4-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK4-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK4: omp.inner.for.end18:			// CHECK4: omp.inner.for.end18:
	// CHECK4-NEXT: br label [[OMP_IF_END]]			// CHECK4-NEXT: br label [[OMP_IF_END]]
	// CHECK4: omp_if.end:			// CHECK4: omp_if.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !42
	// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !42
	// CHECK4-NEXT: call void @_Z3fn6v()			// CHECK4-NEXT: call void @_Z3fn6v(), !llvm.access.group !42
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK4-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK4-NEXT: call void @_Z3fn6v()			// CHECK4-NEXT: call void @_Z3fn6v()
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK4: omp.body.continue15:			// CHECK4: omp.body.continue15:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK4: omp.inner.for.inc16:			// CHECK4: omp.inner.for.inc16:
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK4-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK4-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP45:![0-9]+]]
	// CHECK4: omp.inner.for.end18:			// CHECK4: omp.inner.for.end18:
	// CHECK4-NEXT: br label [[OMP_IF_END]]			// CHECK4-NEXT: br label [[OMP_IF_END]]
	// CHECK4: omp_if.end:			// CHECK4: omp_if.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK4-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !46
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK4-NEXT: call void @_Z3fn1v()			// CHECK4-NEXT: call void @_Z3fn1v(), !llvm.access.group !49
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK4-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: call void @_Z3fn2v()			// CHECK4-NEXT: call void @_Z3fn2v()
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK4-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK4-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK4-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK4-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !54
	// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK4: omp_if.then:			// CHECK4: omp_if.then:
	// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK4-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !54
	// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK4: omp_if.else:			// CHECK4: omp_if.else:
	// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !54
	// CHECK4-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK4-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !54
	// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !54
	// CHECK4-NEXT: br label [[OMP_IF_END]]			// CHECK4-NEXT: br label [[OMP_IF_END]]
	// CHECK4: omp_if.end:			// CHECK4: omp_if.end:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !54
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP55:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK4-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK4-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !57
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !57
	// CHECK4-NEXT: call void @_Z3fn3v()			// CHECK4-NEXT: call void @_Z3fn3v(), !llvm.access.group !57
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !57
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP58:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 1,288 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK9-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK9-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK9-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: store i32 0, i32* [[CONV]], align 8			// CHECK9-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !22
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !22
	// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK9-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !22
	// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !22
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: call void @_Z9gtid_testv()			// CHECK9-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !25
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: call void @_Z3fn4v()			// CHECK9-NEXT: call void @_Z3fn4v(), !llvm.access.group !31
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
	// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK9-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !34
	// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: call void @_Z3fn5v()			// CHECK9-NEXT: call void @_Z3fn5v(), !llvm.access.group !37
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !40
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK9: omp_if.then:			// CHECK9: omp_if.then:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK9: omp_if.else:			// CHECK9: omp_if.else:
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40
	// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK9-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !40
	// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
	// CHECK9-NEXT: br label [[OMP_IF_END]]			// CHECK9-NEXT: br label [[OMP_IF_END]]
	// CHECK9: omp_if.end:			// CHECK9: omp_if.end:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: call void @_Z3fn6v()			// CHECK9-NEXT: call void @_Z3fn6v(), !llvm.access.group !43
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !46
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: call void @_Z3fn1v()			// CHECK9-NEXT: call void @_Z3fn1v(), !llvm.access.group !49
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !52
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !52
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !52
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !52
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !52
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !52
	// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK9-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !52
	// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !52
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !52
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !52
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !52
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !55
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !55
	// CHECK9-NEXT: call void @_Z3fn2v()			// CHECK9-NEXT: call void @_Z3fn2v(), !llvm.access.group !55
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK9-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK9: omp_if.then:			// CHECK9: omp_if.then:
	// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK9-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK9-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK9: omp_if.else:			// CHECK9: omp_if.else:
	// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
	// CHECK9-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK9-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !58
	// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK9-NEXT: br label [[OMP_IF_END]]			// CHECK9-NEXT: br label [[OMP_IF_END]]
	// CHECK9: omp_if.end:			// CHECK9: omp_if.end:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK9-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !61
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !61
	// CHECK9-NEXT: call void @_Z3fn3v()			// CHECK9-NEXT: call void @_Z3fn3v(), !llvm.access.group !61
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP62:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK10-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK10-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK10-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: store i32 0, i32* [[CONV]], align 8			// CHECK10-NEXT: store i32 0, i32* [[CONV]], align 8, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !22
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !22
	// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK10-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !22
	// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !22
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: call void @_Z9gtid_testv()			// CHECK10-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !25
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !28
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: call void @_Z3fn4v()			// CHECK10-NEXT: call void @_Z3fn4v(), !llvm.access.group !31
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !31
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !34
	// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK10-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !34
	// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !34
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !34
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: call void @_Z3fn5v()			// CHECK10-NEXT: call void @_Z3fn5v(), !llvm.access.group !37
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !37
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !40
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK10: omp_if.then:			// CHECK10: omp_if.then:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !40
	// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK10: omp_if.else:			// CHECK10: omp_if.else:
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !40
	// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK10-NEXT: call void @.omp_outlined..9(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !40
	// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !40
	// CHECK10-NEXT: br label [[OMP_IF_END]]			// CHECK10-NEXT: br label [[OMP_IF_END]]
	// CHECK10: omp_if.end:			// CHECK10: omp_if.end:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !40
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: call void @_Z3fn6v()			// CHECK10-NEXT: call void @_Z3fn6v(), !llvm.access.group !43
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !43
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..13 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !46
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: call void @_Z3fn1v()			// CHECK10-NEXT: call void @_Z3fn1v(), !llvm.access.group !49
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !49
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !52
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !52
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !52
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !52
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !52
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !52
	// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK10-NEXT: call void @.omp_outlined..15(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !52
	// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !52
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !52
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !52
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !52
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !55
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !55
	// CHECK10-NEXT: call void @_Z3fn2v()			// CHECK10-NEXT: call void @_Z3fn2v(), !llvm.access.group !55
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !55
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK10-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK10: omp_if.then:			// CHECK10: omp_if.then:
	// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK10-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..17 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK10-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK10: omp_if.else:			// CHECK10: omp_if.else:
	// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
	// CHECK10-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK10-NEXT: call void @.omp_outlined..17(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !58
	// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK10-NEXT: br label [[OMP_IF_END]]			// CHECK10-NEXT: br label [[OMP_IF_END]]
	// CHECK10: omp_if.end:			// CHECK10: omp_if.end:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK10-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !61
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !61
	// CHECK10-NEXT: call void @_Z3fn3v()			// CHECK10-NEXT: call void @_Z3fn3v(), !llvm.access.group !61
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP62:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !13, !llvm.access.group !12			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13
	// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK11-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK11-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK11-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK11-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK11-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !13, !llvm.access.group !17			// CHECK11-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !23
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !23
	// CHECK11-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK11-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !23
	// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !23
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: call void @_Z9gtid_testv()			// CHECK11-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !26
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !29
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK11-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !32
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
	// CHECK11-NEXT: call void @_Z3fn4v()			// CHECK11-NEXT: call void @_Z3fn4v(), !llvm.access.group !32
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK11-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: call void @_Z3fn5v()			// CHECK11-NEXT: call void @_Z3fn5v()
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8			// CHECK11-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK11-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK11-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK11-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8			// CHECK11-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK11-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK11-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK11-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK11-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1			// CHECK11-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK11-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8			// CHECK11-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK11-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then5:			// CHECK11: omp_if.then5:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
	// CHECK11-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]]			// CHECK11-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !38
	// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK11-NEXT: br label [[OMP_IF_END]]			// CHECK11-NEXT: br label [[OMP_IF_END]]
	// CHECK11: omp_if.end:			// CHECK11: omp_if.end:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_IF_END22:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END22:%.*]]
	// CHECK11: omp_if.else6:			// CHECK11: omp_if.else6:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]
	// CHECK11: omp.inner.for.cond7:			// CHECK11: omp.inner.for.cond7:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK11-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	Show All 23 Lines
	// CHECK11-NEXT: br label [[OMP_IF_END18]]			// CHECK11-NEXT: br label [[OMP_IF_END18]]
	// CHECK11: omp_if.end18:			// CHECK11: omp_if.end18:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]
	// CHECK11: omp.inner.for.inc19:			// CHECK11: omp.inner.for.inc19:
	// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK11-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK11: omp.inner.for.end21:			// CHECK11: omp.inner.for.end21:
	// CHECK11-NEXT: br label [[OMP_IF_END22]]			// CHECK11-NEXT: br label [[OMP_IF_END22]]
	// CHECK11: omp_if.end22:			// CHECK11: omp_if.end22:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0			// CHECK11-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
	▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !42
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !42
	// CHECK11-NEXT: call void @_Z3fn6v()			// CHECK11-NEXT: call void @_Z3fn6v(), !llvm.access.group !42
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK11-NEXT: call void @_Z3fn6v()			// CHECK11-NEXT: call void @_Z3fn6v()
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK11: omp.body.continue15:			// CHECK11: omp.body.continue15:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK11: omp.inner.for.inc16:			// CHECK11: omp.inner.for.inc16:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP45:![0-9]+]]
	// CHECK11: omp.inner.for.end18:			// CHECK11: omp.inner.for.end18:
	// CHECK11-NEXT: br label [[OMP_IF_END]]			// CHECK11-NEXT: br label [[OMP_IF_END]]
	// CHECK11: omp_if.end:			// CHECK11: omp_if.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !46
	// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !46
	// CHECK11-NEXT: call void @_Z3fn6v()			// CHECK11-NEXT: call void @_Z3fn6v(), !llvm.access.group !46
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK11-NEXT: call void @_Z3fn6v()			// CHECK11-NEXT: call void @_Z3fn6v()
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK11: omp.body.continue15:			// CHECK11: omp.body.continue15:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK11: omp.inner.for.inc16:			// CHECK11: omp.inner.for.inc16:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP30:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK11: omp.inner.for.end18:			// CHECK11: omp.inner.for.end18:
	// CHECK11-NEXT: br label [[OMP_IF_END]]			// CHECK11-NEXT: br label [[OMP_IF_END]]
	// CHECK11: omp_if.end:			// CHECK11: omp_if.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !50
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !50
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !50
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !50
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !50
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK11-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK11-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !53
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !53
	// CHECK11-NEXT: call void @_Z3fn1v()			// CHECK11-NEXT: call void @_Z3fn1v(), !llvm.access.group !53
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP54:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK11-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: call void @_Z3fn2v()			// CHECK11-NEXT: call void @_Z3fn2v()
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP57:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK11-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK11-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK11-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK11-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK11: omp_if.then:			// CHECK11: omp_if.then:
	// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK11-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK11-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK11: omp_if.else:			// CHECK11: omp_if.else:
	// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
	// CHECK11-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK11-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !58
	// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK11-NEXT: br label [[OMP_IF_END]]			// CHECK11-NEXT: br label [[OMP_IF_END]]
	// CHECK11: omp_if.end:			// CHECK11: omp_if.end:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK11-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK11-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !61
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !61
	// CHECK11-NEXT: call void @_Z3fn3v()			// CHECK11-NEXT: call void @_Z3fn3v(), !llvm.access.group !61
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP62:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !13, !llvm.access.group !12			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[CONV]], align 8, !nontemporal !14, !llvm.access.group !13
	// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*			// CHECK12-NEXT: [[CONV2:%.]] = bitcast i64 [[ARG_CASTED]] to i32*
	// CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4			// CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8			// CHECK12-NEXT: [[TMP12:%.]] = load i64, i64 [[ARG_CASTED]], align 8, !llvm.access.group !13
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..1 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group !13
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK12-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK12-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !13, !llvm.access.group !17			// CHECK12-NEXT: store i32 0, i32* [[CONV]], align 8, !nontemporal !14, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !23
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !23
	// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK12-NEXT: call void @.omp_outlined..3(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !23
	// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !23
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: call void @_Z9gtid_testv()			// CHECK12-NEXT: call void @_Z9gtid_testv(), !llvm.access.group !26
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..5 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !29
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !29
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK12-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !32
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !32
	// CHECK12-NEXT: call void @_Z3fn4v()			// CHECK12-NEXT: call void @_Z3fn4v(), !llvm.access.group !32
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK12-NEXT: call void @.omp_outlined..7(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: call void @_Z3fn5v()			// CHECK12-NEXT: call void @_Z3fn5v()
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8			// CHECK12-NEXT: [[TMP5:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE6:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64			// CHECK12-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64			// CHECK12-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
	// CHECK12-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8			// CHECK12-NEXT: [[TMP12:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1			// CHECK12-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP12]] to i1
	// CHECK12-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*			// CHECK12-NEXT: [[CONV3:%.]] = bitcast i64 [[DOTCAPTURE_EXPR__CASTED]] to i8*
	// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8			// CHECK12-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL2]] to i8
	// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1			// CHECK12-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8			// CHECK12-NEXT: [[TMP13:%.]] = load i64, i64 [[DOTCAPTURE_EXPR__CASTED]], align 8, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8			// CHECK12-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !38
	// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK12-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN5:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then5:			// CHECK12: omp_if.then5:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 3, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64, i64)* @.omp_outlined..9 to void (i32, i32, ...)*), i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group !38
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !38
	// CHECK12-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]]			// CHECK12-NEXT: call void @.omp_outlined..9(i32* [[TMP15]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]]) #[[ATTR2]], !llvm.access.group !38
	// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !38
	// CHECK12-NEXT: br label [[OMP_IF_END]]			// CHECK12-NEXT: br label [[OMP_IF_END]]
	// CHECK12: omp_if.end:			// CHECK12: omp_if.end:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !38
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_IF_END22:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END22:%.*]]
	// CHECK12: omp_if.else6:			// CHECK12: omp_if.else6:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND7:%.*]]
	// CHECK12: omp.inner.for.cond7:			// CHECK12: omp.inner.for.cond7:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK12-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	Show All 23 Lines
	// CHECK12-NEXT: br label [[OMP_IF_END18]]			// CHECK12-NEXT: br label [[OMP_IF_END18]]
	// CHECK12: omp_if.end18:			// CHECK12: omp_if.end18:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]
	// CHECK12: omp.inner.for.inc19:			// CHECK12: omp.inner.for.inc19:
	// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP29:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]			// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
	// CHECK12-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD20]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP26:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND7]], !llvm.loop [[LOOP41:![0-9]+]]
	// CHECK12: omp.inner.for.end21:			// CHECK12: omp.inner.for.end21:
	// CHECK12-NEXT: br label [[OMP_IF_END22]]			// CHECK12-NEXT: br label [[OMP_IF_END22]]
	// CHECK12: omp_if.end22:			// CHECK12: omp_if.end22:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP30:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0			// CHECK12-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
	▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !42
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !42
	// CHECK12-NEXT: call void @_Z3fn6v()			// CHECK12-NEXT: call void @_Z3fn6v(), !llvm.access.group !42
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !42
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK12-NEXT: call void @_Z3fn6v()			// CHECK12-NEXT: call void @_Z3fn6v()
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK12: omp.body.continue15:			// CHECK12: omp.body.continue15:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK12: omp.inner.for.inc16:			// CHECK12: omp.inner.for.inc16:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP28:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP45:![0-9]+]]
	// CHECK12: omp.inner.for.end18:			// CHECK12: omp.inner.for.end18:
	// CHECK12-NEXT: br label [[OMP_IF_END]]			// CHECK12-NEXT: br label [[OMP_IF_END]]
	// CHECK12: omp_if.end:			// CHECK12: omp_if.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !46
	// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK12-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !46
	// CHECK12-NEXT: call void @_Z3fn6v()			// CHECK12-NEXT: call void @_Z3fn6v(), !llvm.access.group !46
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !46
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[TMP12]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)			// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP14]], 99
	Show All 22 Lines
	// CHECK12-NEXT: call void @_Z3fn6v()			// CHECK12-NEXT: call void @_Z3fn6v()
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK12: omp.body.continue15:			// CHECK12: omp.body.continue15:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK12: omp.inner.for.inc16:			// CHECK12: omp.inner.for.inc16:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP30:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP49:![0-9]+]]
	// CHECK12: omp.inner.for.end18:			// CHECK12: omp.inner.for.end18:
	// CHECK12-NEXT: br label [[OMP_IF_END]]			// CHECK12-NEXT: br label [[OMP_IF_END]]
	// CHECK12: omp_if.end:			// CHECK12: omp_if.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[TMP21]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]])
	▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !50
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !50
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !50
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..14 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !50
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !50
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !50
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !50
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP51:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0			// CHECK12-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
	// CHECK12-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !53
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !53
	// CHECK12-NEXT: call void @_Z3fn1v()			// CHECK12-NEXT: call void @_Z3fn1v(), !llvm.access.group !53
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !53
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP54:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK12-NEXT: call void @.omp_outlined..16(i32* [[TMP11]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]
	// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP56:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0			// CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
	// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: call void @_Z3fn2v()			// CHECK12-NEXT: call void @_Z3fn2v()
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP57:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4
	// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP4:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_COMB_LB]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64			// CHECK12-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_COMB_UB]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64			// CHECK12-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
	// CHECK12-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8			// CHECK12-NEXT: [[TMP11:%.]] = load i8, i8 [[CONV]], align 8, !llvm.access.group !58
	// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1			// CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1
	// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK12: omp_if.then:			// CHECK12: omp_if.then:
	// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]])			// CHECK12-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32, i32, ...)* bitcast (void (i32, i32, i64, i64)* @.omp_outlined..18 to void (i32, i32, ...)*), i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group !58
	// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK12-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK12: omp_if.else:			// CHECK12: omp_if.else:
	// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group !58
	// CHECK12-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]]			// CHECK12-NEXT: call void @.omp_outlined..18(i32* [[TMP12]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]], !llvm.access.group !58
	// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB3]], i32 [[TMP1]]), !llvm.access.group !58
	// CHECK12-NEXT: br label [[OMP_IF_END]]			// CHECK12-NEXT: br label [[OMP_IF_END]]
	// CHECK12: omp_if.end:			// CHECK12: omp_if.end:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !58
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP59:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK12-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK12-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !61
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !61
	// CHECK12-NEXT: call void @_Z3fn3v()			// CHECK12-NEXT: call void @_Z3fn3v(), !llvm.access.group !61
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !61
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP62:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 1,198 Lines • Show Last 20 Lines

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp

This file has a very large number of changes (4,960 lines). Show File Contents

clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp

This file has a very large number of changes (3,256 lines). Show File Contents

clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 831 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK9-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK9-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !26			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 337 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK10-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[I5]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK10-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !26			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP16]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP1]], i32 [[TMP19]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP20]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,260 Lines • Show Last 20 Lines

clang/test/OpenMP/task_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i32 15, i32* @a, align 4			// CHECK1-NEXT: store i32 15, i32* @a, align 4
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4
	// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8			// CHECK1-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8
	// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0			// CHECK1-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8			// CHECK1-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8
	// CHECK1-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1			// CHECK1-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8
	Show All 19 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !22
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !22
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !22
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !22
	// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK1-NEXT: store i32 15, i32* @a, align 4			// CHECK1-NEXT: store i32 15, i32* @a, align 4
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8			// CHECK1-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1
	// CHECK1-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0			// CHECK1-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0
	// CHECK1-NEXT: store i32 10, i32* [[A_I]], align 4			// CHECK1-NEXT: store i32 10, i32* [[A_I]], align 4
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	Show All 15 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK1-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK1-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK1-NEXT: ]			// CHECK1-NEXT: ]
	// CHECK1: .untied.done..i:			// CHECK1: .untied.done..i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK1: .untied.jmp..i:			// CHECK1: .untied.jmp..i:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK1-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK1-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
	// CHECK1: .untied.jmp.1.i:			// CHECK1: .untied.jmp.1.i:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK1-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK1-NEXT: store i32 1, i32* @a, align 4			// CHECK1-NEXT: store i32 1, i32* @a, align 4
	// CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK1-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK1-NEXT: br label [[CLEANUP_I]]			// CHECK1-NEXT: br label [[CLEANUP_I]]
	// CHECK1: cleanup.i:			// CHECK1: cleanup.i:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK1: .omp_outlined..3.exit:			// CHECK1: .omp_outlined..3.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..6			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..6
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 11 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !41			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !42
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK1-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK1-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK1-NEXT: ]			// CHECK1-NEXT: ]
	// CHECK1: .untied.done..i:			// CHECK1: .untied.done..i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK1: .untied.jmp..i:			// CHECK1: .untied.jmp..i:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !41			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !42
	// CHECK1-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK1-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]
	// CHECK1: .untied.jmp.1.i:			// CHECK1: .untied.jmp.1.i:
	// CHECK1-NEXT: store i32 1, i32* @a, align 4			// CHECK1-NEXT: store i32 1, i32* @a, align 4
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK1-NEXT: br label [[CLEANUP_I]]			// CHECK1-NEXT: br label [[CLEANUP_I]]
	// CHECK1: cleanup.i:			// CHECK1: cleanup.i:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]
	// CHECK1: .omp_outlined..5.exit:			// CHECK1: .omp_outlined..5.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..8			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..8
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 11 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK1-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK1-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK1-NEXT: ]			// CHECK1-NEXT: ]
	// CHECK1: .untied.done..i:			// CHECK1: .untied.done..i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK1: .untied.jmp..i:			// CHECK1: .untied.jmp..i:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK1-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK1-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK1-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]
	// CHECK1: .untied.jmp.1.i:			// CHECK1: .untied.jmp.1.i:
	// CHECK1-NEXT: store i32 1, i32* @a, align 4			// CHECK1-NEXT: store i32 1, i32* @a, align 4
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[CLEANUP_I]]			// CHECK1-NEXT: br label [[CLEANUP_I]]
	// CHECK1: cleanup.i:			// CHECK1: cleanup.i:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]
	// CHECK1: .omp_outlined..7.exit:			// CHECK1: .omp_outlined..7.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..10			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..10
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	Show All 10 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !61			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !62
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK1-NEXT: store i32 2, i32* @a, align 4			// CHECK1-NEXT: store i32 2, i32* @a, align 4
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..12			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..12
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !71			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !72
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !71			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !72
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !71			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !72
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !71			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !72
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !71			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !72
	// CHECK1-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK1-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK1-NEXT: store i32 2, i32* @a, align 4			// CHECK1-NEXT: store i32 2, i32* @a, align 4
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..14			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..14
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !81			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !82
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !81			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !82
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !81			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !82
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !81			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !82
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !81			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !82
	// CHECK1-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK1-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK1-NEXT: store i32 3, i32* @a, align 4			// CHECK1-NEXT: store i32 3, i32* @a, align 4
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..16			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..16
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !91			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !92
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !91			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !92
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !91			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !92
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !91			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !92
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !91			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !92
	// CHECK1-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK1-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK1-NEXT: store i32 4, i32* @a, align 4			// CHECK1-NEXT: store i32 4, i32* @a, align 4
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8
	// CHECK1-NEXT: store i32 5, i32* [[TMP12]], align 128			// CHECK1-NEXT: store i32 5, i32* [[TMP12]], align 128
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
	Show All 29 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !101			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !102
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !101			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !102
	// CHECK1-NEXT: store i32 4, i32* [[TMP16]], align 128			// CHECK1-NEXT: store i32 4, i32* [[TMP16]], align 128
	// CHECK1-NEXT: store i32 4, i32* @a, align 4			// CHECK1-NEXT: store i32 4, i32* @a, align 4
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev			// CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev
	// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S*) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S*) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S*** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S*** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP19:%.]] = load %struct.S, %struct.S** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load %struct.S, %struct.S** [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK1-NEXT: switch i32 [[TMP21]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK1-NEXT: switch i32 [[TMP21]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]			// CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]
	// CHECK1-NEXT: i32 2, label [[DOTUNTIED_JMP_3_I:%.*]]			// CHECK1-NEXT: i32 2, label [[DOTUNTIED_JMP_3_I:%.*]]
	// CHECK1-NEXT: i32 3, label [[DOTUNTIED_JMP_5_I:%.*]]			// CHECK1-NEXT: i32 3, label [[DOTUNTIED_JMP_5_I:%.*]]
	// CHECK1-NEXT: i32 4, label [[DOTUNTIED_JMP_7_I:%.*]]			// CHECK1-NEXT: i32 4, label [[DOTUNTIED_JMP_7_I:%.*]]
	// CHECK1-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]]			// CHECK1-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]]
	// CHECK1-NEXT: ]			// CHECK1-NEXT: ]
	// CHECK1: .untied.done..i:			// CHECK1: .untied.done..i:
	// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK1-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK1-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK1: .untied.jmp..i:			// CHECK1: .untied.jmp..i:
	// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store i32 1, i32* [[TMP22]], align 4			// CHECK1-NEXT: store i32 1, i32* [[TMP22]], align 4
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP25:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP23]], i8* [[TMP24]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP25:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP23]], i8* [[TMP24]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]
	// CHECK1: .untied.jmp.2.i:			// CHECK1: .untied.jmp.2.i:
	// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]			// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[DOTS2__VOID_ADDR_I:%.]] = call i8 @__kmpc_alloc(i32 [[TMP26]], i64 4, i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]			// CHECK1-NEXT: [[DOTS2__VOID_ADDR_I:%.]] = call i8 @__kmpc_alloc(i32 [[TMP26]], i64 4, i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]
	// CHECK1-NEXT: [[DOTS2__ADDR_I:%.]] = bitcast i8 [[DOTS2__VOID_ADDR_I]] to %struct.S*			// CHECK1-NEXT: [[DOTS2__ADDR_I:%.]] = bitcast i8 [[DOTS2__VOID_ADDR_I]] to %struct.S*
	// CHECK1-NEXT: store %struct.S* [[DOTS2__ADDR_I]], %struct.S** [[TMP18]], align 8			// CHECK1-NEXT: store %struct.S* [[DOTS2__ADDR_I]], %struct.S** [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store i32 2, i32* [[TMP27]], align 4			// CHECK1-NEXT: store i32 2, i32* [[TMP27]], align 4
	// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i8* [[TMP29]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i8* [[TMP29]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK1: .untied.jmp.3.i:			// CHECK1: .untied.jmp.3.i:
	// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]			// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]
	// CHECK1-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0			// CHECK1-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0
	// CHECK1-NEXT: store i32 0, i32* [[A_I]], align 4			// CHECK1-NEXT: store i32 0, i32* [[A_I]], align 4
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP32:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]			// CHECK1-NEXT: [[TMP32:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP33:%.]] = bitcast i8 [[TMP32]] to %struct.kmp_task_t_with_privates.18*			// CHECK1-NEXT: [[TMP33:%.]] = bitcast i8 [[TMP32]] to %struct.kmp_task_t_with_privates.18*
	// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP33]], i32 0, i32 0			// CHECK1-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP33]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP33]], i32 0, i32 2			// CHECK1-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP33]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP35]], i32 0, i32 0			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP35]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP16]], align 128			// CHECK1-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP16]], align 128
	// CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 128			// CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 128
	// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP39:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP38]], i8* [[TMP32]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP39:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP38]], i8* [[TMP32]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP40:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP40:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store i32 3, i32* [[TMP40]], align 4			// CHECK1-NEXT: store i32 3, i32* [[TMP40]], align 4
	// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP41]], i8* [[TMP42]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP41]], i8* [[TMP42]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK1: .untied.jmp.5.i:			// CHECK1: .untied.jmp.5.i:
	// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP45:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[TMP44]], i32 0) #[[ATTR4]]			// CHECK1-NEXT: [[TMP45:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[TMP44]], i32 0) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store i32 4, i32* [[TMP46]], align 4			// CHECK1-NEXT: store i32 4, i32* [[TMP46]], align 4
	// CHECK1-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP48:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP48:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP49:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP47]], i8* [[TMP48]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP49:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP47]], i8* [[TMP48]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK1: .untied.jmp.7.i:			// CHECK1: .untied.jmp.7.i:
	// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP50:%.]] = bitcast %struct.S [[TMP17]] to i8*			// CHECK1-NEXT: [[TMP50:%.]] = bitcast %struct.S [[TMP17]] to i8*
	// CHECK1-NEXT: [[TMP51:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*			// CHECK1-NEXT: [[TMP51:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*
	// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i64 4, i1 false) #[[ATTR4]]			// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i64 4, i1 false) #[[ATTR4]]
	// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[A9_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0			// CHECK1-NEXT: [[A9_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0
	// CHECK1-NEXT: store i32 10, i32* [[A9_I]], align 4			// CHECK1-NEXT: store i32 10, i32* [[A9_I]], align 4
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP53:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[TMP52]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP53:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[TMP52]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP54:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: store i32 5, i32* [[TMP54]], align 4			// CHECK1-NEXT: store i32 5, i32* [[TMP54]], align 4
	// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP56:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK1-NEXT: [[TMP56:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK1-NEXT: [[TMP57:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP55]], i8* [[TMP56]]) #[[ATTR4]]			// CHECK1-NEXT: [[TMP57:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP55]], i8* [[TMP56]]) #[[ATTR4]]
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK1: .untied.jmp.10.i:			// CHECK1: .untied.jmp.10.i:
	// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]			// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK1-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK1-NEXT: [[TMP59:%.]] = bitcast %struct.S [[TMP19]] to i8*			// CHECK1-NEXT: [[TMP59:%.]] = bitcast %struct.S [[TMP19]] to i8*
	// CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP58]], i8* [[TMP59]], i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]			// CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP58]], i8* [[TMP59]], i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]
	// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]			// CHECK1-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]
	// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK1-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK1-NEXT: br label [[CLEANUP_I]]			// CHECK1-NEXT: br label [[CLEANUP_I]]
	// CHECK1: cleanup.i:			// CHECK1: cleanup.i:
	// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK1-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK1: .omp_outlined..17.exit:			// CHECK1: .omp_outlined..17.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META117:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META119:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !121			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !122
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !121			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !122
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !121			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !122
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !121			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !122
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !121			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !122
	// CHECK1-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK1-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8
	// CHECK1-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0			// CHECK1-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0
	// CHECK1-NEXT: store i32 0, i32* [[A_I]], align 4			// CHECK1-NEXT: store i32 0, i32* [[A_I]], align 4
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_Z4xxxxv			// CHECK1-LABEL: define {{[^@]+}}@_Z4xxxxv
	▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.]], %struct.kmp_task_t_with_privates.24* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.]], %struct.kmp_task_t_with_privates.24* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.23*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.23*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], %struct.kmp_task_t_with_privates.24 [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], %struct.kmp_task_t_with_privates.24 [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.25 [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.25 [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.24 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.24 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META127:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META129:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !131			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !132
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.25, double) @.omp_task_privates_map..26 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.25, double) @.omp_task_privates_map..26 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: store %struct.anon.23* [[TMP8]], %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: store %struct.anon.23* [[TMP8]], %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon.23, %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon.23, %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, double)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, double)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]
	// CHECK1-NEXT: [[TMP16:%.]] = load double, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !131			// CHECK1-NEXT: [[TMP16:%.]] = load double, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !132
	// CHECK1-NEXT: [[TMP17:%.]] = load double, double [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load double, double [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_ANON_23:%.]], %struct.anon.23* [[TMP12]], i32 0, i32 0			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_ANON_23:%.]], %struct.anon.23* [[TMP12]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP19:%.]] = load float, float** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load float, float** [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load float, float [[TMP19]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load float, float [[TMP19]], align 4
	// CHECK1-NEXT: [[CONV_I:%.*]] = fpext float [[TMP20]] to double			// CHECK1-NEXT: [[CONV_I:%.*]] = fpext float [[TMP20]] to double
	// CHECK1-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP17]]			// CHECK1-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP17]]
	// CHECK1-NEXT: [[CONV1_I:%.*]] = fptrunc double [[ADD_I]] to float			// CHECK1-NEXT: [[CONV1_I:%.*]] = fptrunc double [[ADD_I]] to float
	// CHECK1-NEXT: store float [[CONV1_I]], float* [[TMP19]], align 4			// CHECK1-NEXT: store float [[CONV1_I]], float* [[TMP19]], align 4
	▲ Show 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i32 15, i32* @a, align 4			// CHECK2-NEXT: store i32 15, i32* @a, align 4
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4
	// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8			// CHECK2-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8
	// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0			// CHECK2-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8			// CHECK2-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8
	// CHECK2-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1			// CHECK2-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8
	Show All 19 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !22
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !22
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !22
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !22
	// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK2-NEXT: store i32 15, i32* @a, align 4			// CHECK2-NEXT: store i32 15, i32* @a, align 4
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8			// CHECK2-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1
	// CHECK2-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0			// CHECK2-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0
	// CHECK2-NEXT: store i32 10, i32* [[A_I]], align 4			// CHECK2-NEXT: store i32 10, i32* [[A_I]], align 4
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	Show All 15 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK2-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK2-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK2-NEXT: ]			// CHECK2-NEXT: ]
	// CHECK2: .untied.done..i:			// CHECK2: .untied.done..i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK2: .untied.jmp..i:			// CHECK2: .untied.jmp..i:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK2-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK2-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK2-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
	// CHECK2: .untied.jmp.1.i:			// CHECK2: .untied.jmp.1.i:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK2-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK2-NEXT: store i32 1, i32* @a, align 4			// CHECK2-NEXT: store i32 1, i32* @a, align 4
	// CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK2-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK2-NEXT: br label [[CLEANUP_I]]			// CHECK2-NEXT: br label [[CLEANUP_I]]
	// CHECK2: cleanup.i:			// CHECK2: cleanup.i:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK2: .omp_outlined..3.exit:			// CHECK2: .omp_outlined..3.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..6			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..6
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 11 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !41			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !42
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK2-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK2-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK2-NEXT: ]			// CHECK2-NEXT: ]
	// CHECK2: .untied.done..i:			// CHECK2: .untied.done..i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK2: .untied.jmp..i:			// CHECK2: .untied.jmp..i:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK2-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !41			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !42
	// CHECK2-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK2-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]
	// CHECK2: .untied.jmp.1.i:			// CHECK2: .untied.jmp.1.i:
	// CHECK2-NEXT: store i32 1, i32* @a, align 4			// CHECK2-NEXT: store i32 1, i32* @a, align 4
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK2-NEXT: br label [[CLEANUP_I]]			// CHECK2-NEXT: br label [[CLEANUP_I]]
	// CHECK2: cleanup.i:			// CHECK2: cleanup.i:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]
	// CHECK2: .omp_outlined..5.exit:			// CHECK2: .omp_outlined..5.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..8			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..8
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 11 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK2-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK2-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK2-NEXT: ]			// CHECK2-NEXT: ]
	// CHECK2: .untied.done..i:			// CHECK2: .untied.done..i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK2: .untied.jmp..i:			// CHECK2: .untied.jmp..i:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK2-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK2-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK2-NEXT: [[TMP15:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP16:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP14]], i8* [[TMP15]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]
	// CHECK2: .untied.jmp.1.i:			// CHECK2: .untied.jmp.1.i:
	// CHECK2-NEXT: store i32 1, i32* @a, align 4			// CHECK2-NEXT: store i32 1, i32* @a, align 4
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[CLEANUP_I]]			// CHECK2-NEXT: br label [[CLEANUP_I]]
	// CHECK2: cleanup.i:			// CHECK2: cleanup.i:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]
	// CHECK2: .omp_outlined..7.exit:			// CHECK2: .omp_outlined..7.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..10			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..10
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 10 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !61			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !62
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK2-NEXT: store i32 2, i32* @a, align 4			// CHECK2-NEXT: store i32 2, i32* @a, align 4
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..12			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..12
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !71			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !72
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !71			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !72
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !71			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !72
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !71			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !72
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !71			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !72
	// CHECK2-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK2-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK2-NEXT: store i32 2, i32* @a, align 4			// CHECK2-NEXT: store i32 2, i32* @a, align 4
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..14			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..14
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !81			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !82
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !81			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !82
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !81			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !82
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !81			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !82
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !81			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !82
	// CHECK2-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK2-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK2-NEXT: store i32 3, i32* @a, align 4			// CHECK2-NEXT: store i32 3, i32* @a, align 4
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..16			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..16
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !91			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !92
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !91			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !92
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !91			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !92
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !91			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !92
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !91			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !92
	// CHECK2-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK2-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK2-NEXT: store i32 4, i32* @a, align 4			// CHECK2-NEXT: store i32 4, i32* @a, align 4
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8
	// CHECK2-NEXT: store i32 5, i32* [[TMP12]], align 128			// CHECK2-NEXT: store i32 5, i32* [[TMP12]], align 128
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
	Show All 29 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !101			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !102
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !101			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !102
	// CHECK2-NEXT: store i32 4, i32* [[TMP16]], align 128			// CHECK2-NEXT: store i32 4, i32* [[TMP16]], align 128
	// CHECK2-NEXT: store i32 4, i32* @a, align 4			// CHECK2-NEXT: store i32 4, i32* @a, align 4
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev			// CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev
	// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S*) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S*) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S*** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S*** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP19:%.]] = load %struct.S, %struct.S** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load %struct.S, %struct.S** [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[TMP20]], align 4
	// CHECK2-NEXT: switch i32 [[TMP21]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK2-NEXT: switch i32 [[TMP21]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]			// CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]
	// CHECK2-NEXT: i32 2, label [[DOTUNTIED_JMP_3_I:%.*]]			// CHECK2-NEXT: i32 2, label [[DOTUNTIED_JMP_3_I:%.*]]
	// CHECK2-NEXT: i32 3, label [[DOTUNTIED_JMP_5_I:%.*]]			// CHECK2-NEXT: i32 3, label [[DOTUNTIED_JMP_5_I:%.*]]
	// CHECK2-NEXT: i32 4, label [[DOTUNTIED_JMP_7_I:%.*]]			// CHECK2-NEXT: i32 4, label [[DOTUNTIED_JMP_7_I:%.*]]
	// CHECK2-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]]			// CHECK2-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]]
	// CHECK2-NEXT: ]			// CHECK2-NEXT: ]
	// CHECK2: .untied.done..i:			// CHECK2: .untied.done..i:
	// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK2-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK2-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK2: .untied.jmp..i:			// CHECK2: .untied.jmp..i:
	// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP22:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store i32 1, i32* [[TMP22]], align 4			// CHECK2-NEXT: store i32 1, i32* [[TMP22]], align 4
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP25:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP23]], i8* [[TMP24]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP25:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP23]], i8* [[TMP24]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]
	// CHECK2: .untied.jmp.2.i:			// CHECK2: .untied.jmp.2.i:
	// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]			// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP26:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[DOTS2__VOID_ADDR_I:%.]] = call i8 @__kmpc_alloc(i32 [[TMP26]], i64 4, i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]			// CHECK2-NEXT: [[DOTS2__VOID_ADDR_I:%.]] = call i8 @__kmpc_alloc(i32 [[TMP26]], i64 4, i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]
	// CHECK2-NEXT: [[DOTS2__ADDR_I:%.]] = bitcast i8 [[DOTS2__VOID_ADDR_I]] to %struct.S*			// CHECK2-NEXT: [[DOTS2__ADDR_I:%.]] = bitcast i8 [[DOTS2__VOID_ADDR_I]] to %struct.S*
	// CHECK2-NEXT: store %struct.S* [[DOTS2__ADDR_I]], %struct.S** [[TMP18]], align 8			// CHECK2-NEXT: store %struct.S* [[DOTS2__ADDR_I]], %struct.S** [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store i32 2, i32* [[TMP27]], align 4			// CHECK2-NEXT: store i32 2, i32* [[TMP27]], align 4
	// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP28:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i8* [[TMP29]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP28]], i8* [[TMP29]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK2: .untied.jmp.3.i:			// CHECK2: .untied.jmp.3.i:
	// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]			// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]
	// CHECK2-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0			// CHECK2-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0
	// CHECK2-NEXT: store i32 0, i32* [[A_I]], align 4			// CHECK2-NEXT: store i32 0, i32* [[A_I]], align 4
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP32:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]			// CHECK2-NEXT: [[TMP32:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP33:%.]] = bitcast i8 [[TMP32]] to %struct.kmp_task_t_with_privates.18*			// CHECK2-NEXT: [[TMP33:%.]] = bitcast i8 [[TMP32]] to %struct.kmp_task_t_with_privates.18*
	// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP33]], i32 0, i32 0			// CHECK2-NEXT: [[TMP34:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP33]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP33]], i32 0, i32 2			// CHECK2-NEXT: [[TMP35:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP33]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP35]], i32 0, i32 0			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP35]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP16]], align 128			// CHECK2-NEXT: [[TMP37:%.]] = load i32, i32 [[TMP16]], align 128
	// CHECK2-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 128			// CHECK2-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 128
	// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP38:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP39:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP38]], i8* [[TMP32]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP39:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP38]], i8* [[TMP32]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP40:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP40:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store i32 3, i32* [[TMP40]], align 4			// CHECK2-NEXT: store i32 3, i32* [[TMP40]], align 4
	// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP41:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP41]], i8* [[TMP42]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP41]], i8* [[TMP42]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK2: .untied.jmp.5.i:			// CHECK2: .untied.jmp.5.i:
	// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP44:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP45:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[TMP44]], i32 0) #[[ATTR4]]			// CHECK2-NEXT: [[TMP45:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[TMP44]], i32 0) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store i32 4, i32* [[TMP46]], align 4			// CHECK2-NEXT: store i32 4, i32* [[TMP46]], align 4
	// CHECK2-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP47:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP48:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP48:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP49:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP47]], i8* [[TMP48]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP49:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP47]], i8* [[TMP48]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK2: .untied.jmp.7.i:			// CHECK2: .untied.jmp.7.i:
	// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP50:%.]] = bitcast %struct.S [[TMP17]] to i8*			// CHECK2-NEXT: [[TMP50:%.]] = bitcast %struct.S [[TMP17]] to i8*
	// CHECK2-NEXT: [[TMP51:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*			// CHECK2-NEXT: [[TMP51:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*
	// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i64 4, i1 false) #[[ATTR4]]			// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i64 4, i1 false) #[[ATTR4]]
	// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[A9_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0			// CHECK2-NEXT: [[A9_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[TMP19]], i32 0, i32 0
	// CHECK2-NEXT: store i32 10, i32* [[A9_I]], align 4			// CHECK2-NEXT: store i32 10, i32* [[A9_I]], align 4
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP53:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[TMP52]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP53:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[TMP52]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP54:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: store i32 5, i32* [[TMP54]], align 4			// CHECK2-NEXT: store i32 5, i32* [[TMP54]], align 4
	// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP55:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP56:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK2-NEXT: [[TMP56:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK2-NEXT: [[TMP57:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP55]], i8* [[TMP56]]) #[[ATTR4]]			// CHECK2-NEXT: [[TMP57:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[TMP55]], i8* [[TMP56]]) #[[ATTR4]]
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK2: .untied.jmp.10.i:			// CHECK2: .untied.jmp.10.i:
	// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]			// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP19]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK2-NEXT: [[TMP58:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK2-NEXT: [[TMP59:%.]] = bitcast %struct.S [[TMP19]] to i8*			// CHECK2-NEXT: [[TMP59:%.]] = bitcast %struct.S [[TMP19]] to i8*
	// CHECK2-NEXT: call void @__kmpc_free(i32 [[TMP58]], i8* [[TMP59]], i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]			// CHECK2-NEXT: call void @__kmpc_free(i32 [[TMP58]], i8* [[TMP59]], i8* inttoptr (i64 7 to i8*)) #[[ATTR4]]
	// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]			// CHECK2-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP17]]) #[[ATTR4]]
	// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK2-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK2-NEXT: br label [[CLEANUP_I]]			// CHECK2-NEXT: br label [[CLEANUP_I]]
	// CHECK2: cleanup.i:			// CHECK2: cleanup.i:
	// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK2-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK2: .omp_outlined..17.exit:			// CHECK2: .omp_outlined..17.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META117:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META119:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !121			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !122
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !121			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !122
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !121			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !122
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !121			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !122
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !121			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !122
	// CHECK2-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK2-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8
	// CHECK2-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0			// CHECK2-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0
	// CHECK2-NEXT: store i32 0, i32* [[A_I]], align 4			// CHECK2-NEXT: store i32 0, i32* [[A_I]], align 4
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z4xxxxv			// CHECK2-LABEL: define {{[^@]+}}@_Z4xxxxv
	▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.]], %struct.kmp_task_t_with_privates.24* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.]], %struct.kmp_task_t_with_privates.24* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.23*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.23*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], %struct.kmp_task_t_with_privates.24 [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], %struct.kmp_task_t_with_privates.24 [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.25 [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.25 [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.24 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.24 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META127:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META129:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !131			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !132
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.25, double) @.omp_task_privates_map..26 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.25, double) @.omp_task_privates_map..26 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: store %struct.anon.23* [[TMP8]], %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: store %struct.anon.23* [[TMP8]], %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon.23, %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon.23, %struct.anon.23** [[__CONTEXT_ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, double)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, double)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]
	// CHECK2-NEXT: [[TMP16:%.]] = load double, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !131			// CHECK2-NEXT: [[TMP16:%.]] = load double, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !132
	// CHECK2-NEXT: [[TMP17:%.]] = load double, double [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load double, double [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_ANON_23:%.]], %struct.anon.23* [[TMP12]], i32 0, i32 0			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_ANON_23:%.]], %struct.anon.23* [[TMP12]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP19:%.]] = load float, float** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load float, float** [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load float, float [[TMP19]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load float, float [[TMP19]], align 4
	// CHECK2-NEXT: [[CONV_I:%.*]] = fpext float [[TMP20]] to double			// CHECK2-NEXT: [[CONV_I:%.*]] = fpext float [[TMP20]] to double
	// CHECK2-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP17]]			// CHECK2-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP17]]
	// CHECK2-NEXT: [[CONV1_I:%.*]] = fptrunc double [[ADD_I]] to float			// CHECK2-NEXT: [[CONV1_I:%.*]] = fptrunc double [[ADD_I]] to float
	// CHECK2-NEXT: store float [[CONV1_I]], float* [[TMP19]], align 4			// CHECK2-NEXT: store float [[CONV1_I]], float* [[TMP19]], align 4
	▲ Show 20 Lines • Show All 352 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK3-NEXT: store i32 15, i32* @a, align 4			// CHECK3-NEXT: store i32 15, i32* @a, align 4
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4
	// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8			// CHECK3-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8
	// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0			// CHECK3-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8			// CHECK3-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8
	// CHECK3-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1			// CHECK3-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1
	// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1			// CHECK3-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1
	// CHECK3-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8			// CHECK3-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8
	Show All 19 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !22
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !22
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !22
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !22
	// CHECK3-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK3-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK3-NEXT: store i32 15, i32* @a, align 4			// CHECK3-NEXT: store i32 15, i32* @a, align 4
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8
	// CHECK3-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1			// CHECK3-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1
	// CHECK3-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0			// CHECK3-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0
	// CHECK3-NEXT: store i32 10, i32* [[A_I]], align 4			// CHECK3-NEXT: store i32 10, i32* [[A_I]], align 4
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	Show All 15 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK3-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK3-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK3-NEXT: ]			// CHECK3-NEXT: ]
	// CHECK3: .untied.done..i:			// CHECK3: .untied.done..i:
	// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK3: .untied.jmp..i:			// CHECK3: .untied.jmp..i:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK3-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB7]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB7]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
	// CHECK3: .untied.jmp.1.i:			// CHECK3: .untied.jmp.1.i:
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]
	// CHECK3-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK3-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK3-NEXT: store i32 1, i32* @a, align 4			// CHECK3-NEXT: store i32 1, i32* @a, align 4
	// CHECK3-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK3-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK3-NEXT: br label [[CLEANUP_I]]			// CHECK3-NEXT: br label [[CLEANUP_I]]
	// CHECK3: cleanup.i:			// CHECK3: cleanup.i:
	// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK3: .omp_outlined..3.exit:			// CHECK3: .omp_outlined..3.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..6			// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..6
	// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 11 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !41			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !42
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK3-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK3-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK3-NEXT: ]			// CHECK3-NEXT: ]
	// CHECK3: .untied.done..i:			// CHECK3: .untied.done..i:
	// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK3: .untied.jmp..i:			// CHECK3: .untied.jmp..i:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK3-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB9]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB9]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]
	// CHECK3: .untied.jmp.1.i:			// CHECK3: .untied.jmp.1.i:
	// CHECK3-NEXT: store i32 1, i32* @a, align 4			// CHECK3-NEXT: store i32 1, i32* @a, align 4
	// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK3-NEXT: br label [[CLEANUP_I]]			// CHECK3-NEXT: br label [[CLEANUP_I]]
	// CHECK3: cleanup.i:			// CHECK3: cleanup.i:
	// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]
	// CHECK3: .omp_outlined..5.exit:			// CHECK3: .omp_outlined..5.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..8			// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..8
	// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 11 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK3-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK3-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK3-NEXT: ]			// CHECK3-NEXT: ]
	// CHECK3: .untied.done..i:			// CHECK3: .untied.done..i:
	// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK3: .untied.jmp..i:			// CHECK3: .untied.jmp..i:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK3-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB11]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB11]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]
	// CHECK3: .untied.jmp.1.i:			// CHECK3: .untied.jmp.1.i:
	// CHECK3-NEXT: store i32 1, i32* @a, align 4			// CHECK3-NEXT: store i32 1, i32* @a, align 4
	// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK3-NEXT: br label [[CLEANUP_I]]			// CHECK3-NEXT: br label [[CLEANUP_I]]
	// CHECK3: cleanup.i:			// CHECK3: cleanup.i:
	// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]
	// CHECK3: .omp_outlined..7.exit:			// CHECK3: .omp_outlined..7.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..10			// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..10
	// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	Show All 10 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !61			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !62
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !61			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !62
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !61			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !62
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !61			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !62
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !61			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !62
	// CHECK3-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK3-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK3-NEXT: store i32 2, i32* @a, align 4			// CHECK3-NEXT: store i32 2, i32* @a, align 4
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..12			// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..12
	// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !71			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !72
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !71			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !72
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !71			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !72
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !71			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !72
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !71			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !72
	// CHECK3-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK3-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK3-NEXT: store i32 2, i32* @a, align 4			// CHECK3-NEXT: store i32 2, i32* @a, align 4
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..14			// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..14
	// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !81			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !82
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !81			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !82
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !81			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !82
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !81			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !82
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !81			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !82
	// CHECK3-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK3-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK3-NEXT: store i32 3, i32* @a, align 4			// CHECK3-NEXT: store i32 3, i32* @a, align 4
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..16			// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..16
	// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK3-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !91			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !92
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !91			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !92
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !91			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !92
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !91			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !92
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !91			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !92
	// CHECK3-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK3-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK3-NEXT: store i32 4, i32* @a, align 4			// CHECK3-NEXT: store i32 4, i32* @a, align 4
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8
	// CHECK3-NEXT: store i32 5, i32* [[TMP12]], align 128			// CHECK3-NEXT: store i32 5, i32* [[TMP12]], align 128
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.			// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
	Show All 29 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !101			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !102
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)			// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)
	// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !101			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !102
	// CHECK3-NEXT: store i32 4, i32* [[TMP16]], align 128			// CHECK3-NEXT: store i32 4, i32* [[TMP16]], align 128
	// CHECK3-NEXT: store i32 4, i32* @a, align 4			// CHECK3-NEXT: store i32 4, i32* @a, align 4
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev			// CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev
	// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2			// CHECK3-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*			// CHECK3-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*
	// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S)			// CHECK3-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S)
	// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK3-NEXT: switch i32 [[TMP20]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK3-NEXT: switch i32 [[TMP20]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]			// CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]
	// CHECK3-NEXT: i32 2, label [[DOTUNTIED_JMP_6_I:%.*]]			// CHECK3-NEXT: i32 2, label [[DOTUNTIED_JMP_6_I:%.*]]
	// CHECK3-NEXT: i32 3, label [[DOTUNTIED_JMP_10_I:%.*]]			// CHECK3-NEXT: i32 3, label [[DOTUNTIED_JMP_10_I:%.*]]
	// CHECK3-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]]			// CHECK3-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]]
	// CHECK3-NEXT: ]			// CHECK3-NEXT: ]
	// CHECK3: .untied.done..i:			// CHECK3: .untied.done..i:
	// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK3-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK3-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK3: .untied.jmp..i:			// CHECK3: .untied.jmp..i:
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store i32 1, i32* [[TMP21]], align 4			// CHECK3-NEXT: store i32 1, i32* [[TMP21]], align 4
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP22:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP22:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP23:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP22]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP23:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP22]]) #[[ATTR4]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]
	// CHECK3: .untied.jmp.2.i:			// CHECK3: .untied.jmp.2.i:
	// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]
	// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]
	// CHECK3-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0			// CHECK3-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0
	// CHECK3-NEXT: store i32 0, i32* [[A_I]], align 4, !noalias !111			// CHECK3-NEXT: store i32 0, i32* [[A_I]], align 4, !noalias !112
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23:[0-9]+]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23:[0-9]+]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP24:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]			// CHECK3-NEXT: [[TMP24:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP25:%.]] = bitcast i8 [[TMP24]] to %struct.kmp_task_t_with_privates.18*			// CHECK3-NEXT: [[TMP25:%.]] = bitcast i8 [[TMP24]] to %struct.kmp_task_t_with_privates.18*
	// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP25]], i32 0, i32 0			// CHECK3-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP25]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP25]], i32 0, i32 2			// CHECK3-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP25]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP27]], i32 0, i32 0			// CHECK3-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP27]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP16]], align 128			// CHECK3-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP16]], align 128
	// CHECK3-NEXT: store i32 [[TMP29]], i32* [[TMP28]], align 128			// CHECK3-NEXT: store i32 [[TMP29]], i32* [[TMP28]], align 128
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], i8* [[TMP24]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], i8* [[TMP24]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store i32 2, i32* [[TMP31]], align 4			// CHECK3-NEXT: store i32 2, i32* [[TMP31]], align 4
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP32:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP32:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP33:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], i8* [[TMP32]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP33:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], i8* [[TMP32]]) #[[ATTR4]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK3: .untied.jmp.6.i:			// CHECK3: .untied.jmp.6.i:
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP34:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) #[[ATTR4]]			// CHECK3-NEXT: [[TMP34:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP35:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store i32 3, i32* [[TMP35]], align 4			// CHECK3-NEXT: store i32 3, i32* [[TMP35]], align 4
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP36:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP36:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP37:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], i8* [[TMP36]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP37:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], i8* [[TMP36]]) #[[ATTR4]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK3: .untied.jmp.10.i:			// CHECK3: .untied.jmp.10.i:
	// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP38:%.]] = bitcast %struct.S [[S1_I]] to i8*			// CHECK3-NEXT: [[TMP38:%.]] = bitcast %struct.S [[S1_I]] to i8*
	// CHECK3-NEXT: [[TMP39:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*			// CHECK3-NEXT: [[TMP39:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*
	// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) #[[ATTR4]], !noalias !111			// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) #[[ATTR4]], !noalias !112
	// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK3-NEXT: [[A12_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0			// CHECK3-NEXT: [[A12_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0
	// CHECK3-NEXT: store i32 10, i32* [[A12_I]], align 4, !noalias !111			// CHECK3-NEXT: store i32 10, i32* [[A12_I]], align 4, !noalias !112
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP40:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP40:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: store i32 4, i32* [[TMP41]], align 4			// CHECK3-NEXT: store i32 4, i32* [[TMP41]], align 4
	// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK3-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK3-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK3-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], i8* [[TMP42]]) #[[ATTR4]]			// CHECK3-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], i8* [[TMP42]]) #[[ATTR4]]
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK3: .untied.jmp.15.i:			// CHECK3: .untied.jmp.15.i:
	// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]
	// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]			// CHECK3-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]
	// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK3-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK3-NEXT: br label [[CLEANUP_I]]			// CHECK3-NEXT: br label [[CLEANUP_I]]
	// CHECK3: cleanup.i:			// CHECK3: cleanup.i:
	// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK3-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK3: .omp_outlined..17.exit:			// CHECK3: .omp_outlined..17.exit:
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK3-NEXT: entry:			// CHECK3-NEXT: entry:
	▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK3-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8			// CHECK3-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8
	// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0			// CHECK3-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK3-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK3-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK3-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*			// CHECK3-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*
	// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*			// CHECK3-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META117:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]])
	// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META119:![0-9]+]])			// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]])
	// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !121			// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !122
	// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !121			// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !122
	// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !121			// CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !122
	// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !121			// CHECK3-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !122
	// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !121			// CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !122
	// CHECK3-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK3-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK3-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0			// CHECK3-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8			// CHECK3-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8
	// CHECK3-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0			// CHECK3-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0
	// CHECK3-NEXT: store i32 0, i32* [[A_I]], align 4			// CHECK3-NEXT: store i32 0, i32* [[A_I]], align 4
	// CHECK3-NEXT: ret i32 0			// CHECK3-NEXT: ret i32 0
	//			//
	//			//
	// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp			// CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp
	▲ Show 20 Lines • Show All 348 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK4-NEXT: store i32 15, i32* @a, align 4			// CHECK4-NEXT: store i32 15, i32* @a, align 4
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 @a, align 4
	// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8			// CHECK4-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP11]] to i8
	// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0			// CHECK4-NEXT: [[TMP12:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP10]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8			// CHECK4-NEXT: [[TMP13:%.]] = load i8, i8** [[TMP12]], align 8
	// CHECK4-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1			// CHECK4-NEXT: store i8 [[CONV_I]], i8* [[TMP13]], align 1
	// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1			// CHECK4-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP10]], i32 0, i32 1
	// CHECK4-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8			// CHECK4-NEXT: [[TMP15:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP14]], align 8
	Show All 19 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !22
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !22
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !22
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !22
	// CHECK4-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK4-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !21			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !22
	// CHECK4-NEXT: store i32 15, i32* @a, align 4			// CHECK4-NEXT: store i32 15, i32* @a, align 4
	// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0			// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_0:%.]], %struct.anon.0* [[TMP10]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load [2 x %struct.S], [2 x %struct.S]** [[TMP11]], align 8
	// CHECK4-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1			// CHECK4-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S] [[TMP12]], i64 0, i64 1
	// CHECK4-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0			// CHECK4-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S:%.]], %struct.S* [[ARRAYIDX_I]], i32 0, i32 0
	// CHECK4-NEXT: store i32 10, i32* [[A_I]], align 4			// CHECK4-NEXT: store i32 10, i32* [[A_I]], align 4
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	Show All 15 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !31			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK4-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK4-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK4-NEXT: ]			// CHECK4-NEXT: ]
	// CHECK4: .untied.done..i:			// CHECK4: .untied.done..i:
	// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK4: .untied.jmp..i:			// CHECK4: .untied.jmp..i:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK4-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB7]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB7]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !31			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
	// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
	// CHECK4: .untied.jmp.1.i:			// CHECK4: .untied.jmp.1.i:
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]
	// CHECK4-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK4-NEXT: call void @__kmpc_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK4-NEXT: store i32 1, i32* @a, align 4			// CHECK4-NEXT: store i32 1, i32* @a, align 4
	// CHECK4-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]			// CHECK4-NEXT: call void @__kmpc_end_critical(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], [8 x i32]* @.gomp_critical_user_.var) #[[ATTR4]]
	// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK4-NEXT: br label [[CLEANUP_I]]			// CHECK4-NEXT: br label [[CLEANUP_I]]
	// CHECK4: cleanup.i:			// CHECK4: cleanup.i:
	// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !31			// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !32
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
	// CHECK4: .omp_outlined..3.exit:			// CHECK4: .omp_outlined..3.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..6			// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..6
	// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 11 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !41			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !42
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK4-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK4-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK4-NEXT: ]			// CHECK4-NEXT: ]
	// CHECK4: .untied.done..i:			// CHECK4: .untied.done..i:
	// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK4: .untied.jmp..i:			// CHECK4: .untied.jmp..i:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK4-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB9]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB9]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !41			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !42
	// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]]
	// CHECK4: .untied.jmp.1.i:			// CHECK4: .untied.jmp.1.i:
	// CHECK4-NEXT: store i32 1, i32* @a, align 4			// CHECK4-NEXT: store i32 1, i32* @a, align 4
	// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK4-NEXT: br label [[CLEANUP_I]]			// CHECK4-NEXT: br label [[CLEANUP_I]]
	// CHECK4: cleanup.i:			// CHECK4: cleanup.i:
	// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !41			// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !42
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]]
	// CHECK4: .omp_outlined..5.exit:			// CHECK4: .omp_outlined..5.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..8			// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..8
	// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 11 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !51			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !52
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[TMP11]], align 4
	// CHECK4-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK4-NEXT: switch i32 [[TMP12]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]			// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]]
	// CHECK4-NEXT: ]			// CHECK4-NEXT: ]
	// CHECK4: .untied.done..i:			// CHECK4: .untied.done..i:
	// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK4: .untied.jmp..i:			// CHECK4: .untied.jmp..i:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: store i32 1, i32* [[TMP13]], align 4			// CHECK4-NEXT: store i32 1, i32* [[TMP13]], align 4
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB11]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB11]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !51			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !52
	// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP15:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP14]]) #[[ATTR4]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]]
	// CHECK4: .untied.jmp.1.i:			// CHECK4: .untied.jmp.1.i:
	// CHECK4-NEXT: store i32 1, i32* @a, align 4			// CHECK4-NEXT: store i32 1, i32* @a, align 4
	// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK4-NEXT: br label [[CLEANUP_I]]			// CHECK4-NEXT: br label [[CLEANUP_I]]
	// CHECK4: cleanup.i:			// CHECK4: cleanup.i:
	// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !51			// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !52
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]]
	// CHECK4: .omp_outlined..7.exit:			// CHECK4: .omp_outlined..7.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..10			// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..10
	// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.9 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	Show All 10 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !61			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !62
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !61			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !62
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !61			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !62
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !61			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !62
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !61			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !62
	// CHECK4-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK4-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !61			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !62
	// CHECK4-NEXT: store i32 2, i32* @a, align 4			// CHECK4-NEXT: store i32 2, i32* @a, align 4
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..12			// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..12
	// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !71			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !72
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !71			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !72
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !71			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !72
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !71			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !72
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !71			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !72
	// CHECK4-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK4-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !71			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !72
	// CHECK4-NEXT: store i32 2, i32* @a, align 4			// CHECK4-NEXT: store i32 2, i32* @a, align 4
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..14			// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..14
	// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !81			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !82
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !81			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !82
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !81			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !82
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !81			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !82
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !81			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !82
	// CHECK4-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK4-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !81			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !82
	// CHECK4-NEXT: store i32 3, i32* @a, align 4			// CHECK4-NEXT: store i32 3, i32* @a, align 4
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..16			// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry..16
	// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK4-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !91			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !92
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !91			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !92
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !91			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !92
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !91			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !92
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !91			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !92
	// CHECK4-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK4-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !91			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !92
	// CHECK4-NEXT: store i32 4, i32* @a, align 4			// CHECK4-NEXT: store i32 4, i32* @a, align 4
	// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0			// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_14:%.]], %struct.anon.14* [[TMP10]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8
	// CHECK4-NEXT: store i32 5, i32* [[TMP12]], align 128			// CHECK4-NEXT: store i32 5, i32* [[TMP12]], align 128
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.			// CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.
	Show All 29 Lines
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.17*
	// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2			// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP3]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.18 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !101			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !102
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i32) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: store %struct.anon.17* [[TMP8]], %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon.17, %struct.anon.17** [[__CONTEXT_ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)			// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32)
	// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !101			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !102
	// CHECK4-NEXT: store i32 4, i32* [[TMP16]], align 128			// CHECK4-NEXT: store i32 4, i32* [[TMP16]], align 128
	// CHECK4-NEXT: store i32 4, i32* @a, align 4			// CHECK4-NEXT: store i32 4, i32* @a, align 4
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev			// CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev
	// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 128
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2			// CHECK4-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], %struct.kmp_task_t_with_privates.19 [[TMP3]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*			// CHECK4-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t.20 [[TMP9]] to i8*
	// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !111			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !112
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t.20, i32, %struct.S, %struct.S) @.omp_task_privates_map..20 to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP12:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S)			// CHECK4-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i32, %struct.S, %struct.S)
	// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i32 [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.S [[DOTLOCAL_PTR_ADDR_I]], %struct.S** [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP17:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP18:%.]] = load %struct.S, %struct.S** [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK4-NEXT: switch i32 [[TMP20]], label [[DOTUNTIED_DONE__I:%.*]] [			// CHECK4-NEXT: switch i32 [[TMP20]], label [[DOTUNTIED_DONE__I:%.*]] [
	// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]			// CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]]
	// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]			// CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]]
	// CHECK4-NEXT: i32 2, label [[DOTUNTIED_JMP_6_I:%.*]]			// CHECK4-NEXT: i32 2, label [[DOTUNTIED_JMP_6_I:%.*]]
	// CHECK4-NEXT: i32 3, label [[DOTUNTIED_JMP_10_I:%.*]]			// CHECK4-NEXT: i32 3, label [[DOTUNTIED_JMP_10_I:%.*]]
	// CHECK4-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]]			// CHECK4-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]]
	// CHECK4-NEXT: ]			// CHECK4-NEXT: ]
	// CHECK4: .untied.done..i:			// CHECK4: .untied.done..i:
	// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK4-NEXT: store i32 1, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]			// CHECK4-NEXT: br label [[CLEANUP_I:%.*]]
	// CHECK4: .untied.jmp..i:			// CHECK4: .untied.jmp..i:
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store i32 1, i32* [[TMP21]], align 4			// CHECK4-NEXT: store i32 1, i32* [[TMP21]], align 4
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP22:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP22:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP23:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP22]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP23:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], i8* [[TMP22]]) #[[ATTR4]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]]
	// CHECK4: .untied.jmp.2.i:			// CHECK4: .untied.jmp.2.i:
	// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]
	// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]
	// CHECK4-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0			// CHECK4-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0
	// CHECK4-NEXT: store i32 0, i32* [[A_I]], align 4, !noalias !111			// CHECK4-NEXT: store i32 0, i32* [[A_I]], align 4, !noalias !112
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23:[0-9]+]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23:[0-9]+]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP24:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]			// CHECK4-NEXT: [[TMP24:%.]] = call i8 @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, i32 (i32, i8) bitcast (i32 (i32, %struct.kmp_task_t_with_privates.18) @.omp_task_entry..19 to i32 (i32, i8))) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP25:%.]] = bitcast i8 [[TMP24]] to %struct.kmp_task_t_with_privates.18*			// CHECK4-NEXT: [[TMP25:%.]] = bitcast i8 [[TMP24]] to %struct.kmp_task_t_with_privates.18*
	// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP25]], i32 0, i32 0			// CHECK4-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.]], %struct.kmp_task_t_with_privates.18* [[TMP25]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP25]], i32 0, i32 2			// CHECK4-NEXT: [[TMP27:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], %struct.kmp_task_t_with_privates.18 [[TMP25]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP27]], i32 0, i32 0			// CHECK4-NEXT: [[TMP28:%.]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.]], %struct..kmp_privates.t* [[TMP27]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP16]], align 128			// CHECK4-NEXT: [[TMP29:%.]] = load i32, i32 [[TMP16]], align 128
	// CHECK4-NEXT: store i32 [[TMP29]], i32* [[TMP28]], align 128			// CHECK4-NEXT: store i32 [[TMP29]], i32* [[TMP28]], align 128
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB23]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], i8* [[TMP24]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP30:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], i8* [[TMP24]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP31:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store i32 2, i32* [[TMP31]], align 4			// CHECK4-NEXT: store i32 2, i32* [[TMP31]], align 4
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP32:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP32:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP33:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], i8* [[TMP32]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP33:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], i8* [[TMP32]]) #[[ATTR4]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK4: .untied.jmp.6.i:			// CHECK4: .untied.jmp.6.i:
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP34:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) #[[ATTR4]]			// CHECK4-NEXT: [[TMP34:%.]] = call i32 @__kmpc_omp_taskyield(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP35:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store i32 3, i32* [[TMP35]], align 4			// CHECK4-NEXT: store i32 3, i32* [[TMP35]], align 4
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP36:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP36:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP37:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], i8* [[TMP36]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP37:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], i8* [[TMP36]]) #[[ATTR4]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK4: .untied.jmp.10.i:			// CHECK4: .untied.jmp.10.i:
	// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP38:%.]] = bitcast %struct.S [[S1_I]] to i8*			// CHECK4-NEXT: [[TMP38:%.]] = bitcast %struct.S [[S1_I]] to i8*
	// CHECK4-NEXT: [[TMP39:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*			// CHECK4-NEXT: [[TMP39:%.]] = bitcast %struct.S [[REF_TMP_I]] to i8*
	// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) #[[ATTR4]], !noalias !111			// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP38]], i8* align 4 [[TMP39]], i64 4, i1 false) #[[ATTR4]], !noalias !112
	// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]]
	// CHECK4-NEXT: [[A12_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0			// CHECK4-NEXT: [[A12_I:%.]] = getelementptr inbounds [[STRUCT_S]], %struct.S [[S2_I]], i32 0, i32 0
	// CHECK4-NEXT: store i32 10, i32* [[A12_I]], align 4, !noalias !111			// CHECK4-NEXT: store i32 10, i32* [[A12_I]], align 4, !noalias !112
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP40:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP40:%.]] = call i32 @__kmpc_omp_taskwait(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP41:%.]] = load i32, i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: store i32 4, i32* [[TMP41]], align 4			// CHECK4-NEXT: store i32 4, i32* [[TMP41]], align 4
	// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]			// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB21]]) #[[ATTR4]]
	// CHECK4-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !111			// CHECK4-NEXT: [[TMP42:%.]] = load i8, i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !112
	// CHECK4-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], i8* [[TMP42]]) #[[ATTR4]]			// CHECK4-NEXT: [[TMP43:%.]] = call i32 @__kmpc_omp_task(%struct.ident_t @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], i8* [[TMP42]]) #[[ATTR4]]
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK4: .untied.jmp.15.i:			// CHECK4: .untied.jmp.15.i:
	// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]]
	// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]			// CHECK4-NEXT: call void @_ZN1SD1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]]
	// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK4-NEXT: store i32 0, i32* [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK4-NEXT: br label [[CLEANUP_I]]			// CHECK4-NEXT: br label [[CLEANUP_I]]
	// CHECK4: cleanup.i:			// CHECK4: cleanup.i:
	// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !111			// CHECK4-NEXT: [[CLEANUP_DEST_I:%.]] = load i32, i32 [[CLEANUP_DEST_SLOT_I]], align 4, !noalias !112
	// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]			// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]]
	// CHECK4: .omp_outlined..17.exit:			// CHECK4: .omp_outlined..17.exit:
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK4-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK4-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8			// CHECK4-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.22, %struct.kmp_task_t_with_privates.22** [[DOTADDR1]], align 8
	// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0			// CHECK4-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.]], %struct.kmp_task_t_with_privates.22* [[TMP3]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK4-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK4-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK4-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*			// CHECK4-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.21*
	// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*			// CHECK4-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.22 [[TMP3]] to i8*
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META117:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]])
	// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META119:![0-9]+]])			// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]])
	// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !121			// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !122
	// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !121			// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !122
	// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !121			// CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !122
	// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !121			// CHECK4-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !122
	// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !121			// CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !122
	// CHECK4-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK4-NEXT: store %struct.anon.21* [[TMP8]], %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !121			// CHECK4-NEXT: [[TMP10:%.]] = load %struct.anon.21, %struct.anon.21** [[__CONTEXT_ADDR_I]], align 8, !noalias !122
	// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0			// CHECK4-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_21:%.]], %struct.anon.21* [[TMP10]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8			// CHECK4-NEXT: [[TMP12:%.]] = load %struct.S1, %struct.S1** [[TMP11]], align 8
	// CHECK4-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0			// CHECK4-NEXT: [[A_I:%.]] = getelementptr inbounds [[STRUCT_S1:%.]], %struct.S1* [[TMP12]], i32 0, i32 0
	// CHECK4-NEXT: store i32 0, i32* [[A_I]], align 4			// CHECK4-NEXT: store i32 0, i32* [[A_I]], align 4
	// CHECK4-NEXT: ret i32 0			// CHECK4-NEXT: ret i32 0
	//			//
	//			//
	// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp			// CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp
	// CHECK4-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" {			// CHECK4-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" {
	// CHECK4-NEXT: entry:			// CHECK4-NEXT: entry:
	// CHECK4-NEXT: call void @__cxx_global_var_init()			// CHECK4-NEXT: call void @__cxx_global_var_init()
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/task_if_codegen.cpp

	Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@main			// CHECK1-LABEL: define {{[^@]+}}@main
	// CHECK1-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: call void @_Z3fn7v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn7v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..5			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..5
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !34
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !34
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !34
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !34
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !34
	// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK1-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK1-NEXT: call void @_Z3fn8v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn8v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..7			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..7
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !44
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !44
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !44
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !44
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !44
	// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK1-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK1-NEXT: call void @_Z3fn9v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn9v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..9			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..9
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !54
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !54
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !54
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !54
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !54
	// CHECK1-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK1-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK1-NEXT: call void @_Z4fn10v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z4fn10v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_			// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
	// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {			// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK1-NEXT: call void @_Z3fn1v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn1v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..13			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..13
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !74
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !74
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !74
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !74
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !74
	// CHECK1-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK1-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK1-NEXT: call void @_Z3fn2v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn2v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..15			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..15
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !84
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !84
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !84
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !84
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !84
	// CHECK1-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK1-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK1-NEXT: call void @_Z3fn3v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn3v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..17			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..17
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !94
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !94
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !94
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !94
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !94
	// CHECK1-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK1-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK1-NEXT: call void @_Z3fn4v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn4v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..19			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..19
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !104
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !104
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !104
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !104
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !104
	// CHECK1-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK1-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK1-NEXT: call void @_Z3fn5v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn5v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..21			// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..21
	// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK1-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !114
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !114
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !114
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !114
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !114
	// CHECK1-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK1-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK1-NEXT: call void @_Z3fn6v() #[[ATTR3]]			// CHECK1-NEXT: call void @_Z3fn6v() #[[ATTR3]]
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z9gtid_testv			// CHECK2-LABEL: define {{[^@]+}}@_Z9gtid_testv
	// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*))			// CHECK2-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*))
	Show All 35 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@main			// CHECK2-LABEL: define {{[^@]+}}@main
	// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: call void @_Z3fn7v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn7v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..5			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..5
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !34
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !34
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !34
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !34
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !34
	// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK2-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK2-NEXT: call void @_Z3fn8v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn8v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..7			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..7
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !44
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !44
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !44
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !44
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !44
	// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK2-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK2-NEXT: call void @_Z3fn9v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn9v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..9			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..9
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !54
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !54
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !54
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !54
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !54
	// CHECK2-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK2-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK2-NEXT: call void @_Z4fn10v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z4fn10v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_			// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
	// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {			// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK2-NEXT: call void @_Z3fn1v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn1v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..13			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..13
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !74
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !74
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !74
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !74
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !74
	// CHECK2-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK2-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK2-NEXT: call void @_Z3fn2v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn2v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..15			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..15
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !84
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !84
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !84
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !84
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !84
	// CHECK2-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK2-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK2-NEXT: call void @_Z3fn3v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn3v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..17			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..17
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !94
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !94
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !94
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !94
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !94
	// CHECK2-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK2-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK2-NEXT: call void @_Z3fn4v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn4v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..19			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..19
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !104
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !104
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !104
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !104
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !104
	// CHECK2-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK2-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK2-NEXT: call void @_Z3fn5v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn5v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..21			// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..21
	// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK2-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !114
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !114
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !114
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !114
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !114
	// CHECK2-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK2-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK2-NEXT: call void @_Z3fn6v() #[[ATTR3]]			// CHECK2-NEXT: call void @_Z3fn6v() #[[ATTR3]]
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv			// CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv
	// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*))			// CHECK5-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*))
	Show All 35 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK5-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@main			// CHECK5-LABEL: define {{[^@]+}}@main
	// CHECK5-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK5-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK5-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK5-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK5-NEXT: call void @_Z3fn7v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn7v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..5			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..5
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !34
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !34
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !34
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !34
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !34
	// CHECK5-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK5-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK5-NEXT: call void @_Z3fn8v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn8v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..7			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..7
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !44
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !44
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !44
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !44
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !44
	// CHECK5-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK5-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK5-NEXT: call void @_Z3fn9v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn9v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..9			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..9
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !54
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !54
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !54
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !54
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !54
	// CHECK5-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK5-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK5-NEXT: call void @_Z4fn10v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z4fn10v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_			// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
	// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {			// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK5-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK5-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK5-NEXT: call void @_Z3fn1v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn1v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..13			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..13
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !74
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !74
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !74
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !74
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !74
	// CHECK5-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK5-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK5-NEXT: call void @_Z3fn2v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn2v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..15			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..15
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !84
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !84
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !84
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !84
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !84
	// CHECK5-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK5-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK5-NEXT: call void @_Z3fn3v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn3v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..17			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..17
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !94
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !94
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !94
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !94
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !94
	// CHECK5-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK5-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK5-NEXT: call void @_Z3fn4v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn4v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..19			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..19
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !104
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !104
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !104
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !104
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !104
	// CHECK5-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK5-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK5-NEXT: call void @_Z3fn5v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn5v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..21			// CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry..21
	// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK5-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK5-NEXT: entry:			// CHECK5-NEXT: entry:
	// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK5-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8			// CHECK5-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8
	// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK5-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK5-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK5-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK5-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*			// CHECK5-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*
	// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK5-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]])			// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])
	// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113			// CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !114
	// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113			// CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !114
	// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113			// CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !114
	// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113			// CHECK5-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !114
	// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113			// CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !114
	// CHECK5-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK5-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK5-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK5-NEXT: call void @_Z3fn6v() #[[ATTR3]]			// CHECK5-NEXT: call void @_Z3fn6v() #[[ATTR3]]
	// CHECK5-NEXT: ret i32 0			// CHECK5-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@_Z9gtid_testv			// CHECK6-LABEL: define {{[^@]+}}@_Z9gtid_testv
	// CHECK6-SAME: () #[[ATTR0:[0-9]+]] {			// CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*))			// CHECK6-NEXT: call void (%struct.ident_t, i32, void (i32, i32, ...), ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32, i32, ...)* bitcast (void (i32, i32)* @.omp_outlined. to void (i32, i32, ...)*))
	Show All 35 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK6-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK6-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z9gtid_testv() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@main			// CHECK6-LABEL: define {{[^@]+}}@main
	// CHECK6-SAME: () #[[ATTR4:[0-9]+]] {			// CHECK6-SAME: () #[[ATTR4:[0-9]+]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.1, %struct.kmp_task_t_with_privates.1** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.]], %struct.kmp_task_t_with_privates.1* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.0*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.1 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK6-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK6-NEXT: store %struct.anon.0* [[TMP8]], %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.0, %struct.anon.0** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK6-NEXT: call void @_Z3fn7v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn7v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..5			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..5
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.3 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.3, %struct.kmp_task_t_with_privates.3** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.]], %struct.kmp_task_t_with_privates.3* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.2*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.3 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !33			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !34
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !33			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !34
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !33			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !34
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !33			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !34
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !33			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !34
	// CHECK6-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK6-NEXT: store %struct.anon.2* [[TMP8]], %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !33			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.2, %struct.anon.2** [[__CONTEXT_ADDR_I]], align 8, !noalias !34
	// CHECK6-NEXT: call void @_Z3fn8v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn8v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..7			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..7
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.5 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.5, %struct.kmp_task_t_with_privates.5** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.]], %struct.kmp_task_t_with_privates.5* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.4*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.5 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META34:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META37:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !43			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !44
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !43			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !44
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !43			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !44
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !43			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !44
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !43			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !44
	// CHECK6-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK6-NEXT: store %struct.anon.4* [[TMP8]], %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !43			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.4, %struct.anon.4** [[__CONTEXT_ADDR_I]], align 8, !noalias !44
	// CHECK6-NEXT: call void @_Z3fn9v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn9v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..9			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..9
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.7 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.7, %struct.kmp_task_t_with_privates.7** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.]], %struct.kmp_task_t_with_privates.7* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.6*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.7 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META44:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META47:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META49:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !53			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !54
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !53			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !54
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !53			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !54
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !53			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !54
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !53			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !54
	// CHECK6-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK6-NEXT: store %struct.anon.6* [[TMP8]], %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !53			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.6, %struct.anon.6** [[__CONTEXT_ADDR_I]], align 8, !noalias !54
	// CHECK6-NEXT: call void @_Z4fn10v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z4fn10v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_			// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
	// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {			// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
	▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.9, %struct.kmp_task_t_with_privates.9** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.]], %struct.kmp_task_t_with_privates.9* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.8*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.9 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META57:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META59:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META61:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !63			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !64
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !63			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !64
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !63			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !64
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !63			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !64
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !63			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !64
	// CHECK6-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK6-NEXT: store %struct.anon.8* [[TMP8]], %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !63			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.8, %struct.anon.8** [[__CONTEXT_ADDR_I]], align 8, !noalias !64
	// CHECK6-NEXT: call void @_Z3fn1v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn1v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..13			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..13
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.11 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.11, %struct.kmp_task_t_with_privates.11** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.]], %struct.kmp_task_t_with_privates.11* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.10*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.11 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META64:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META67:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META69:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META71:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !73			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !74
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !73			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !74
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !73			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !74
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !73			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !74
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !73			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !74
	// CHECK6-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK6-NEXT: store %struct.anon.10* [[TMP8]], %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !73			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.10, %struct.anon.10** [[__CONTEXT_ADDR_I]], align 8, !noalias !74
	// CHECK6-NEXT: call void @_Z3fn2v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn2v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..15			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..15
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.13 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.13, %struct.kmp_task_t_with_privates.13** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.]], %struct.kmp_task_t_with_privates.13* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.12*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.13 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META74:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META77:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META79:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META81:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !83			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !84
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !83			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !84
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !83			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !84
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !83			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !84
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !83			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !84
	// CHECK6-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK6-NEXT: store %struct.anon.12* [[TMP8]], %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !83			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.12, %struct.anon.12** [[__CONTEXT_ADDR_I]], align 8, !noalias !84
	// CHECK6-NEXT: call void @_Z3fn3v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn3v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..17			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..17
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.15 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.15, %struct.kmp_task_t_with_privates.15** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.]], %struct.kmp_task_t_with_privates.15* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.14*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.15 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META84:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META87:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META89:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META91:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !93			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !94
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !93			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !94
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !93			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !94
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !93			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !94
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !93			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !94
	// CHECK6-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK6-NEXT: store %struct.anon.14* [[TMP8]], %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !93			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.14, %struct.anon.14** [[__CONTEXT_ADDR_I]], align 8, !noalias !94
	// CHECK6-NEXT: call void @_Z3fn4v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn4v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..19			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..19
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.17 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.17, %struct.kmp_task_t_with_privates.17** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_17:%.]], %struct.kmp_task_t_with_privates.17* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.16*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.17 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META94:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META97:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META99:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META101:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !103			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !104
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !103			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !104
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !103			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !104
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !103			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !104
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !103			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !104
	// CHECK6-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK6-NEXT: store %struct.anon.16* [[TMP8]], %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !103			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.16, %struct.anon.16** [[__CONTEXT_ADDR_I]], align 8, !noalias !104
	// CHECK6-NEXT: call void @_Z3fn5v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn5v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//			//
	// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..21			// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..21
	// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {			// CHECK6-SAME: (i32 [[TMP0:%.]], %struct.kmp_task_t_with_privates.19 noalias [[TMP1:%.*]]) #[[ATTR2]] {
	// CHECK6-NEXT: entry:			// CHECK6-NEXT: entry:
	// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4			// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
	Show All 9 Lines
	// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK6-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8			// CHECK6-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.19, %struct.kmp_task_t_with_privates.19** [[DOTADDR1]], align 8
	// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0			// CHECK6-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.]], %struct.kmp_task_t_with_privates.19* [[TMP3]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK6-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK6-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK6-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*			// CHECK6-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.18*
	// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*			// CHECK6-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.19 [[TMP3]] to i8*
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META104:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META107:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META109:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]])
	// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META111:![0-9]+]])			// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]])
	// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !113			// CHECK6-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !114
	// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !113			// CHECK6-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !114
	// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !113			// CHECK6-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !114
	// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !113			// CHECK6-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !114
	// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !113			// CHECK6-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !114
	// CHECK6-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK6-NEXT: store %struct.anon.18* [[TMP8]], %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !113			// CHECK6-NEXT: [[TMP10:%.]] = load %struct.anon.18, %struct.anon.18** [[__CONTEXT_ADDR_I]], align 8, !noalias !114
	// CHECK6-NEXT: call void @_Z3fn6v() #[[ATTR3]]			// CHECK6-NEXT: call void @_Z3fn6v() #[[ATTR3]]
	// CHECK6-NEXT: ret i32 0			// CHECK6-NEXT: ret i32 0
	//			//
	//
	No newline at end of file

clang/test/OpenMP/task_in_reduction_codegen.cpp

	Show First 20 Lines • Show All 582 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP13:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP14:%.]] = load i64, i64 [[TMP13]], align 8			// CHECK1-NEXT: [[TMP14:%.]] = load i64, i64 [[TMP13]], align 8
	// CHECK1-NEXT: [[TMP15:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP15:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = bitcast void (i8, ...)* [[TMP15]] to void (i8, i8, i8)			// CHECK1-NEXT: [[TMP17:%.]] = bitcast void (i8, ...)* [[TMP15]] to void (i8, i8, i8)
	// CHECK1-NEXT: call void [[TMP17]](i8* [[TMP16]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP17]](i8* [[TMP16]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP18:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP18:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 0			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP20]], align 8
	// CHECK1-NEXT: [[TMP22:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK1-NEXT: [[TMP22:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP24:%.]] = bitcast i32 [[TMP21]] to i8*			// CHECK1-NEXT: [[TMP24:%.]] = bitcast i32 [[TMP21]] to i8*
	// CHECK1-NEXT: [[TMP25:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP23]], i8* [[TMP22]], i8* [[TMP24]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP25:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP23]], i8* [[TMP22]], i8* [[TMP24]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP25]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP25]] to i32*
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP27:%.]] = load i16, i16** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i16, i16** [[TMP26]], align 8
	// CHECK1-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP14]], 2			// CHECK1-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP14]], 2
	// CHECK1-NEXT: [[TMP29:%.]] = udiv exact i64 [[TMP28]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP29:%.]] = udiv exact i64 [[TMP28]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP30:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK1-NEXT: [[TMP30:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	Show All 30 Lines
	// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK1-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.2, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8			// CHECK1-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.2, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.1*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.1*
	// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.2 [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.2 [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK1-NEXT: [[TMP10:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP10]], i32 0, i32 0			// CHECK1-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP10]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK1-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP12]] to i8*			// CHECK1-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP12]] to i8*
	// CHECK1-NEXT: [[TMP15:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP13]], i8* null, i8* [[TMP14]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP15:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP13]], i8* null, i8* [[TMP14]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP15]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP15]] to i32*
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK1-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK1-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK1-NEXT: store i32 [[INC_I]], i32* [[CONV_I]], align 4			// CHECK1-NEXT: store i32 [[INC_I]], i32* [[CONV_I]], align 4
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	▲ Show 20 Lines • Show All 572 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP13:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP14:%.]] = load i64, i64 [[TMP13]], align 8			// CHECK2-NEXT: [[TMP14:%.]] = load i64, i64 [[TMP13]], align 8
	// CHECK2-NEXT: [[TMP15:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP15:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = bitcast void (i8, ...)* [[TMP15]] to void (i8, i8, i8)			// CHECK2-NEXT: [[TMP17:%.]] = bitcast void (i8, ...)* [[TMP15]] to void (i8, i8, i8)
	// CHECK2-NEXT: call void [[TMP17]](i8* [[TMP16]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP17]](i8* [[TMP16]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP18:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP18:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 0			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32** [[TMP20]], align 8
	// CHECK2-NEXT: [[TMP22:%.]] = load i8, i8** [[TMP18]], align 8			// CHECK2-NEXT: [[TMP22:%.]] = load i8, i8** [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP24:%.]] = bitcast i32 [[TMP21]] to i8*			// CHECK2-NEXT: [[TMP24:%.]] = bitcast i32 [[TMP21]] to i8*
	// CHECK2-NEXT: [[TMP25:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP23]], i8* [[TMP22]], i8* [[TMP24]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP25:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP23]], i8* [[TMP22]], i8* [[TMP24]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP25]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP25]] to i32*
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP27:%.]] = load i16, i16** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i16, i16** [[TMP26]], align 8
	// CHECK2-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP14]], 2			// CHECK2-NEXT: [[TMP28:%.*]] = mul nuw i64 [[TMP14]], 2
	// CHECK2-NEXT: [[TMP29:%.]] = udiv exact i64 [[TMP28]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP29:%.]] = udiv exact i64 [[TMP28]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP30:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK2-NEXT: [[TMP30:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	Show All 30 Lines
	// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4			// CHECK2-NEXT: [[TMP2:%.]] = load i32, i32 [[DOTADDR]], align 4
	// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.2, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8			// CHECK2-NEXT: [[TMP3:%.]] = load %struct.kmp_task_t_with_privates.2, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.1*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon.1*
	// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.2 [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP9:%.]] = bitcast %struct.kmp_task_t_with_privates.2 [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store void (i8, ...) null, void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !23			// CHECK2-NEXT: [[TMP10:%.]] = load %struct.anon.1, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
	// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP10]], i32 0, i32 0			// CHECK2-NEXT: [[TMP11:%.]] = getelementptr inbounds [[STRUCT_ANON_1:%.]], %struct.anon.1* [[TMP10]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32** [[TMP11]], align 8
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !23			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
	// CHECK2-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP12]] to i8*			// CHECK2-NEXT: [[TMP14:%.]] = bitcast i32 [[TMP12]] to i8*
	// CHECK2-NEXT: [[TMP15:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP13]], i8* null, i8* [[TMP14]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP15:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP13]], i8* null, i8* [[TMP14]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP15]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP15]] to i32*
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK2-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP16]], 1			// CHECK2-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP16]], 1
	// CHECK2-NEXT: store i32 [[INC_I]], i32* [[CONV_I]], align 4			// CHECK2-NEXT: store i32 [[INC_I]], i32* [[CONV_I]], align 4
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	Show All 36 Lines
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca %struct.S, align 8
	// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
	// CHECK2-NEXT: [[THIS1:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/taskloop_in_reduction_codegen.cpp

	Show First 20 Lines • Show All 588 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2			// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2
	// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4			// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK1: .omp_outlined..9.exit:			// CHECK1: .omp_outlined..9.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	▲ Show 20 Lines • Show All 587 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2			// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2
	// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4			// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4
	// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4			// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]]
	// CHECK2: .omp_outlined..9.exit:			// CHECK2: .omp_outlined..9.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	Show All 32 Lines
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca %struct.S, align 8
	// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8			// CHECK2-NEXT: store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
	// CHECK2-NEXT: [[THIS1:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8			// CHECK2-NEXT: [[THIS1:%.]] = load %struct.S, %struct.S** [[THIS_ADDR]], align 8
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp

	Show First 20 Lines • Show All 588 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK1-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK1-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK1-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK1-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK1-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK1-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK1-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK1-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK1-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK1-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK1-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK1-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK1-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK1-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK1-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK1-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK1-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK1-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK1-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK1-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK1-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK1-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK1-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK1-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK1-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK1-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK1: omp.inner.for.cond.i:			// CHECK1: omp.inner.for.cond.i:
	// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK1: omp.inner.for.body.i:			// CHECK1: omp.inner.for.body.i:
	// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK1-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !14			// CHECK1-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !15
	// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK1-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: .omp_outlined..9.exit:			// CHECK1: .omp_outlined..9.exit:
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK1-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	▲ Show 20 Lines • Show All 586 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6			// CHECK2-NEXT: [[TMP14:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 6
	// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8			// CHECK2-NEXT: [[TMP15:%.]] = load i64, i64 [[TMP14]], align 8
	// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7			// CHECK2-NEXT: [[TMP16:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 7
	// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8			// CHECK2-NEXT: [[TMP17:%.]] = load i64, i64 [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8			// CHECK2-NEXT: [[TMP18:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9			// CHECK2-NEXT: [[TMP20:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 9
	// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8			// CHECK2-NEXT: [[TMP21:%.]] = load i8, i8** [[TMP20]], align 8
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8, i8) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP22:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP22]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i64, i64 [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP25:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP26:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)			// CHECK2-NEXT: [[TMP27:%.]] = bitcast void (i8, ...)* [[TMP25]] to void (i8, i8, i8)
	// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]			// CHECK2-NEXT: call void [[TMP27]](i8* [[TMP26]], i8* [[DOTFIRSTPRIV_PTR_ADDR_I]], i8* [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP28:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP29:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0			// CHECK2-NEXT: [[TMP30:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8			// CHECK2-NEXT: [[TMP31:%.]] = load i32, i32** [[TMP30]], align 8
	// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8			// CHECK2-NEXT: [[TMP32:%.]] = load i8, i8** [[TMP28]], align 8
	// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !13			// CHECK2-NEXT: [[TMP33:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
	// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*			// CHECK2-NEXT: [[TMP34:%.]] = bitcast i32 [[TMP31]] to i8*
	// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP35:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP32]], i8* [[TMP34]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP35]] to i32*
	// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2			// CHECK2-NEXT: [[TMP36:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP22]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8			// CHECK2-NEXT: [[TMP37:%.]] = load i16, i16** [[TMP36]], align 8
	// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2			// CHECK2-NEXT: [[TMP38:%.*]] = mul nuw i64 [[TMP24]], 2
	// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP39:%.]] = udiv exact i64 [[TMP38]], ptrtoint (i16 getelementptr (i16, i16* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]			// CHECK2-NEXT: [[TMP40:%.]] = call i8 @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]], i8* bitcast (i64* @{{reduction_size[.].+[.]}}) #[[ATTR3]]
	// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*			// CHECK2-NEXT: [[TMP41:%.]] = bitcast i8 [[TMP40]] to i64*
	// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8			// CHECK2-NEXT: store i64 [[TMP39]], i64* [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP29]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*			// CHECK2-NEXT: [[TMP43:%.]] = bitcast i16 [[TMP37]] to i8*
	// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]			// CHECK2-NEXT: [[TMP44:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP33]], i8* [[TMP42]], i8* [[TMP43]]) #[[ATTR3]]
	// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*			// CHECK2-NEXT: [[CONV2_I:%.]] = bitcast i8 [[TMP44]] to i16*
	// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !13			// CHECK2-NEXT: [[TMP45:%.]] = load i64, i64 [[DOTLB__ADDR_I]], align 8, !noalias !14
	// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32			// CHECK2-NEXT: [[CONV3_I:%.*]] = trunc i64 [[TMP45]] to i32
	// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13			// CHECK2-NEXT: store i32 [[CONV3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
	// CHECK2: omp.inner.for.cond.i:			// CHECK2: omp.inner.for.cond.i:
	// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP46:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64			// CHECK2-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP46]] to i64
	// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP47:%.]] = load i64, i64 [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]			// CHECK2-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP47]]
	// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]			// CHECK2-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.]], label [[DOTOMP_OUTLINED__9_EXIT:%.]]
	// CHECK2: omp.inner.for.body.i:			// CHECK2: omp.inner.for.body.i:
	// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP48:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[TMP48]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP49:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64			// CHECK2-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP49]] to i64
	// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]			// CHECK2-NEXT: [[ARRAYIDX_I:%.]] = getelementptr inbounds i16, i16 [[CONV2_I]], i64 [[IDXPROM_I]]
	// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !14			// CHECK2-NEXT: [[TMP50:%.]] = load i16, i16 [[ARRAYIDX_I]], align 2, !llvm.access.group !15
	// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32			// CHECK2-NEXT: [[CONV5_I:%.*]] = sext i16 [[TMP50]] to i32
	// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP51:%.]] = load i32, i32 [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]			// CHECK2-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP51]], [[CONV5_I]]
	// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD6_I]], i32* [[CONV_I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: [[TMP52:%.]] = load i32, i32 [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1			// CHECK2-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP52]], 1
	// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !13, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: .omp_outlined..9.exit:			// CHECK2: .omp_outlined..9.exit:
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev			// CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev
	// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {			// CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8			// CHECK2-NEXT: [[THIS_ADDR:%.]] = alloca %struct.S, align 8
	▲ Show 20 Lines • Show All 297 Lines • Show Last 20 Lines

clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 426 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 309 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 307 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 307 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !8			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !8			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !8			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 548 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 548 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !10			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 540 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 540 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !11			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]			// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
	// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK12: omp.dispatch.end:			// CHECK12: omp.dispatch.end:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//			//
	// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK12-SAME: () #[[ATTR5:[0-9]+]] {
	// CHECK12-NEXT: entry:			// CHECK12-NEXT: entry:
	// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK12-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK12-NEXT: ret void			// CHECK12-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp

	Show First 20 Lines • Show All 811 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK1-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK1-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK1-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK1-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK1-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK1-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK1-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK1-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK1-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK1-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK1-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK1-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK1-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK1-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK1-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK1-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK1-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK1-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK1-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK1-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK1-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK1-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK1-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK1-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK1-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK1-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK1-NEXT: ret i32 0			// CHECK1-NEXT: ret i32 0
	//			//
	//			//
	// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK1-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK1-NEXT: entry:			// CHECK1-NEXT: entry:
	// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK1-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 866 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0			// CHECK2-NEXT: [[TMP4:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2			// CHECK2-NEXT: [[TMP5:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0			// CHECK2-NEXT: [[TMP6:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t [[TMP4]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8			// CHECK2-NEXT: [[TMP7:%.]] = load i8, i8** [[TMP6]], align 8
	// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*			// CHECK2-NEXT: [[TMP8:%.]] = bitcast i8 [[TMP7]] to %struct.anon*
	// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1			// CHECK2-NEXT: [[TMP9:%.]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates [[TMP3]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*			// CHECK2-NEXT: [[TMP10:%.]] = bitcast %struct..kmp_privates.t [[TMP9]] to i8*
	// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*			// CHECK2-NEXT: [[TMP11:%.]] = bitcast %struct.kmp_task_t_with_privates [[TMP3]] to i8*
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META2:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
	// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]])			// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
	// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store void (i8, ...) bitcast (void (%struct..kmp_privates.t, i8*) @.omp_task_privates_map. to void (i8, ...)), void (i8, ...)* [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP12:%.]] = load %struct.anon, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP13:%.]] = load void (i8, ...), void (i8, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP14:%.]] = load i8, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)			// CHECK2-NEXT: [[TMP15:%.]] = bitcast void (i8, ...)* [[TMP13]] to void (i8, i8*)
	// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]			// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i8*** [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR5]]
	// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !11			// CHECK2-NEXT: [[TMP16:%.]] = load i8, i8** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
	// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP17:%.]] = getelementptr inbounds [[STRUCT_ANON:%.]], %struct.anon* [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[TMP17]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i8, i8** [[TMP16]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !11			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
	// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*			// CHECK2-NEXT: [[TMP21:%.]] = bitcast i32 [[TMP18]] to i8*
	// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]			// CHECK2-NEXT: [[TMP22:%.]] = call i8 @__kmpc_task_reduction_get_th_data(i32 [[TMP20]], i8* [[TMP19]], i8* [[TMP21]]) #[[ATTR5]]
	// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*			// CHECK2-NEXT: [[CONV_I:%.]] = bitcast i8 [[TMP22]] to i32*
	// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP23:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8			// CHECK2-NEXT: [[TMP24:%.]] = load i8, i8** [[TMP23]], align 8
	// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8			// CHECK2-NEXT: [[TMP25:%.]] = load i8, i8** [[TMP24]], align 8
	// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1			// CHECK2-NEXT: [[TMP26:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 1
	// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8			// CHECK2-NEXT: [[TMP27:%.]] = load i32, i32** [[TMP26]], align 8
	Show All 17 Lines
	// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2			// CHECK2-NEXT: [[TMP41:%.]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon [[TMP12]], i32 0, i32 2
	// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8			// CHECK2-NEXT: [[TMP42:%.]] = load i8, i8** [[TMP41]], align 8
	// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8			// CHECK2-NEXT: [[TMP43:%.]] = load i8, i8** [[TMP42]], align 8
	// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64			// CHECK2-NEXT: [[TMP44:%.]] = ptrtoint i8 [[TMP43]] to i64
	// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64			// CHECK2-NEXT: [[TMP45:%.]] = ptrtoint i8 [[TMP25]] to i64
	// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]			// CHECK2-NEXT: [[TMP46:%.*]] = sub i64 [[TMP44]], [[TMP45]]
	// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)			// CHECK2-NEXT: [[TMP47:%.]] = sdiv exact i64 [[TMP46]], ptrtoint (i8 getelementptr (i8, i8* null, i32 1) to i64)
	// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]			// CHECK2-NEXT: [[TMP48:%.]] = getelementptr i8, i8 [[TMP40]], i64 [[TMP47]]
	// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8 [[TMP4_I]], i8* [[TMP_I]], align 8, !noalias !12
	// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !11			// CHECK2-NEXT: store i8* [[TMP48]], i8** [[TMP4_I]], align 8, !noalias !12
	// CHECK2-NEXT: ret i32 0			// CHECK2-NEXT: ret i32 0
	//			//
	//			//
	// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func			// CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
	// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {			// CHECK2-SAME: (i8* [[TMP0:%.]], i8 [[TMP1:%.*]]) #[[ATTR3]] {
	// CHECK2-NEXT: entry:			// CHECK2-NEXT: entry:
	// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR:%.]] = alloca i8, align 8
	// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8			// CHECK2-NEXT: [[DOTADDR1:%.]] = alloca i8, align 8
	▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1			// CHECK2-NEXT: store i8 [[CONV4]], i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1			// CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i8, i8* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
	// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]			// CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.]] = icmp eq i8 [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP21]]
	// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]			// CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
	// CHECK2: omp.arraycpy.done5:			// CHECK2: omp.arraycpy.done5:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 931 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK1-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK1: omp.dispatch.end:			// CHECK1: omp.dispatch.end:
	// CHECK1-NEXT: ret void			// CHECK1-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK2-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK2: omp.dispatch.end:			// CHECK2: omp.dispatch.end:
	// CHECK2-NEXT: ret void			// CHECK2-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK3-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK3-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK3: omp.dispatch.end:			// CHECK3: omp.dispatch.end:
	// CHECK3-NEXT: ret void			// CHECK3-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK4-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK4-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK4: omp.dispatch.end:			// CHECK4: omp.dispatch.end:
	// CHECK4-NEXT: ret void			// CHECK4-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK5-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK5: omp.dispatch.body:			// CHECK5: omp.dispatch.body:
	// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK5-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK5: omp.inner.for.cond:			// CHECK5: omp.inner.for.cond:
	// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK5: omp.inner.for.body:			// CHECK5: omp.inner.for.body:
	// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK5-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK5-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK5: omp.body.continue:			// CHECK5: omp.body.continue:
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK5: omp.inner.for.inc:			// CHECK5: omp.inner.for.inc:
	// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK5: omp.inner.for.end:			// CHECK5: omp.inner.for.end:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK5: omp.dispatch.inc:			// CHECK5: omp.dispatch.inc:
	// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK5: omp.dispatch.end:			// CHECK5: omp.dispatch.end:
	// CHECK5-NEXT: ret void			// CHECK5-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 728 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9			// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
	// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK6-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK6: omp.dispatch.body:			// CHECK6: omp.dispatch.body:
	// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK6-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK6: omp.inner.for.cond:			// CHECK6: omp.inner.for.cond:
	// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK6: omp.inner.for.body:			// CHECK6: omp.inner.for.body:
	// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK6-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK6-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK6: omp.body.continue:			// CHECK6: omp.body.continue:
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK6: omp.inner.for.inc:			// CHECK6: omp.inner.for.inc:
	// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12			// CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK6: omp.inner.for.end:			// CHECK6: omp.inner.for.end:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK6: omp.dispatch.inc:			// CHECK6: omp.dispatch.inc:
	// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK6: omp.dispatch.end:			// CHECK6: omp.dispatch.end:
	// CHECK6-NEXT: ret void			// CHECK6-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK7: omp.dispatch.end:			// CHECK7: omp.dispatch.end:
	// CHECK7-NEXT: ret void			// CHECK7-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK7-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK7: omp.dispatch.body:			// CHECK7: omp.dispatch.body:
	// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK7-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK7-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK7: omp.inner.for.cond:			// CHECK7: omp.inner.for.cond:
	// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK7: omp.inner.for.body:			// CHECK7: omp.inner.for.body:
	// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK7-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK7-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK7: omp.body.continue:			// CHECK7: omp.body.continue:
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK7: omp.inner.for.inc:			// CHECK7: omp.inner.for.inc:
	// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK7-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK7: omp.inner.for.end:			// CHECK7: omp.inner.for.end:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK7: omp.dispatch.inc:			// CHECK7: omp.dispatch.inc:
	// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK7-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK7: omp.dispatch.end:			// CHECK7: omp.dispatch.end:
	// CHECK7-NEXT: ret void			// CHECK7-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10			// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK8: omp.dispatch.end:			// CHECK8: omp.dispatch.end:
	// CHECK8-NEXT: ret void			// CHECK8-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
	// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK8-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK8-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK8-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK8: omp.dispatch.body:			// CHECK8: omp.dispatch.body:
	// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK8-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK8-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK8: omp.inner.for.cond:			// CHECK8: omp.inner.for.cond:
	// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK8: omp.inner.for.body:			// CHECK8: omp.inner.for.body:
	// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK8-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]			// CHECK8-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP12]]
	// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK8: omp.body.continue:			// CHECK8: omp.body.continue:
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK8: omp.inner.for.inc:			// CHECK8: omp.inner.for.inc:
	// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13			// CHECK8-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK8: omp.inner.for.end:			// CHECK8: omp.inner.for.end:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK8: omp.dispatch.inc:			// CHECK8: omp.dispatch.inc:
	// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK8-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK8: omp.dispatch.end:			// CHECK8: omp.dispatch.end:
	// CHECK8-NEXT: ret void			// CHECK8-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,239 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: br label [[OMP_PRECOND_END]]			// CHECK13-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK13: omp.precond.end:			// CHECK13: omp.precond.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK13-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: br label [[OMP_PRECOND_END]]			// CHECK13-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK13: omp.precond.end:			// CHECK13: omp.precond.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	▲ Show 20 Lines • Show All 755 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK13-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK13-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK13-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK13: omp.dispatch.body:			// CHECK13: omp.dispatch.body:
	// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK13-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK13-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK13-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK13: omp.inner.for.cond:			// CHECK13: omp.inner.for.cond:
	// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK13: omp.inner.for.body:			// CHECK13: omp.inner.for.body:
	// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK13-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK13: omp.body.continue:			// CHECK13: omp.body.continue:
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK13: omp.inner.for.inc:			// CHECK13: omp.inner.for.inc:
	// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK13-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK13: omp.inner.for.end:			// CHECK13: omp.inner.for.end:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK13: omp.dispatch.inc:			// CHECK13: omp.dispatch.inc:
	// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK13-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK13: omp.dispatch.end:			// CHECK13: omp.dispatch.end:
	// CHECK13-NEXT: ret void			// CHECK13-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,239 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK14-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK14-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK14-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: br label [[OMP_PRECOND_END]]			// CHECK14-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK14: omp.precond.end:			// CHECK14: omp.precond.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK14-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK14-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK14-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: br label [[OMP_PRECOND_END]]			// CHECK14-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK14: omp.precond.end:			// CHECK14: omp.precond.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	▲ Show 20 Lines • Show All 755 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK14-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK14-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK14-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK14-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK14-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK14-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK14: omp.dispatch.body:			// CHECK14: omp.dispatch.body:
	// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK14-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK14-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK14-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK14: omp.inner.for.cond:			// CHECK14: omp.inner.for.cond:
	// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK14: omp.inner.for.body:			// CHECK14: omp.inner.for.body:
	// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK14-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK14: omp.body.continue:			// CHECK14: omp.body.continue:
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK14: omp.inner.for.inc:			// CHECK14: omp.inner.for.inc:
	// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK14-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK14-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK14: omp.inner.for.end:			// CHECK14: omp.inner.for.end:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK14: omp.dispatch.inc:			// CHECK14: omp.dispatch.inc:
	// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK14-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK14: omp.dispatch.end:			// CHECK14: omp.dispatch.end:
	// CHECK14-NEXT: ret void			// CHECK14-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,208 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK15-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK15-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK15-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: br label [[OMP_PRECOND_END]]			// CHECK15-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK15: omp.precond.end:			// CHECK15: omp.precond.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK15-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK15-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: br label [[OMP_PRECOND_END]]			// CHECK15-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK15: omp.precond.end:			// CHECK15: omp.precond.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	▲ Show 20 Lines • Show All 726 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
	// CHECK15-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK15-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK15-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK15: omp.dispatch.body:			// CHECK15: omp.dispatch.body:
	// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK15-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK15: omp.inner.for.cond:			// CHECK15: omp.inner.for.cond:
	// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK15: omp.inner.for.body:			// CHECK15: omp.inner.for.body:
	// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK15-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK15: omp.body.continue:			// CHECK15: omp.body.continue:
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK15: omp.inner.for.inc:			// CHECK15: omp.inner.for.inc:
	// CHECK15-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK15-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK15: omp.inner.for.end:			// CHECK15: omp.inner.for.end:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK15: omp.dispatch.inc:			// CHECK15: omp.dispatch.inc:
	// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK15-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK15: omp.dispatch.end:			// CHECK15: omp.dispatch.end:
	// CHECK15-NEXT: ret void			// CHECK15-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,208 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK16-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK16-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK16-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: br label [[OMP_PRECOND_END]]			// CHECK16-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK16: omp.precond.end:			// CHECK16: omp.precond.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK16-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK16-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK16-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: br label [[OMP_PRECOND_END]]			// CHECK16-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK16: omp.precond.end:			// CHECK16: omp.precond.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	▲ Show 20 Lines • Show All 726 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
	// CHECK16-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK16-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK16-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK16-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK16: omp.dispatch.body:			// CHECK16: omp.dispatch.body:
	// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK16-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK16-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK16-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK16: omp.inner.for.cond:			// CHECK16: omp.inner.for.cond:
	// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK16: omp.inner.for.body:			// CHECK16: omp.inner.for.body:
	// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK16-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK16: omp.body.continue:			// CHECK16: omp.body.continue:
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK16: omp.inner.for.inc:			// CHECK16: omp.inner.for.inc:
	// CHECK16-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK16-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK16-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK16: omp.inner.for.end:			// CHECK16: omp.inner.for.end:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK16: omp.dispatch.inc:			// CHECK16: omp.dispatch.inc:
	// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK16-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK16: omp.dispatch.end:			// CHECK16: omp.dispatch.end:
	// CHECK16-NEXT: ret void			// CHECK16-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,239 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK17-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK17-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: br label [[OMP_PRECOND_END]]			// CHECK17-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK17: omp.precond.end:			// CHECK17: omp.precond.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: br label [[OMP_PRECOND_END]]			// CHECK17-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK17: omp.precond.end:			// CHECK17: omp.precond.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	▲ Show 20 Lines • Show All 755 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK17-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK17: omp.dispatch.body:			// CHECK17: omp.dispatch.body:
	// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK17-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK17-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK17: omp.dispatch.inc:			// CHECK17: omp.dispatch.inc:
	// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK17: omp.dispatch.end:			// CHECK17: omp.dispatch.end:
	// CHECK17-NEXT: ret void			// CHECK17-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,239 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK18-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !14			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK18-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK18-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: br label [[OMP_PRECOND_END]]			// CHECK18-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK18: omp.precond.end:			// CHECK18: omp.precond.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !17			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I6]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP21:%.]] = load i32, i32 [[I6]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: br label [[OMP_PRECOND_END]]			// CHECK18-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK18: omp.precond.end:			// CHECK18: omp.precond.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	▲ Show 20 Lines • Show All 755 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !20			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !20			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20			// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK18-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK18: omp.dispatch.body:			// CHECK18: omp.dispatch.body:
	// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !23			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !23			// CHECK18-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23			// CHECK18-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK18: omp.dispatch.inc:			// CHECK18: omp.dispatch.inc:
	// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK18: omp.dispatch.end:			// CHECK18: omp.dispatch.end:
	// CHECK18-NEXT: ret void			// CHECK18-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,208 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK19-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK19-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: br label [[OMP_PRECOND_END]]			// CHECK19-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK19: omp.precond.end:			// CHECK19: omp.precond.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK19-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: br label [[OMP_PRECOND_END]]			// CHECK19-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK19: omp.precond.end:			// CHECK19: omp.precond.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	▲ Show 20 Lines • Show All 726 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK19-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK19: omp.dispatch.body:			// CHECK19: omp.dispatch.body:
	// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK19-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK19-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK19-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK19: omp.dispatch.inc:			// CHECK19: omp.dispatch.inc:
	// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK19: omp.dispatch.end:			// CHECK19: omp.dispatch.end:
	// CHECK19-NEXT: ret void			// CHECK19-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 1,208 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP15:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK20-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK20-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: br label [[OMP_PRECOND_END]]			// CHECK20-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK20: omp.precond.end:			// CHECK20: omp.precond.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP16:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP15]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP17]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]			// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP18]], [[TMP19]]
	// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP20]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP21:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP21]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1			// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1
	// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK20-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: br label [[OMP_PRECOND_END]]			// CHECK20-NEXT: br label [[OMP_PRECOND_END]]
	// CHECK20: omp.precond.end:			// CHECK20: omp.precond.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	▲ Show 20 Lines • Show All 726 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP7:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP6]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]			// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
	// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP12]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1			// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP13]], 1
	// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21			// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//			//
	▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])			// CHECK20-NEXT: [[TMP8:%.]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t @[[GLOB3]], i32 [[TMP7]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
	// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0			// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP8]], 0
	// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK20: omp.dispatch.body:			// CHECK20: omp.dispatch.body:
	// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]			// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
	// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP13:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP13]]
	// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24			// CHECK20-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1			// CHECK20-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP14]], 1
	// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24			// CHECK20-NEXT: store i32 [[ADD1]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK20: omp.dispatch.inc:			// CHECK20: omp.dispatch.inc:
	// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]			// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
	// CHECK20: omp.dispatch.end:			// CHECK20: omp.dispatch.end:
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//			//
	// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg			// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
	// CHECK20-SAME: () #[[ATTR5:[0-9]+]] {			// CHECK20-SAME: () #[[ATTR5:[0-9]+]] {
	// CHECK20-NEXT: entry:			// CHECK20-NEXT: entry:
	// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)			// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
	// CHECK20-NEXT: ret void			// CHECK20-NEXT: ret void
	//			//
	//
	No newline at end of file

clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp

This file has a very large number of changes (4,720 lines). Show File Contents

clang/test/OpenMP/teams_distribute_simd_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 446 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK1-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK1-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK1-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK2-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK2-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK2-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 246 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i32 0, i32 [[TMP17]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i32 0, i32 [[TMP17]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK3-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK3-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK3-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 246 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i32 0, i32 [[TMP17]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [100 x i32], [100 x i32] [[TMP2]], i32 0, i32 [[TMP17]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK4-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1			// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1
	// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK4-NEXT: [[TMP18:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4			// CHECK4-NEXT: [[TMP19:%.]] = load i32, i32 [[TMP18]], align 4
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]])
	// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0			// CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
	▲ Show 20 Lines • Show All 713 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 442 Lines • ▼ Show 20 Lines
	// CHECK17-NEXT: br label [[COND_END]]			// CHECK17-NEXT: br label [[COND_END]]
	// CHECK17: cond.end:			// CHECK17: cond.end:
	// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK17-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK17-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK17: omp.inner.for.cond:			// CHECK17: omp.inner.for.cond:
	// CHECK17-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK17-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK17: omp.inner.for.body:			// CHECK17: omp.inner.for.body:
	// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK17-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK17-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4			// CHECK17-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32			// CHECK17-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32
	// CHECK17-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK17-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4			// CHECK17-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64			// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64
	// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK17-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK17-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4			// CHECK17-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK17: omp.body.continue:			// CHECK17: omp.body.continue:
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK17: omp.inner.for.inc:			// CHECK17: omp.inner.for.inc:
	// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK17-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK17: omp.inner.for.end:			// CHECK17: omp.inner.for.end:
	// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK17: omp.loop.exit:			// CHECK17: omp.loop.exit:
	// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK17-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK17: .omp.final.then:			// CHECK17: .omp.final.then:
	▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
	// CHECK18-NEXT: br label [[COND_END]]			// CHECK18-NEXT: br label [[COND_END]]
	// CHECK18: cond.end:			// CHECK18: cond.end:
	// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK18-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK18-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK18: omp.inner.for.cond:			// CHECK18: omp.inner.for.cond:
	// CHECK18-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK18-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK18: omp.inner.for.body:			// CHECK18: omp.inner.for.body:
	// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK18-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK18-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4			// CHECK18-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32			// CHECK18-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32
	// CHECK18-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK18-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4			// CHECK18-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64			// CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64
	// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK18-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK18-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4			// CHECK18-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK18: omp.body.continue:			// CHECK18: omp.body.continue:
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK18: omp.inner.for.inc:			// CHECK18: omp.inner.for.inc:
	// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK18-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK18-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]			// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
	// CHECK18: omp.inner.for.end:			// CHECK18: omp.inner.for.end:
	// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK18: omp.loop.exit:			// CHECK18: omp.loop.exit:
	// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK18-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK18: .omp.final.then:			// CHECK18: .omp.final.then:
	▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
	// CHECK19-NEXT: br label [[COND_END]]			// CHECK19-NEXT: br label [[COND_END]]
	// CHECK19: cond.end:			// CHECK19: cond.end:
	// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK19-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK19-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK19: omp.inner.for.cond:			// CHECK19: omp.inner.for.cond:
	// CHECK19-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK19-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK19: omp.inner.for.body:			// CHECK19: omp.inner.for.body:
	// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK19-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK19-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4			// CHECK19-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32			// CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32
	// CHECK19-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK19-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4			// CHECK19-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP10]]			// CHECK19-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP10]]
	// CHECK19-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4			// CHECK19-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK19: omp.body.continue:			// CHECK19: omp.body.continue:
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK19: omp.inner.for.inc:			// CHECK19: omp.inner.for.inc:
	// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK19-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK19: omp.inner.for.end:			// CHECK19: omp.inner.for.end:
	// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK19: omp.loop.exit:			// CHECK19: omp.loop.exit:
	// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK19-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK19-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK19-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK19-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK19-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK19: .omp.final.then:			// CHECK19: .omp.final.then:
	▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
	// CHECK20-NEXT: br label [[COND_END]]			// CHECK20-NEXT: br label [[COND_END]]
	// CHECK20: cond.end:			// CHECK20: cond.end:
	// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK20-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK20-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK20: omp.inner.for.cond:			// CHECK20: omp.inner.for.cond:
	// CHECK20-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK20-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK20: omp.inner.for.body:			// CHECK20: omp.inner.for.body:
	// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK20-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK20-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4			// CHECK20-NEXT: [[TMP9:%.]] = load float, float [[B]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32			// CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32
	// CHECK20-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK20-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4			// CHECK20-NEXT: [[TMP10:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP10]]			// CHECK20-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP10]]
	// CHECK20-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4			// CHECK20-NEXT: store i32 [[CONV]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK20: omp.body.continue:			// CHECK20: omp.body.continue:
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK20: omp.inner.for.inc:			// CHECK20: omp.inner.for.inc:
	// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK20-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1			// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
	// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK20-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK20: omp.inner.for.end:			// CHECK20: omp.inner.for.end:
	// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK20: omp.loop.exit:			// CHECK20: omp.loop.exit:
	// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK20-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK20-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0			// CHECK20-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
	// CHECK20-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK20-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK20: .omp.final.then:			// CHECK20: .omp.final.then:
	▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
	// CHECK21-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK21-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK21-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 8			// CHECK21-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1			// CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
	// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK21: omp_if.then:			// CHECK21: omp_if.then:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK21: omp.inner.for.cond:			// CHECK21: omp.inner.for.cond:
	// CHECK21-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK21: omp.inner.for.body:			// CHECK21: omp.inner.for.body:
	// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK21-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK21-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !4, !llvm.access.group !3			// CHECK21-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !5, !llvm.access.group !4
	// CHECK21-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32			// CHECK21-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32
	// CHECK21-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK21-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK21-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK21-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK21-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4			// CHECK21-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK21: omp.body.continue:			// CHECK21: omp.body.continue:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK21: omp.inner.for.inc:			// CHECK21: omp.inner.for.inc:
	// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK21-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK21: omp.inner.for.end:			// CHECK21: omp.inner.for.end:
	// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK21-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK21: omp_if.else:			// CHECK21: omp_if.else:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]
	// CHECK21: omp.inner.for.cond4:			// CHECK21: omp.inner.for.cond4:
	// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK21-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK21-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	Show All 13 Lines
	// CHECK21-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX13]], align 4			// CHECK21-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX13]], align 4
	// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]			// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]
	// CHECK21: omp.body.continue14:			// CHECK21: omp.body.continue14:
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]
	// CHECK21: omp.inner.for.inc15:			// CHECK21: omp.inner.for.inc15:
	// CHECK21-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK21-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK21-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK21-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4			// CHECK21-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4
	// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK21-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK21: omp.inner.for.end17:			// CHECK21: omp.inner.for.end17:
	// CHECK21-NEXT: br label [[OMP_IF_END]]			// CHECK21-NEXT: br label [[OMP_IF_END]]
	// CHECK21: omp_if.end:			// CHECK21: omp_if.end:
	// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK21: omp.loop.exit:			// CHECK21: omp.loop.exit:
	// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK21-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK21-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK21-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK21-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
	▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
	// CHECK22-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK22-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK22-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 8			// CHECK22-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1			// CHECK22-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
	// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK22-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK22: omp_if.then:			// CHECK22: omp_if.then:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK22: omp.inner.for.cond:			// CHECK22: omp.inner.for.cond:
	// CHECK22-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK22-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK22-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK22: omp.inner.for.body:			// CHECK22: omp.inner.for.body:
	// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK22-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK22-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK22-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK22-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !4, !llvm.access.group !3			// CHECK22-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !5, !llvm.access.group !4
	// CHECK22-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32			// CHECK22-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32
	// CHECK22-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK22-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK22-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK22-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK22-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4			// CHECK22-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK22: omp.body.continue:			// CHECK22: omp.body.continue:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK22: omp.inner.for.inc:			// CHECK22: omp.inner.for.inc:
	// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK22-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK22-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK22: omp.inner.for.end:			// CHECK22: omp.inner.for.end:
	// CHECK22-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK22-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK22: omp_if.else:			// CHECK22: omp_if.else:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]
	// CHECK22: omp.inner.for.cond4:			// CHECK22: omp.inner.for.cond4:
	// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK22-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK22-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK22-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	Show All 13 Lines
	// CHECK22-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX13]], align 4			// CHECK22-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX13]], align 4
	// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]			// CHECK22-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]
	// CHECK22: omp.body.continue14:			// CHECK22: omp.body.continue14:
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]
	// CHECK22: omp.inner.for.inc15:			// CHECK22: omp.inner.for.inc15:
	// CHECK22-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK22-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK22-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK22-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4			// CHECK22-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4
	// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK22-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK22: omp.inner.for.end17:			// CHECK22: omp.inner.for.end17:
	// CHECK22-NEXT: br label [[OMP_IF_END]]			// CHECK22-NEXT: br label [[OMP_IF_END]]
	// CHECK22: omp_if.end:			// CHECK22: omp_if.end:
	// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK22-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK22: omp.loop.exit:			// CHECK22: omp.loop.exit:
	// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK22-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK22-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK22-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK22-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK22-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
	▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
	// CHECK23-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK23-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 4			// CHECK23-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 4
	// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1			// CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
	// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK23: omp_if.then:			// CHECK23: omp_if.then:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK23: omp.inner.for.cond:			// CHECK23: omp.inner.for.cond:
	// CHECK23-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK23: omp.inner.for.body:			// CHECK23: omp.inner.for.body:
	// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK23-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK23-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !5, !llvm.access.group !4			// CHECK23-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !6, !llvm.access.group !5
	// CHECK23-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32			// CHECK23-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32
	// CHECK23-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK23-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK23-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK23-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK23-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4			// CHECK23-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK23: omp.body.continue:			// CHECK23: omp.body.continue:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK23: omp.inner.for.inc:			// CHECK23: omp.inner.for.inc:
	// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK23-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK23: omp.inner.for.end:			// CHECK23: omp.inner.for.end:
	// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK23-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK23: omp_if.else:			// CHECK23: omp_if.else:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]
	// CHECK23: omp.inner.for.cond4:			// CHECK23: omp.inner.for.cond4:
	// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK23-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	Show All 12 Lines
	// CHECK23-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX12]], align 4			// CHECK23-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX12]], align 4
	// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]]			// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]]
	// CHECK23: omp.body.continue13:			// CHECK23: omp.body.continue13:
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC14:%.*]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC14:%.*]]
	// CHECK23: omp.inner.for.inc14:			// CHECK23: omp.inner.for.inc14:
	// CHECK23-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK23-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK23-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK23-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4			// CHECK23-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4
	// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK23-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK23: omp.inner.for.end16:			// CHECK23: omp.inner.for.end16:
	// CHECK23-NEXT: br label [[OMP_IF_END]]			// CHECK23-NEXT: br label [[OMP_IF_END]]
	// CHECK23: omp_if.end:			// CHECK23: omp_if.end:
	// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK23: omp.loop.exit:			// CHECK23: omp.loop.exit:
	// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK23-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK23-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK23-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK23-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
	▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
	// CHECK24-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK24-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 4			// CHECK24-NEXT: [[TMP6:%.]] = load i8, i8 [[CONV]], align 4
	// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1			// CHECK24-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
	// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK24-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK24: omp_if.then:			// CHECK24: omp_if.then:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK24: omp.inner.for.cond:			// CHECK24: omp.inner.for.cond:
	// CHECK24-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]			// CHECK24-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
	// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK24-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK24: omp.inner.for.body:			// CHECK24: omp.inner.for.body:
	// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1			// CHECK24-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
	// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK24-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1			// CHECK24-NEXT: [[B:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 1
	// CHECK24-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !5, !llvm.access.group !4			// CHECK24-NEXT: [[TMP10:%.]] = load float, float [[B]], align 4, !nontemporal !6, !llvm.access.group !5
	// CHECK24-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32			// CHECK24-NEXT: [[CONV2:%.*]] = fptosi float [[TMP10]] to i32
	// CHECK24-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0			// CHECK24-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS [[TMP0]], i32 0, i32 0
	// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4			// CHECK24-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK24-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK24-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4			// CHECK24-NEXT: store i32 [[CONV2]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK24: omp.body.continue:			// CHECK24: omp.body.continue:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK24: omp.inner.for.inc:			// CHECK24: omp.inner.for.inc:
	// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK24-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK24-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK24: omp.inner.for.end:			// CHECK24: omp.inner.for.end:
	// CHECK24-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK24-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK24: omp_if.else:			// CHECK24: omp_if.else:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND4:%.*]]
	// CHECK24: omp.inner.for.cond4:			// CHECK24: omp.inner.for.cond4:
	// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK24-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK24-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]			// CHECK24-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
	Show All 12 Lines
	// CHECK24-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX12]], align 4			// CHECK24-NEXT: store i32 [[CONV10]], i32* [[ARRAYIDX12]], align 4
	// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]]			// CHECK24-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]]
	// CHECK24: omp.body.continue13:			// CHECK24: omp.body.continue13:
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC14:%.*]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_INC14:%.*]]
	// CHECK24: omp.inner.for.inc14:			// CHECK24: omp.inner.for.inc14:
	// CHECK24-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK24-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK24-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK24-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4			// CHECK24-NEXT: store i32 [[ADD15]], i32* [[DOTOMP_IV]], align 4
	// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK24-NEXT: br label [[OMP_INNER_FOR_COND4]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK24: omp.inner.for.end16:			// CHECK24: omp.inner.for.end16:
	// CHECK24-NEXT: br label [[OMP_IF_END]]			// CHECK24-NEXT: br label [[OMP_IF_END]]
	// CHECK24: omp_if.end:			// CHECK24: omp_if.end:
	// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK24-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK24: omp.loop.exit:			// CHECK24: omp.loop.exit:
	// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK24-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK24-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK24-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK24-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0			// CHECK24-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
	▲ Show 20 Lines • Show All 804 Lines • ▼ Show 20 Lines
	// CHECK33-NEXT: br label [[COND_END]]			// CHECK33-NEXT: br label [[COND_END]]
	// CHECK33: cond.end:			// CHECK33: cond.end:
	// CHECK33-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK33-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK33-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK33-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK33-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK33-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK33-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK33-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK33: omp.inner.for.cond:			// CHECK33: omp.inner.for.cond:
	// CHECK33-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK33-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK33-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK33-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK33-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK33-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK33: omp.inner.for.body:			// CHECK33: omp.inner.for.body:
	// CHECK33-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK33-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK33-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK33-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK33-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK33-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK33-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK33-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK33-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK33-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK33-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK33-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK33: omp.body.continue:			// CHECK33: omp.body.continue:
	// CHECK33-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK33-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK33: omp.inner.for.inc:			// CHECK33: omp.inner.for.inc:
	// CHECK33-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK33-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK33-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK33-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK33-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK33: omp.inner.for.end:			// CHECK33: omp.inner.for.end:
	// CHECK33-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK33-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK33: omp.loop.exit:			// CHECK33: omp.loop.exit:
	// CHECK33-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK33-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK33-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK33-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK33-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK33-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK33-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK33-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK33-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK33-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
	// CHECK33-NEXT: br label [[COND_END]]			// CHECK33-NEXT: br label [[COND_END]]
	// CHECK33: cond.end:			// CHECK33: cond.end:
	// CHECK33-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK33-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK33-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK33-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK33-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK33-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK33-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK33-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK33: omp.inner.for.cond:			// CHECK33: omp.inner.for.cond:
	// CHECK33-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK33-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK33-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK33-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK33-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK33-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK33: omp.inner.for.body:			// CHECK33: omp.inner.for.body:
	// CHECK33-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK33-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK33-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK33-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK33-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK33-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK33-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK33-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK33-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK33-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK33-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK33-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK33-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK33: omp.body.continue:			// CHECK33: omp.body.continue:
	// CHECK33-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK33-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK33: omp.inner.for.inc:			// CHECK33: omp.inner.for.inc:
	// CHECK33-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK33-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK33-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK33-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK33-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK33-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK33: omp.inner.for.end:			// CHECK33: omp.inner.for.end:
	// CHECK33-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK33-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK33: omp.loop.exit:			// CHECK33: omp.loop.exit:
	// CHECK33-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK33-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK33-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK33-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK33-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK33-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK33-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK33-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK33: .omp.final.then:			// CHECK33: .omp.final.then:
	▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines
	// CHECK34-NEXT: br label [[COND_END]]			// CHECK34-NEXT: br label [[COND_END]]
	// CHECK34: cond.end:			// CHECK34: cond.end:
	// CHECK34-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK34-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK34-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK34-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK34-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK34-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK34-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK34-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK34: omp.inner.for.cond:			// CHECK34: omp.inner.for.cond:
	// CHECK34-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK34-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK34-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK34-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK34-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK34-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK34: omp.inner.for.body:			// CHECK34: omp.inner.for.body:
	// CHECK34-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK34-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK34-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK34-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK34-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK34-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK34-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK34-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK34-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK34-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK34-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK34-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK34: omp.body.continue:			// CHECK34: omp.body.continue:
	// CHECK34-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK34-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK34: omp.inner.for.inc:			// CHECK34: omp.inner.for.inc:
	// CHECK34-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK34-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK34-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK34-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK34-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK34: omp.inner.for.end:			// CHECK34: omp.inner.for.end:
	// CHECK34-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK34-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK34: omp.loop.exit:			// CHECK34: omp.loop.exit:
	// CHECK34-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK34-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK34-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK34-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK34-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK34-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK34-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK34-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK34-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK34-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
	// CHECK34-NEXT: br label [[COND_END]]			// CHECK34-NEXT: br label [[COND_END]]
	// CHECK34: cond.end:			// CHECK34: cond.end:
	// CHECK34-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK34-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK34-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK34-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK34-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK34-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK34-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK34-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK34: omp.inner.for.cond:			// CHECK34: omp.inner.for.cond:
	// CHECK34-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK34-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK34-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK34-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK34-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK34-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK34: omp.inner.for.body:			// CHECK34: omp.inner.for.body:
	// CHECK34-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK34-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK34-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK34-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK34-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK34-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK34-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK34-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK34-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK34-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK34-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK34-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK34-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK34: omp.body.continue:			// CHECK34: omp.body.continue:
	// CHECK34-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK34-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK34: omp.inner.for.inc:			// CHECK34: omp.inner.for.inc:
	// CHECK34-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK34-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK34-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK34-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK34-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11
	// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK34-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
	// CHECK34: omp.inner.for.end:			// CHECK34: omp.inner.for.end:
	// CHECK34-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK34-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK34: omp.loop.exit:			// CHECK34: omp.loop.exit:
	// CHECK34-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK34-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK34-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK34-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK34-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK34-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK34-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK34-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK34: .omp.final.then:			// CHECK34: .omp.final.then:
	▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
	// CHECK35-NEXT: br label [[COND_END]]			// CHECK35-NEXT: br label [[COND_END]]
	// CHECK35: cond.end:			// CHECK35: cond.end:
	// CHECK35-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK35-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK35-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK35-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK35-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK35-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK35-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK35-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK35: omp.inner.for.cond:			// CHECK35: omp.inner.for.cond:
	// CHECK35-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK35-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK35-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK35-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK35-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK35-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK35: omp.inner.for.body:			// CHECK35: omp.inner.for.body:
	// CHECK35-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK35-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK35-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK35-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK35-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK35-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK35-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK35-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK35-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK35-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK35-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK35-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK35: omp.body.continue:			// CHECK35: omp.body.continue:
	// CHECK35-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK35-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK35: omp.inner.for.inc:			// CHECK35: omp.inner.for.inc:
	// CHECK35-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK35-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK35-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK35-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK35-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK35: omp.inner.for.end:			// CHECK35: omp.inner.for.end:
	// CHECK35-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK35-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK35: omp.loop.exit:			// CHECK35: omp.loop.exit:
	// CHECK35-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK35-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK35-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK35-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK35-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK35-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK35-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK35-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK35-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK35-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
	// CHECK35-NEXT: br label [[COND_END]]			// CHECK35-NEXT: br label [[COND_END]]
	// CHECK35: cond.end:			// CHECK35: cond.end:
	// CHECK35-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK35-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK35-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK35-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK35-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK35-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK35-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK35-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK35: omp.inner.for.cond:			// CHECK35: omp.inner.for.cond:
	// CHECK35-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK35-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK35-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK35-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK35-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK35-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK35: omp.inner.for.body:			// CHECK35: omp.inner.for.body:
	// CHECK35-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK35-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK35-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK35-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK35-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK35-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK35-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK35-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK35-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK35-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK35-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK35-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK35: omp.body.continue:			// CHECK35: omp.body.continue:
	// CHECK35-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK35-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK35: omp.inner.for.inc:			// CHECK35: omp.inner.for.inc:
	// CHECK35-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK35-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK35-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK35-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK35-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK35-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK35: omp.inner.for.end:			// CHECK35: omp.inner.for.end:
	// CHECK35-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK35-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK35: omp.loop.exit:			// CHECK35: omp.loop.exit:
	// CHECK35-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK35-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK35-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK35-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK35-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK35-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK35-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK35-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK35: .omp.final.then:			// CHECK35: .omp.final.then:
	▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
	// CHECK36-NEXT: br label [[COND_END]]			// CHECK36-NEXT: br label [[COND_END]]
	// CHECK36: cond.end:			// CHECK36: cond.end:
	// CHECK36-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK36-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK36-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK36-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK36-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK36-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK36-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK36-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK36: omp.inner.for.cond:			// CHECK36: omp.inner.for.cond:
	// CHECK36-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK36-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK36-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK36-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK36-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK36-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK36: omp.inner.for.body:			// CHECK36: omp.inner.for.body:
	// CHECK36-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK36-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK36-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK36-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK36-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK36-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK36-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK36-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK36-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK36-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK36-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK36-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK36: omp.body.continue:			// CHECK36: omp.body.continue:
	// CHECK36-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK36-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK36: omp.inner.for.inc:			// CHECK36: omp.inner.for.inc:
	// CHECK36-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK36-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK36-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK36-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK36-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK36: omp.inner.for.end:			// CHECK36: omp.inner.for.end:
	// CHECK36-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK36-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK36: omp.loop.exit:			// CHECK36: omp.loop.exit:
	// CHECK36-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK36-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK36-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK36-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK36-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK36-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK36-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK36-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK36-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK36-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
	// CHECK36-NEXT: br label [[COND_END]]			// CHECK36-NEXT: br label [[COND_END]]
	// CHECK36: cond.end:			// CHECK36: cond.end:
	// CHECK36-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK36-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK36-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK36-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK36-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK36-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK36-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK36-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK36: omp.inner.for.cond:			// CHECK36: omp.inner.for.cond:
	// CHECK36-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK36-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK36-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK36-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK36-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK36-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK36: omp.inner.for.body:			// CHECK36: omp.inner.for.body:
	// CHECK36-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK36-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK36-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK36-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK36-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK36-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK36-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK36-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK36-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK36-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK36-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK36-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK36: omp.body.continue:			// CHECK36: omp.body.continue:
	// CHECK36-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK36-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK36: omp.inner.for.inc:			// CHECK36: omp.inner.for.inc:
	// CHECK36-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK36-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK36-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK36-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK36-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK36-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK36: omp.inner.for.end:			// CHECK36: omp.inner.for.end:
	// CHECK36-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK36-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK36: omp.loop.exit:			// CHECK36: omp.loop.exit:
	// CHECK36-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK36-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK36-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK36-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK36-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK36-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK36-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK36-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK36: .omp.final.then:			// CHECK36: .omp.final.then:
	▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
	// CHECK37-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK37-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK37-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK37-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK37-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8			// CHECK37-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK37-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK37-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK37-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK37-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK37: omp_if.then:			// CHECK37: omp_if.then:
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK37: omp.inner.for.cond:			// CHECK37: omp.inner.for.cond:
	// CHECK37-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK37-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK37-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK37-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK37-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK37: omp.inner.for.body:			// CHECK37: omp.inner.for.body:
	// CHECK37-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK37-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK37-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK37-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK37-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK37-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4			// CHECK37-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK37-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK37-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK37-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK37-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK37-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK37-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK37: omp.body.continue:			// CHECK37: omp.body.continue:
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK37: omp.inner.for.inc:			// CHECK37: omp.inner.for.inc:
	// CHECK37-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK37-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK37-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK37-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK37: omp.inner.for.end:			// CHECK37: omp.inner.for.end:
	// CHECK37-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK37-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK37: omp_if.else:			// CHECK37: omp_if.else:
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
	// CHECK37: omp.inner.for.cond8:			// CHECK37: omp.inner.for.cond8:
	// CHECK37-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK37-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK37-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK37-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK37-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	Show All 9 Lines
	// CHECK37-NEXT: store i32 0, i32* [[ARRAYIDX14]], align 4			// CHECK37-NEXT: store i32 0, i32* [[ARRAYIDX14]], align 4
	// CHECK37-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK37-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK37: omp.body.continue15:			// CHECK37: omp.body.continue15:
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK37: omp.inner.for.inc16:			// CHECK37: omp.inner.for.inc16:
	// CHECK37-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK37-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK37-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK37-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK37-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK37: omp.inner.for.end18:			// CHECK37: omp.inner.for.end18:
	// CHECK37-NEXT: br label [[OMP_IF_END]]			// CHECK37-NEXT: br label [[OMP_IF_END]]
	// CHECK37: omp_if.end:			// CHECK37: omp_if.end:
	// CHECK37-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK37-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK37: omp.loop.exit:			// CHECK37: omp.loop.exit:
	// CHECK37-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK37-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK37-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK37-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK37-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK37-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
	// CHECK37-NEXT: br label [[COND_END]]			// CHECK37-NEXT: br label [[COND_END]]
	// CHECK37: cond.end:			// CHECK37: cond.end:
	// CHECK37-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK37-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK37-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK37-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK37-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK37-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK37-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK37-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK37: omp.inner.for.cond:			// CHECK37: omp.inner.for.cond:
	// CHECK37-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK37-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK37-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK37-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK37-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK37: omp.inner.for.body:			// CHECK37: omp.inner.for.body:
	// CHECK37-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK37-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK37-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK37-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK37-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK37-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK37-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK37-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK37-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK37-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK37-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK37-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK37-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK37: omp.body.continue:			// CHECK37: omp.body.continue:
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK37: omp.inner.for.inc:			// CHECK37: omp.inner.for.inc:
	// CHECK37-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK37-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK37-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK37-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK37-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK37-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK37: omp.inner.for.end:			// CHECK37: omp.inner.for.end:
	// CHECK37-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK37-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK37: omp.loop.exit:			// CHECK37: omp.loop.exit:
	// CHECK37-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK37-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK37-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK37-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK37-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK37-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK37-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK37-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK37: .omp.final.then:			// CHECK37: .omp.final.then:
	▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
	// CHECK38-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK38-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK38-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK38-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK38-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8			// CHECK38-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 8
	// CHECK38-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK38-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK38-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK38-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK38: omp_if.then:			// CHECK38: omp_if.then:
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK38: omp.inner.for.cond:			// CHECK38: omp.inner.for.cond:
	// CHECK38-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK38-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK38-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK38-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK38-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK38: omp.inner.for.body:			// CHECK38: omp.inner.for.body:
	// CHECK38-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK38-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK38-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK38-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK38-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK38-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4			// CHECK38-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64			// CHECK38-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
	// CHECK38-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK38-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK38-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK38-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK38-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK38: omp.body.continue:			// CHECK38: omp.body.continue:
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK38: omp.inner.for.inc:			// CHECK38: omp.inner.for.inc:
	// CHECK38-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK38-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK38-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK38-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
	// CHECK38: omp.inner.for.end:			// CHECK38: omp.inner.for.end:
	// CHECK38-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK38-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK38: omp_if.else:			// CHECK38: omp_if.else:
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
	// CHECK38: omp.inner.for.cond8:			// CHECK38: omp.inner.for.cond8:
	// CHECK38-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK38-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK38-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK38-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK38-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	Show All 9 Lines
	// CHECK38-NEXT: store i32 0, i32* [[ARRAYIDX14]], align 4			// CHECK38-NEXT: store i32 0, i32* [[ARRAYIDX14]], align 4
	// CHECK38-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]			// CHECK38-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]]
	// CHECK38: omp.body.continue15:			// CHECK38: omp.body.continue15:
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_INC16:%.*]]
	// CHECK38: omp.inner.for.inc16:			// CHECK38: omp.inner.for.inc16:
	// CHECK38-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK38-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK38-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK38-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4			// CHECK38-NEXT: store i32 [[ADD17]], i32* [[DOTOMP_IV]], align 4
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP9:![0-9]+]]
	// CHECK38: omp.inner.for.end18:			// CHECK38: omp.inner.for.end18:
	// CHECK38-NEXT: br label [[OMP_IF_END]]			// CHECK38-NEXT: br label [[OMP_IF_END]]
	// CHECK38: omp_if.end:			// CHECK38: omp_if.end:
	// CHECK38-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK38-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK38: omp.loop.exit:			// CHECK38: omp.loop.exit:
	// CHECK38-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK38-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK38-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK38-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK38-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK38-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
	// CHECK38-NEXT: br label [[COND_END]]			// CHECK38-NEXT: br label [[COND_END]]
	// CHECK38: cond.end:			// CHECK38: cond.end:
	// CHECK38-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK38-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK38-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK38-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK38-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK38-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK38-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK38-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK38: omp.inner.for.cond:			// CHECK38: omp.inner.for.cond:
	// CHECK38-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK38-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK38-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK38-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK38-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK38: omp.inner.for.body:			// CHECK38: omp.inner.for.body:
	// CHECK38-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK38-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK38-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK38-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK38-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK38-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK38-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK38-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK38-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK38-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK38-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK38-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK38-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK38: omp.body.continue:			// CHECK38: omp.body.continue:
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK38: omp.inner.for.inc:			// CHECK38: omp.inner.for.inc:
	// CHECK38-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK38-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK38-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK38-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK38-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK38-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK38: omp.inner.for.end:			// CHECK38: omp.inner.for.end:
	// CHECK38-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK38-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK38: omp.loop.exit:			// CHECK38: omp.loop.exit:
	// CHECK38-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK38-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK38-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK38-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK38-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK38-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK38-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK38-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK38: .omp.final.then:			// CHECK38: .omp.final.then:
	▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Lines
	// CHECK39-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK39-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK39-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK39-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK39-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 4			// CHECK39-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 4
	// CHECK39-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK39-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK39-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK39-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK39: omp_if.then:			// CHECK39: omp_if.then:
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK39: omp.inner.for.cond:			// CHECK39: omp.inner.for.cond:
	// CHECK39-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK39-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK39-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK39-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK39-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK39: omp.inner.for.body:			// CHECK39: omp.inner.for.body:
	// CHECK39-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK39-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK39-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK39-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK39-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK39-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4			// CHECK39-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP18]]			// CHECK39-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP18]]
	// CHECK39-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK39-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK39-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK39: omp.body.continue:			// CHECK39: omp.body.continue:
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK39: omp.inner.for.inc:			// CHECK39: omp.inner.for.inc:
	// CHECK39-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK39-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK39-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK39-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK39: omp.inner.for.end:			// CHECK39: omp.inner.for.end:
	// CHECK39-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK39-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK39: omp_if.else:			// CHECK39: omp_if.else:
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
	// CHECK39: omp.inner.for.cond8:			// CHECK39: omp.inner.for.cond8:
	// CHECK39-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK39-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK39-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK39-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK39-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK39-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.]], label [[OMP_INNER_FOR_END17:%.]]			// CHECK39-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.]], label [[OMP_INNER_FOR_END17:%.]]
	// CHECK39: omp.inner.for.body10:			// CHECK39: omp.inner.for.body10:
	// CHECK39-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK39-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP22]], 1			// CHECK39-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP22]], 1
	// CHECK39-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]			// CHECK39-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]
	// CHECK39-NEXT: store i32 [[ADD12]], i32* [[I4]], align 4			// CHECK39-NEXT: store i32 [[ADD12]], i32* [[I4]], align 4
	// CHECK39-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4			// CHECK39-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4
	// CHECK39-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP23]]			// CHECK39-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP23]]
	// CHECK39-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4			// CHECK39-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4
	// CHECK39-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]			// CHECK39-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]
	// CHECK39: omp.body.continue14:			// CHECK39: omp.body.continue14:
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]
	// CHECK39: omp.inner.for.inc15:			// CHECK39: omp.inner.for.inc15:
	// CHECK39-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK39-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK39-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK39-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4			// CHECK39-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK39: omp.inner.for.end17:			// CHECK39: omp.inner.for.end17:
	// CHECK39-NEXT: br label [[OMP_IF_END]]			// CHECK39-NEXT: br label [[OMP_IF_END]]
	// CHECK39: omp_if.end:			// CHECK39: omp_if.end:
	// CHECK39-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK39-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK39: omp.loop.exit:			// CHECK39: omp.loop.exit:
	// CHECK39-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK39-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK39-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK39-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK39-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK39-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
	// CHECK39-NEXT: br label [[COND_END]]			// CHECK39-NEXT: br label [[COND_END]]
	// CHECK39: cond.end:			// CHECK39: cond.end:
	// CHECK39-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK39-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK39-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK39-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK39-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK39-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK39-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK39-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK39: omp.inner.for.cond:			// CHECK39: omp.inner.for.cond:
	// CHECK39-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK39-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK39-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK39-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK39-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK39: omp.inner.for.body:			// CHECK39: omp.inner.for.body:
	// CHECK39-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK39-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK39-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK39-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK39-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK39-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK39-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK39-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK39-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK39-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK39-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK39: omp.body.continue:			// CHECK39: omp.body.continue:
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK39: omp.inner.for.inc:			// CHECK39: omp.inner.for.inc:
	// CHECK39-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK39-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK39-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK39-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK39-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK39-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK39: omp.inner.for.end:			// CHECK39: omp.inner.for.end:
	// CHECK39-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK39-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK39: omp.loop.exit:			// CHECK39: omp.loop.exit:
	// CHECK39-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK39-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK39-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK39-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK39-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK39-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK39-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK39-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK39: .omp.final.then:			// CHECK39: .omp.final.then:
	▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Lines
	// CHECK40-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK40-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK40-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK40-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK40-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 4			// CHECK40-NEXT: [[TMP14:%.]] = load i8, i8 [[CONV]], align 4
	// CHECK40-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1			// CHECK40-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1
	// CHECK40-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]			// CHECK40-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.]], label [[OMP_IF_ELSE:%.]]
	// CHECK40: omp_if.then:			// CHECK40: omp_if.then:
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK40: omp.inner.for.cond:			// CHECK40: omp.inner.for.cond:
	// CHECK40-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK40-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK40-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK40-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK40-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK40: omp.inner.for.body:			// CHECK40: omp.inner.for.body:
	// CHECK40-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1			// CHECK40-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1
	// CHECK40-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK40-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK40-NEXT: store i32 [[ADD]], i32* [[I4]], align 4			// CHECK40-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4			// CHECK40-NEXT: [[TMP18:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP18]]			// CHECK40-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP18]]
	// CHECK40-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK40-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK40-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK40: omp.body.continue:			// CHECK40: omp.body.continue:
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK40: omp.inner.for.inc:			// CHECK40: omp.inner.for.inc:
	// CHECK40-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1			// CHECK40-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
	// CHECK40-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4			// CHECK40-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK40: omp.inner.for.end:			// CHECK40: omp.inner.for.end:
	// CHECK40-NEXT: br label [[OMP_IF_END:%.*]]			// CHECK40-NEXT: br label [[OMP_IF_END:%.*]]
	// CHECK40: omp_if.else:			// CHECK40: omp_if.else:
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]]
	// CHECK40: omp.inner.for.cond8:			// CHECK40: omp.inner.for.cond8:
	// CHECK40-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP20:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK40-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK40-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK40-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]			// CHECK40-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]]
	// CHECK40-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.]], label [[OMP_INNER_FOR_END17:%.]]			// CHECK40-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.]], label [[OMP_INNER_FOR_END17:%.]]
	// CHECK40: omp.inner.for.body10:			// CHECK40: omp.inner.for.body10:
	// CHECK40-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK40-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP22]], 1			// CHECK40-NEXT: [[MUL11:%.*]] = mul nsw i32 [[TMP22]], 1
	// CHECK40-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]			// CHECK40-NEXT: [[ADD12:%.*]] = add nsw i32 0, [[MUL11]]
	// CHECK40-NEXT: store i32 [[ADD12]], i32* [[I4]], align 4			// CHECK40-NEXT: store i32 [[ADD12]], i32* [[I4]], align 4
	// CHECK40-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4			// CHECK40-NEXT: [[TMP23:%.]] = load i32, i32 [[I4]], align 4
	// CHECK40-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP23]]			// CHECK40-NEXT: [[ARRAYIDX13:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP23]]
	// CHECK40-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4			// CHECK40-NEXT: store i32 0, i32* [[ARRAYIDX13]], align 4
	// CHECK40-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]			// CHECK40-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]]
	// CHECK40: omp.body.continue14:			// CHECK40: omp.body.continue14:
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_INC15:%.*]]
	// CHECK40: omp.inner.for.inc15:			// CHECK40: omp.inner.for.inc15:
	// CHECK40-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK40-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP24]], 1			// CHECK40-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP24]], 1
	// CHECK40-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4			// CHECK40-NEXT: store i32 [[ADD16]], i32* [[DOTOMP_IV]], align 4
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP7:![0-9]+]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK40: omp.inner.for.end17:			// CHECK40: omp.inner.for.end17:
	// CHECK40-NEXT: br label [[OMP_IF_END]]			// CHECK40-NEXT: br label [[OMP_IF_END]]
	// CHECK40: omp_if.end:			// CHECK40: omp_if.end:
	// CHECK40-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK40-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK40: omp.loop.exit:			// CHECK40: omp.loop.exit:
	// CHECK40-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK40-NEXT: [[TMP25:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK40-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4			// CHECK40-NEXT: [[TMP26:%.]] = load i32, i32 [[TMP25]], align 4
	// CHECK40-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])			// CHECK40-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]])
	▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
	// CHECK40-NEXT: br label [[COND_END]]			// CHECK40-NEXT: br label [[COND_END]]
	// CHECK40: cond.end:			// CHECK40: cond.end:
	// CHECK40-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK40-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK40-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK40-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK40-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK40-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK40-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK40-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK40: omp.inner.for.cond:			// CHECK40: omp.inner.for.cond:
	// CHECK40-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK40-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK40-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK40-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK40-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK40: omp.inner.for.body:			// CHECK40: omp.inner.for.body:
	// CHECK40-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK40-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK40-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK40-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK40-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK40-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK40-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK40-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK40-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK40-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK40-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK40: omp.body.continue:			// CHECK40: omp.body.continue:
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK40: omp.inner.for.inc:			// CHECK40: omp.inner.for.inc:
	// CHECK40-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK40-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK40-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK40-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK40-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14
	// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK40-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
	// CHECK40: omp.inner.for.end:			// CHECK40: omp.inner.for.end:
	// CHECK40-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK40-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK40: omp.loop.exit:			// CHECK40: omp.loop.exit:
	// CHECK40-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK40-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK40-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK40-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK40-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK40-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK40-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK40-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK40: .omp.final.then:			// CHECK40: .omp.final.then:
	▲ Show 20 Lines • Show All 1,202 Lines • Show Last 20 Lines

clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: br label [[COND_END]]			// CHECK1-NEXT: br label [[COND_END]]
	// CHECK1: cond.end:			// CHECK1: cond.end:
	// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK1: omp.loop.exit:			// CHECK1: omp.loop.exit:
	// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK1: .omp.final.then:			// CHECK1: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK1-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK1: omp.dispatch.body:			// CHECK1: omp.dispatch.body:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK1: omp.inner.for.cond:			// CHECK1: omp.inner.for.cond:
	// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK1: omp.inner.for.body:			// CHECK1: omp.inner.for.body:
	// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK1-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK1-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK1: omp.body.continue:			// CHECK1: omp.body.continue:
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK1: omp.inner.for.inc:			// CHECK1: omp.inner.for.inc:
	// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK1: omp.inner.for.end:			// CHECK1: omp.inner.for.end:
	// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK1: omp.dispatch.inc:			// CHECK1: omp.dispatch.inc:
	// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK1-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK1-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK1-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: br label [[COND_END]]			// CHECK2-NEXT: br label [[COND_END]]
	// CHECK2: cond.end:			// CHECK2: cond.end:
	// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK2: omp.loop.exit:			// CHECK2: omp.loop.exit:
	// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK2-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK2: .omp.final.then:			// CHECK2: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK2-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK2: omp.dispatch.body:			// CHECK2: omp.dispatch.body:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK2: omp.inner.for.cond:			// CHECK2: omp.inner.for.cond:
	// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK2: omp.inner.for.body:			// CHECK2: omp.inner.for.body:
	// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK2-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]			// CHECK2-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i64 0, i64 [[IDXPROM]]
	// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK2: omp.body.continue:			// CHECK2: omp.body.continue:
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK2: omp.inner.for.inc:			// CHECK2: omp.inner.for.inc:
	// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14			// CHECK2-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]			// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK2: omp.inner.for.end:			// CHECK2: omp.inner.for.end:
	// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK2: omp.dispatch.inc:			// CHECK2: omp.dispatch.inc:
	// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK2-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK2-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK2-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: br label [[COND_END]]			// CHECK3-NEXT: br label [[COND_END]]
	// CHECK3: cond.end:			// CHECK3: cond.end:
	// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK3: omp.loop.exit:			// CHECK3: omp.loop.exit:
	// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK3: .omp.final.then:			// CHECK3: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK3-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK3: omp.dispatch.body:			// CHECK3: omp.dispatch.body:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK3: omp.inner.for.cond:			// CHECK3: omp.inner.for.cond:
	// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK3: omp.inner.for.body:			// CHECK3: omp.inner.for.body:
	// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK3-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK3-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK3: omp.body.continue:			// CHECK3: omp.body.continue:
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK3: omp.inner.for.inc:			// CHECK3: omp.inner.for.inc:
	// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK3-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK3: omp.inner.for.end:			// CHECK3: omp.inner.for.end:
	// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK3: omp.dispatch.inc:			// CHECK3: omp.dispatch.inc:
	// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK3-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK3-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK3-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: br label [[COND_END]]			// CHECK4-NEXT: br label [[COND_END]]
	// CHECK4: cond.end:			// CHECK4: cond.end:
	// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP9]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK4: omp.loop.exit:			// CHECK4: omp.loop.exit:
	// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK4-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK4: .omp.final.then:			// CHECK4: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK4-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK4: omp.dispatch.body:			// CHECK4: omp.dispatch.body:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK4: omp.inner.for.cond:			// CHECK4: omp.inner.for.cond:
	// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK4: omp.inner.for.body:			// CHECK4: omp.inner.for.body:
	// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0			// CHECK4-NEXT: [[A:%.]] = getelementptr inbounds [[STRUCT_SS:%.]], %struct.SS* [[TMP0]], i32 0, i32 0
	// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]			// CHECK4-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [123 x i32], [123 x i32] [[A]], i32 0, i32 [[TMP11]]
	// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK4: omp.body.continue:			// CHECK4: omp.body.continue:
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK4: omp.inner.for.inc:			// CHECK4: omp.inner.for.inc:
	// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15			// CHECK4-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK4: omp.inner.for.end:			// CHECK4: omp.inner.for.end:
	// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK4: omp.dispatch.inc:			// CHECK4: omp.dispatch.inc:
	// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK4-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK4-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK4-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 808 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK9-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: br label [[COND_END]]			// CHECK9-NEXT: br label [[COND_END]]
	// CHECK9: cond.end:			// CHECK9: cond.end:
	// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK9: omp.loop.exit:			// CHECK9: omp.loop.exit:
	// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK9-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK9-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK9: .omp.final.then:			// CHECK9: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK9-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK9: omp.dispatch.body:			// CHECK9: omp.dispatch.body:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK9: omp.inner.for.cond:			// CHECK9: omp.inner.for.cond:
	// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK9: omp.inner.for.body:			// CHECK9: omp.inner.for.body:
	// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK9-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !26			// CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK9: omp.body.continue:			// CHECK9: omp.body.continue:
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK9: omp.inner.for.inc:			// CHECK9: omp.inner.for.inc:
	// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK9-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK9: omp.inner.for.end:			// CHECK9: omp.inner.for.end:
	// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK9: omp.dispatch.inc:			// CHECK9: omp.dispatch.inc:
	// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK9-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK9-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK9-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 314 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !9
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !15
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 8
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK10-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !17			// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: br label [[COND_END]]			// CHECK10-NEXT: br label [[COND_END]]
	// CHECK10: cond.end:			// CHECK10: cond.end:
	// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK10: omp.loop.exit:			// CHECK10: omp.loop.exit:
	// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK10-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK10-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK10: .omp.final.then:			// CHECK10: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK10-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK10: omp.dispatch.body:			// CHECK10: omp.dispatch.body:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK10: omp.inner.for.cond:			// CHECK10: omp.inner.for.cond:
	// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK10: omp.inner.for.body:			// CHECK10: omp.inner.for.body:
	// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !26			// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64			// CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
	// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]			// CHECK10-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i64 0, i64 [[IDXPROM]]
	// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !26			// CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK10: omp.body.continue:			// CHECK10: omp.body.continue:
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK10: omp.inner.for.inc:			// CHECK10: omp.inner.for.inc:
	// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26			// CHECK10-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27
	// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]			// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
	// CHECK10: omp.inner.for.end:			// CHECK10: omp.inner.for.end:
	// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK10: omp.dispatch.inc:			// CHECK10: omp.dispatch.inc:
	// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK10-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK10-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK10-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK11-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: br label [[COND_END]]			// CHECK11-NEXT: br label [[COND_END]]
	// CHECK11: cond.end:			// CHECK11: cond.end:
	// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK11: omp.loop.exit:			// CHECK11: omp.loop.exit:
	// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK11-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK11-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK11: .omp.final.then:			// CHECK11: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK11-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK11: omp.dispatch.body:			// CHECK11: omp.dispatch.body:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK11: omp.inner.for.cond:			// CHECK11: omp.inner.for.cond:
	// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK11: omp.inner.for.body:			// CHECK11: omp.inner.for.body:
	// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27			// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK11-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27			// CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK11: omp.body.continue:			// CHECK11: omp.body.continue:
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK11: omp.inner.for.inc:			// CHECK11: omp.inner.for.inc:
	// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK11-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK11: omp.inner.for.end:			// CHECK11: omp.inner.for.end:
	// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK11: omp.dispatch.inc:			// CHECK11: omp.dispatch.inc:
	// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK11-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK11-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK11-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]			// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
	// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[I3]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP17]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1			// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1
	// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !16
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32** [[DOTGLOBAL_TID__ADDR]], align 4
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[TMP19]], align 4
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP20]])
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0			// CHECK12-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
	▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP16:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]			// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
	// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP17:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP18:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]			// CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
	// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP19:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I4]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP20:%.]] = load i32, i32 [[I4]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds i32, i32 [[TMP2]], i32 [[TMP20]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: [[TMP21:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1			// CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], 1
	// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !18			// CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !19
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP22:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP23:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]			// CHECK12-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
	// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP24:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !22
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: br label [[COND_END]]			// CHECK12-NEXT: br label [[COND_END]]
	// CHECK12: cond.end:			// CHECK12: cond.end:
	// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]			// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
	// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4			// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP5:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP9]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !25
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]			// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
	// CHECK12: omp.loop.exit:			// CHECK12: omp.loop.exit:
	// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])			// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[DOTOMP_IS_LAST]], align 4
	// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0			// CHECK12-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
	// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]			// CHECK12-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.]], label [[DOTOMP_FINAL_DONE:%.]]
	// CHECK12: .omp.final.then:			// CHECK12: .omp.final.then:
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4			// CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4			// CHECK12-NEXT: [[TMP6:%.]] = load i32, i32 [[DOTOMP_IV]], align 4
	// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP7:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]			// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
	// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]			// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.]], label [[OMP_DISPATCH_END:%.]]
	// CHECK12: omp.dispatch.body:			// CHECK12: omp.dispatch.body:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
	// CHECK12: omp.inner.for.cond:			// CHECK12: omp.inner.for.cond:
	// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP8:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP9:%.]] = load i32, i32 [[DOTOMP_UB]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]			// CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
	// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]			// CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.]], label [[OMP_INNER_FOR_END:%.]]
	// CHECK12: omp.inner.for.body:			// CHECK12: omp.inner.for.body:
	// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP10:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1			// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
	// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]			// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
	// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !27			// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP11:%.]] = load i32, i32 [[I]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]			// CHECK12-NEXT: [[ARRAYIDX:%.]] = getelementptr inbounds [10 x i32], [10 x i32] [[TMP0]], i32 0, i32 [[TMP11]]
	// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !27			// CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]			// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
	// CHECK12: omp.body.continue:			// CHECK12: omp.body.continue:
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
	// CHECK12: omp.inner.for.inc:			// CHECK12: omp.inner.for.inc:
	// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: [[TMP12:%.]] = load i32, i32 [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1			// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
	// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27			// CHECK12-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !28
	// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]			// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
	// CHECK12: omp.inner.for.end:			// CHECK12: omp.inner.for.end:
	// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]			// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
	// CHECK12: omp.dispatch.inc:			// CHECK12: omp.dispatch.inc:
	// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4			// CHECK12-NEXT: [[TMP13:%.]] = load i32, i32 [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4			// CHECK12-NEXT: [[TMP14:%.]] = load i32, i32 [[DOTOMP_STRIDE]], align 4
	// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]			// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
	// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4			// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_LB]], align 4
	// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4			// CHECK12-NEXT: [[TMP15:%.]] = load i32, i32 [[DOTOMP_UB]], align 4
	▲ Show 20 Lines • Show All 1,260 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[OpenMP] Add Module metadata for OpenMP compilationClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 354592

clang/lib/CodeGen/CodeGenModule.cpp

clang/test/OpenMP/cancel_codegen.cpp

clang/test/OpenMP/cancellation_point_codegen.cpp

clang/test/OpenMP/distribute_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp

clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp

clang/test/OpenMP/distribute_simd_codegen.cpp

clang/test/OpenMP/for_reduction_codegen_UDR.cpp

clang/test/OpenMP/for_reduction_task_codegen.cpp

clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp

clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp

clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp

clang/test/OpenMP/ordered_codegen.cpp

clang/test/OpenMP/parallel_for_codegen.cpp

clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp

clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp

clang/test/OpenMP/parallel_master_taskloop_codegen.cpp

clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp

clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp

clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp

clang/test/OpenMP/parallel_reduction_task_codegen.cpp

clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp

clang/test/OpenMP/sections_reduction_task_codegen.cpp

clang/test/OpenMP/target_parallel_codegen.cpp

clang/test/OpenMP/target_parallel_for_codegen.cpp

clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp

clang/test/OpenMP/target_parallel_for_simd_codegen.cpp

clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp

clang/test/OpenMP/target_teams_codegen.cpp

clang/test/OpenMP/target_teams_distribute_codegen.cpp

clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp

clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp

clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp

clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp

clang/test/OpenMP/task_codegen.cpp

clang/test/OpenMP/task_if_codegen.cpp

clang/test/OpenMP/task_in_reduction_codegen.cpp

clang/test/OpenMP/taskloop_in_reduction_codegen.cpp

clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp

clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp

clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp

clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp

clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp

clang/test/OpenMP/teams_distribute_simd_codegen.cpp

clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp

[OpenMP] Add Module metadata for OpenMP compilation
ClosedPublic