[AArch64] Add missing UINT_TO_FP promotions for v16i8

[david-arm]

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll

175

Shouldn't we have some CHECK lines for the codegen in these functions?

[joechrisellis]

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll

175

Hi @david-arm -- the codegen here is not particularly interesting at the moment (and is actually quite poor). These functions are actually defending against selection failures. At this point I'm not entirely convinced that writing CHECK lines for the codegen here is valuable. Do we definitely need them? 🙂

[paulwalker-arm]

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll

175

@joechrisellis This is true for much of this file. If you look at the other tests you'll see reference to CHECK-COUNT-### to ensure the code generation is somewhat sensible. I recommend following this same pattern.

[joechrisellis]

Address review comments.

• @paulwalker-arm and @david-arm:
  • add CHECK-COUNT-* lines to new tests.

[joechrisellis]

Gentle ping. 🙂

[paulwalker-arm]

Looks fine to me given this is more a "compiler shouldn't crash" test that will be updated once we have support to custom lower these nodes.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasNEON()) {
     setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
 
     setOperationAction(ISD::MUL, MVT::v1i64, Expand);
 
     // AArch64 doesn't have a direct vector ->f32 conversion instructions for
     // elements smaller than i32, so promote the input to i32 first.
     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
-    // i8 vector elements also need promotion to i32 for v8i8
     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
+    setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v16i8, MVT::v16i32);
+    setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v16i8, MVT::v16i32);
+
     // Similarly, there is no direct i32 -> f64 vector conversion instruction.
     setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
     setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
     setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
     setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
     // Or, direct i32 -> f16 vector conversion.  Set it so custom, so the
     // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
     setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll

 ; CHECK-NOT: fcvt
 ; CHECK: ret
   %a = load <32 x double>, <32 x double>* %in
   %b = fptrunc <32 x double> %a to <32 x float>
   store <32 x float> %b, <32 x float>* %out
   ret void
 }
 
+;
+; vector uint_to_fp i8 -> f32
+; AArch64 doesn't have a direct vector->f32 conversion instructions for
+; elements smaller than i32, so make sure inputs are promoted to i32 first.
+;
+
+define void @uitofp_v4i8_v4f32(<4 x i8>* %in, <4 x float>* %out) #0 {
+; CHECK-LABEL: uitofp_v4i8_v4f32:
+; CHECK-COUNT-1: ucvt
+  %vec = load <4 x i8>, <4 x i8>* %in
+  %conv = uitofp <4 x i8> %vec to <4 x float>
+  store <4 x float> %conv, <4 x float>* %out
+  ret void
+}
+
+define void @uitofp_v8i8_v8f32(<8 x i8>* %in, <8 x float>* %out) #0 {
+; CHECK-LABEL: uitofp_v8i8_v8f32:
+; CHECK-COUNT-8: ucvt
+  %vec = load <8 x i8>, <8 x i8>* %in
+  %conv = uitofp <8 x i8> %vec to <8 x float>
+  store <8 x float> %conv, <8 x float>* %out
+  ret void
+}
+
+define void @uitofp_v16i8_v16f32(<16 x i8>* %in, <16 x float>* %out) #0 {
+; CHECK-LABEL: uitofp_v16i8_v16f32:
+; CHECK-COUNT-16: ucvt
+  %vec = load <16 x i8>, <16 x i8>* %in
+  %conv = uitofp <16 x i8> %vec to <16 x float>
+  store <16 x float> %conv, <16 x float>* %out
+  ret void
+}
+
+define void @uitofp_v32i8_v32f32(<32 x i8>* %in, <32 x float>* %out) #0 {
+; CHECK-LABEL: uitofp_v32i8_v32f32:
+; CHECK-COUNT-32: ucvt
+  %vec = load <32 x i8>, <32 x i8>* %in
+  %conv = uitofp <32 x i8> %vec to <32 x float>
+  store <32 x float> %conv, <32 x float>* %out
+  ret void
+}
+
 attributes #0 = { nounwind "target-features"="+sve" }