[PoC][RISCV] Using pragma to register vector intrinsic

[kito-cheng]

Summary

This patch is *NOT* ready to commite yet, it's PoC of the pragma approache to
reduce the size of riscv_vector.h and speed up the including effort.

Syntax for the new pragma:

#pragma riscv intrinsic <extension name>

And we only support for vector now:

#pragma riscv intrinsic vector

Size of riscv_vector.h:

       |      size |     LoC |
------------------------------
Before | 4,434,725 |  69,749 |
After  |     5,463 |     159 |

testcase:

#include <riscv_vector.h>

vint32m1_t test_vadd_vv_vfloat32m1_t(vint32m1_t op1, vint32m1_t op2, size_t vl) {
  return vadd(op1, op2, vl);
}

Release build:

Before: 0m0.417s
After:  0m0.090s

Debug build:

Before: 0m8.016s
After:  0m2.295s

• Measure by time command.

LLVM regression on our 48 core server:

Release build:
Before : Testing Time: 203.81s
After : Testing Time: 181.13s
Debug build:
Before : Testing Time: 675.18s
After : Testing Time: 647.20s

[kito-cheng]

Minor cleanup

[craig.topper]

clang/lib/Sema/SemaRISCV.cpp

22

Can we capture Sema in the lambda capture list here so that it's not really passed to initializeTargetOverloadBuiltins. I don't think forward declaring Sema in Builtins.h is a good idea since the "Basic" library isn't supposed to know about Sema. That probably means you need to use a std::function instead of a function pointer.

[kito-cheng]

clang/lib/Sema/SemaRISCV.cpp

22

Thanks for the input, I am not family with modern C++ since GCC still using limited set of C++98 :P

[kito-cheng]

Changes:

• Using less invasive way to add intrinsic functions.

[kito-cheng]

Reupload.

[kito-cheng]

Update:

Send RFC[1] to cfe-dev list, and got useful feedback from OpenCL:

• OpenCL's way is the fastest way to declare builtin, since it defer until symbol look-up, however that require re-implement vector intrinsic with their new intrinsic infrastructure.
• OpenCL folks agree we (RISC-V) need some way to enable that like pragma, OpenCL are default enabled built-in function without including header file, but RVV intrinsic are only need to import until riscv_vector.h included.

So my next step is investigate the OpenCL's intrinsic infrastructure to get the best performance to declare bunch of intrinsic function, it might take several weeks.
and #pragma is still required.

[1] https://lists.llvm.org/pipermail/cfe-dev/2021-June/068340.html

[kito-cheng]

Further development move to https://reviews.llvm.org/D111617

clang/include/clang/Basic/CMakeLists.txt

clang_tablegen(arm_cde_builtin_aliases.inc -gen-arm-cde-builtin-aliases
   SOURCE arm_cde.td
   TARGET ClangARMCdeBuiltinAliases)
 clang_tablegen(riscv_vector_builtins.inc -gen-riscv-vector-builtins
   SOURCE riscv_vector.td
   TARGET ClangRISCVVectorBuiltins)
 clang_tablegen(riscv_vector_builtin_cg.inc -gen-riscv-vector-builtin-codegen
   SOURCE riscv_vector.td
   TARGET ClangRISCVVectorBuiltinCG)
+clang_tablegen(riscv_vector_intrinsic_info.inc -gen-riscv-vector-intrinsic-info
+  SOURCE riscv_vector.td
+  TARGET ClangRISCVVectorIntrinsicInfo)
+clang_tablegen(riscv_vector_intrinsic_overload_info.inc -gen-riscv-vector-intrinsic-overload-info
+  SOURCE riscv_vector.td
+  TARGET ClangRISCVVectorIntrinsicOverloadInfo)

clang/include/clang/Basic/TokenKinds.def

 // handles #pragma loop ... directives.
 PRAGMA_ANNOTATION(pragma_loop_hint)
 
 PRAGMA_ANNOTATION(pragma_fp)
 
 // Annotation for the attribute pragma directives - #pragma clang attribute ...
 PRAGMA_ANNOTATION(pragma_attribute)
 
+// Annotation for the riscv pragma directives - #pragma riscv intrinsic...
+PRAGMA_ANNOTATION(pragma_riscv)
+
 // Annotations for module import translated from #include etc.
 ANNOTATION(module_include)
 ANNOTATION(module_begin)
 ANNOTATION(module_end)
 
 // Annotation for a header_name token that has been looked up and transformed
 // into the name of a header unit.
 ANNOTATION(header_unit)

clang/include/clang/Parse/Parser.h

class Parser : public CodeCompletionHandler {
   std::unique_ptr<PragmaHandler> FPHandler;
   std::unique_ptr<PragmaHandler> STDCFenvAccessHandler;
   std::unique_ptr<PragmaHandler> STDCFenvRoundHandler;
   std::unique_ptr<PragmaHandler> STDCCXLIMITHandler;
   std::unique_ptr<PragmaHandler> STDCUnknownHandler;
   std::unique_ptr<PragmaHandler> AttributePragmaHandler;
   std::unique_ptr<PragmaHandler> MaxTokensHerePragmaHandler;
   std::unique_ptr<PragmaHandler> MaxTokensTotalPragmaHandler;
+  std::unique_ptr<PragmaHandler> RISCVPragmaHandler;
 
   std::unique_ptr<CommentHandler> CommentSemaHandler;
 
   /// Whether the '>' token acts as an operator or not. This will be
   /// true except when we are parsing an expression within a C++
   /// template argument list, where the '>' closes the template
   /// argument list.
   bool GreaterThanIsOperator;

clang/include/clang/Sema/Sema.h

   /// ActOnPragmaFenvAccess - Called on well formed
   /// \#pragma STDC FENV_ACCESS
   void ActOnPragmaFEnvAccess(SourceLocation Loc, bool IsEnabled);
 
   /// Called on well formed '\#pragma clang fp' that has option 'exceptions'.
   void ActOnPragmaFPExceptions(SourceLocation Loc,
                                LangOptions::FPExceptionModeKind);
 
+  /// Called on well formed '\#pragma riscv intrinsic'.
+  void ActOnPragmaRISCVIntrinsic(SourceLocation Loc);
+
   /// Called to set constant rounding mode for floating point operations.
   void setRoundingMode(SourceLocation Loc, llvm::RoundingMode);
 
   /// Called to set exception behavior for floating point operations.
   void setExceptionMode(SourceLocation Loc, LangOptions::FPExceptionModeKind);
 
   /// AddAlignmentAttributesForRecord - Adds any needed alignment attributes to
   /// a the record decl, to handle '\#pragma pack' and '\#pragma options align'.

clang/lib/Parse/ParsePragma.cpp

 };
 
 struct PragmaMaxTokensTotalHandler : public PragmaHandler {
   PragmaMaxTokensTotalHandler() : PragmaHandler("max_tokens_total") {}
   void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
                     Token &FirstToken) override;
 };
 
+struct PragmaRISCVHandler : public PragmaHandler {
+  PragmaRISCVHandler(Sema &S) : PragmaHandler("riscv"), Actions(S) {}
+  void HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer,
+                    Token &FirstToken) override;
+
+private:
+  Sema &Actions;
+};
+
 void markAsReinjectedForRelexing(llvm::MutableArrayRef<clang::Token> Toks) {
   for (auto &T : Toks)
     T.setFlag(clang::Token::IsReinjected);
 }
 }  // end namespace
 
 void Parser::initializePragmaHandlers() {
   AlignHandler = std::make_unique<PragmaAlignHandler>();
AttributePragmaHandler =
       std::make_unique<PragmaAttributeHandler>(AttrFactory);
   PP.AddPragmaHandler("clang", AttributePragmaHandler.get());
 
   MaxTokensHerePragmaHandler = std::make_unique<PragmaMaxTokensHereHandler>();
   PP.AddPragmaHandler("clang", MaxTokensHerePragmaHandler.get());
 
   MaxTokensTotalPragmaHandler = std::make_unique<PragmaMaxTokensTotalHandler>();
   PP.AddPragmaHandler("clang", MaxTokensTotalPragmaHandler.get());
+
+  if (getTargetInfo().getTriple().isRISCV()) {
+    RISCVPragmaHandler = std::make_unique<PragmaRISCVHandler>(Actions);
+    PP.AddPragmaHandler(RISCVPragmaHandler.get());
+  }
 }
 
 void Parser::resetPragmaHandlers() {
   // Remove the pragma handlers we installed.
   PP.RemovePragmaHandler(AlignHandler.get());
   AlignHandler.reset();
   PP.RemovePragmaHandler("GCC", GCCVisibilityHandler.get());
   GCCVisibilityHandler.reset();
void Parser::resetPragmaHandlers() {
   PP.RemovePragmaHandler("clang", AttributePragmaHandler.get());
   AttributePragmaHandler.reset();
 
   PP.RemovePragmaHandler("clang", MaxTokensHerePragmaHandler.get());
   MaxTokensHerePragmaHandler.reset();
 
   PP.RemovePragmaHandler("clang", MaxTokensTotalPragmaHandler.get());
   MaxTokensTotalPragmaHandler.reset();
+
+  if (getTargetInfo().getTriple().isRISCV()) {
+    PP.RemovePragmaHandler(RISCVPragmaHandler.get());
+    RISCVPragmaHandler.reset();
+  }
 }
 
 /// Handle the annotation token produced for #pragma unused(...)
 ///
 /// Each annot_pragma_unused is followed by the argument token so e.g.
 /// "#pragma unused(x,y)" becomes:
 /// annot_pragma_unused 'x' annot_pragma_unused 'y'
 void Parser::HandlePragmaUnused() {
void PragmaMSIntrinsicHandler::HandlePragma(Preprocessor &PP,
   }
   PP.Lex(Tok);
 
   if (Tok.isNot(tok::eod))
     PP.Diag(Tok.getLocation(), diag::warn_pragma_extra_tokens_at_eol)
         << "intrinsic";
 }
 
+// #pragma riscv intrinsic vector
+void PragmaRISCVHandler::HandlePragma(Preprocessor &PP,
+                                      PragmaIntroducer Introducer,
+                                      Token &FirstToken) {
+  Token Tok;
+  PP.Lex(Tok);
+  IdentifierInfo *II = Tok.getIdentifierInfo();
+  if (!II || (!II->isStr("intrinsic"))) {
+    PP.Diag(Tok.getLocation(), diag::warn_pragma_invalid_argument)
+        << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << "'intrinsic'";
+    return;
+  }
+
+  PP.Lex(Tok);
+  II = Tok.getIdentifierInfo();
+  if (!II || (!II->isStr("vector"))) {
+    PP.Diag(Tok.getLocation(), diag::warn_pragma_invalid_argument)
+        << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << "'vector'";
+    return;
+  }
+
+  Actions.ActOnPragmaRISCVIntrinsic(FirstToken.getLocation());
+}
+
 // #pragma optimize("gsty", on|off)
 void PragmaMSOptimizeHandler::HandlePragma(Preprocessor &PP,
                                            PragmaIntroducer Introducer,
                                            Token &Tok) {
   SourceLocation StartLoc = Tok.getLocation();
   PP.Lex(Tok);
 
   if (Tok.isNot(tok::l_paren)) {

clang/lib/Sema/CMakeLists.txt

add_clang_library(clangSema
   SemaInit.cpp
   SemaLambda.cpp
   SemaLookup.cpp
   SemaModule.cpp
   SemaObjCProperty.cpp
   SemaOpenMP.cpp
   SemaOverload.cpp
   SemaPseudoObject.cpp
+  SemaRISCV.cpp
   SemaStmt.cpp
   SemaStmtAsm.cpp
   SemaStmtAttr.cpp
   SemaSYCL.cpp
   SemaTemplate.cpp
   SemaTemplateDeduction.cpp
   SemaTemplateInstantiate.cpp
   SemaTemplateInstantiateDecl.cpp

clang/lib/Sema/SemaRISCV.cpp

+//===--- SemaRISCV.cpp - Semantic Analysis for RISC-V pragmas -------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file implements semantic analysis for RISC-V pragmas.
+///
+//===----------------------------------------------------------------------===//
+
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/TargetBuiltins.h"
+#include "clang/Basic/TargetInfo.h"
+#include "clang/Parse/Parser.h"
+#include "clang/Sema/Sema.h"
+using namespace clang;
+
+enum Features {
+  Feature_F = 1 << 0,
+  Feature_D = 1 << 1,
+  Feature_ZFH = 1 << 2,
+  Feature_ZVAMO = 1 << 3,
+};
+
+struct RVVIntrinsicInfo {
+  const char *TargetName;
+  unsigned TargetBuiltinID;
+  unsigned RequireFeatures;
+};
+
+struct RVVIntrinsicOverloadInfo {
+  const char *TargetName;
+  const char *OverloadName;
+  unsigned TargetBuiltinID;
+  unsigned RequireFeatures;
+};
+
+static const RVVIntrinsicInfo RVVIntrinsicInfos[] = {
+#include "clang/Basic/riscv_vector_intrinsic_info.inc"
+};
+
+static const RVVIntrinsicOverloadInfo RVVIntrinsicOverloadInfos[] = {
+#include "clang/Basic/riscv_vector_intrinsic_overload_info.inc"
+};
+
+void Sema::ActOnPragmaRISCVIntrinsic(SourceLocation Loc) {
+  auto &TI = Context.getTargetInfo();
+  bool HasF = TI.hasFeature("f");
+  bool HasD = TI.hasFeature("d");
+  bool HasZvamo = TI.hasFeature("experimental-zvamo");
+  bool HasZfh = TI.hasFeature("experimental-zfh");
+  unsigned Features = 0;
+  if (HasF)
+    Features |= Feature_F;
+  if (HasD)
+    Features |= Feature_D;
+  if (HasZfh)
+    Features |= Feature_ZFH;
+  if (HasZvamo)
+    Features |= Feature_ZVAMO;
+
+  for (auto InstrInfo : RVVIntrinsicInfos) {
+    // Check feature requirement.
+    if ((InstrInfo.RequireFeatures & Features) != InstrInfo.RequireFeatures)
+      continue;
+
+    PP.getIdentifierTable()
+        .get(InstrInfo.TargetName)
+        .setBuiltinID(InstrInfo.TargetBuiltinID);
+  }
+
+  for (auto InstrInfo : RVVIntrinsicOverloadInfos) {
+    // Check feature requirement.
+    if ((InstrInfo.RequireFeatures & Features) != InstrInfo.RequireFeatures)
+      continue;
+
+    auto &OverloadII = PP.getIdentifierTable().get(InstrInfo.OverloadName);
+    auto &II = PP.getIdentifierTable().get(InstrInfo.TargetName);
+    auto *FuncDecl = LazilyCreateBuiltin(&OverloadII, InstrInfo.TargetBuiltinID,
+                                         getCurScope(), false, Loc);
+    FuncDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
+    FuncDecl->addAttr(BuiltinAliasAttr::CreateImplicit(Context, &II));
+  }
+}

clang/utils/TableGen/RISCVVEmitter.cpp

public:
   uint8_t getRISCVExtensions() const { return RISCVExtensions; }
 
   // Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr() const;
 
   // Emit the code block for switch body in EmitRISCVBuiltinExpr, it should
   // init the RVVIntrinsic ID and IntrinsicTypes.
   void emitCodeGenSwitchBody(raw_ostream &o) const;
-
-  // Emit the macros for mapping C/C++ intrinsic function to builtin functions.
-  void emitIntrinsicMacro(raw_ostream &o) const;
-
-  // Emit the mangled function definition.
-  void emitMangledFuncDef(raw_ostream &o) const;
 };
 
 class RVVEmitter {
 private:
   RecordKeeper &Records;
   std::string HeaderCode;
   // Concat BasicType, LMUL and Proto as key
   StringMap<RVVType> LegalTypes;
   StringSet<> IllegalTypes;
 
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
 
   /// Emit riscv_vector.h
   void createHeader(raw_ostream &o);
 
   /// Emit all the __builtin prototypes and code needed by Sema.
   void createBuiltins(raw_ostream &o);
 
   /// Emit all the information needed to map builtin -> LLVM IR intrinsic.
   void createCodeGen(raw_ostream &o);
 
+  /// Emit all the intrinsic info for `#pragma riscv vector intrinsic`.
+  void createIntrinsicInfo(raw_ostream &o);
+
+  /// Emit all the intrinsic overload info for `#pragma riscv vector intrinsic`.
+  void createIntrinsicOverloadInfo(raw_ostream &o);
+
   std::string getSuffixStr(char Type, int Log2LMUL, StringRef Prototypes);
 
 private:
   /// Create all intrinsics and add them to \p Out
   void createRVVIntrinsics(std::vector<std::unique_ptr<RVVIntrinsic>> &Out);
   /// Compute output and input types by applying different config (basic type
   /// and LMUL with type transformers). It also record result of type in legal
   /// or illegal set to avoid compute the  same config again. The result maybe
   /// have illegal RVVType.
   Optional<RVVTypes> computeTypes(BasicType BT, int Log2LMUL,
                                   ArrayRef<std::string> PrototypeSeq);
   Optional<RVVTypePtr> computeType(BasicType BT, int Log2LMUL, StringRef Proto);
 
-  /// Emit Acrh predecessor definitions and body, assume the element of Defs are
-  /// sorted by extension.
-  void emitArchMacroAndBody(
-      std::vector<std::unique_ptr<RVVIntrinsic>> &Defs, raw_ostream &o,
-      std::function<void(raw_ostream &, const RVVIntrinsic &)>);
-
-  // Emit the architecture preprocessor definitions. Return true when emits
-  // non-empty string.
-  bool emitExtDefStr(uint8_t Extensions, raw_ostream &o);
   // Slice Prototypes string into sub prototype string and process each sub
   // prototype string individually in the Handler.
   void parsePrototypes(StringRef Prototypes,
                        std::function<void(StringRef)> Handler);
 };
 
 } // namespace
 
void RVVIntrinsic::emitCodeGenSwitchBody(raw_ostream &OS) const {
   // VL could be i64 or i32, need to encode it in IntrinsicTypes. VL is
   // always last operand.
   if (hasVL())
     OS << ", Ops.back()->getType()";
   OS << "};\n";
   OS << "  break;\n";
 }
 
-void RVVIntrinsic::emitIntrinsicMacro(raw_ostream &OS) const {
-  OS << "#define " << getName() << "(";
-  if (!InputTypes.empty()) {
-    ListSeparator LS;
-    for (unsigned i = 0, e = InputTypes.size(); i != e; ++i)
-      OS << LS << "op" << i;
-  }
-  OS << ") \\\n";
-  OS << "__builtin_rvv_" << getName() << "(";
-  if (!InputTypes.empty()) {
-    ListSeparator LS;
-    for (unsigned i = 0, e = InputTypes.size(); i != e; ++i)
-      OS << LS << "(" << InputTypes[i]->getTypeStr() << ")(op" << i << ")";
-  }
-  OS << ")\n";
-}
-
-void RVVIntrinsic::emitMangledFuncDef(raw_ostream &OS) const {
-  OS << "__attribute__((clang_builtin_alias(";
-  OS << "__builtin_rvv_" << getName() << ")))\n";
-  OS << OutputType->getTypeStr() << " " << getMangledName() << "(";
-  // Emit function arguments
-  if (!InputTypes.empty()) {
-    ListSeparator LS;
-    for (unsigned i = 0; i < InputTypes.size(); ++i)
-      OS << LS << InputTypes[i]->getTypeStr() << " op" << i;
-  }
-  OS << ");\n\n";
-}
-
 //===----------------------------------------------------------------------===//
 // RVVEmitter implementation
 //===----------------------------------------------------------------------===//
 void RVVEmitter::createHeader(raw_ostream &OS) {
 
   OS << "/*===---- riscv_vector.h - RISC-V V-extension RVVIntrinsics "
         "-------------------===\n"
         " *\n"
void RVVEmitter::createHeader(raw_ostream &OS) {
 
   OS << "#ifndef __riscv_vector\n";
   OS << "#error \"Vector intrinsics require the vector extension.\"\n";
   OS << "#endif\n\n";
 
   OS << "#ifdef __cplusplus\n";
   OS << "extern \"C\" {\n";
   OS << "#endif\n\n";
+  OS << "#pragma riscv intrinsic vector\n\n";
 
   std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
   createRVVIntrinsics(Defs);
 
   // Print header code
   if (!HeaderCode.empty()) {
     OS << HeaderCode;
   }
void RVVEmitter::createHeader(raw_ostream &OS) {
 
   // The same extension include in the same arch guard marco.
   std::stable_sort(Defs.begin(), Defs.end(),
                    [](const std::unique_ptr<RVVIntrinsic> &A,
                       const std::unique_ptr<RVVIntrinsic> &B) {
                      return A->getRISCVExtensions() < B->getRISCVExtensions();
                    });
 
-  // Print intrinsic functions with macro
-  emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
-    Inst.emitIntrinsicMacro(OS);
-  });
-
   OS << "#define __riscv_v_intrinsic_overloading 1\n";
 
-  // Print Overloaded APIs
-  OS << "#define __rvv_overloaded static inline "
-        "__attribute__((__always_inline__, __nodebug__, __overloadable__))\n";
-
-  emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) {
-    if (!Inst.isMask() && !Inst.hasNoMaskedOverloaded())
-      return;
-    OS << "__rvv_overloaded ";
-    Inst.emitMangledFuncDef(OS);
-  });
-
   OS << "\n#ifdef __cplusplus\n";
   OS << "}\n";
   OS << "#endif // __riscv_vector\n";
   OS << "#endif // __RISCV_VECTOR_H\n";
 }
 
 void RVVEmitter::createBuiltins(raw_ostream &OS) {
   std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
if (T.isValid()) {
     LegalTypes.insert({Idx, T});
     return &(LegalTypes[Idx]);
   }
   // Record illegal type index.
   IllegalTypes.insert(Idx);
   return llvm::None;
 }
 
-void RVVEmitter::emitArchMacroAndBody(
-    std::vector<std::unique_ptr<RVVIntrinsic>> &Defs, raw_ostream &OS,
-    std::function<void(raw_ostream &, const RVVIntrinsic &)> PrintBody) {
-  uint8_t PrevExt = (*Defs.begin())->getRISCVExtensions();
-  bool NeedEndif = emitExtDefStr(PrevExt, OS);
-  for (auto &Def : Defs) {
-    uint8_t CurExt = Def->getRISCVExtensions();
-    if (CurExt != PrevExt) {
-      if (NeedEndif)
-        OS << "#endif\n\n";
-      NeedEndif = emitExtDefStr(CurExt, OS);
-      PrevExt = CurExt;
-    }
-    if (Def->hasAutoDef())
-      PrintBody(OS, *Def);
-  }
-  if (NeedEndif)
-    OS << "#endif\n\n";
+static void emitFeatureCheckStr(uint8_t Extents, raw_ostream &OS) {
+  if (Extents == RISCVExtension::Basic) {
+    OS << 0;
+    return;
   }
 
-bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
-  if (Extents == RISCVExtension::Basic)
-    return false;
-  OS << "#if ";
-  ListSeparator LS(" && ");
+  ListSeparator LS("|");
   if (Extents & RISCVExtension::F)
-    OS << LS << "defined(__riscv_f)";
+    OS << LS << "Feature_F";
   if (Extents & RISCVExtension::D)
-    OS << LS << "defined(__riscv_d)";
+    OS << LS << "Feature_D";
   if (Extents & RISCVExtension::Zfh)
-    OS << LS << "defined(__riscv_zfh)";
+    OS << LS << "Feature_ZFH";
   if (Extents & RISCVExtension::Zvamo)
-    OS << LS << "defined(__riscv_zvamo)";
-  OS << "\n";
-  return true;
+    OS << LS << "Feature_ZVAMO";
+}
+
+void RVVEmitter::createIntrinsicInfo(raw_ostream &OS) {
+  std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
+  createRVVIntrinsics(Defs);
+  for (auto &Def : Defs) {
+    OS << "  {\"" << Def->getName() << "\", ";
+    OS << "RISCV::BI__builtin_rvv_" << Def->getName() << ", ";
+    emitFeatureCheckStr(Def->getRISCVExtensions(), OS);
+    OS << "},\n";
+  }
+}
+
+void RVVEmitter::createIntrinsicOverloadInfo(raw_ostream &OS) {
+  std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
+  createRVVIntrinsics(Defs);
+  for (auto &Def : Defs) {
+    if (!Def->isMask() && !Def->hasNoMaskedOverloaded())
+      continue;
+    OS << "  {\"__builtin_rvv_" << Def->getName() << "\", ";
+    OS << "\"" << Def->getMangledName() << "\", ";
+    OS << "RISCV::BI__builtin_rvv_" << Def->getName() << ", ";
+    emitFeatureCheckStr(Def->getRISCVExtensions(), OS);
+    OS << "},\n";
+  }
 }
 
 namespace clang {
 void EmitRVVHeader(RecordKeeper &Records, raw_ostream &OS) {
   RVVEmitter(Records).createHeader(OS);
 }
 
 void EmitRVVBuiltins(RecordKeeper &Records, raw_ostream &OS) {
   RVVEmitter(Records).createBuiltins(OS);
 }
 
 void EmitRVVBuiltinCG(RecordKeeper &Records, raw_ostream &OS) {
   RVVEmitter(Records).createCodeGen(OS);
 }
 
+void EmitRVVIntrinsicInfo(RecordKeeper &Records, raw_ostream &OS) {
+  RVVEmitter(Records).createIntrinsicInfo(OS);
+}
+
+void EmitRVVIntrinsicOverloadInfo(RecordKeeper &Records, raw_ostream &OS) {
+  RVVEmitter(Records).createIntrinsicOverloadInfo(OS);
+}
+
 } // End namespace clang

clang/utils/TableGen/TableGen.cpp

enum ActionType {
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
   GenArmCdeBuiltinCG,
   GenArmCdeBuiltinAliases,
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
+  GenRISCVVectorIntrinsicInfo,
+  GenRISCVVectorIntrinsicOverloadInfo,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
   GenDataCollectors,
   GenTestPragmaAttributeSupportedAttributes
 };
 
 namespace {
cl::values(
         clEnumValN(GenArmCdeBuiltinAliases, "gen-arm-cde-builtin-aliases",
                    "Generate list of valid ARM CDE builtin aliases for clang"),
         clEnumValN(GenRISCVVectorHeader, "gen-riscv-vector-header",
                    "Generate riscv_vector.h for clang"),
         clEnumValN(GenRISCVVectorBuiltins, "gen-riscv-vector-builtins",
                    "Generate riscv_vector_builtins.inc for clang"),
         clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
                    "Generate riscv_vector_builtin_cg.inc for clang"),
+        clEnumValN(GenRISCVVectorIntrinsicInfo,
+                   "gen-riscv-vector-intrinsic-info",
+                   "Generate riscv_vector_intrinsic_info.inc for clang."),
+        clEnumValN(
+            GenRISCVVectorIntrinsicOverloadInfo,
+            "gen-riscv-vector-intrinsic-overload-info",
+            "Generate riscv_vector_intrinsic_overload_info.inc for clang."),
         clEnumValN(GenAttrDocs, "gen-attr-docs",
                    "Generate attribute documentation"),
         clEnumValN(GenDiagDocs, "gen-diag-docs",
                    "Generate diagnostic documentation"),
         clEnumValN(GenOptDocs, "gen-opt-docs", "Generate option documentation"),
         clEnumValN(GenDataCollectors, "gen-clang-data-collectors",
                    "Generate data collectors for AST nodes"),
         clEnumValN(GenTestPragmaAttributeSupportedAttributes,
case GenRISCVVectorHeader:
     EmitRVVHeader(Records, OS);
     break;
   case GenRISCVVectorBuiltins:
     EmitRVVBuiltins(Records, OS);
     break;
   case GenRISCVVectorBuiltinCG:
     EmitRVVBuiltinCG(Records, OS);
     break;
+  case GenRISCVVectorIntrinsicInfo:
+    EmitRVVIntrinsicInfo(Records, OS);
+    break;
+  case GenRISCVVectorIntrinsicOverloadInfo:
+    EmitRVVIntrinsicOverloadInfo(Records, OS);
+    break;
   case GenAttrDocs:
     EmitClangAttrDocs(Records, OS);
     break;
   case GenDiagDocs:
     EmitClangDiagDocs(Records, OS);
     break;
   case GenOptDocs:
     EmitClangOptDocs(Records, OS);

clang/utils/TableGen/TableGenBackends.h

 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinAliases(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitRVVHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitRVVBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVIntrinsicInfo(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitRVVIntrinsicOverloadInfo(llvm::RecordKeeper &Records,
+                                  llvm::raw_ostream &OS);
 
 void EmitCdeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitCdeBuiltinAliases(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitClangAttrDocs(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);

llvm/docs/CommandGuide/tblgen.rst

 .. option:: -gen-riscv-vector-builtins
 
   Generate ``riscv_vector_builtins.inc`` for Clang.
 
 .. option:: -gen-riscv-vector-builtin-codegen
 
   Generate ``riscv_vector_builtin_cg.inc`` for Clang.
 
+.. option:: -gen-riscv-vector-intrinsic-info
+
+  Generate ``riscv_vector_intrinsic_info.inc`` for Clang.
+
+.. option:: -gen-riscv-vector-intrinsic-overload-info
+
+  Generate ``riscv_vector_intrinsic_overload_info.inc`` for Clang.
+
 .. option:: -gen-attr-docs
 
   Generate attribute documentation.
 
 .. option:: -gen-diag-docs
 
   Generate diagnostic documentation.