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kito-cheng (Kito Cheng)
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User Since
Oct 20 2016, 2:25 AM (227 w, 4 d)

Recent Activity

Mon, Feb 1

kito-cheng added inline comments to D95781: [RISCV] Add new vector instructions in v0.10..
Mon, Feb 1, 6:12 AM · Restricted Project

Jan 25 2021

kito-cheng added a comment to D94583: [RISCV] Update V extension to v1.0-draft 08a0b464..

Could you also update macros and attributes which implemented in https://reviews.llvm.org/D94403 and https://reviews.llvm.org/D94931

Jan 25 2021, 1:31 AM · Restricted Project, Restricted Project

Jan 24 2021

kito-cheng accepted D94403: [RISCV] Implement new architecture extension macros.

LGTM

Jan 24 2021, 7:14 PM · Restricted Project
kito-cheng accepted D94931: [RISCV] Add attribute support for all supported extensions.

LGTM

Jan 24 2021, 7:11 PM · Restricted Project

Jan 22 2021

kito-cheng added a comment to D95146: [RISCV] Make v extension imply zvamo, zvlsseg.

In the mean time I will park this change, and add 'v' implying its subfeatures in clang, since this would catch most cases we expect users to use (I don't think manually enabling features is a common use case). I can then later look at a more detailed/complete fix when enabling features directly with -mattr.

Jan 22 2021, 1:50 AM · Restricted Project

Jan 21 2021

kito-cheng added a comment to D94583: [RISCV] Update V extension to v1.0-draft 08a0b464..

@jrtc27 just let you know I have same concern too, that's one major reason why we don't upstream those extension on GNU toolchain... we are intend to introduce an internal revision number on ELF attribute in near future, e.g. v-ext 0.9.1 / v0p9p1 to prevent compatible issue here.

Jan 21 2021, 7:43 PM · Restricted Project, Restricted Project
kito-cheng added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

Note from the last sync up call, it's ok to landing that once review is done without refactor, refactor could be done separately after LLVM 12 release, that's won't be a blocker issue for this patch.

Jan 21 2021, 7:22 PM · Restricted Project
kito-cheng added a comment to D95146: [RISCV] Make v extension imply zvamo, zvlsseg.

Doesn't this mean that if you only enable zvlsseg, you'll be able to use the instruction in that extension but not the vsetvli instruction that you need to program the VL register?

@craig.topper To be honest, I'm not at all familiar with the v extension or any of the zv* extensions. I wrote this in response to D94931 which says that V should imply zv* but not the other way around. Looking back now at D85069 it looks there was some discussion suggesting which way around it should be, so it could be this patch is unnecessary and breaks stuff. Do you have any better understand of the vector spec as to which way round is correct?

@kito-cheng Similarly, do you know if the correct order of implication/requirements is well defined somewhere. If there are gcc/binutils patches what does it do here?

Jan 21 2021, 7:04 PM · Restricted Project
kito-cheng added a comment to D94403: [RISCV] Implement new architecture extension macros.
In D94403#2512232, @asb wrote:

@kito-cheng could you please confirm that this patch handles sub-extensions in the same way GCC does. i.e. -march=rv32izbb0p92 defines __riscv_zbb but NOT __riscv_b?

Jan 21 2021, 8:00 AM · Restricted Project
kito-cheng accepted D94403: [RISCV] Implement new architecture extension macros.

I believe the behavior has aligned to GCC now.

Jan 21 2021, 7:59 AM · Restricted Project
kito-cheng added inline comments to D94931: [RISCV] Add attribute support for all supported extensions.
Jan 21 2021, 7:55 AM · Restricted Project
kito-cheng added a comment to D95134: [RISCV] Use v8-v23 as argument registers to conform to the proposal..

Add a dedicated test file to demonstrate and verify the ABI would be better.

Jan 21 2021, 7:33 AM · Restricted Project

Jan 19 2021

kito-cheng added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

I think maybe we could extract the arch parser from driver[1] to llvm/lib/Support, so that we could just maintain one parser for driver and assembler, and there is also other potential user for that, like the C front-end for the target attribute, e.g. __attribute__ ((target ("arch=rv64gcv"))), and the linker can re-use that to read/merge/write the attribute too.

[1] https://github.com/llvm/llvm-project/blob/main/clang/lib/Driver/ToolChains/Arch/RISCV.cpp#L171

I was thinking about this too and was going to discuss it on Thursday's call. At the very least, even if we don't move the parser, the number of places that extension version numbers are add and used throughout the tools seems to call for it being centralised somewhere.

Jan 19 2021, 1:36 AM · Restricted Project
kito-cheng added a comment to D94403: [RISCV] Implement new architecture extension macros.

Just note how current GCC implemented, GCC implement that like implied extension, e.g. V implied Zvamo and Zvlsseg, so __riscv_zvamo is naturally defined when V-ext is enabled.

Jan 19 2021, 1:33 AM · Restricted Project
kito-cheng added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

I think maybe we could extract the arch parser from driver[1] to llvm/lib/Support, so that we could just maintain one parser for driver and assembler, and there is also other potential user for that, like the C front-end for the target attribute, e.g. __attribute__ ((target ("arch=rv64gcv"))), and the linker can re-use that to read/merge/write the attribute too.

Jan 19 2021, 1:24 AM · Restricted Project

Jan 17 2021

kito-cheng added a comment to D94403: [RISCV] Implement new architecture extension macros.

Thanks you implement that on clang, I think it's really great to included that in LLVM 12 release.

Jan 17 2021, 7:50 PM · Restricted Project

Jan 12 2021

kito-cheng added inline comments to D94579: [RISCV] add the MC layer support of P extension.
Jan 12 2021, 10:42 PM · Restricted Project
kito-cheng added a comment to D94568: [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec..

RVB 0.93 is an awkward version to me, there is mnemonic conflict which is not resolved during release process since it's kind of too rush, the conflict one is bext in zbe and zbs...

Jan 12 2021, 7:05 PM · Restricted Project
kito-cheng added a comment to D94142: [IR] Allow scalable vectors in structs to support intrinsics returning multiple values..

It won't be a struct in clang's type system. It's it own special builtin type. I hope we can control the codegen of that type and emit it as multiple allocas/loads/stores. I haven't looked at this yet. Clang can also emit fixed size memcpys of structs which would be broken for this. So we are going to need to customize clang.

Jan 12 2021, 6:54 PM · Restricted Project

Jan 10 2021

kito-cheng added a comment to D94142: [IR] Allow scalable vectors in structs to support intrinsics returning multiple values..

This patch removes the existing restriction for this. I've modified
StructType::isSized to consider a struct containing scalable vectors
as unsized so the verifier won't allow loads/stores/allocas of these
structs.

Jan 10 2021, 11:21 PM · Restricted Project

Jan 7 2021

kito-cheng added a comment to D94142: [IR] Allow scalable vectors in structs to support intrinsics returning multiple values..

Don't allow function arguments or returns to use structs containing scalable vectors unless they are intrinsics.

Jan 7 2021, 4:57 AM · Restricted Project

Jan 5 2021

kito-cheng added a comment to D93826: [RISCV] Don't print zext.b alias..

Note from gnu toolchain side, GCC will detect bintuils version and behavior during configure time and set different default behavior according the version or feature support test result, but I know clang/llvm doing different way on this part.

Jan 5 2021, 5:03 AM · Restricted Project

Dec 21 2020

kito-cheng added inline comments to D93613: [RISCV] Add new V instructions and aliases in v1.0-08a0b46..
Dec 21 2020, 2:26 AM · Restricted Project

Dec 19 2020

kito-cheng added a comment to D93312: [RISCV] Add ISel support for RVV vector/scalar forms.

64 bit splat on rv32 code gen sequence is LGTM, but I think that's all I can review :P

Dec 19 2020, 7:11 PM · Restricted Project

Dec 17 2020

kito-cheng added a comment to D93312: [RISCV] Add ISel support for RVV vector/scalar forms.

I was wondering if we could do something like (with a0=lo and a1=hi):

vmv.v.x vX, a1
vsll.vx vX, vX, /*32*/
vor.vx vX, vX, a0

And then do a .vv operation.

We can then optimize for a sign-extended 32-bit value later. What do you think?

Dec 17 2020, 9:20 AM · Restricted Project
kito-cheng added a comment to D93312: [RISCV] Add ISel support for RVV vector/scalar forms.

Also, it will not handle 64-bit scalars in RV32, but I don't believe that's
actually supported in the spec?

Dec 17 2020, 6:50 AM · Restricted Project

Dec 16 2020

kito-cheng added a comment to D93298: [RISCV] add the MC layer support of Zfinx extension.

Do you have implement register pair for rv32ifd_zfinx? I didn't saw the related implementation, but I could be wrong since I am not LLVM expert, in case you have implemented, you need a test case for that.

Dec 16 2020, 7:28 AM · Restricted Project, Restricted Project

Dec 10 2020

kito-cheng added inline comments to D92479: [RISCV] remove redundant instruction when eliminate frame index.
Dec 10 2020, 10:54 PM · Restricted Project
kito-cheng added inline comments to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..
Dec 10 2020, 5:42 AM · Restricted Project

Dec 9 2020

kito-cheng added a comment to D92793: [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions.

Spec changes has been merged :)

Dec 9 2020, 7:25 PM · Restricted Project

Dec 8 2020

kito-cheng added a comment to D92793: [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions.

That's LGTM too, just waiting the spec merge :)

Dec 8 2020, 1:03 AM · Restricted Project

Dec 7 2020

kito-cheng added inline comments to D92715: [Clang][RISCV] Define RISC-V V builtin types.
Dec 7 2020, 9:10 PM · Restricted Project

Nov 11 2020

kito-cheng added a comment to D91319: [RISCV] ELF attribute for B and V extension..

I think zv* need to set too, seems like we should have more word about extension is consisted with several sub-extensions on the ELF attribute spec.

Nov 11 2020, 11:44 PM · Restricted Project

Nov 10 2020

kito-cheng added a comment to D90738: [RISCV] Support Zfh half-precision floating-point extension..

Could you add zfh to ELF attribute output?

Nov 10 2020, 6:38 PM · Restricted Project

Oct 14 2020

kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

@MaskRay Thanks, that's first time I know the suffix -SAME :P

Oct 14 2020, 8:43 PM · Restricted Project, Restricted Project
kito-cheng updated the diff for D89025: [RISCV] Add -mtune support.

ChangeLog:

  • Update testcase according to MaskRay's suggestion.
Oct 14 2020, 8:41 PM · Restricted Project, Restricted Project
kito-cheng added reviewers for D89288: [RISCV] Enable the use of the old sptbr name: luismarques, lenary.
Oct 14 2020, 7:41 PM · Restricted Project
kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

RISCV supports -mcpu with default empty arch to align gcc's -mtune behavior since clang didn't support -mtune before. But now clang has -mtune, is it a good idea to remove those options? (ex. rocket-rv32/rv64, sifive-7-rv32/64)

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang with GCC. But I wonder if this might be too problematic, in terms of compatibility.

Oct 14 2020, 1:06 AM · Restricted Project, Restricted Project
kito-cheng updated the diff for D89025: [RISCV] Add -mtune support.

ChangeLog

  • Fix wording in comment
  • Add more comment in testcase
  • Fix format issue.
Oct 14 2020, 1:02 AM · Restricted Project, Restricted Project

Oct 13 2020

kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang with GCC. But I wonder if this might be too problematic, in terms of compatibility.

Oct 13 2020, 8:52 PM · Restricted Project, Restricted Project

Oct 12 2020

kito-cheng added inline comments to D89244: [RISCV][ASAN] Fix TLS offsets.
Oct 12 2020, 7:59 PM · Restricted Project

Oct 7 2020

kito-cheng requested review of D89025: [RISCV] Add -mtune support.
Oct 7 2020, 8:45 PM · Restricted Project, Restricted Project
kito-cheng requested review of D88951: [Tablegen][SubtargetEmitter] Print TuneCPU in Subtarget::ParseSubtargetFeatures.
Oct 7 2020, 2:12 AM · Restricted Project

Sep 24 2020

kito-cheng accepted D87997: [RISCV][crt] support building without init_array.

But this logic is enabled only if CRT_HAS_INITFINI_ARRAY is not defined. Which is controlled by cmake (configuration script). In addition, other architectures (x86, sparc, arm, aarch64, sparc, powerpc) - do allow such fallback option. It just seems strange that RISCV does not have one.

Sep 24 2020, 2:33 AM · Restricted Project
kito-cheng added a comment to D87997: [RISCV][crt] support building without init_array.

RISC-V LLVM and GCC are default using init_array, curious why we need this?

Actually, yes. You are correct - this one is not needed for ASAN support... My understanding is that this may be needed if we link against some custom runtime. I'll adjust the description of the patch.

Sep 24 2020, 2:07 AM · Restricted Project

Sep 22 2020

kito-cheng added a comment to D87997: [RISCV][crt] support building without init_array.

RISC-V LLVM and GCC are default using init_array, curious why we need this?

Sep 22 2020, 8:18 PM · Restricted Project

Aug 19 2020

kito-cheng added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.

Hi Jun:

GCC part should review at gcc-patch mailing list instead of here, for other files (sanitizer_platform.h, sanitizer_common.h and sanitizer_symbolizer_libcdep.cpp), it's right place to review, but it should using the diff which generated within LLVM source-tree, and GCC will sync libsanitizer after LLVM is accepted.

What about config/riscv/riscv.c? Should I place it here to review?

Aug 19 2020, 12:28 AM

Aug 18 2020

kito-cheng added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.

Hi Jun:

Aug 18 2020, 11:36 PM

Aug 6 2020

kito-cheng added a comment to D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.

Zvamo implies A-extension.

I think it's require instead of imply?

Aug 6 2020, 11:53 PM · Restricted Project

May 28 2020

kito-cheng added inline comments to D80690: [RISCV] Support libunwind for riscv32.
May 28 2020, 7:15 PM · Restricted Project, Restricted Project

May 7 2020

kito-cheng added a comment to D79521: [RISCV] Add SiFive's interrupt modes.

Upstream didn't support those SiFive specific function attribute, and there is no plan to upstream unless CLIC ratified.
And I guess the attribute name would changed after GCC upstream, at least the prefix of SiFive- would be removed.

May 7 2020, 7:20 AM · Restricted Project

Apr 30 2020

kito-cheng added inline comments to D71124: [RISCV] support clang driver to select cpu.
Apr 30 2020, 7:56 AM · Restricted Project, Restricted Project
kito-cheng added a comment to D71124: [RISCV] support clang driver to select cpu.

Another proposal for -mcpu and -mtune:

Apr 30 2020, 2:06 AM · Restricted Project, Restricted Project

Feb 23 2020

kito-cheng added a comment to D74023: [RISCV] ELF attribute section for RISC-V.

Could you add following kind of test:

Feb 23 2020, 10:23 PM · Restricted Project, Restricted Project

Jan 10 2020

kito-cheng added a comment to D69987: [RISCV] Assemble/Disassemble v-ext instructions..

It seems to me that all remarks have already been addressed. Is there anything holding this patch? For it pretty much LGTM.

Jan 10 2020, 11:57 PM · Restricted Project, Restricted Project

Jan 9 2020

kito-cheng added a comment to D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.

Seems like this patch mixed with LTO related changes? Could you clean it up?

Jan 9 2020, 8:49 AM · Restricted Project, Restricted Project

Nov 14 2019

kito-cheng added a comment to D70116: [RISCV] add subtargets initialized with target feature.

In addition, I think my testcase is so weird and it does not make sense there are different isa extension are used in the same compilation unit...

Nov 14 2019, 7:30 AM · Restricted Project

Nov 8 2019

kito-cheng added inline comments to D69987: [RISCV] Assemble/Disassemble v-ext instructions..
Nov 8 2019, 1:15 AM · Restricted Project, Restricted Project

Oct 16 2019

kito-cheng added a reviewer for D68685: [RISCV] Scheduler description for Rocket Core: HsiangKai.
Oct 16 2019, 12:47 AM · Restricted Project

Oct 8 2019

kito-cheng added inline comments to D68685: [RISCV] Scheduler description for Rocket Core.
Oct 8 2019, 11:08 PM · Restricted Project

Sep 17 2019

kito-cheng added inline comments to D67508: [RISCV] support mutilib in baremetal environment.
Sep 17 2019, 3:33 PM · Restricted Project
kito-cheng committed rG42fe2fc8c935: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow (authored by kito-cheng).
[RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow
Sep 17 2019, 1:19 AM
kito-cheng committed rG645593844164: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly (authored by kito-cheng).
[RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly
Sep 17 2019, 1:10 AM

Sep 12 2019

kito-cheng added inline comments to D67409: [RISCV] enable LTO support, pass some options to linker..
Sep 12 2019, 1:48 PM · Restricted Project

Sep 2 2019

kito-cheng created D67066: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow.
Sep 2 2019, 2:16 AM · Restricted Project, Restricted Project
kito-cheng created D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly.
Sep 2 2019, 2:11 AM · Restricted Project, Restricted Project

Aug 1 2019

kito-cheng added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 1 2019, 5:25 AM · Restricted Project

Jul 2 2019

kito-cheng committed rGeb9bc3827605: [ELF][RISCV] Support RISC-V in getBitcodeMachineKind (authored by kito-cheng).
[ELF][RISCV] Support RISC-V in getBitcodeMachineKind
Jul 2 2019, 7:14 PM

Jul 1 2019

kito-cheng updated the diff for D52165: [RISCV] Support RISC-V in getBitcodeMachineKind.

Add 2 test cases.

Jul 1 2019, 10:39 PM · Restricted Project
kito-cheng added a comment to D52165: [RISCV] Support RISC-V in getBitcodeMachineKind.

@MaskRay Thanks, I'll add test case soon :)

Jul 1 2019, 8:42 PM · Restricted Project

Feb 19 2019

kito-cheng committed rG303217e8b43d: [RISCV] Implement pseudo instructions for load/store from a symbol address. (authored by kito-cheng).
[RISCV] Implement pseudo instructions for load/store from a symbol address.
Feb 19 2019, 7:32 PM

Feb 10 2019

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Update test/MC/RISCV/rvi-pseudos-invalid.s
Feb 10 2019, 7:28 PM · Restricted Project

Feb 5 2019

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Fix parseBareSymbol with a constant symbols.
  • Rebase to D55325
Feb 5 2019, 10:47 AM · Restricted Project

Jan 24 2019

kito-cheng added a comment to D57141: [RISCV] Add implied zero offset load/store alias patterns.

@jrtc27 feel free to upload your one, it's just a 5 minute quick patch :P

Jan 24 2019, 6:56 PM · Restricted Project

Jan 23 2019

kito-cheng created D57141: [RISCV] Add implied zero offset load/store alias patterns.
Jan 23 2019, 11:31 PM · Restricted Project

Jan 16 2019

kito-cheng updated the diff for D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..

Changes:

  • Update testcase, R_RISCV_RELAX won't bind with symbol to fit binutils's behavior.
Jan 16 2019, 6:32 PM

Jan 14 2019

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Add missing tests
Jan 14 2019, 10:31 PM · Restricted Project

Jan 10 2019

kito-cheng added a comment to D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..

Okay, I'll take a look :)

Jan 10 2019, 8:38 AM
kito-cheng added inline comments to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
Jan 10 2019, 7:58 AM · Restricted Project
kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Merge emitLoadLocalAddress/emitLoadSymbol/emitStoreSymbol
  • Fix wrong operand type and syntax for floating point load instruction.
Jan 10 2019, 7:53 AM · Restricted Project

Oct 15 2018

kito-cheng added a comment to D53291: add riscv32e to the llvm.

rv32e arch and ilp32e ABI is decoupling in GCC, that's mean rv32i with ilp32e is possible, so I would suggest separate two thing.

Oct 15 2018, 7:26 PM · Restricted Project

Oct 4 2018

kito-cheng added a comment to D51828: [RISCV] Fix disassembling of fence instruction with invalid field.

Hi Ana:

Oct 4 2018, 12:52 AM
kito-cheng added a comment to D48430: [RISCV] Add support for lowering jumptables.

GCC using 5 as threshold to decide using jump table or not for RISC-V and LLVM using 4.

Oct 4 2018, 12:26 AM

Sep 26 2018

kito-cheng added inline comments to D38719: [llvm-dwarfdump] Verify compatible TAG for attributes..
Sep 26 2018, 1:37 AM · debug-info

Sep 17 2018

kito-cheng created D52165: [RISCV] Support RISC-V in getBitcodeMachineKind.
Sep 17 2018, 1:59 AM · Restricted Project

Aug 29 2018

kito-cheng added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 29 2018, 2:21 AM

Aug 22 2018

kito-cheng updated the diff for D50043: [RISCV] RISC-V using -fuse-init-array by default.

Changes:

  • Add test.
Aug 22 2018, 10:26 AM
kito-cheng updated the diff for D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..

Changes:

  • Move declaration of RelaxCandidate.
  • Add comment.
  • Update testcase
Aug 22 2018, 10:01 AM
kito-cheng added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Hi Roger:

Aug 22 2018, 8:27 AM · Restricted Project
kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Rebase.
Aug 22 2018, 8:23 AM · Restricted Project

Aug 13 2018

kito-cheng added inline comments to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
Aug 13 2018, 2:30 AM · Restricted Project
kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Rename functions
    • emitLoadSymbolAddress -> emitLoadSymbolAddressHi
    • emitLoadWithSymbol -> emitLoadSymbol
    • emitStoreWithSymbol -> emitStoreSymbol
  • Return shouldForceImediateOperand to true for new pseudo instructions.
  • Add negative test
Aug 13 2018, 2:26 AM · Restricted Project

Aug 9 2018

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
  • Add default case in switch.
Aug 9 2018, 1:59 AM · Restricted Project
kito-cheng created D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
Aug 9 2018, 1:55 AM · Restricted Project

Aug 2 2018

kito-cheng updated the diff for D50217: [RISCV] Add mnemonic alias: move, sbreak and scall..

Rearrange order for testcase.

Aug 2 2018, 8:12 PM
kito-cheng created D50217: [RISCV] Add mnemonic alias: move, sbreak and scall..
Aug 2 2018, 8:08 PM
kito-cheng updated the diff for D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..

Changes:

  • Update testcase for rv32i-aliases-invalid.s and rv64i-aliases-invalid.s
  • Fix rv32i-invalid.s
Aug 2 2018, 7:53 PM
kito-cheng updated the diff for D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..

Changes:

  • Add addw, sllw, srlw and sraw including testcase.
  • Add comment in testcase.
Aug 2 2018, 3:08 AM

Jul 31 2018

kito-cheng added inline comments to D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..
Jul 31 2018, 6:34 PM
kito-cheng updated the diff for D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..

Update testcase.

Jul 31 2018, 3:22 AM