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rogfer01 (Roger Ferrer Ibanez)
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User Since
May 10 2016, 6:42 AM (256 w, 4 d)

Recent Activity

Wed, Apr 7

rogfer01 accepted D100035: [RISCV] Add scalable offset under very large stack size..

LGTM. Thanks @HsiangKai.

Wed, Apr 7, 10:57 PM · Restricted Project
rogfer01 accepted D100084: [NFC][RISCV] Add test for scalable offset under large stack size..

LGTM

Wed, Apr 7, 10:57 PM · Restricted Project

Thu, Apr 1

rogfer01 added a comment to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).

My question is how to count the scalar incoming argument with this frame layout,
because scalar incoming arguments cross RVV previous local variables frame objects.
In the current frame(callee), we don't know the RVV previous local variables count.
So we can't get the real stack offset because callee not know the caller vector local variables size.

Thu, Apr 1, 7:52 AM · Restricted Project
rogfer01 added inline comments to D97264: [RISCV] Define types for Zvlsseg..
Thu, Apr 1, 12:48 AM · Restricted Project
rogfer01 added a comment to D99236: [RISCV] Turn splat shuffles of vector loads into scalar loads and a splat..

One could argue that this introduces coupling between the scalar register bank and the vector register bank. But I presume the simpler scalar load makes up for that loss of decoupling.

Thu, Apr 1, 12:21 AM · Restricted Project

Wed, Mar 31

rogfer01 added a comment to D97264: [RISCV] Define types for Zvlsseg..

I was under the impression we didn't want to use class-member access syntax for vector tuples (see https://github.com/riscv/rvv-intrinsic-doc/issues/17#issuecomment-628998077 ) so we don't need a record type, do we?

Wed, Mar 31, 11:50 PM · Restricted Project
rogfer01 added a comment to D99593: [Clang][RISCV] Implement vlseg builtins..

This is just a suggestion, feel free to ignore: a sequence of Ts was easy to parse for the prototype but may be want to consider something like T3v rather than TTTv. I think it would simplify the TString tblgen class and those std::string(N, 'T').

Wed, Mar 31, 11:21 PM · Restricted Project

Tue, Mar 30

rogfer01 added a comment to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).

Hi @SuH wrote:

I have a question about access incoming args.

Tue, Mar 30, 2:26 AM · Restricted Project

Mon, Mar 29

rogfer01 committed rG489ca73ac497: [PrologEpilogInserter][AMDGPU] Only adjust offset for emergency spill slots if… (authored by rogfer01).
[PrologEpilogInserter][AMDGPU] Only adjust offset for emergency spill slots if…
Mon, Mar 29, 10:27 AM
rogfer01 closed D99504: [PrologEpilogInserter][AMDGPU] Only adjust offset for emergency spill slots if the stack grows down.
Mon, Mar 29, 10:27 AM · Restricted Project
rogfer01 committed rGef76a333faca: [RISCV] Fix offset computation for RVV (authored by rogfer01).
[RISCV] Fix offset computation for RVV
Mon, Mar 29, 10:04 AM
rogfer01 closed D98802: [RISCV] Fix offset computation for RVV.
Mon, Mar 29, 10:04 AM · Restricted Project
rogfer01 committed rG3abd0bacc2c5: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers (authored by rogfer01).
[NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers
Mon, Mar 29, 10:03 AM
rogfer01 closed D98801: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers.
Mon, Mar 29, 10:03 AM · Restricted Project
rogfer01 committed rG96d14ff505bf: [NFC][RISCV] Pass file through update_llc_tests to fix whitespace issues (authored by rogfer01).
[NFC][RISCV] Pass file through update_llc_tests to fix whitespace issues
Mon, Mar 29, 10:03 AM
rogfer01 closed D98800: [NFC][RISCV] Pass test through update_llc_tests_checks.py to address whitespace issues.
Mon, Mar 29, 10:03 AM · Restricted Project
rogfer01 updated the diff for D98802: [RISCV] Fix offset computation for RVV.

ChangeLog:

  • Rebase
Mon, Mar 29, 9:30 AM · Restricted Project
rogfer01 added a comment to D98801: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers.

LGTM though (sorry) maybe the tests could have a short comment explaining what they're testing (since they'll be fixed by a future patch anyway) and what to be wary of when the output changes.

Mon, Mar 29, 9:29 AM · Restricted Project
rogfer01 updated the diff for D98801: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers.

ChangeLog:

  • Describe a bit better the purpose of the test.
Mon, Mar 29, 9:29 AM · Restricted Project
rogfer01 requested review of D99504: [PrologEpilogInserter][AMDGPU] Only adjust offset for emergency spill slots if the stack grows down.
Mon, Mar 29, 6:51 AM · Restricted Project

Fri, Mar 26

rogfer01 added inline comments to D96444: [OpenMP][NFC] Use `AsyncInfo` as the variable name for a `__tgt_async_info`.
Fri, Mar 26, 9:17 AM · Restricted Project

Tue, Mar 23

rogfer01 added a comment to D98802: [RISCV] Fix offset computation for RVV.

I have internally validated that the last change (Diff 331637, not Diff 332358 that only adds a comment) is equivalent to the previous change (Diff 331546).

Tue, Mar 23, 8:42 AM · Restricted Project
rogfer01 retitled D98802: [RISCV] Fix offset computation for RVV from [RISCV][WIP] Fix offset computation for RVV to [RISCV] Fix offset computation for RVV.
Tue, Mar 23, 8:39 AM · Restricted Project

Mon, Mar 22

rogfer01 updated the diff for D98802: [RISCV] Fix offset computation for RVV.

ChangeLog:

  • Add comment explaining why we add the alignment of the stack as RVV padding when CSR are not aligned to 8 bytes.
Mon, Mar 22, 10:41 AM · Restricted Project
rogfer01 updated the diff for D98801: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers.

ChangeLog:

  • Clarify the purpose of the change.
  • Adjust syntax of the IR input.
Mon, Mar 22, 10:28 AM · Restricted Project
rogfer01 added inline comments to D98802: [RISCV] Fix offset computation for RVV.
Mon, Mar 22, 1:45 AM · Restricted Project

Fri, Mar 19

rogfer01 added inline comments to D98802: [RISCV] Fix offset computation for RVV.
Fri, Mar 19, 6:45 AM · Restricted Project

Thu, Mar 18

rogfer01 updated the diff for D98802: [RISCV] Fix offset computation for RVV.

ChangeLog:

  • Fold the padding into the main stack size enlargement: adjust CSR offsets accordingly, as suggested by @StephenFan
  • Add {get,set}RVVPadding to RISCVMachineFunctionInfo to materialise the extra padding required by RVV.
Thu, Mar 18, 11:27 AM · Restricted Project
rogfer01 added a comment to D98802: [RISCV] Fix offset computation for RVV.

Hi @rogfer01 ! It is reasonable to me. But I think the instruction of BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), SPReg) can be eliminated. Firstly, the value of calleeSavedStackSize can be regarded as a aligned value(For example, aligned to MFI.getStackAlign()). Then we can calculate the padding size by the aligned calleeSavedStackSize minus the original calleeSavedStackSize. When emits prologue, we can minus the value of MFI.getStackSize() - original calleeSavedStackSize + aligned calleeSavedStackSize. When get the offset of the rvv object, we can MFI.getStackSize() - original calleesavedStackSize, because we just want to calculate the non-calleesaved field size.

Thu, Mar 18, 9:21 AM · Restricted Project
rogfer01 added a comment to D98802: [RISCV] Fix offset computation for RVV.

I feel this might a bit complicated to grasp from my attempt of explanation in the summary, so this is how the stack should look like for wrong-stack-slot-rv32.mir assuming VLENB=128.

Thu, Mar 18, 7:05 AM · Restricted Project
rogfer01 updated the diff for D98802: [RISCV] Fix offset computation for RVV.

ChangeLog:

  • Add extra padding so we can adjust RVV objects within the stack correctly
  • Round the offset to the RVV objects to 8 bytes (when not using fp).
  • Move computation of CalleeSavedStackSize from processFunctionBeforeFrameIndicesReplaced to processFunctionBeforeFrameFinalized because we need that size before we emit the prologue.
Thu, Mar 18, 7:01 AM · Restricted Project
rogfer01 added a reviewer for D98801: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers: frasercrmck.
Thu, Mar 18, 6:41 AM · Restricted Project
rogfer01 updated the diff for D98801: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers.

ChangeLog:

  • Simplify the MIR input
  • Split test in two for RV32 and RV64
Thu, Mar 18, 6:36 AM · Restricted Project

Wed, Mar 17

rogfer01 added a comment to D98802: [RISCV] Fix offset computation for RVV.

Hum, this is not right. I just realized that we may need some extra padding between the end of the scalar part and the RVV stack slots. That padding hasn't been accounted anywhere.

Wed, Mar 17, 12:30 PM · Restricted Project
rogfer01 updated the summary of D98802: [RISCV] Fix offset computation for RVV.
Wed, Mar 17, 11:57 AM · Restricted Project
rogfer01 requested review of D98802: [RISCV] Fix offset computation for RVV.
Wed, Mar 17, 11:54 AM · Restricted Project
rogfer01 requested review of D98801: [NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers.
Wed, Mar 17, 11:37 AM · Restricted Project
rogfer01 requested review of D98800: [NFC][RISCV] Pass test through update_llc_tests_checks.py to address whitespace issues.
Wed, Mar 17, 11:34 AM · Restricted Project

Mar 10 2021

rogfer01 added a comment to D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions..

Overall LGTM. Thanks @khchen!

Mar 10 2021, 11:31 PM · Restricted Project

Mar 9 2021

rogfer01 accepted D98062: [RISCV] Don't modify the SEW immediate on the V extension pseudo instructions after inserting VSETVLI..

Hi. We did this out of an abundance of caution. We wanted to be sure after the vsetvli were emitted, we didn't attempt to use the SEW operand (either by accident or intentionally).

Mar 9 2021, 8:39 AM · Restricted Project
rogfer01 accepted D97111: [RISCV] change rvv frame layout.

Except for the minor comments above, LGTM.

Mar 9 2021, 12:56 AM · Restricted Project

Mar 1 2021

rogfer01 added a comment to D97274: [RISCV] replace unuseful emergency spill slot test with a mir test.

Yes, I referenced this out-of-reach-emergency-slot.mir test. But with a stack object that has a out-of-range size. And I think my use-emergency-spill-slot.mir test and out-of-reach-emergency-slot.mir test are a little repeated. So should I keep my use-emergency-spill-slot.mir test or delete it?

Mar 1 2021, 2:51 AM · Restricted Project
rogfer01 added a comment to D97274: [RISCV] replace unuseful emergency spill slot test with a mir test.

Isn't this very similar to https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir except for a missing SD?

Mar 1 2021, 1:10 AM · Restricted Project
rogfer01 added a comment to D97111: [RISCV] change rvv frame layout.

Can you add some tests for the cases with overaligned stuff and variable sized + rvv?

Mar 1 2021, 12:36 AM · Restricted Project

Feb 23 2021

rogfer01 added inline comments to D97111: [RISCV] change rvv frame layout.
Feb 23 2021, 3:18 AM · Restricted Project

Feb 20 2021

rogfer01 added a comment to D97111: [RISCV] change rvv frame layout.

Hi @StephenFan. I wonder if we want to do this only when we index via sp.

Feb 20 2021, 1:29 PM · Restricted Project

Feb 17 2021

rogfer01 accepted D96937: [RISCV] Fix bugs in pseudo instructions for masked segment load..

Thanks @HsiangKai. LGTM.

Feb 17 2021, 11:44 PM · Restricted Project

Feb 16 2021

rogfer01 accepted D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).

I'm happy with the patch as it stands now. At least it gives us a baseline to improve if that is needed.

Feb 16 2021, 1:42 PM · Restricted Project
rogfer01 added a comment to D96025: [LoopVectorize] Return both fixed and scalable Max VF from computeMaxVF..

Hi Sander, one question OptionalVFCandidates::addMaxVF combines using the maximum but AFAICT it is not used in a loop. Maybe you plan to "update" the corresponding VF values (scalable and/or fixed) in other places (not shown in the current patch, yet)?

Feb 16 2021, 3:53 AM · Restricted Project

Feb 5 2021

rogfer01 added inline comments to D94229: [RISCV] Implement vlseg intrinsics..
Feb 5 2021, 2:37 PM · Restricted Project

Feb 2 2021

rogfer01 added inline comments to D95800: [RISCV] Make scalable vector FMA commutable for register allocation..
Feb 2 2021, 10:55 PM · Restricted Project

Feb 1 2021

rogfer01 added a comment to D95844: [RISCV] Use a ComplexPattern to merge isel patterns for vector load/store with GPR and FrameIndex addresses..

I understand it is not a win to apply a similar scheme to the base RISCVInstrInfo.td and perhaps F's and D's because we do have an offset available there. Is my understanding correct?

Feb 1 2021, 11:29 PM · Restricted Project
rogfer01 accepted D95833: [RISCV] Replace NoX0 SDNodeXForm with a ComplexPattern to do the selection of the VL operand..

I admit that I initially wasn't convinced by the idea of ComplexPattern including both the matching logic (which is only return true) and a bit of selection logic (selectImm) in the input DAG. But on a second thought this allows the two logics be kept together.

Feb 1 2021, 11:23 PM · Restricted Project

Jan 29 2021

rogfer01 added a comment to D95659: [RISCV] Initial support of LoopVectorizer for RISC-V Vector..

Hi Kai, are we OK with having a test that goes from IR to assembly in the Transforms component?

Jan 29 2021, 3:22 AM · Restricted Project

Jan 27 2021

rogfer01 accepted D95491: [RISCV] Group the legal vector types into lists we can iterator over in the RISCVISelLowering constructor.

LGTM. Thanks @craig.topper

Jan 27 2021, 1:47 AM · Restricted Project

Jan 25 2021

rogfer01 added inline comments to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).
Jan 25 2021, 11:19 PM · Restricted Project
rogfer01 added inline comments to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).
Jan 25 2021, 11:17 PM · Restricted Project
rogfer01 added inline comments to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).
Jan 25 2021, 1:16 PM · Restricted Project
rogfer01 added a comment to D95234: [RISCV] Define different pseudo instructions for different FPR..

We're multiplying by 3 the _VF pseudos but to be honest I don't see any better alternative.

Jan 25 2021, 1:02 PM · Restricted Project

Jan 24 2021

rogfer01 added inline comments to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).
Jan 24 2021, 2:29 AM · Restricted Project

Jan 23 2021

rogfer01 committed rGd4ce06234006: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making… (authored by rogfer01).
[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making…
Jan 23 2021, 1:25 AM
rogfer01 closed D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.
Jan 23 2021, 1:25 AM · Restricted Project

Jan 19 2021

rogfer01 added a comment to D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.

Ping.

Jan 19 2021, 12:45 AM · Restricted Project

Jan 18 2021

rogfer01 added a comment to D94286: [RISCV] Add a VL output to vleff intrinsics..

This seems a very sensible approach.

Jan 18 2021, 12:57 PM · Restricted Project

Jan 15 2021

rogfer01 added inline comments to D94294: [RISCV] Add scalable vector vselect ISel patterns.
Jan 15 2021, 2:30 AM · Restricted Project
rogfer01 added inline comments to D94294: [RISCV] Add scalable vector vselect ISel patterns.
Jan 15 2021, 2:27 AM · Restricted Project

Jan 12 2021

rogfer01 added a comment to D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version).

I prefer this approach. Computing the address is a bit more involved but doesn't need an extra memory access.

Jan 12 2021, 12:06 AM · Restricted Project

Jan 11 2021

rogfer01 added a comment to D90853: [RISCV] Add DAG nodes to represent read/write CSR.

Hi Serge,

Jan 11 2021, 1:28 AM · Restricted Project

Jan 10 2021

rogfer01 accepted D94375: [RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags..

This is a very nice cleanup. Thanks @craig.topper!

Jan 10 2021, 12:42 PM · Restricted Project

Jan 9 2021

rogfer01 added inline comments to D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.
Jan 9 2021, 1:58 PM · Restricted Project
rogfer01 updated the diff for D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.

ChangeLog:

  • Largely simplify the testcase by making a call that uses all the eligible registers forcing the RegisterScavenger to use the emergency spill.
Jan 9 2021, 1:29 PM · Restricted Project
rogfer01 committed rG524d8fa9a5a5: [RISCV] Do not grow the stack a second time when we need to realign the stack (authored by rogfer01).
[RISCV] Do not grow the stack a second time when we need to realign the stack
Jan 9 2021, 8:55 AM
rogfer01 closed D89237: [RISCV] Do not grow the stack a second time when we need to realign the stack.
Jan 9 2021, 8:54 AM · Restricted Project
rogfer01 updated the diff for D89237: [RISCV] Do not grow the stack a second time when we need to realign the stack.

ChangeLog:

  • Rebase patch prior committing
Jan 9 2021, 8:36 AM · Restricted Project

Jan 6 2021

rogfer01 added a comment to D90853: [RISCV] Add DAG nodes to represent read/write CSR.

Hi Serge, would it make sense to use a Pseudo for those specific cases with a custom inserter? (usesCustomInserter = 1 in the tablegen definition of the Pseudo)

Jan 6 2021, 10:33 AM · Restricted Project

Dec 17 2020

rogfer01 added a comment to D93487: [RISCV] Sign extend constant arguments to V intrinsics when promoting to XLen..

For instructions that use a uimm5 immediate, this change only affects
constants >= 128 for i8 or >= 32768 for i16. Constants that large
already wouldn't have been eligible for uimm5 and would need to use a
scalar register.

Dec 17 2020, 12:59 PM · Restricted Project

Dec 16 2020

rogfer01 added inline comments to D93364: [RISCV] Load/Store vector mask types..
Dec 16 2020, 2:17 PM · Restricted Project
rogfer01 added inline comments to D93364: [RISCV] Load/Store vector mask types..
Dec 16 2020, 2:16 PM · Restricted Project

Dec 14 2020

rogfer01 added a comment to D93218: [RISCV] Define vminu/vmin/vmaxu/vmax intrinsics..

Agreed, these instructions and their intrinsics seems pretty uncontroversial. LGTM.

Dec 14 2020, 11:59 PM · Restricted Project
rogfer01 added inline comments to D93193: [RISCV] Define vsll/vsrl/vsra intrinsics..
Dec 14 2020, 11:58 PM · Restricted Project
rogfer01 added a comment to D93108: [RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics..

Also LGTM once Craig's comments are addressed. Thanks a lot Kai!

Dec 14 2020, 11:49 PM · Restricted Project

Dec 11 2020

rogfer01 accepted D92679: [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block..

This looks good to me. Thanks a lot @craig.topper

Dec 11 2020, 8:46 AM · Restricted Project

Dec 10 2020

rogfer01 added inline comments to D93013: [RISCV] Define vadd/vsub/vrsub intrinsics and lower to V instructions..
Dec 10 2020, 8:49 AM · Restricted Project

Dec 4 2020

rogfer01 added inline comments to D92679: [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block..
Dec 4 2020, 1:56 PM · Restricted Project
rogfer01 added inline comments to D92679: [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block..
Dec 4 2020, 1:44 PM · Restricted Project
rogfer01 added inline comments to D92679: [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block..
Dec 4 2020, 1:40 PM · Restricted Project
rogfer01 added a comment to D92679: [RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block..

As a first step to remove the most obviously redundant vsetvli cases, this LGTM.

Dec 4 2020, 12:32 PM · Restricted Project
rogfer01 added a comment to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.

I don't know if we're going to have an answer for the masked/unmasked soon. I think we might just use earlyclobber in the initial patches and suffer the bad register allocation so we can make forward progress.

Dec 4 2020, 1:52 AM · Restricted Project

Dec 1 2020

rogfer01 added a comment to D57504: RFC: Prototype & Roadmap for vector predication in LLVM.

Hi @simoll: a quick question regarding vp.load/vp.store/vp.gather/vp.scatter. Does the current definition of VPred allow for something similar to the !nontemporal metadata of regular load/store instructions? I don't see any explicit mention to that but maybe it is already possible using metadata or some other annotation?

Dec 1 2020, 12:30 AM · Restricted Project

Nov 30 2020

rogfer01 added a comment to D92228: [RISCV] Add MIR tests exposing missed InstAliases.

Hi all,

Nov 30 2020, 1:44 PM · Restricted Project

Nov 24 2020

rogfer01 added a comment to D92027: [OpenMP] libomp: fix non-X86 non-AARCH64 builds.

Hi Andrey, I can confirm this fixes the build for RISC-V.

Nov 24 2020, 9:37 AM · Restricted Project

Nov 18 2020

rogfer01 added a comment to D89898: changing OMP rtl to use shared memory instead of env variable .

Hi Todd,

Nov 18 2020, 11:23 PM · Restricted Project
rogfer01 added a comment to D89898: changing OMP rtl to use shared memory instead of env variable .

Hi Todd,

Nov 18 2020, 9:37 AM · Restricted Project
rogfer01 added a comment to D89898: changing OMP rtl to use shared memory instead of env variable .

Random number won't work, because the goal of the library registering is to catch several libraries in a single process. So a process should have deterministic file name (or environment variable name).

Nov 18 2020, 7:44 AM · Restricted Project

Nov 17 2020

rogfer01 added a comment to D89898: changing OMP rtl to use shared memory instead of env variable .

[Drive by] What about appending the process id or a random number to the file name, or both?

Nov 17 2020, 11:23 AM · Restricted Project
rogfer01 added a comment to D89898: changing OMP rtl to use shared memory instead of env variable .

Hi Todd,

Nov 17 2020, 10:18 AM · Restricted Project
rogfer01 added a comment to D89898: changing OMP rtl to use shared memory instead of env variable .

Hi, one question about this change:

Nov 17 2020, 8:52 AM · Restricted Project

Nov 14 2020

rogfer01 added inline comments to D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.
Nov 14 2020, 6:11 AM · Restricted Project

Nov 13 2020

rogfer01 added inline comments to D89239: [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer.
Nov 13 2020, 12:53 AM · Restricted Project

Nov 11 2020

rogfer01 added inline comments to D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension.
Nov 11 2020, 1:45 AM · Restricted Project