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Differential D99655

[RISCV] Test llvm.experimental.vector.insert intrinsics on RV32
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Authored by frasercrmck on Mar 31 2021, 5:08 AM.

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craig.topper
evandro
rogfer01
HsiangKai
khchen
arcbbb
asb

Commits

rG411673e769ac: [RISCV] Test llvm.experimental.vector.insert intrinsics on RV32

Summary

RV32 is able to use the llvm.experimental.vector.insert intrinsics too.
This patch ensures they're tested.

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Repository: rG LLVM Github Monorepo

Event Timeline

frasercrmck created this revision.Mar 31 2021, 5:08 AM

Herald added subscribers: vkmr, luismarques, apazos and 21 others. · View Herald TranscriptMar 31 2021, 5:08 AM

frasercrmck requested review of this revision.Mar 31 2021, 5:08 AM

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frasercrmck edited the summary of this revision. (Show Details)Mar 31 2021, 5:11 AM

Harbormaster completed remote builds in B96512: Diff 334414.Mar 31 2021, 5:26 AM

LGTM.

This revision is now accepted and ready to land.Mar 31 2021, 5:46 AM

asb accepted this revision.Mar 31 2021, 6:02 AM

rebase

Harbormaster completed remote builds in B96655: Diff 334611.Apr 1 2021, 1:27 AM

rebase

Harbormaster completed remote builds in B96670: Diff 334635.Apr 1 2021, 3:40 AM

rebase

Harbormaster completed remote builds in B96879: Diff 334926.Apr 2 2021, 2:38 AM

This revision was landed with ongoing or failed builds.Apr 2 2021, 3:56 AM

Closed by commit rG411673e769ac: [RISCV] Test llvm.experimental.vector.insert intrinsics on RV32 (authored by frasercrmck). · Explain Why

This revision was automatically updated to reflect the committed changes.

frasercrmck added a commit: rG411673e769ac: [RISCV] Test llvm.experimental.vector.insert intrinsics on RV32.

Revision Contents

Path

Size

llvm/

test/

CodeGen/

RISCV/

rvv/

fixed-vectors-insert-subvector.ll

2 lines

insert-subvector.ll

1 line

Diff 334414

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
				; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s \| FileCheck %s --check-prefixes=CHECK,LMULMAX2
				; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s \| FileCheck %s --check-prefixes=CHECK,LMULMAX1
	; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s \| FileCheck %s --check-prefixes=CHECK,LMULMAX2			; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s \| FileCheck %s --check-prefixes=CHECK,LMULMAX2
	; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s \| FileCheck %s --check-prefixes=CHECK,LMULMAX1			; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s \| FileCheck %s --check-prefixes=CHECK,LMULMAX1

	define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {			define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
	; CHECK-LABEL: insert_nxv8i32_v2i32_0:			; CHECK-LABEL: insert_nxv8i32_v2i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vsetivli a1, 2, e32,m1,ta,mu			; CHECK-NEXT: vsetivli a1, 2, e32,m1,ta,mu
	; CHECK-NEXT: vle32.v v28, (a0)			; CHECK-NEXT: vle32.v v28, (a0)
	▲ Show 20 Lines • Show All 655 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

	; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
				; RUN: llc -mtriple riscv32 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s \| FileCheck %s
	; RUN: llc -mtriple riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s \| FileCheck %s			; RUN: llc -mtriple riscv64 -mattr=+m,+d,+experimental-zfh,+experimental-v -verify-machineinstrs < %s \| FileCheck %s

	define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {			define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
	; CHECK-LABEL: insert_nxv8i32_nxv4i32_0:			; CHECK-LABEL: insert_nxv8i32_nxv4i32_0:
	; CHECK: # %bb.0:			; CHECK: # %bb.0:
	; CHECK-NEXT: vmv2r.v v8, v12			; CHECK-NEXT: vmv2r.v v8, v12
	; CHECK-NEXT: ret			; CHECK-NEXT: ret
	%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)			%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
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