[AArch64] Avoid SCALAR_TO_VECTOR for single FP constant vector.

[fhahn]

Summary

Currently the code only checks for integer constants (ConstantSDNode)
and triggers an infinite cycle for single-element floating point
vector constants.

I've added a lambda used in a few places to make sure we always check
for both FP and integer constants.

[david-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

9673

It's just a thought, but this looks like a useful static function in it's own right that could live in a header somewhere? There are other parts of codegen that check the same thing, i.e.

DAGCombiner::visitBITCAST
DAGCombiner::getStoreMergeCandidates

llvm/test/CodeGen/AArch64/arm64-build-vector.ll

94

This appears to be unused

[fhahn]

Updated to use isIntOrFPConstant (D99428) and removed unused pointer argument from test. Thanks!

[fhahn]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

9673

That's a great idea, thanks! I put up D99384

[t.p.northover]

Looks like a good change to me.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
   bool usesOnlyOneConstantValue = true;
   bool isConstant = true;
   bool AllLanesExtractElt = true;
   unsigned NumConstantLanes = 0;
   unsigned NumDifferentLanes = 0;
   unsigned NumUndefLanes = 0;
   SDValue Value;
   SDValue ConstantValue;
   for (unsigned i = 0; i < NumElts; ++i) {
     SDValue V = Op.getOperand(i);
     if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
       AllLanesExtractElt = false;
     if (V.isUndef()) {
       ++NumUndefLanes;
       continue;
     }
     if (i > 0)
if (!Value.getNode()) {
     LLVM_DEBUG(
         dbgs() << "LowerBUILD_VECTOR: value undefined, creating undef node\n");
     return DAG.getUNDEF(VT);
   }
 
   // Convert BUILD_VECTOR where all elements but the lowest are undef into
   // SCALAR_TO_VECTOR, except for when we have a single-element constant vector
   // as SimplifyDemandedBits will just turn that back into BUILD_VECTOR.
-  if (isOnlyLowElement && !(NumElts == 1 && isa<ConstantSDNode>(Value))) {
+  if (isOnlyLowElement && !(NumElts == 1 && isIntOrFPConstant(Value))) {
     LLVM_DEBUG(dbgs() << "LowerBUILD_VECTOR: only low element used, creating 1 "
                          "SCALAR_TO_VECTOR node\n");
     return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
   }
 
   if (AllLanesExtractElt) {
     SDNode *Vector = nullptr;
     bool Even = false;

llvm/test/CodeGen/AArch64/arm64-build-vector.ll

 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fmov d1, #1.00000000
 ; CHECK-NEXT:    fadd d0, d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %add = fadd <1 x double> %arg, <double 1.0>
   ret <1 x double> %add
 }
+
+; Make sure BUILD_VECTOR does not get stuck in a loop trying to convert a
+; single element FP vector constant from a scalar to vector.
+define <1 x double> @convert_single_fp_vector_constant(i1 %cmp) {
+; CHECK-LABEL: convert_single_fp_vector_constant:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    tst w0, #0x1
+; CHECK-NEXT:    mov x8, #4607182418800017408
+; CHECK-NEXT:    csetm x9, ne
+; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    fmov d1, x9
+; CHECK-NEXT:    and.8b v0, v0, v1
+; CHECK-NEXT:    ret
+entry:
+  %sel = select i1 %cmp, <1 x double> <double 1.000000e+00>, <1 x double> zeroinitializer
+  ret <1 x double> %sel
+}