[amdgpu] Update med3 combine to skip i64

[JonChesterfield]

Summary

[amdgpu] Update med3 combine to skip i64

Fixes an assumption that a type which is not i32 will be i16. This asserts
when trying to sign/zero extend an i64 to i32.

Test case was cut down from an openmp application. Variations on it are hit by
other combines before reaching the problematic one, e.g. replacing the
immediate values with other function arguments changes the codegen path and
misses this combine.

[JonChesterfield]

Reviewer list derived from git blame + frequency.

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

SDValue SITargetLowering::performIntMed3ImmCombine(
   EVT VT = K0->getValueType(0);
   unsigned Med3Opc = Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3;
   if (VT == MVT::i32 || (VT == MVT::i16 && Subtarget->hasMed3_16())) {
     return DAG.getNode(Med3Opc, SL, VT,
                        Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
   }
 
   // If there isn't a 16-bit med3 operation, convert to 32-bit.
+  if (VT == MVT::i16) {
     MVT NVT = MVT::i32;
     unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
 
     SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
     SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
     SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
 
     SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
     return DAG.getNode(ISD::TRUNCATE, SL, VT, Med3);
   }
 
+  return SDValue();
+}
+
 static ConstantFPSDNode *getSplatConstantFP(SDValue Op) {
   if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op))
     return C;
 
   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op)) {
     if (ConstantFPSDNode *C = BV->getConstantFPSplatNode())
       return C;
   }

llvm/test/CodeGen/AMDGPU/smed3.ll

define amdgpu_kernel void @v_test_smed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 {
 
   %icmp1 = icmp slt i64 %i0, 17
   %i1 = select i1 %icmp1, i64 %i0, i64 17
 
   store i64 %i1, i64 addrspace(1)* %outgep
   ret void
 }
 
+; Regression test for performIntMed3ImmCombine extending arguments to 32 bit
+; which failed for 64 bit arguments. Previously asserted / crashed.
+; GCN-LABEL: {{^}}test_intMed3ImmCombine_no_32bit_extend:
+; GCN: v_cmp_lt_i64
+; GCN: v_cmp_gt_i64
+define i64 @test_intMed3ImmCombine_no_32bit_extend(i64 %x) {
+  %smax = call i64 @llvm.smax.i64(i64 %x, i64 -2)
+  %smin = call i64 @llvm.smin.i64(i64 %smax, i64 2)
+  ret i64 %smin
+}
+declare i64 @llvm.smax.i64(i64, i64)
+declare i64 @llvm.smin.i64(i64, i64)
+
 ; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i16:
 ; SICIVI: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
 ; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17
 define amdgpu_kernel void @v_test_smed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid
   %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid
   %a = load i16, i16 addrspace(1)* %gep0