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Test cases for rem-seteq fold with illegal types
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Authored by nagisa on Mar 10 2021, 5:35 AM.

Details

Summary

This also briefly tests a larger set of architectures than the more
exhaustive functionality tests for AArch64 and x86.

As requested in D88785

Diff Detail

Event Timeline

nagisa created this revision.Mar 10 2021, 5:35 AM
nagisa requested review of this revision.Mar 10 2021, 5:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 10 2021, 5:35 AM

It might be better to split the srem/urem files - its very minor, but it means that all the srem-seteq-* and urem-seteq-* tests group together in file lists

It might be better to split the srem/urem files - its very minor, but it means that all the srem-seteq-* and urem-seteq-* tests group together in file lists

Okay, will split them up later today.

nagisa updated this revision to Diff 329757.Mar 10 2021, 1:12 PM

Split up the test files into srem and urem variants

RKSimon accepted this revision.Mar 11 2021, 1:22 AM

LGTM - cheers

This revision is now accepted and ready to land.Mar 11 2021, 1:22 AM
craig.topper added inline comments.
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
418

Fixed size vectors on RISCV are scalarized unless you pass a value to -riscv-v-vector-bits-min command line option. Enabling the V extension by itself is not sufficient.

nagisa added inline comments.Mar 11 2021, 12:56 PM
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
418

Ah, I see! Unfortunately enabling the option causes the backend to assert today :(

I'll file some bug reports.

craig.topper added inline comments.Mar 11 2021, 1:08 PM
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
418

We don't support fixed vector arguments or returns yet either. There's an open patch for it. Loads/store of vectors should work.

nagisa added inline comments.Mar 11 2021, 1:24 PM
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
418

I ended up filing https://bugs.llvm.org/show_bug.cgi?id=49549

(and https://bugs.llvm.org/show_bug.cgi?id=49550)


Besides that do you have any suggestions on how to best proceed here? I could remove or comment out the test case that involves vectors for now, but it is not clear to me if that's the best way forward.

craig.topper added inline comments.Mar 11 2021, 1:34 PM
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
418

Can you use something like this?

define void @test_urem_vec(<3 x i11>* %X) nounwind {                                                                                                                                                                                                                                                                                                                                                                                                                     
  %a = load <3 x i11>, <3 x i11>* %X                                                                                                                                                                                                                                                                                                                                                                                                                                     
  %urem = urem <3 x i11> %a, <i11 6, i11 7, i11 -5>                                                                                                                                                                                                                                                                                                                                                                                                                      
  %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>                                                                                                                                                                                                                                                                                                                                                                                                                  
  %ext = sext <3 x i1> %cmp to <3 x i11>                                                                                                                                                                                                                                                                                                                                                                                                                                 
  store <3 x i11> %ext, <3 x i11>* %X                                                                                                                                                                                                                                                                                                                                                                                                                                    
  ret void                                                                                                                                                                                                                                                                                                                                                                                                                                                               
}
nagisa updated this revision to Diff 330079.Mar 11 2021, 3:03 PM
nagisa marked 3 inline comments as done.

Adjust the RISCV tests as per the comments.

Thanks, Craig!

nagisa added inline comments.Mar 11 2021, 3:05 PM
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
418

Yes, that works! Thanks!

nagisa updated this revision to Diff 330208.Mar 12 2021, 4:30 AM

Rebase before land

This revision was automatically updated to reflect the committed changes.