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Differential D94356

[RISCV] Define the vfclass RVV intrinsics
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Authored by evandro on Jan 8 2021, 6:55 PM.

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craig.topper
HsiangKai
khchen
rogfer01
Commits
rG7470017f2472: [RISCV] Define the vfclass RVV intrinsics
Summary

Define the vfclass IR intrinsics for the respective V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Evandro Menezes <evandro.menezes@sifive.com>

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evandro created this revision.Jan 8 2021, 6:55 PM
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evandro updated this revision to Diff 315566.Jan 8 2021, 6:57 PM
craig.topper accepted this revision.Jan 8 2021, 9:13 PM

LGTM

This revision is now accepted and ready to land.Jan 8 2021, 9:13 PM
Closed by commit rG7470017f2472: [RISCV] Define the vfclass RVV intrinsics (authored by evandro). · Explain WhyJan 11 2021, 3:40 PM
This revision was automatically updated to reflect the committed changes.
evandro added a commit: rG7470017f2472: [RISCV] Define the vfclass RVV intrinsics.
Herald added a subscriber: jrtc27. · View Herald TranscriptJan 11 2021, 3:40 PM

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
30 lines
lib/
Target/
RISCV/
12 lines
test/
CodeGen/
RISCV/
rvv/
512 lines
698 lines

Diff 315955

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 293 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
class RISCVCompareMask class RISCVCompareMask
: Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyvector_ty, llvm_any_ty, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let ExtendOperand = 3; let ExtendOperand = 3;
} }
// For FP classify operations.
// Output: (bit mask type output)
// Input: (vector_in, vl)
class RISCVClassifyNoMask
: Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
[llvm_anyvector_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic;
// For FP classify operations with mask.
// Output: (bit mask type output)
// Input: (maskedoff, vector_in, mask, vl)
class RISCVClassifyMask
: Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
[LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic;
// For Saturating binary operations. // For Saturating binary operations.
// The destination vector type is the same as first source vector. // The destination vector type is the same as first source vector.
// Input: (vector_in, vector_in/scalar_in, vl) // Input: (vector_in, vector_in/scalar_in, vl)
class RISCVSaturatingBinaryAAXNoMask class RISCVSaturatingBinaryAAXNoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, llvm_anyint_ty], [LLVMMatchType<0>, llvm_any_ty, llvm_anyint_ty],
[IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic { [IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
let ExtendOperand = 2; let ExtendOperand = 2;
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
multiclass RISCVIStore { multiclass RISCVIStore {
def "int_riscv_" # NAME : RISCVIStore; def "int_riscv_" # NAME : RISCVIStore;
def "int_riscv_" # NAME # "_mask" : RISCVIStoreMask; def "int_riscv_" # NAME # "_mask" : RISCVIStoreMask;
} }
multiclass RISCVUnaryAA { multiclass RISCVUnaryAA {
def "int_riscv_" # NAME : RISCVUnaryAANoMask; def "int_riscv_" # NAME : RISCVUnaryAANoMask;
def "int_riscv_" # NAME # "_mask" : RISCVUnaryAAMask; def "int_riscv_" # NAME # "_mask" : RISCVUnaryAAMask;
} }
multiclass RISCVUnaryAB {
def "int_riscv_" # NAME : RISCVUnaryABNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVUnaryABMask;
}
// AAX means the destination type(A) is the same as the first source // AAX means the destination type(A) is the same as the first source
// type(A). X means any type for the second source operand. // type(A). X means any type for the second source operand.
multiclass RISCVBinaryAAX { multiclass RISCVBinaryAAX {
def "int_riscv_" # NAME : RISCVBinaryAAXNoMask; def "int_riscv_" # NAME : RISCVBinaryAAXNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVBinaryAAXMask; def "int_riscv_" # NAME # "_mask" : RISCVBinaryAAXMask;
} }
// ABX means the destination type(A) is different from the first source // ABX means the destination type(A) is different from the first source
// type(B). X means any type for the second source operand. // type(B). X means any type for the second source operand.
Show All 25 Lineslet TargetPrefix = "riscv" in {
multiclass RISCVTernaryAAXA { multiclass RISCVTernaryAAXA {
def "int_riscv_" # NAME : RISCVTernaryAAXANoMask; def "int_riscv_" # NAME : RISCVTernaryAAXANoMask;
def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMask; def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMask;
} }
multiclass RISCVCompare { multiclass RISCVCompare {
def "int_riscv_" # NAME : RISCVCompareNoMask; def "int_riscv_" # NAME : RISCVCompareNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVCompareMask; def "int_riscv_" # NAME # "_mask" : RISCVCompareMask;
} }
multiclass RISCVClassify {
def "int_riscv_" # NAME : RISCVClassifyNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVClassifyMask;
}
multiclass RISCVTernaryWide { multiclass RISCVTernaryWide {
def "int_riscv_" # NAME : RISCVTernaryWideNoMask; def "int_riscv_" # NAME : RISCVTernaryWideNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVTernaryWideMask; def "int_riscv_" # NAME # "_mask" : RISCVTernaryWideMask;
} }
multiclass RISCVReduction { multiclass RISCVReduction {
def "int_riscv_" # NAME : RISCVReductionNoMask; def "int_riscv_" # NAME : RISCVReductionNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVReductionMask; def "int_riscv_" # NAME # "_mask" : RISCVReductionMask;
} }
multiclass RISCVMaskUnarySOut { multiclass RISCVMaskUnarySOut {
def "int_riscv_" # NAME : RISCVMaskUnarySOutNoMask; def "int_riscv_" # NAME : RISCVMaskUnarySOutNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVMaskUnarySOutMask; def "int_riscv_" # NAME # "_mask" : RISCVMaskUnarySOutMask;
} }
multiclass RISCVUnaryAB {
def "int_riscv_" # NAME : RISCVUnaryABNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVUnaryABMask;
}
multiclass RISCVMaskUnaryMOut { multiclass RISCVMaskUnaryMOut {
def "int_riscv_" # NAME : RISCVUnaryNoMask; def "int_riscv_" # NAME : RISCVUnaryNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVMaskUnaryMOutMask; def "int_riscv_" # NAME # "_mask" : RISCVMaskUnaryMOutMask;
} }
multiclass RISCVConversion { multiclass RISCVConversion {
def "int_riscv_" #NAME :RISCVConversionNoMask; def "int_riscv_" #NAME :RISCVConversionNoMask;
def "int_riscv_" # NAME # "_mask" : RISCVConversionMask; def "int_riscv_" # NAME # "_mask" : RISCVConversionMask;
} }
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
defm vfmin : RISCVBinaryAAX; defm vfmin : RISCVBinaryAAX;
defm vfmax : RISCVBinaryAAX; defm vfmax : RISCVBinaryAAX;
defm vfsgnj : RISCVBinaryAAX; defm vfsgnj : RISCVBinaryAAX;
defm vfsgnjn : RISCVBinaryAAX; defm vfsgnjn : RISCVBinaryAAX;
defm vfsgnjx : RISCVBinaryAAX; defm vfsgnjx : RISCVBinaryAAX;
defm vfclass : RISCVClassify;
defm vfmerge : RISCVBinaryWithV0; defm vfmerge : RISCVBinaryWithV0;
defm vslideup : RISCVTernaryAAAX; defm vslideup : RISCVTernaryAAAX;
defm vslidedown : RISCVTernaryAAAX; defm vslidedown : RISCVTernaryAAAX;
defm vslide1up : RISCVBinaryAAX; defm vslide1up : RISCVBinaryAAX;
defm vslide1down : RISCVBinaryAAX; defm vslide1down : RISCVBinaryAAX;
defm vfslide1up : RISCVBinaryAAX; defm vfslide1up : RISCVBinaryAAX;
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 2,701 Lines • ▼ Show 20 Lines
defm PseudoVMFEQ : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; defm PseudoVMFEQ : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
defm PseudoVMFNE : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; defm PseudoVMFNE : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
defm PseudoVMFLT : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; defm PseudoVMFLT : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
defm PseudoVMFLE : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; defm PseudoVMFLE : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
defm PseudoVMFGT : VPseudoBinaryM_VX</*IsFloat=*/1>; defm PseudoVMFGT : VPseudoBinaryM_VX</*IsFloat=*/1>;
defm PseudoVMFGE : VPseudoBinaryM_VX</*IsFloat=*/1>; defm PseudoVMFGE : VPseudoBinaryM_VX</*IsFloat=*/1>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.14. Vector Floating-Point Classify Instruction
//===----------------------------------------------------------------------===//
defm PseudoVFCLASS : VPseudoUnaryV_V;
//===----------------------------------------------------------------------===//
// 14.15. Vector Floating-Point Merge Instruction // 14.15. Vector Floating-Point Merge Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVFMERGE : VPseudoBinaryV_XM</*CarryOut =*/0,/*CarryIn =*/true, defm PseudoVFMERGE : VPseudoBinaryV_XM</*CarryOut =*/0,/*CarryIn =*/true,
/*Constraint =*/"", /*IsFloat=*/true>; /*Constraint =*/"", /*IsFloat=*/true>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.16. Vector Floating-Point Move Instruction // 14.16. Vector Floating-Point Move Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
defm PseudoVFREDMIN : VPseudoReductionV_VS; defm PseudoVFREDMIN : VPseudoReductionV_VS;
defm PseudoVFREDMAX : VPseudoReductionV_VS; defm PseudoVFREDMAX : VPseudoReductionV_VS;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 15.4. Vector Widening Floating-Point Reduction Instructions // 15.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVFWREDSUM : VPseudoReductionV_VS; defm PseudoVFWREDSUM : VPseudoReductionV_VS;
defm PseudoVFWREDOSUM : VPseudoReductionV_VS; defm PseudoVFWREDOSUM : VPseudoReductionV_VS;
} // Predicates = [HasStdExtV, HasStdExtF] } // Predicates = [HasStdExtV, HasStdExtF]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 16. Vector Mask Instructions // 16. Vector Mask Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 16.1 Vector Mask-Register Logical Instructions // 16.1 Vector Mask-Register Logical Instructions
▲ Show 20 Lines • Show All 547 Lines • ▼ Show 20 Lines
defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ", AllFloatVectors>; defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ", AllFloatVectors>;
defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE", AllFloatVectors>; defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE", AllFloatVectors>;
defm "" : VPatBinaryM_VV_VX<"int_riscv_vmflt", "PseudoVMFLT", AllFloatVectors>; defm "" : VPatBinaryM_VV_VX<"int_riscv_vmflt", "PseudoVMFLT", AllFloatVectors>;
defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfne", "PseudoVMFNE", AllFloatVectors>; defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfne", "PseudoVMFNE", AllFloatVectors>;
defm "" : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT", AllFloatVectors>; defm "" : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT", AllFloatVectors>;
defm "" : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>; defm "" : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.14. Vector Floating-Point Classify Instruction
//===----------------------------------------------------------------------===//
defm "" : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">;
//===----------------------------------------------------------------------===//
// 14.15. Vector Floating-Point Merge Instruction // 14.15. Vector Floating-Point Merge Instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// We can use vmerge.vvm to support vector-vector vfmerge. // We can use vmerge.vvm to support vector-vector vfmerge.
defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE", defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE",
/*CarryOut = */0, /*vtilist=*/AllFloatVectors>; /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE", defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE",
/*CarryOut = */0, /*vtilist=*/AllFloatVectors>; /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
defm "" : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", /*IsFloat=*/1>; defm "" : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", /*IsFloat=*/1>;
defm "" : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>; defm "" : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 15.4. Vector Widening Floating-Point Reduction Instructions // 15.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatReductionW_VS<"int_riscv_vfwredsum", "PseudoVFWREDSUM", /*IsFloat=*/1>; defm "" : VPatReductionW_VS<"int_riscv_vfwredsum", "PseudoVFWREDSUM", /*IsFloat=*/1>;
defm "" : VPatReductionW_VS<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>; defm "" : VPatReductionW_VS<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>;
} // Predicates = [HasStdExtV, HasStdExtF] } // Predicates = [HasStdExtV, HasStdExtF]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 16. Vector Mask Instructions // 16. Vector Mask Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x half>,
i32);
define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x half> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x half> %0,
i32 %1)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16(
<vscale x 2 x half>,
i32);
define <vscale x 2 x i16> @intrinsic_vfclass_v_nxv2i16_nxv2f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x half> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16(
<vscale x 2 x half> %0,
i32 %1)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i16> @intrinsic_vfclass_mask_v_nxv2i16_nxv2f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x i16> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16(
<vscale x 4 x half>,
i32);
define <vscale x 4 x i16> @intrinsic_vfclass_v_nxv4i16_nxv4f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x half> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16(
<vscale x 4 x half> %0,
i32 %1)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i16> @intrinsic_vfclass_mask_v_nxv4i16_nxv4f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x i16> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16(
<vscale x 8 x half>,
i32);
define <vscale x 8 x i16> @intrinsic_vfclass_v_nxv8i16_nxv8f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x half> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16(
<vscale x 8 x half> %0,
i32 %1)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i16> @intrinsic_vfclass_mask_v_nxv8i16_nxv8f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfclass.v v16, v18, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x i16> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16(
<vscale x 16 x half>,
i32);
define <vscale x 16 x i16> @intrinsic_vfclass_v_nxv16i16_nxv16f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x half> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16(
<vscale x 16 x half> %0,
i32 %1)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x i16> @intrinsic_vfclass_mask_v_nxv16i16_nxv16f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfclass.v v16, v20, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x i16> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i1> %2,
i32 %3)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16(
<vscale x 32 x half>,
i32);
define <vscale x 32 x i16> @intrinsic_vfclass_v_nxv32i16_nxv32f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 32 x half> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16(
<vscale x 32 x half> %0,
i32 %1)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i32);
define <vscale x 32 x i16> @intrinsic_vfclass_mask_v_nxv32i16_nxv32f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfclass.v v16, v8, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 32 x i16> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i1> %2,
i32 %3)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32(
<vscale x 1 x float>,
i32);
define <vscale x 1 x i32> @intrinsic_vfclass_v_nxv1i32_nxv1f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x float> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32(
<vscale x 1 x float> %0,
i32 %1)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i32);
define <vscale x 1 x i32> @intrinsic_vfclass_mask_v_nxv1i32_nxv1f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x i32> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32(
<vscale x 2 x float>,
i32);
define <vscale x 2 x i32> @intrinsic_vfclass_v_nxv2i32_nxv2f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x float> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32(
<vscale x 2 x float> %0,
i32 %1)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i32);
define <vscale x 2 x i32> @intrinsic_vfclass_mask_v_nxv2i32_nxv2f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x i32> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(
<vscale x 4 x float>,
i32);
define <vscale x 4 x i32> @intrinsic_vfclass_v_nxv4i32_nxv4f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x float> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(
<vscale x 4 x float> %0,
i32 %1)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i32);
define <vscale x 4 x i32> @intrinsic_vfclass_mask_v_nxv4i32_nxv4f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfclass.v v16, v18, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x i32> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32(
<vscale x 8 x float>,
i32);
define <vscale x 8 x i32> @intrinsic_vfclass_v_nxv8i32_nxv8f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x float> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32(
<vscale x 8 x float> %0,
i32 %1)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i32);
define <vscale x 8 x i32> @intrinsic_vfclass_mask_v_nxv8i32_nxv8f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfclass.v v16, v20, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x i32> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32(
<vscale x 16 x float>,
i32);
define <vscale x 16 x i32> @intrinsic_vfclass_v_nxv16i32_nxv16f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x float> %0,
i32 %1) nounwind {
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32(
<vscale x 16 x float> %0,
i32 %1)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i32);
define <vscale x 16 x i32> @intrinsic_vfclass_mask_v_nxv16i32_nxv16f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfclass.v v16, v8, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x i32> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i1> %2,
i32 %3) nounwind {
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i1> %2,
i32 %3)
ret <vscale x 16 x i32> %a
}

llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x half>,
i64);
define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x half> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(
<vscale x 1 x half> %0,
i64 %1)
ret <vscale x 1 x i16> %a
}
declare <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16(
<vscale x 1 x i16> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16(
<vscale x 2 x half>,
i64);
define <vscale x 2 x i16> @intrinsic_vfclass_v_nxv2i16_nxv2f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x half> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16(
<vscale x 2 x half> %0,
i64 %1)
ret <vscale x 2 x i16> %a
}
declare <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i16> @intrinsic_vfclass_mask_v_nxv2i16_nxv2f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x i16> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16(
<vscale x 2 x i16> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16(
<vscale x 4 x half>,
i64);
define <vscale x 4 x i16> @intrinsic_vfclass_v_nxv4i16_nxv4f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x half> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16(
<vscale x 4 x half> %0,
i64 %1)
ret <vscale x 4 x i16> %a
}
declare <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i16> @intrinsic_vfclass_mask_v_nxv4i16_nxv4f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x i16> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16(
<vscale x 4 x i16> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16(
<vscale x 8 x half>,
i64);
define <vscale x 8 x i16> @intrinsic_vfclass_v_nxv8i16_nxv8f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x half> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16(
<vscale x 8 x half> %0,
i64 %1)
ret <vscale x 8 x i16> %a
}
declare <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i16> @intrinsic_vfclass_mask_v_nxv8i16_nxv8f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfclass.v v16, v18, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x i16> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16(
<vscale x 8 x i16> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16(
<vscale x 16 x half>,
i64);
define <vscale x 16 x i16> @intrinsic_vfclass_v_nxv16i16_nxv16f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x half> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16(
<vscale x 16 x half> %0,
i64 %1)
ret <vscale x 16 x i16> %a
}
declare <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i16> @intrinsic_vfclass_mask_v_nxv16i16_nxv16f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfclass.v v16, v20, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x i16> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16(
<vscale x 16 x i16> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16(
<vscale x 32 x half>,
i64);
define <vscale x 32 x i16> @intrinsic_vfclass_v_nxv32i16_nxv32f16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 32 x half> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16(
<vscale x 32 x half> %0,
i64 %1)
ret <vscale x 32 x i16> %a
}
declare <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i16> @intrinsic_vfclass_mask_v_nxv32i16_nxv32f16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfclass.v v16, v8, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 32 x i16> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16(
<vscale x 32 x i16> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i16> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32(
<vscale x 1 x float>,
i64);
define <vscale x 1 x i32> @intrinsic_vfclass_v_nxv1i32_nxv1f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x float> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfclass.nxv1i32(
<vscale x 1 x float> %0,
i64 %1)
ret <vscale x 1 x i32> %a
}
declare <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i32> @intrinsic_vfclass_mask_v_nxv1i32_nxv1f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x i32> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfclass.mask.nxv1i32(
<vscale x 1 x i32> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32(
<vscale x 2 x float>,
i64);
define <vscale x 2 x i32> @intrinsic_vfclass_v_nxv2i32_nxv2f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x float> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfclass.nxv2i32(
<vscale x 2 x float> %0,
i64 %1)
ret <vscale x 2 x i32> %a
}
declare <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i32> @intrinsic_vfclass_mask_v_nxv2i32_nxv2f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x i32> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfclass.mask.nxv2i32(
<vscale x 2 x i32> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(
<vscale x 4 x float>,
i64);
define <vscale x 4 x i32> @intrinsic_vfclass_v_nxv4i32_nxv4f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x float> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfclass.nxv4i32(
<vscale x 4 x float> %0,
i64 %1)
ret <vscale x 4 x i32> %a
}
declare <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i32> @intrinsic_vfclass_mask_v_nxv4i32_nxv4f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfclass.v v16, v18, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x i32> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfclass.mask.nxv4i32(
<vscale x 4 x i32> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32(
<vscale x 8 x float>,
i64);
define <vscale x 8 x i32> @intrinsic_vfclass_v_nxv8i32_nxv8f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x float> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfclass.nxv8i32(
<vscale x 8 x float> %0,
i64 %1)
ret <vscale x 8 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i32> @intrinsic_vfclass_mask_v_nxv8i32_nxv8f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfclass.v v16, v20, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x i32> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfclass.mask.nxv8i32(
<vscale x 8 x i32> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32(
<vscale x 16 x float>,
i64);
define <vscale x 16 x i32> @intrinsic_vfclass_v_nxv16i32_nxv16f32(
; CHECK-LABEL: intrinsic_vfclass_v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x float> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfclass.nxv16i32(
<vscale x 16 x float> %0,
i64 %1)
ret <vscale x 16 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i32> @intrinsic_vfclass_mask_v_nxv16i32_nxv16f32(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfclass.v v16, v8, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 16 x i32> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfclass.mask.nxv16i32(
<vscale x 16 x i32> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i32> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1i64(
<vscale x 1 x double>,
i64);
define <vscale x 1 x i64> @intrinsic_vfclass_v_nxv1i64_nxv1f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x double> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfclass.nxv1i64(
<vscale x 1 x double> %0,
i64 %1)
ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i64> @intrinsic_vfclass_mask_v_nxv1i64_nxv1f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfclass.v v16, v17, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 1 x i64> %0,
<vscale x 1 x double> %1,
<vscale x 1 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfclass.mask.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x double> %1,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2i64(
<vscale x 2 x double>,
i64);
define <vscale x 2 x i64> @intrinsic_vfclass_v_nxv2i64_nxv2f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x double> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfclass.nxv2i64(
<vscale x 2 x double> %0,
i64 %1)
ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i64> @intrinsic_vfclass_mask_v_nxv2i64_nxv2f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfclass.v v16, v18, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 2 x i64> %0,
<vscale x 2 x double> %1,
<vscale x 2 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfclass.mask.nxv2i64(
<vscale x 2 x i64> %0,
<vscale x 2 x double> %1,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4i64(
<vscale x 4 x double>,
i64);
define <vscale x 4 x i64> @intrinsic_vfclass_v_nxv4i64_nxv4f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x double> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfclass.nxv4i64(
<vscale x 4 x double> %0,
i64 %1)
ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i64> @intrinsic_vfclass_mask_v_nxv4i64_nxv4f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfclass.v v16, v20, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 4 x i64> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfclass.mask.nxv4i64(
<vscale x 4 x i64> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8i64(
<vscale x 8 x double>,
i64);
define <vscale x 8 x i64> @intrinsic_vfclass_v_nxv8i64_nxv8f64(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfclass.v v16, v16
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x double> %0,
i64 %1) nounwind {
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfclass.nxv8i64(
<vscale x 8 x double> %0,
i64 %1)
ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i64> @intrinsic_vfclass_mask_v_nxv8i64_nxv8f64(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfclass.v v16, v8, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
<vscale x 8 x i64> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i1> %2,
i64 %3) nounwind {
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfclass.mask.nxv8i64(
<vscale x 8 x i64> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i64> %a
}