[RISCV] Upgrade RISC-V V extension MC to v1.0-08a0b46.

[HsiangKai]

Summary

• Update the VTYPE encoding. Make LMUL encoding in a continuous field.
• Add new instructions in V1.0.
• Update instruction constraints.
• Update test cases accordingly.

[craig.topper]

Can this be split up? Seems like some of this could be done in independent changes. Like changing LMUL layout. Changing loads. Changing madc.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2310

Why is this being dropped? This was a bug fix I just earlier this week. I don't think vmerge can ever V0 as a destination and the parser previously crashed on it.

[HsiangKai]

In D93578#2464538, @craig.topper wrote:

Can this be split up? Seems like some of this could be done in independent changes. Like changing LMUL layout. Changing loads. Changing madc.

I will do it.

[HsiangKai]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2310

I could not find the description that the destination of vmerge could not be V0 as I scanned the V specification. So, I remove it. Maybe I misread the specification. We should confirm it first.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2310

It should be covered by this "The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., comparisons) or the scalar result of a reduction. Otherwise, an illegal instruction exception is raised.
This constraint supports restart with a non-zero vstart value"

[HsiangKai]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2310

Got it. Thanks. I will revert it.

[HsiangKai]

Split this commit into D93611, D93612, D93613, D93614.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool RISCVAsmParser::validateInstruction(MCInst &Inst,
   }
   if ((TargetFlags & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) {
     CheckReg = Inst.getOperand(2).getReg();
     if (DestReg == CheckReg)
       return Error(Loc, "The destination vector register group cannot overlap"
                         " the source vector register group.");
   }
   if ((TargetFlags & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) {
-    // vadc, vsbc are special cases. These instructions have no mask register.
-    // The destination register could not be V0.
+    // vadc and vsbc are special cases. These instructions have no mask
+    // register. The destination register could not be V0.
     unsigned Opcode = Inst.getOpcode();
     if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM ||
         Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM ||
-        Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM ||
-        Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM ||
-        Opcode == RISCV::VMERGE_VXM)
+        Opcode == RISCV::VSBC_VXM)
       return Error(Loc, "The destination vector register group cannot be V0.");
-
     // Regardless masked or unmasked version, the number of operands is the
     // same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
     // actually. We need to check the last operand to ensure whether it is
     // masked or not.
     if ((TargetFlags & RISCVII::OneInput) && (Inst.getNumOperands() == 3))
       CheckReg = Inst.getOperand(2).getReg();
     else if (Inst.getNumOperands() == 4)
       CheckReg = Inst.getOperand(3).getReg();

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 def WidenCvt     : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value,
                                         OneInput.Value)>;
 def Narrow       : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value)>;
 def NarrowCvt    : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value,
                                         OneInput.Value)>;
-def Vmadc        : RISCVVConstraint<!or(VS2Constraint.Value,
-                                        VS1Constraint.Value)>;
 def Iota         : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value,
                                         OneInput.Value)>;
 def SlideUp      : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value)>;
 def Vrgather     : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VS1Constraint.Value,
                                         VMConstraint.Value)>;

llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

 def OPIVI : RISCVVFormat<0b011>;
 def OPIVX : RISCVVFormat<0b100>;
 def OPFVF : RISCVVFormat<0b101>;
 def OPMVX : RISCVVFormat<0b110>;
 
 class RISCVMOP<bits<2> val> {
   bits<2> Value = val;
 }
-def MOPLDUnitStride : RISCVMOP<0b00>;
-def MOPLDStrided    : RISCVMOP<0b10>;
-def MOPLDIndexed    : RISCVMOP<0b11>;
+def MOPLDUnitStride   : RISCVMOP<0b00>;
+def MOPLDIndexedUnord : RISCVMOP<0b01>;
+def MOPLDStrided      : RISCVMOP<0b10>;
+def MOPLDIndexedOrder : RISCVMOP<0b11>;
 
 def MOPSTUnitStride   : RISCVMOP<0b00>;
 def MOPSTIndexedUnord : RISCVMOP<0b01>;
 def MOPSTStrided      : RISCVMOP<0b10>;
 def MOPSTIndexedOrder : RISCVMOP<0b11>;
 
 class RISCVLSUMOP<bits<5> val> {
   bits<5> Value = val;
class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
   let Inst{14-12} = width;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];
   let RVVConstraint = VMConstraint;
 }
 
-class RVInstVLX<bits<3> nf, bit mew, bits<3> width,
+class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-29} = nf;
   let Inst{28} = mew;
-  let Inst{27-26} = MOPLDIndexed.Value;
+  let Inst{27-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 // load vd, (rs1), rs2, vm
 class VStridedLoad<RISCVWidth width, string opcodestr>
     : RVInstVLS<0b000, width.Value{3}, width.Value{2-0},
                 (outs VR:$vd),
                 (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $rs2$vm">;
 
 // load vd, (rs1), vs2, vm
-class VIndexedLoad<RISCVWidth width, string opcodestr>
-    : RVInstVLX<0b000, width.Value{3}, width.Value{2-0},
+class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0},
                 (outs VR:$vd),
                 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $vs2$vm">;
 
 // vl<nf>r.v vd, (rs1)
-class VWholeLoad<bits<3> nf, string opcodestr>
-    : RVInstVLU<nf, 0b0, LUMOPUnitStrideWholeReg,
-                0b000, (outs VR:$vd), (ins GPR:$rs1),
+class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
+                width.Value{2-0}, (outs VR:$vd), (ins GPR:$rs1),
                 opcodestr, "$vd, (${rs1})"> {
   let vm = 1;
   let Uses = [];
 }
 
 // segment load vd, (rs1), vm
 class VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop,
                              RISCVWidth width, string opcodestr>
     : RVInstVLU<nf, width.Value{3}, lumop, width.Value{2-0},
                 (outs VR:$vd),
                 (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
 
 // segment load vd, (rs1), rs2, vm
 class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
     : RVInstVLS<nf, width.Value{3}, width.Value{2-0},
                 (outs VR:$vd),
                 (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $rs2$vm">;
 
 // segment load vd, (rs1), vs2, vm
-class VIndexedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
-    : RVInstVLX<nf, width.Value{3}, width.Value{2-0},
+class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                          string opcodestr>
+    : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0},
                 (outs VR:$vd),
                 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 1, mayStore = 0
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 // store vd, vs3, (rs1), vm
 class VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width,

 // store vd, vs3, (rs1), vs2, vm
 class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
     : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
                 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
                 opcodestr, "$vs3, (${rs1}), $vs2$vm">;
 
 // vs<nf>r.v vd, (rs1)
 class VWholeStore<bits<3> nf, string opcodestr>
-    : RVInstVSU<nf, 0b0, SUMOPUnitStrideWholeReg,
+    : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg,
                 0b000, (outs), (ins VR:$vs3, GPR:$rs1),
                 opcodestr, "$vs3, (${rs1})"> {
   let vm = 1;
   let Uses = [];
 }
 
 // segment store vd, vs3, (rs1), vm
 class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
     : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
                 (outs), (ins VR:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
                 "$vs3, (${rs1})$vm">;
 
 // segment store vd, vs3, (rs1), rs2, vm
 class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
     : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
                 (ins VR:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
                 opcodestr, "$vs3, (${rs1}), $rs2$vm">;
 
 // segment store vd, vs3, (rs1), vs2, vm
-class VIndexedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
-    : RVInstVSX<nf, width.Value{3}, MOPSTIndexedOrder, width.Value{2-0}, (outs),
+class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+                           string opcodestr>
+    : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
                 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
                 opcodestr, "$vs3, (${rs1}), $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 1
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // op vd, vs2, vs1, vm
 class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : RVInstVV<funct6, opv, (outs VR:$vd),
multiclass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>;
 }
 
 multiclass VAMO<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> {
   def _WD : VAMOWd<amoop, width, opcodestr>;
   def _UNWD : VAMONoWd<amoop, width, opcodestr>;
 }
 
+multiclass VWholeLoad<bits<3> nf, string opcodestr> {
+  def E8_V : VWholeLoad<nf, LSWidth8, opcodestr # "e8.v">;
+  def E16_V : VWholeLoad<nf, LSWidth16, opcodestr # "e16.v">;
+  def E32_V : VWholeLoad<nf, LSWidth32, opcodestr # "e32.v">;
+  def E64_V : VWholeLoad<nf, LSWidth64, opcodestr # "e64.v">;
+  def E128_V : VWholeLoad<nf, LSWidth128, opcodestr # "e128.v">;
+  def E256_V : VWholeLoad<nf, LSWidth256, opcodestr # "e256.v">;
+  def E512_V : VWholeLoad<nf, LSWidth512, opcodestr # "e512.v">;
+  def E1024_V : VWholeLoad<nf, LSWidth1024, opcodestr # "e1024.v">;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
 def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei),
                            "vsetvli", "$rd, $rs1, $vtypei">;

 def VSSE32_V : VStridedStore<LSWidth32, "vsse32.v">;
 def VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">;
 def VSSE128_V : VStridedStore<LSWidth128, "vsse128.v">;
 def VSSE256_V : VStridedStore<LSWidth256, "vsse256.v">;
 def VSSE512_V : VStridedStore<LSWidth512, "vsse512.v">;
 def VSSE1024_V : VStridedStore<LSWidth1024, "vsse1024.v">;
 
 // Vector Indexed Instructions
-def VLXEI8_V : VIndexedLoad<LSWidth8, "vlxei8.v">;
-def VLXEI16_V : VIndexedLoad<LSWidth16, "vlxei16.v">;
-def VLXEI32_V : VIndexedLoad<LSWidth32, "vlxei32.v">;
-def VLXEI64_V : VIndexedLoad<LSWidth64, "vlxei64.v">;
-def VLXEI128_V : VIndexedLoad<LSWidth128, "vlxei128.v">;
-def VLXEI256_V : VIndexedLoad<LSWidth256, "vlxei256.v">;
-def VLXEI512_V : VIndexedLoad<LSWidth512, "vlxei512.v">;
-def VLXEI1024_V : VIndexedLoad<LSWidth1024, "vlxei1024.v">;
-
-def VSXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsxei8.v">;
-def VSXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsxei16.v">;
-def VSXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsxei32.v">;
-def VSXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsxei64.v">;
-def VSXEI128_V : VIndexedStore<MOPSTIndexedOrder, LSWidth128, "vsxei128.v">;
-def VSXEI256_V : VIndexedStore<MOPSTIndexedOrder, LSWidth256, "vsxei256.v">;
-def VSXEI512_V : VIndexedStore<MOPSTIndexedOrder, LSWidth512, "vsxei512.v">;
-def VSXEI1024_V : VIndexedStore<MOPSTIndexedOrder, LSWidth1024, "vsxei1024.v">;
+def VLUXEI8_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth8, "vluxei8.v">;
+def VLUXEI16_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth16, "vluxei16.v">;
+def VLUXEI32_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth32, "vluxei32.v">;
+def VLUXEI64_V : VIndexedLoad<MOPLDIndexedUnord, LSWidth64, "vluxei64.v">;
+
+def VLOXEI8_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth8, "vloxei8.v">;
+def VLOXEI16_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth16, "vloxei16.v">;
+def VLOXEI32_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth32, "vloxei32.v">;
+def VLOXEI64_V : VIndexedLoad<MOPLDIndexedOrder, LSWidth64, "vloxei64.v">;
 
 def VSUXEI8_V : VIndexedStore<MOPSTIndexedUnord, LSWidth8, "vsuxei8.v">;
 def VSUXEI16_V : VIndexedStore<MOPSTIndexedUnord, LSWidth16, "vsuxei16.v">;
 def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">;
 def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">;
-def VSUXEI128_V : VIndexedStore<MOPSTIndexedUnord, LSWidth128, "vsuxei128.v">;
-def VSUXEI256_V : VIndexedStore<MOPSTIndexedUnord, LSWidth256, "vsuxei256.v">;
-def VSUXEI512_V : VIndexedStore<MOPSTIndexedUnord, LSWidth512, "vsuxei512.v">;
-def VSUXEI1024_V : VIndexedStore<MOPSTIndexedUnord, LSWidth1024, "vsuxei1024.v">;
 
-def VL1R_V : VWholeLoad<0, "vl1r.v">;
-def VS1R_V : VWholeStore<0, "vs1r.v">;
+def VSOXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsoxei8.v">;
+def VSOXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsoxei16.v">;
+def VSOXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsoxei32.v">;
+def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">;
+
+defm VL1R : VWholeLoad<1, "vl1r">;
+defm VL2R : VWholeLoad<2, "vl2r">;
+defm VL4R : VWholeLoad<4, "vl4r">;
+defm VL8R : VWholeLoad<8, "vl8r">;
+def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
+def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VR:$vd, GPR:$rs1)>;
+def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VR:$vd, GPR:$rs1)>;
+def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VR:$vd, GPR:$rs1)>;
+
+def VS1R_V : VWholeStore<1, "vs1r.v">;
+def VS2R_V : VWholeStore<2, "vs2r.v">;
+def VS4R_V : VWholeStore<4, "vs4r.v">;
+def VS8R_V : VWholeStore<8, "vs8r.v">;
 
 // Vector Single-Width Integer Add and Subtract
 defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
 defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
 defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
 
+def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
+
 // Vector Widening Integer Add/Subtract
 // Refer to 11.2 Widening Vector Arithmetic Instructions
 // The destination vector register group cannot overlap a source vector
 // register group of a different element width (including the mask register
 // if masked), otherwise an illegal instruction exception is raised.
 let Constraints = "@earlyclobber $vd" in {
 let RVVConstraint = WidenV in {
 defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>;

 defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>;
 defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>;
 defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>;
 defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>;
 defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>;
 
 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
 defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
+let RVVConstraint = NoConstraint in {
 defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
 defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
+} // RVVConstraint = NoConstraint
 defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
+let RVVConstraint = NoConstraint in {
 defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
 defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
+} // RVVConstraint = NoConstraint
 
 // Vector Bitwise Logical Instructions
 defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
 defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
 defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
 
 def : InstAlias<"vnot.v $vd, $vs$vm",
                 (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>;
 
 // Vector Single-Width Bit Shift Instructions
 defm VSLL_V : VALU_IV_V_X_I<"vsll", 0b100101, uimm5>;
 defm VSRL_V : VALU_IV_V_X_I<"vsrl", 0b101000, uimm5>;
 defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>;
 
 // Vector Narrowing Integer Right Shift Instructions
 // Refer to 11.3. Narrowing Vector Arithmetic Instructions
 // The destination vector register group cannot overlap the first source
 // vector register group (specified by vs2). The destination vector register
 // group cannot overlap the mask register if used, unless LMUL=1.
 let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
 defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">;
 defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
 
+def : InstAlias<"vncvt.x.x.w $vd, $vs$vm",
+                (VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
+
 // Vector Integer Comparison Instructions
 let RVVConstraint = NoConstraint in {
 defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>;
 defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>;
 defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>;
 defm VMSLT_V : VALU_IV_V_X<"vmslt", 0b011011>;
 defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>;
 defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>;

 defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>;
 defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>;
 defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>;
 defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
 
 // Vector Floating-Point Square-Root Instruction
 defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>;
+defm VFRSQRTE7_V : VALU_FV_VS2<"vfrsqrte7.v", 0b010011, 0b00100>;
+defm VFRECE7_V : VALU_FV_VS2<"vfrece7.v", 0b010011, 0b00101>;
 
 // Vector Floating-Point MIN/MAX Instructions
 defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
 defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>;
 
 // Vector Floating-Point Sign-Injection Instructions
 defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>;
 defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>;
 defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
 
+def : InstAlias<"vfneg.v $vd, $vs$vm",
+                (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
+
 // Vector Floating-Point Compare Instructions
 let RVVConstraint = NoConstraint in {
 defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>;
 defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>;
 defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>;
 defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>;
 defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>;
 defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>;
def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
                         "vpopc.m", "$vd, $vs2$vm">;
 
 // vfirst find-first-set mask bit
 def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
                         (ins VR:$vs2, VMaskOp:$vm),
                         "vfirst.m", "$vd, $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
+let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
 // vmsbf.m set-before-first mask bit
 defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>;
-
 // vmsif.m set-including-first mask bit
 defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>;
-
 // vmsof.m set-only-first mask bit
 defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>;
-
 // Vector Iota Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
 defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
 
 // Vector Element Index Instruction
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
                       (ins VMaskOp:$vm), "vid.v", "$vd$vm"> {
   let vs2 = 0;

 
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
 } // Predicates = [HasStdExtV, HasStdExtF]
 
 let Predicates = [HasStdExtV] in {
 // Vector Slide Instructions
 let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
-defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
-
-let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
 defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtV, HasStdExtF] in {
 let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VFSLIDE1UP_V : VALU_FV_F<"vfslide1up", 0b001110>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
 defm VFSLIDE1DOWN_V : VALU_FV_F<"vfslide1down", 0b001111>;
 } // Predicates = [HasStdExtV, HasStdExtF]
 
 let Predicates = [HasStdExtV] in {
 // Vector Register Gather Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
 defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>;
+def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
 
 // Vector Compress Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
foreach nf=2-8 in {
     def VSSSEG#nf#E32_V : VStridedSegmentStore<!add(nf, -1), LSWidth32, "vssseg"#nf#"e32.v">;
     def VSSSEG#nf#E64_V : VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">;
     def VSSSEG#nf#E128_V : VStridedSegmentStore<!add(nf, -1), LSWidth128, "vssseg"#nf#"e128.v">;
     def VSSSEG#nf#E256_V : VStridedSegmentStore<!add(nf, -1), LSWidth256, "vssseg"#nf#"e256.v">;
     def VSSSEG#nf#E512_V : VStridedSegmentStore<!add(nf, -1), LSWidth512, "vssseg"#nf#"e512.v">;
     def VSSSEG#nf#E1024_V : VStridedSegmentStore<!add(nf, -1), LSWidth1024, "vssseg"#nf#"e1024.v">;
 
     // Vector Indexed Instructions
-    def VLXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth8, "vlxseg"#nf#"ei8.v">;
-    def VLXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth16, "vlxseg"#nf#"ei16.v">;
-    def VLXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth32, "vlxseg"#nf#"ei32.v">;
-    def VLXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth64, "vlxseg"#nf#"ei64.v">;
-    def VLXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth128, "vlxseg"#nf#"ei128.v">;
-    def VLXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth256, "vlxseg"#nf#"ei256.v">;
-    def VLXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth512, "vlxseg"#nf#"ei512.v">;
-    def VLXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth1024, "vlxseg"#nf#"ei1024.v">;
-
-    def VSXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), LSWidth8, "vsxseg"#nf#"ei8.v">;
-    def VSXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), LSWidth16, "vsxseg"#nf#"ei16.v">;
-    def VSXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), LSWidth32, "vsxseg"#nf#"ei32.v">;
-    def VSXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), LSWidth64, "vsxseg"#nf#"ei64.v">;
-    def VSXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), LSWidth128, "vsxseg"#nf#"ei128.v">;
-    def VSXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), LSWidth256, "vsxseg"#nf#"ei256.v">;
-    def VSXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), LSWidth512, "vsxseg"#nf#"ei512.v">;
-    def VSXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), LSWidth1024, "vsxseg"#nf#"ei1024.v">;
+    def VLUXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                             LSWidth8, "vluxseg"#nf#"ei8.v">;
+    def VLUXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                              LSWidth16, "vluxseg"#nf#"ei16.v">;
+    def VLUXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                              LSWidth32, "vluxseg"#nf#"ei32.v">;
+    def VLUXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                              LSWidth64, "vluxseg"#nf#"ei64.v">;
+    def VLUXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth128, "vluxseg"#nf#"ei128.v">;
+    def VLUXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth256, "vluxseg"#nf#"ei256.v">;
+    def VLUXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth512, "vluxseg"#nf#"ei512.v">;
+    def VLUXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord,
+                               LSWidth1024, "vluxseg"#nf#"ei1024.v">;
+
+    def VLOXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                             LSWidth8, "vloxseg"#nf#"ei8.v">;
+    def VLOXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                              LSWidth16, "vloxseg"#nf#"ei16.v">;
+    def VLOXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                              LSWidth32, "vloxseg"#nf#"ei32.v">;
+    def VLOXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                              LSWidth64, "vloxseg"#nf#"ei64.v">;
+    def VLOXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth128, "vloxseg"#nf#"ei128.v">;
+    def VLOXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth256, "vloxseg"#nf#"ei256.v">;
+    def VLOXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth512, "vloxseg"#nf#"ei512.v">;
+    def VLOXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder,
+                               LSWidth1024, "vloxseg"#nf#"ei1024.v">;
+
+    def VSUXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                             LSWidth8, "vsuxseg"#nf#"ei8.v">;
+    def VSUXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                              LSWidth16, "vsuxseg"#nf#"ei16.v">;
+    def VSUXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                              LSWidth32, "vsuxseg"#nf#"ei32.v">;
+    def VSUXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                              LSWidth64, "vsuxseg"#nf#"ei64.v">;
+    def VSUXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                               LSWidth128, "vsuxseg"#nf#"ei128.v">;
+    def VSUXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                               LSWidth256, "vsuxseg"#nf#"ei256.v">;
+    def VSUXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                               LSWidth512, "vsuxseg"#nf#"ei512.v">;
+    def VSUXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord,
+                                LSWidth1024, "vsuxseg"#nf#"ei1024.v">;
+
+    def VSOXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                             LSWidth8, "vsoxseg"#nf#"ei8.v">;
+    def VSOXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                              LSWidth16, "vsoxseg"#nf#"ei16.v">;
+    def VSOXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                              LSWidth32, "vsoxseg"#nf#"ei32.v">;
+    def VSOXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                              LSWidth64, "vsoxseg"#nf#"ei64.v">;
+    def VSOXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                               LSWidth128, "vsoxseg"#nf#"ei128.v">;
+    def VSOXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                               LSWidth256, "vsoxseg"#nf#"ei256.v">;
+    def VSOXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                               LSWidth512, "vsoxseg"#nf#"ei512.v">;
+    def VSOXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder,
+                                LSWidth1024, "vsoxseg"#nf#"ei1024.v">;
   }
 } // Predicates = [HasStdExtZvlsseg]
 
 let Predicates = [HasStdExtZvamo, HasStdExtA] in {
   defm VAMOSWAPEI8 : VAMO<AMOOPVamoSwap, LSWidth8, "vamoswapei8.v">;
   defm VAMOSWAPEI16 : VAMO<AMOOPVamoSwap, LSWidth16, "vamoswapei16.v">;
   defm VAMOSWAPEI32 : VAMO<AMOOPVamoSwap, LSWidth32, "vamoswapei32.v">;
 

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

enum RVVConstraintType {
 
   // Illegal instructions:
   //
   // * The destination vector register group for a masked vector instruction
   // cannot overlap the source mask register (v0), unless the destination vector
   // register is being written with a mask value (e.g., comparisons) or the
   // scalar result of a reduction.
   //
-  // * Widening: The destination vector register group cannot overlap a source
-  // vector register group of a different EEW
+  // * Widening: The destination EEW is greater than the source EEW, the source
+  // EMUL is at least 1. The destination vector register group cannot overlap
+  // with the source vector register groups besides the highest-numbered part of
+  // the destination register group.
+  //
+  // * Narrowing: The destination EEW is smaller than the source EEW. The
+  // destination vector register group cannot overlap with the source vector
+  // register groups besides the lowest-numbered part of the source register
+  // group.
   //
-  // * Narrowing: The destination vector register group cannot overlap the
-  // first source vector register group
+  // * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the
+  // source register and, if masked, cannot overlap the mask register ('v0').
   //
-  // * For vadc and vsbc, an illegal instruction exception is raised if the
-  // destination vector register is v0.
-  //
-  // * For vmadc and vmsbc, an illegal instruction exception is raised if the
-  // destination vector register overlaps a source vector register group.
-  //
-  // * viota: An illegal instruction exception is raised if the destination
-  // vector register group overlaps the source vector mask register. If the
-  // instruction is masked, an illegal instruction exception is issued if the
-  // destination vector register group overlaps v0.
+  // * viota: The destination register cannot overlap the source register and,
+  // if masked, cannot overlap the mask register ('v0').
   //
   // * v[f]slide[1]up: The destination vector register group for vslideup cannot
   // overlap the source vector register group.
   //
   // * vrgather: The destination vector register group cannot overlap with the
   // source vector register groups.
   //
   // * vcompress: The destination vector register group cannot overlap the
   // source vector register group or the source mask register
   WidenV = VS2Constraint | VS1Constraint | VMConstraint,
   WidenW = VS1Constraint | VMConstraint,
   WidenCvt = VS2Constraint | VMConstraint | OneInput,
-  Narrow = VS2Constraint | VMConstraint,
-  NarrowCvt = VS2Constraint | VMConstraint | OneInput,
-  Vmadc = VS2Constraint | VS1Constraint,
+  Narrow = VMConstraint,
+  NarrowCvt = VMConstraint | OneInput,
   Iota = VS2Constraint | VMConstraint | OneInput,
-  SlideUp = VS2Constraint | VMConstraint,
-  Vrgather = VS2Constraint | VS1Constraint | VMConstraint,
+  SlideUp = VS2Constraint,
+  Vrgather = VS2Constraint | VS1Constraint,
   Vcompress = VS2Constraint | VS1Constraint,
 };
 
 // RISC-V Specific Machine Operand Flags
 enum {
   MO_None = 0,
   MO_CALL = 1,
   MO_PLT = 2,

 
 // Encode VTYPE into the binary format used by the the VSETVLI instruction which
 // is used by our MC layer representation.
 //
 // Bits | Name       | Description
 // -----+------------+------------------------------------------------
 // 7    | vma        | Vector mask agnostic
 // 6    | vta        | Vector tail agnostic
-// 5    | vlmul[2]   | Fractional lmul?
-// 4:2  | vsew[2:0]  | Standard element width (SEW) setting
-// 1:0  | vlmul[1:0] | Vector register group multiplier (LMUL) setting
-//
-// TODO: This format will change for the V extensions spec v1.0.
+// 5:3  | vsew[2:0]  | Standard element width (SEW) setting
+// 2:0  | vlmul[2:0] | Vector register group multiplier (LMUL) setting
 inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW,
                                    bool TailAgnostic, bool MaskAgnostic) {
   unsigned VLMULBits = static_cast<unsigned>(VLMUL);
   unsigned VSEWBits = static_cast<unsigned>(VSEW);
-  unsigned VTypeI =
-      ((VLMULBits & 0x4) << 3) | (VSEWBits << 2) | (VLMULBits & 0x3);
+  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
   if (TailAgnostic)
     VTypeI |= 0x40;
   if (MaskAgnostic)
     VTypeI |= 0x80;
 
   return VTypeI;
 }
 
-// TODO: This format will change for the V extensions spec v1.0.
 inline static RISCVVLMUL getVLMUL(unsigned VType) {
-  unsigned VLMUL = (VType & 0x3) | ((VType & 0x20) >> 3);
+  unsigned VLMUL = VType & 0x7;
   return static_cast<RISCVVLMUL>(VLMUL);
 }
 
 inline static RISCVVSEW getVSEW(unsigned VType) {
-  unsigned VSEW = (VType >> 2) & 0x7;
+  unsigned VSEW = (VType >> 3) & 0x7;
   return static_cast<RISCVVSEW>(VSEW);
 }
 
 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
 
 inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
 
 void printVType(unsigned VType, raw_ostream &OS);

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir

bb.0 (%ir-block.0):
     PseudoRET
 
 ...
 
 # POST-INSERTER: %0:gpr = COPY $x13
 # POST-INSERTER: %1:gpr = COPY $x12
 # POST-INSERTER: %2:gpr = COPY $x11
 # POST-INSERTER: %3:gpr = COPY $x10
-# POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
+# POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
 # POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
-# POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
+# POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
 # POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
+# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
 # POST-INSERTER: %6:vr = PseudoVADD_VV_M1 killed %4, killed %5, $noreg, -1, implicit $vl, implicit $vtype
-# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype
+# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype
 # POST-INSERTER: PseudoVSE64_V_M1 killed %6, %3, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
 
 # CODEGEN: vsetvli  a3, a3, e64,m1,ta,mu
 # CODEGEN-NEXT: vle64.v v25, (a1)
 # CODEGEN-NEXT: vle64.v v26, (a2)
 # CODEGEN-NEXT: vadd.vv v25, v25, v26
 # CODEGEN-NEXT: vse64.v v25, (a0)
 # CODEGEN-NEXT: ret

llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

define void @vadd_vint64m1(
   ret void
 }
 
 ; PRE-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
 ; PRE-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
 ; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 64, implicit $vl, implicit $vtype
 ; PRE-INSERTER:  PseudoVSE64_V_M1 killed %5, %0, $x0, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)
 
-; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
+; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
 ; POST-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
-; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
+; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
 ; POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
-; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
+; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
 ; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, -1, implicit $vl, implicit $vtype
-; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype
+; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
 ; POST-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)

llvm/test/MC/RISCV/rvv/aliases.s

+# RUN: llvm-mc --triple=riscv64 -mattr +experimental-v < %s --show-encoding 2>&1 \
+# RUN:   -mattr +d | FileCheck --check-prefix=ALIAS %s
+# RUN: llvm-mc --triple=riscv64 -mattr=+experimental-v --riscv-no-aliases < %s \
+# RUN:   -mattr +d --show-encoding 2>&1 | FileCheck --check-prefix=NO-ALIAS %s
+
+# ALIAS:    vwcvt.x.x.v     v2, v1, v0.t    # encoding: [0x57,0x61,0x10,0xc4]
+# NO-ALIAS: vwadd.vx        v2, v1, zero, v0.t # encoding: [0x57,0x61,0x10,0xc4]
+vwcvt.x.x.v v2, v1, v0.t
+# ALIAS:    vwcvtu.x.x.v    v2, v1, v0.t    # encoding: [0x57,0x61,0x10,0xc0]
+# NO-ALIAS: vwaddu.vx       v2, v1, zero, v0.t # encoding: [0x57,0x61,0x10,0xc0]
+vwcvtu.x.x.v v2, v1, v0.t
+# ALIAS:    vnot.v  v2, v2, v0.t            # encoding: [0x57,0xb1,0x2f,0x2c]
+# NO-ALIAS: vxor.vi v2, v2, -1, v0.t        # encoding: [0x57,0xb1,0x2f,0x2c]
+vnot.v v2, v2, v0.t
+# ALIAS:    vmsltu.vv       v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x68]
+# NO-ALIAS: vmsltu.vv       v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x68]
+vmsgtu.vv v2, v2, v1, v0.t
+# ALIAS:    vmslt.vv        v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x6c]
+# NO-ALIAS: vmslt.vv        v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x6c]
+vmsgt.vv v2, v2, v1, v0.t
+# ALIAS:    vmsleu.vv       v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x70]
+# NO-ALIAS: vmsleu.vv       v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x70]
+vmsgeu.vv v2, v2, v1, v0.t
+# ALIAS:    vmsle.vv        v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x74]
+# NO-ALIAS: vmsle.vv        v2, v1, v2, v0.t # encoding: [0x57,0x01,0x11,0x74]
+vmsge.vv v2, v2, v1, v0.t
+# ALIAS:    vmsleu.vi       v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x70]
+# NO-ALIAS: vmsleu.vi       v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x70]
+vmsltu.vi v2, v2, 16, v0.t
+# ALIAS:    vmsle.vi        v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x74]
+# NO-ALIAS: vmsle.vi        v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x74]
+vmslt.vi v2, v2, 16, v0.t
+# ALIAS:    vmsgtu.vi       v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x78]
+# NO-ALIAS: vmsgtu.vi       v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x78]
+vmsgeu.vi v2, v2, 16, v0.t
+# ALIAS:    vmsgt.vi        v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x7c]
+# NO-ALIAS: vmsgt.vi        v2, v2, 15, v0.t # encoding: [0x57,0xb1,0x27,0x7c]
+vmsge.vi v2, v2, 16, v0.t
+# ALIAS:    vmflt.vv        v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x6c]
+# NO-ALIAS: vmflt.vv        v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x6c]
+vmfgt.vv v2, v2, v1, v0.t
+# ALIAS:    vmfle.vv        v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x64]
+# NO-ALIAS: vmfle.vv        v2, v1, v2, v0.t # encoding: [0x57,0x11,0x11,0x64]
+vmfge.vv v2, v2, v1, v0.t
+# ALIAS:    vmmv.m v0, v1                  # encoding: [0x57,0xa0,0x10,0x66]
+# NO-ALIAS: vmand.mm        v0, v1, v1      # encoding: [0x57,0xa0,0x10,0x66]
+vmmv.m v0, v1
+# ALIAS:    vmclr.m v0                      # encoding: [0x57,0x20,0x00,0x6e]
+# NO-ALIAS: vmxor.mm        v0, v0, v0      # encoding: [0x57,0x20,0x00,0x6e]
+vmclr.m v0
+# ALIAS:    vmset.m v0                      # encoding: [0x57,0x20,0x00,0x7e]
+# NO-ALIAS: vmxnor.mm       v0, v0, v0      # encoding: [0x57,0x20,0x00,0x7e]
+vmset.m v0
+# ALIAS:    vmnot.m v0, v1                  # encoding: [0x57,0xa0,0x10,0x76]
+# NO-ALIAS: vmnand.mm       v0, v1, v1      # encoding: [0x57,0xa0,0x10,0x76]
+vmnot.m v0, v1
+# ALIAS:    vl1r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x22]
+# NO-ALIAS: vl1re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x22]
+vl1r.v v0, (a0) 
+# ALIAS:    vl2r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x42]
+# NO-ALIAS: vl2re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x42]
+vl2r.v v0, (a0) 
+# ALIAS:    vl4r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x82]
+# NO-ALIAS: vl4re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x82]
+vl4r.v v0, (a0) 
+# ALIAS:    vl8r.v          v0, (a0)        # encoding: [0x07,0x00,0x85,0x02]
+# NO-ALIAS: vl8re8.v        v0, (a0)        # encoding: [0x07,0x00,0x85,0x02]
+vl8r.v v0, (a0) 
+# ALIAS:    vneg.v          v2, v1, v0.t    # encoding: [0x57,0x41,0x10,0x0c]
+# NO-ALIAS: vrsub.vx        v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c]
+vneg.v v2, v1, v0.t 
+# ALIAS:    vncvt.x.x.w     v2, v1, v0.t    # encoding: [0x57,0x41,0x10,0xb0]
+# NO-ALIAS: vnsrl.wx        v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0xb0]
+vncvt.x.x.w v2, v1, v0.t 
+# ALIAS:    vfneg.v         v2, v1, v0.t     # encoding: [0x57,0x91,0x10,0x24]
+# NO-ALIAS: vfsgnjn.vv      v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
+vfneg.v v2, v1, v0.t 

llvm/test/MC/RISCV/rvv/fothers.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN:         --mattr=+f \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN:   --mattr=+f --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:         --mattr=+f \
-# RUN:        | llvm-objdump -d --mattr=+experimental-v --mattr=+f - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN:   --mattr=+f | llvm-objdump -d --mattr=+experimental-v \
+# RUN:   --mattr=+f --riscv-no-aliases - \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:         --mattr=+f \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   --mattr=+f | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vfsqrt.v v8, v4, v0.t
 # CHECK-INST: vfsqrt.v v8, v4, v0.t
 # CHECK-ENCODING: [0x57,0x14,0x40,0x4c]
 # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
 # CHECK-UNKNOWN: 57 14 40 4c <unknown>
 
 vfsqrt.v v8, v4
 # CHECK-INST: vfsqrt.v v8, v4
 # CHECK-ENCODING: [0x57,0x14,0x40,0x4e]
 # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
 # CHECK-UNKNOWN: 57 14 40 4e <unknown>
 
+vfrsqrte7.v v8, v4, v0.t
+# CHECK-INST: vfrsqrte7.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x42,0x4c]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 14 42 4c <unknown>
+
+vfrsqrte7.v v8, v4
+# CHECK-INST: vfrsqrte7.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x42,0x4e]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 14 42 4e <unknown>
+
+vfrece7.v v8, v4, v0.t
+# CHECK-INST: vfrece7.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x42,0x4c]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 94 42 4c <unknown>
+
+vfrece7.v v8, v4
+# CHECK-INST: vfrece7.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x42,0x4e]
+# CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
+# CHECK-UNKNOWN: 57 94 42 4e <unknown>
+
 vfclass.v v8, v4, v0.t
 # CHECK-INST: vfclass.v v8, v4, v0.t
 # CHECK-ENCODING: [0x57,0x14,0x48,0x4c]
 # CHECK-ERROR: instruction requires the following: 'F'{{.*}}'V'
 # CHECK-UNKNOWN: 57 14 48 4c <unknown>
 
 vfclass.v v8, v4
 # CHECK-INST: vfclass.v v8, v4

llvm/test/MC/RISCV/rvv/invalid.s

 vfwsub.wf v0, v2, fa0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwsub.wf v0, v2, fa0, v0.t
 
 vadc.vvm v0, v2, v4, v0
 # CHECK-ERROR: The destination vector register group cannot be V0.
 # CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0
 
-vmadc.vvm v2, v2, v4, v0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0
-
-vmadc.vvm v4, v2, v4, v0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0
-
 vadd.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t
 
 vadd.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vadd.vx v0, v2, a0, v0.t
 
 vadd.vi v0, v2, 1, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vadd.vi v0, v2, 1, v0.t
 
 vmsge.vx v0, v4, a0, v0.t
 # CHECK-ERROR: too few operands for instruction
 # CHECK-ERROR-LABEL: vmsge.vx v0, v4, a0, v0.t
 
 vmsge.vx v8, v4, a0, v0.t, v2
 # CHECK-ERROR: invalid operand for instruction
 # CHECK-ERROR-LABEL: vmsge.vx v8, v4, a0, v0.t, v2
-
-vmerge.vim v0, v1, 1, v0
-# CHECK-ERROR: The destination vector register group cannot be V0.
-# CHECK-ERROR-LABEL: vmerge.vim v0, v1, 1, v0
-
-vmerge.vvm v0, v1, v2, v0
-# CHECK-ERROR: The destination vector register group cannot be V0.
-# CHECK-ERROR-LABEL: vmerge.vvm v0, v1, v2, v0
-
-vmerge.vxm v0, v1, x1, v0
-# CHECK-ERROR: The destination vector register group cannot be V0.
-# CHECK-ERROR-LABEL: vmerge.vxm v0, v1, x1, v0
-
-vfmerge.vfm v0, v1, f1, v0
-# CHECK-ERROR: The destination vector register group cannot be V0.
-# CHECK-ERROR-LABEL: vfmerge.vfm v0, v1, f1, v0

llvm/test/MC/RISCV/rvv/load.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN:   --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN:   | llvm-objdump -d --mattr=+experimental-v - --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vle8.v v8, (a0), v0.t
 # CHECK-INST: vle8.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 05 00 <unknown>
 
 vle8.v v8, (a0)

 # CHECK-UNKNOWN: 07 74 b5 18 <unknown>
 
 vlse1024.v v8, (a0), a1
 # CHECK-INST: vlse1024.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x74,0xb5,0x1a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 b5 1a <unknown>
 
-vlxei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei8.v v8, (a0), v4, v0.t
+vluxei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 04 <unknown>
+
+vluxei8.v v8, (a0), v4
+# CHECK-INST: vluxei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 06 <unknown>
+
+vluxei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 04 <unknown>
+
+vluxei16.v v8, (a0), v4
+# CHECK-INST: vluxei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 06 <unknown>
+
+vluxei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 04 <unknown>
+
+vluxei32.v v8, (a0), v4
+# CHECK-INST: vluxei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 06 <unknown>
+
+vluxei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 04 <unknown>
+
+vluxei64.v v8, (a0), v4
+# CHECK-INST: vluxei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 06 <unknown>
+
+vloxei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei8.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x04,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 45 0c <unknown>
 
-vlxei8.v v8, (a0), v4
-# CHECK-INST: vlxei8.v v8, (a0), v4
+vloxei8.v v8, (a0), v4
+# CHECK-INST: vloxei8.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 45 0e <unknown>
 
-vlxei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei16.v v8, (a0), v4, v0.t
+vloxei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei16.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x54,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 45 0c <unknown>
 
-vlxei16.v v8, (a0), v4
-# CHECK-INST: vlxei16.v v8, (a0), v4
+vloxei16.v v8, (a0), v4
+# CHECK-INST: vloxei16.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 45 0e <unknown>
 
-vlxei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei32.v v8, (a0), v4, v0.t
+vloxei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei32.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x64,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 45 0c <unknown>
 
-vlxei32.v v8, (a0), v4
-# CHECK-INST: vlxei32.v v8, (a0), v4
+vloxei32.v v8, (a0), v4
+# CHECK-INST: vloxei32.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 45 0e <unknown>
 
-vlxei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei64.v v8, (a0), v4, v0.t
+vloxei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxei64.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x74,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 45 0c <unknown>
 
-vlxei64.v v8, (a0), v4
-# CHECK-INST: vlxei64.v v8, (a0), v4
+vloxei64.v v8, (a0), v4
+# CHECK-INST: vloxei64.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 45 0e <unknown>
 
-vlxei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+vl1re8.v v8, (a0)
+# CHECK-INST: vl1re8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 22 <unknown>
+
+vl1re16.v v8, (a0)
+# CHECK-INST: vl1re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 22 <unknown>
+
+vl1re32.v v8, (a0)
+# CHECK-INST: vl1re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 22 <unknown>
+
+vl1re64.v v8, (a0)
+# CHECK-INST: vl1re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 22 <unknown>
+
+vl1re128.v v8, (a0)
+# CHECK-INST: vl1re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 32 <unknown>
+
+vl1re256.v v8, (a0)
+# CHECK-INST: vl1re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 32 <unknown>
+
+vl1re512.v v8, (a0)
+# CHECK-INST: vl1re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 32 <unknown>
+
+vl1re1024.v v8, (a0)
+# CHECK-INST: vl1re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 32 <unknown>
+
+vl2re8.v v8, (a0)
+# CHECK-INST: vl2re8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 42 <unknown>
+
+vl2re16.v v8, (a0)
+# CHECK-INST: vl2re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 42 <unknown>
+
+vl2re32.v v8, (a0)
+# CHECK-INST: vl2re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 42 <unknown>
+
+vl2re64.v v8, (a0)
+# CHECK-INST: vl2re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 42 <unknown>
+
+vl2re128.v v8, (a0)
+# CHECK-INST: vl2re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 52 <unknown>
+
+vl2re256.v v8, (a0)
+# CHECK-INST: vl2re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 52 <unknown>
+
+vl2re512.v v8, (a0)
+# CHECK-INST: vl2re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 52 <unknown>
+
+vl2re1024.v v8, (a0)
+# CHECK-INST: vl2re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x52]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+# CHECK-UNKNOWN: 07 74 85 52 <unknown>
 
-vlxei128.v v8, (a0), v4
-# CHECK-INST: vlxei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+vl4re8.v v8, (a0)
+# CHECK-INST: vl4re8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+# CHECK-UNKNOWN: 07 04 85 82 <unknown>
 
-vlxei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+vl4re16.v v8, (a0)
+# CHECK-INST: vl4re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+# CHECK-UNKNOWN: 07 54 85 82 <unknown>
 
-vlxei256.v v8, (a0), v4
-# CHECK-INST: vlxei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+vl4re32.v v8, (a0)
+# CHECK-INST: vl4re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+# CHECK-UNKNOWN: 07 64 85 82 <unknown>
 
-vlxei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+vl4re64.v v8, (a0)
+# CHECK-INST: vl4re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+# CHECK-UNKNOWN: 07 74 85 82 <unknown>
 
-vlxei512.v v8, (a0), v4
-# CHECK-INST: vlxei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+vl4re128.v v8, (a0)
+# CHECK-INST: vl4re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x92]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+# CHECK-UNKNOWN: 07 04 85 92 <unknown>
 
-vlxei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x1c]
+vl4re256.v v8, (a0)
+# CHECK-INST: vl4re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x92]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 74 45 1c <unknown>
+# CHECK-UNKNOWN: 07 54 85 92 <unknown>
 
-vlxei1024.v v8, (a0), v4
-# CHECK-INST: vlxei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x1e]
+vl4re512.v v8, (a0)
+# CHECK-INST: vl4re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x92]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 74 45 1e <unknown>
+# CHECK-UNKNOWN: 07 64 85 92 <unknown>
 
-vl1r.v v8, (a0)
-# CHECK-INST: vl1r.v v8, (a0)
+vl4re1024.v v8, (a0)
+# CHECK-INST: vl4re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 92 <unknown>
+
+vl8re8.v v8, (a0)
+# CHECK-INST: vl8re8.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x85,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 85 02 <unknown>
+
+vl8re16.v v8, (a0)
+# CHECK-INST: vl8re16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 02 <unknown>
+
+vl8re32.v v8, (a0)
+# CHECK-INST: vl8re32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 02 <unknown>
+
+vl8re64.v v8, (a0)
+# CHECK-INST: vl8re64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 02 <unknown>
+
+vl8re128.v v8, (a0)
+# CHECK-INST: vl8re128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 85 12 <unknown>
+
+vl8re256.v v8, (a0)
+# CHECK-INST: vl8re256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 85 12 <unknown>
+
+vl8re512.v v8, (a0)
+# CHECK-INST: vl8re512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 85 12 <unknown>
+
+vl8re1024.v v8, (a0)
+# CHECK-INST: vl8re1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 12 <unknown>

llvm/test/MC/RISCV/rvv/others.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN:   --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN:   | llvm-objdump -d --mattr=+experimental-v - --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vmerge.vvm v8, v4, v20, v0
 # CHECK-INST: vmerge.vvm v8, v4, v20, v0
 # CHECK-ENCODING: [0x57,0x04,0x4a,0x5c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 04 4a 5c <unknown>
 
 vmerge.vxm v8, v4, a0, v0

 # CHECK-UNKNOWN: 57 b4 4f 30 <unknown>
 
 vrgather.vi v8, v4, 31
 # CHECK-INST: vrgather.vi v8, v4, 31
 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x32]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 b4 4f 32 <unknown>
 
+vrgatherei16.vv v8, v4, v20, v0.t
+# CHECK-INST: vrgatherei16.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 38 <unknown>
+
+vrgatherei16.vv v8, v4, v20
+# CHECK-INST: vrgatherei16.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 3a <unknown>
+
 vcompress.vm v8, v4, v20
 # CHECK-INST: vcompress.vm v8, v4, v20
 # CHECK-ENCODING: [0x57,0x24,0x4a,0x5e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 24 4a 5e <unknown>

llvm/test/MC/RISCV/rvv/snippet.s

 ## A snippet from https://github.com/riscv/riscv-v-spec.
 
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN: | llvm-objdump -d --mattr=+experimental-v - \
 # RUN: | FileCheck %s --check-prefix=CHECK-INST
 
 loop:
     vsetvli a3, a0, e16,m4,ta,ma  # vtype = 16-bit integer vectors
-# CHECK-INST: d7 76 65 0c    vsetvli a3, a0, e16,m4,ta,ma
+# CHECK-INST: d7 76 a5 0c    vsetvli a3, a0, e16,m4,ta,ma
     vle16.v v4, (a1)              # Get 16b vector
 # CHECK-INST: 07 d2 05 02    vle16.v   v4, (a1)
     slli t1, a3, 1                # Multiply length by two bytes/element
 # CHECK-INST: 13 93 16 00    slli    t1, a3, 1
     add a1, a1, t1                # Bump pointer
 # CHECK-INST: b3 85 65 00    add     a1, a1, t1
     vwmul.vx v8, v4, x10          # 32b in <v8--v15>
 # CHECK-INST: 57 64 45 ee    vwmul.vx        v8, v4, a0
 
     vsetvli x0, a0, e32,m8,ta,ma  # Operate on 32b values
-# CHECK-INST: 57 70 b5 0c    vsetvli zero, a0, e32,m8,ta,ma
+# CHECK-INST: 57 70 35 0d    vsetvli zero, a0, e32,m8,ta,ma
     vsrl.vi v8, v8, 3
 # CHECK-INST: 57 b4 81 a2    vsrl.vi v8, v8, 3
     vse32.v v8, (a2)              # Store vector of 32b
 # CHECK-INST: 27 64 06 02    vse32.v   v8, (a2)
     slli t1, a3, 2                # Multiply length by four bytes/element
 # CHECK-INST: 13 93 26 00    slli    t1, a3, 2
     add a2, a2, t1                # Bump pointer
 # CHECK-INST: 33 06 66 00    add     a2, a2, t1
     sub a0, a0, a3                # Decrement count
 # CHECK-INST: 33 05 d5 40    sub     a0, a0, a3
     bnez a0, loop                 # Any more?
 # CHECK-INST: e3 1a 05 fc    bnez    a0, 0x0

llvm/test/MC/RISCV/rvv/store.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN:   --riscv-no-aliases | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN:   | llvm-objdump -d --mattr=+experimental-v - --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vse8.v v24, (a0), v0.t
 # CHECK-INST: vse8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 00 <unknown>
 
 vse8.v v24, (a0)

 # CHECK-UNKNOWN: 27 7c b5 18 <unknown>
 
 vsse1024.v v24, (a0), a1
 # CHECK-INST: vsse1024.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x1a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c b5 1a <unknown>
 
-vsxei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei8.v v24, (a0), v4, v0.t
+vsuxei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 04 <unknown>
+
+vsuxei8.v v24, (a0), v4
+# CHECK-INST: vsuxei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 06 <unknown>
+
+vsuxei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 04 <unknown>
+
+vsuxei16.v v24, (a0), v4
+# CHECK-INST: vsuxei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 06 <unknown>
+
+vsuxei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 04 <unknown>
+
+vsuxei32.v v24, (a0), v4
+# CHECK-INST: vsuxei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 06 <unknown>
+
+vsuxei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 04 <unknown>
+
+vsuxei64.v v24, (a0), v4
+# CHECK-INST: vsuxei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 06 <unknown>
+
+vsoxei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei8.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 0c <unknown>
 
-vsxei8.v v24, (a0), v4
-# CHECK-INST: vsxei8.v v24, (a0), v4
+vsoxei8.v v24, (a0), v4
+# CHECK-INST: vsoxei8.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 0e <unknown>
 
-vsxei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei16.v v24, (a0), v4, v0.t
+vsoxei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei16.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 0c <unknown>
 
-vsxei16.v v24, (a0), v4
-# CHECK-INST: vsxei16.v v24, (a0), v4
+vsoxei16.v v24, (a0), v4
+# CHECK-INST: vsoxei16.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 0e <unknown>
 
-vsxei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei32.v v24, (a0), v4, v0.t
+vsoxei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei32.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 0c <unknown>
 
-vsxei32.v v24, (a0), v4
-# CHECK-INST: vsxei32.v v24, (a0), v4
+vsoxei32.v v24, (a0), v4
+# CHECK-INST: vsoxei32.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 0e <unknown>
 
-vsxei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei64.v v24, (a0), v4, v0.t
+vsoxei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxei64.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 0c <unknown>
 
-vsxei64.v v24, (a0), v4
-# CHECK-INST: vsxei64.v v24, (a0), v4
+vsoxei64.v v24, (a0), v4
+# CHECK-INST: vsoxei64.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 0e <unknown>
 
-vsxei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x1c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 0c 45 1c <unknown>
-
-vsxei128.v v24, (a0), v4
-# CHECK-INST: vsxei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x1e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 0c 45 1e <unknown>
-
-vsxei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x1c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 5c 45 1c <unknown>
-
-vsxei256.v v24, (a0), v4
-# CHECK-INST: vsxei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x1e]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 5c 45 1e <unknown>
-
-vsxei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x1c]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 6c 45 1c <unknown>
-
-vsxei512.v v24, (a0), v4
-# CHECK-INST: vsxei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x1e]
+vs1r.v v24, (a0)
+# CHECK-INST: vs1r.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x22]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 6c 45 1e <unknown>
+# CHECK-UNKNOWN: 27 0c 85 22 <unknown>
 
-vsxei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x1c]
+vs2r.v v24, (a0)
+# CHECK-INST: vs2r.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x42]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 7c 45 1c <unknown>
+# CHECK-UNKNOWN: 27 0c 85 42 <unknown>
 
-vsxei1024.v v24, (a0), v4
-# CHECK-INST: vsxei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x1e]
+vs4r.v v24, (a0)
+# CHECK-INST: vs4r.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x82]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 7c 45 1e <unknown>
+# CHECK-UNKNOWN: 27 0c 85 82 <unknown>
 
-vs1r.v v24, (a0)
-# CHECK-INST: vs1r.v v24, (a0)
+vs8r.v v24, (a0)
+# CHECK-INST: vs8r.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0x85,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 85 02 <unknown>

llvm/test/MC/RISCV/rvv/vsetvl.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d --mattr=+experimental-v - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vsetvli a2, a0, e32,m1,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 85 0c <unknown>
+# CHECK-UNKNOWN: 57 76 05 0d <unknown>
 
 vsetvli a2, a0, e32,m2,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,m2,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0x95,0x0c]
+# CHECK-ENCODING: [0x57,0x76,0x15,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 95 0c <unknown>
+# CHECK-UNKNOWN: 57 76 15 0d <unknown>
 
 vsetvli a2, a0, e32,m4,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,m4,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0xa5,0x0c]
+# CHECK-ENCODING: [0x57,0x76,0x25,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 a5 0c <unknown>
+# CHECK-UNKNOWN: 57 76 25 0d <unknown>
 
 vsetvli a2, a0, e32,m8,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,m8,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0xb5,0x0c]
+# CHECK-ENCODING: [0x57,0x76,0x35,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 b5 0c <unknown>
+# CHECK-UNKNOWN: 57 76 35 0d <unknown>
 
 vsetvli a2, a0, e32,mf2,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,mf2,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0xb5,0x0e]
+# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 b5 0e <unknown>
+# CHECK-UNKNOWN: 57 76 75 0d <unknown>
 
 vsetvli a2, a0, e32,mf4,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,mf4,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0xa5,0x0e]
+# CHECK-ENCODING: [0x57,0x76,0x65,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 a5 0e <unknown>
+# CHECK-UNKNOWN: 57 76 65 0d <unknown>
 
 vsetvli a2, a0, e32,mf8,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,mf8,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0x95,0x0e]
+# CHECK-ENCODING: [0x57,0x76,0x55,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 95 0e <unknown>
+# CHECK-UNKNOWN: 57 76 55 0d <unknown>
 
 vsetvli a2, a0, e32,m1,ta,ma
 # CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
-# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 85 0c <unknown>
+# CHECK-UNKNOWN: 57 76 05 0d <unknown>
 
 vsetvli a2, a0, e32,m1,tu,ma
 # CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
-# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ENCODING: [0x57,0x76,0x05,0x09]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 85 08 <unknown>
+# CHECK-UNKNOWN: 57 76 05 09 <unknown>
 
 vsetvli a2, a0, e32,m1,ta,mu
 # CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
-# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ENCODING: [0x57,0x76,0x05,0x05]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 85 04 <unknown>
+# CHECK-UNKNOWN: 57 76 05 05 <unknown>
 
 vsetvli a2, a0, e32,m1,tu,mu
 # CHECK-INST: vsetvli a2, a0, e32,m1
-# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ENCODING: [0x57,0x76,0x05,0x01]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 85 00 <unknown>
+# CHECK-UNKNOWN: 57 76 05 01 <unknown>
 
 vsetvl a2, a0, a1
 # CHECK-INST: vsetvl a2, a0, a1
 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 76 b5 80 <unknown>

llvm/test/MC/RISCV/rvv/zvlsseg.s

-# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvlsseg %s \
-# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:   --mattr=+experimental-zvlsseg --riscv-no-aliases \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
-# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvlsseg %s \
-# RUN:        | llvm-objdump -d --mattr=+experimental-zvlsseg - \
-# RUN:        | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvlsseg %s \
-# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \
+# RUN:   --mattr=+experimental-zvlsseg %s \
+# RUN:   | llvm-objdump -d --mattr=+experimental-v --mattr=+experimental-zvlsseg \
+# RUN:   --riscv-no-aliases - \
+# RUN:   | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \
+# RUN:   --mattr=+experimental-zvlsseg %s \
+# RUN:   | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vlseg2e8.v v8, (a0)
-# CHECK-INST: vlseg2e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 22 <unknown>
-
-vlseg2e16.v v8, (a0)
-# CHECK-INST: vlseg2e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 22 <unknown>
-
-vlseg2e32.v v8, (a0)
-# CHECK-INST: vlseg2e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 22 <unknown>
-
-vlseg2e64.v v8, (a0)
-# CHECK-INST: vlseg2e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 22 <unknown>
-
-vlseg2e128.v v8, (a0)
-# CHECK-INST: vlseg2e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 32 <unknown>
-
-vlseg2e256.v v8, (a0)
-# CHECK-INST: vlseg2e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 32 <unknown>
-
-vlseg2e512.v v8, (a0)
-# CHECK-INST: vlseg2e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 32 <unknown>
-
-vlseg2e1024.v v8, (a0)
-# CHECK-INST: vlseg2e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 32 <unknown>
-
 vlseg2e8.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e8.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 20 <unknown>
 
+vlseg2e8.v v8, (a0)
+# CHECK-INST: vlseg2e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 22 <unknown>
+
 vlseg2e16.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e16.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x54,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 20 <unknown>
 
+vlseg2e16.v v8, (a0)
+# CHECK-INST: vlseg2e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 22 <unknown>
+
 vlseg2e32.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e32.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x64,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 20 <unknown>
 
+vlseg2e32.v v8, (a0)
+# CHECK-INST: vlseg2e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 22 <unknown>
+
 vlseg2e64.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e64.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x74,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 20 <unknown>
 
+vlseg2e64.v v8, (a0)
+# CHECK-INST: vlseg2e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 22 <unknown>
+
 vlseg2e128.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e128.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 30 <unknown>
 
+vlseg2e128.v v8, (a0)
+# CHECK-INST: vlseg2e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 32 <unknown>
+
 vlseg2e256.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e256.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x54,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 30 <unknown>
 
+vlseg2e256.v v8, (a0)
+# CHECK-INST: vlseg2e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 32 <unknown>
+
 vlseg2e512.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e512.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x64,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 30 <unknown>
 
+vlseg2e512.v v8, (a0)
+# CHECK-INST: vlseg2e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 32 <unknown>
+
 vlseg2e1024.v v8, (a0), v0.t
 # CHECK-INST: vlseg2e1024.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x74,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 30 <unknown>
 
-vlseg3e8.v v8, (a0)
-# CHECK-INST: vlseg3e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 42 <unknown>
-
-vlseg3e16.v v8, (a0)
-# CHECK-INST: vlseg3e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 42 <unknown>
-
-vlseg3e32.v v8, (a0)
-# CHECK-INST: vlseg3e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 42 <unknown>
-
-vlseg3e64.v v8, (a0)
-# CHECK-INST: vlseg3e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 42 <unknown>
-
-vlseg3e128.v v8, (a0)
-# CHECK-INST: vlseg3e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 52 <unknown>
-
-vlseg3e256.v v8, (a0)
-# CHECK-INST: vlseg3e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 52 <unknown>
-
-vlseg3e512.v v8, (a0)
-# CHECK-INST: vlseg3e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 52 <unknown>
-
-vlseg3e1024.v v8, (a0)
-# CHECK-INST: vlseg3e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 52 <unknown>
-
-vlseg3e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 40 <unknown>
-
-vlseg3e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 40 <unknown>
-
-vlseg3e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 40 <unknown>
-
-vlseg3e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 40 <unknown>
-
-vlseg3e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 50 <unknown>
-
-vlseg3e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 50 <unknown>
-
-vlseg3e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 50 <unknown>
-
-vlseg3e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 50 <unknown>
-
-vlseg4e8.v v8, (a0)
-# CHECK-INST: vlseg4e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 62 <unknown>
-
-vlseg4e16.v v8, (a0)
-# CHECK-INST: vlseg4e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 62 <unknown>
-
-vlseg4e32.v v8, (a0)
-# CHECK-INST: vlseg4e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 62 <unknown>
-
-vlseg4e64.v v8, (a0)
-# CHECK-INST: vlseg4e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 62 <unknown>
-
-vlseg4e128.v v8, (a0)
-# CHECK-INST: vlseg4e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 72 <unknown>
-
-vlseg4e256.v v8, (a0)
-# CHECK-INST: vlseg4e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 72 <unknown>
-
-vlseg4e512.v v8, (a0)
-# CHECK-INST: vlseg4e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 72 <unknown>
-
-vlseg4e1024.v v8, (a0)
-# CHECK-INST: vlseg4e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 72 <unknown>
-
-vlseg4e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 60 <unknown>
-
-vlseg4e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 60 <unknown>
-
-vlseg4e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 60 <unknown>
-
-vlseg4e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 60 <unknown>
-
-vlseg4e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 70 <unknown>
-
-vlseg4e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 70 <unknown>
-
-vlseg4e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 70 <unknown>
-
-vlseg4e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 70 <unknown>
-
-vlseg5e8.v v8, (a0)
-# CHECK-INST: vlseg5e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 82 <unknown>
-
-vlseg5e16.v v8, (a0)
-# CHECK-INST: vlseg5e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 82 <unknown>
-
-vlseg5e32.v v8, (a0)
-# CHECK-INST: vlseg5e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 82 <unknown>
-
-vlseg5e64.v v8, (a0)
-# CHECK-INST: vlseg5e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 82 <unknown>
-
-vlseg5e128.v v8, (a0)
-# CHECK-INST: vlseg5e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 92 <unknown>
-
-vlseg5e256.v v8, (a0)
-# CHECK-INST: vlseg5e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 92 <unknown>
+vlseg2e1024.v v8, (a0)
+# CHECK-INST: vlseg2e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 32 <unknown>
 
-vlseg5e512.v v8, (a0)
-# CHECK-INST: vlseg5e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 92 <unknown>
+vlseg2e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 21 <unknown>
 
-vlseg5e1024.v v8, (a0)
-# CHECK-INST: vlseg5e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 92 <unknown>
+vlseg2e8ff.v v8, (a0)
+# CHECK-INST: vlseg2e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 23 <unknown>
 
-vlseg5e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 80 <unknown>
+vlseg2e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 21 <unknown>
 
-vlseg5e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 80 <unknown>
+vlseg2e16ff.v v8, (a0)
+# CHECK-INST: vlseg2e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 23 <unknown>
 
-vlseg5e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 80 <unknown>
+vlseg2e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 21 <unknown>
 
-vlseg5e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 80 <unknown>
+vlseg2e32ff.v v8, (a0)
+# CHECK-INST: vlseg2e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 23 <unknown>
 
-vlseg5e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 90 <unknown>
+vlseg2e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 21 <unknown>
 
-vlseg5e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 90 <unknown>
+vlseg2e64ff.v v8, (a0)
+# CHECK-INST: vlseg2e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 23 <unknown>
 
-vlseg5e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 90 <unknown>
+vlseg2e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 31 <unknown>
 
-vlseg5e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 90 <unknown>
+vlseg2e128ff.v v8, (a0)
+# CHECK-INST: vlseg2e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 33 <unknown>
 
-vlseg6e8.v v8, (a0)
-# CHECK-INST: vlseg6e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 a2 <unknown>
+vlseg2e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 31 <unknown>
 
-vlseg6e16.v v8, (a0)
-# CHECK-INST: vlseg6e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 a2 <unknown>
+vlseg2e256ff.v v8, (a0)
+# CHECK-INST: vlseg2e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 33 <unknown>
 
-vlseg6e32.v v8, (a0)
-# CHECK-INST: vlseg6e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 a2 <unknown>
+vlseg2e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 31 <unknown>
 
-vlseg6e64.v v8, (a0)
-# CHECK-INST: vlseg6e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 a2 <unknown>
+vlseg2e512ff.v v8, (a0)
+# CHECK-INST: vlseg2e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 33 <unknown>
 
-vlseg6e128.v v8, (a0)
-# CHECK-INST: vlseg6e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 b2 <unknown>
+vlseg2e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 31 <unknown>
 
-vlseg6e256.v v8, (a0)
-# CHECK-INST: vlseg6e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 b2 <unknown>
+vlseg2e1024ff.v v8, (a0)
+# CHECK-INST: vlseg2e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 33 <unknown>
 
-vlseg6e512.v v8, (a0)
-# CHECK-INST: vlseg6e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 b2 <unknown>
+vlsseg2e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 28 <unknown>
 
-vlseg6e1024.v v8, (a0)
-# CHECK-INST: vlseg6e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 b2 <unknown>
+vlsseg2e8.v v8, (a0), a1
+# CHECK-INST: vlsseg2e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
 
-vlseg6e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 a0 <unknown>
+vlsseg2e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 28 <unknown>
 
-vlseg6e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 a0 <unknown>
+vlsseg2e16.v v8, (a0), a1
+# CHECK-INST: vlsseg2e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 2a <unknown>
 
-vlseg6e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 a0 <unknown>
+vlsseg2e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 28 <unknown>
 
-vlseg6e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 a0 <unknown>
+vlsseg2e32.v v8, (a0), a1
+# CHECK-INST: vlsseg2e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 2a <unknown>
 
-vlseg6e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 b0 <unknown>
+vlsseg2e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 28 <unknown>
 
-vlseg6e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 b0 <unknown>
+vlsseg2e64.v v8, (a0), a1
+# CHECK-INST: vlsseg2e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 2a <unknown>
 
-vlseg6e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 b0 <unknown>
+vlsseg2e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 38 <unknown>
 
-vlseg6e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 b0 <unknown>
+vlsseg2e128.v v8, (a0), a1
+# CHECK-INST: vlsseg2e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 3a <unknown>
 
-vlseg7e8.v v8, (a0)
-# CHECK-INST: vlseg7e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 c2 <unknown>
+vlsseg2e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 38 <unknown>
 
-vlseg7e16.v v8, (a0)
-# CHECK-INST: vlseg7e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 c2 <unknown>
+vlsseg2e256.v v8, (a0), a1
+# CHECK-INST: vlsseg2e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 3a <unknown>
 
-vlseg7e32.v v8, (a0)
-# CHECK-INST: vlseg7e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 c2 <unknown>
+vlsseg2e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 38 <unknown>
 
-vlseg7e64.v v8, (a0)
-# CHECK-INST: vlseg7e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 c2 <unknown>
+vlsseg2e512.v v8, (a0), a1
+# CHECK-INST: vlsseg2e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 3a <unknown>
 
-vlseg7e128.v v8, (a0)
-# CHECK-INST: vlseg7e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 d2 <unknown>
+vlsseg2e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 38 <unknown>
 
-vlseg7e256.v v8, (a0)
-# CHECK-INST: vlseg7e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 d2 <unknown>
+vlsseg2e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg2e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 3a <unknown>
 
-vlseg7e512.v v8, (a0)
-# CHECK-INST: vlseg7e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d2 <unknown>
+vluxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 24 <unknown>
+
+vluxseg2ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 26 <unknown>
+
+vluxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 24 <unknown>
+
+vluxseg2ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 26 <unknown>
+
+vluxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 24 <unknown>
+
+vluxseg2ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 26 <unknown>
+
+vluxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 24 <unknown>
+
+vluxseg2ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg2ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 26 <unknown>
 
-vlseg7e1024.v v8, (a0)
-# CHECK-INST: vlseg7e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d2 <unknown>
+vloxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 2c <unknown>
 
-vlseg7e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 c0 <unknown>
+vloxseg2ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 2e <unknown>
 
-vlseg7e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 c0 <unknown>
+vloxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 2c <unknown>
 
-vlseg7e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 c0 <unknown>
+vloxseg2ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 2e <unknown>
 
-vlseg7e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 c0 <unknown>
+vloxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 2c <unknown>
 
-vlseg7e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 d0 <unknown>
+vloxseg2ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 2e <unknown>
 
-vlseg7e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 d0 <unknown>
+vloxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 2c <unknown>
 
-vlseg7e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d0 <unknown>
+vloxseg2ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg2ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 2e <unknown>
 
-vlseg7e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d0 <unknown>
+vlseg3e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 40 <unknown>
 
-vlseg8e8.v v8, (a0)
-# CHECK-INST: vlseg8e8.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 e2 <unknown>
+vlseg3e8.v v8, (a0)
+# CHECK-INST: vlseg3e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 42 <unknown>
 
-vlseg8e16.v v8, (a0)
-# CHECK-INST: vlseg8e16.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 e2 <unknown>
+vlseg3e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 40 <unknown>
 
-vlseg8e32.v v8, (a0)
-# CHECK-INST: vlseg8e32.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 e2 <unknown>
+vlseg3e16.v v8, (a0)
+# CHECK-INST: vlseg3e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 42 <unknown>
 
-vlseg8e64.v v8, (a0)
-# CHECK-INST: vlseg8e64.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 e2 <unknown>
+vlseg3e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 40 <unknown>
 
-vlseg8e128.v v8, (a0)
-# CHECK-INST: vlseg8e128.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 f2 <unknown>
+vlseg3e32.v v8, (a0)
+# CHECK-INST: vlseg3e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 42 <unknown>
 
-vlseg8e256.v v8, (a0)
-# CHECK-INST: vlseg8e256.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 f2 <unknown>
+vlseg3e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 40 <unknown>
 
-vlseg8e512.v v8, (a0)
-# CHECK-INST: vlseg8e512.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 f2 <unknown>
+vlseg3e64.v v8, (a0)
+# CHECK-INST: vlseg3e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 42 <unknown>
 
-vlseg8e1024.v v8, (a0)
-# CHECK-INST: vlseg8e1024.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 f2 <unknown>
+vlseg3e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 50 <unknown>
 
-vlseg8e8.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e8.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 e0 <unknown>
+vlseg3e128.v v8, (a0)
+# CHECK-INST: vlseg3e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 52 <unknown>
 
-vlseg8e16.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e16.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 e0 <unknown>
+vlseg3e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 50 <unknown>
 
-vlseg8e32.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e32.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 e0 <unknown>
+vlseg3e256.v v8, (a0)
+# CHECK-INST: vlseg3e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 52 <unknown>
 
-vlseg8e64.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e64.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 e0 <unknown>
+vlseg3e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 50 <unknown>
 
-vlseg8e128.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e128.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 f0 <unknown>
+vlseg3e512.v v8, (a0)
+# CHECK-INST: vlseg3e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 52 <unknown>
 
-vlseg8e256.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e256.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 f0 <unknown>
+vlseg3e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 50 <unknown>
 
-vlseg8e512.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e512.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 f0 <unknown>
+vlseg3e1024.v v8, (a0)
+# CHECK-INST: vlseg3e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 52 <unknown>
 
-vlseg8e1024.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e1024.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 f0 <unknown>
+vlseg3e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 41 <unknown>
 
-vlsseg2e8.v v8, (a0), a1
-# CHECK-INST: vlsseg2e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
+vlseg3e8ff.v v8, (a0)
+# CHECK-INST: vlseg3e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 43 <unknown>
 
-vlsseg2e16.v v8, (a0), a1
-# CHECK-INST: vlsseg2e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 2a <unknown>
+vlseg3e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 41 <unknown>
 
-vlsseg2e32.v v8, (a0), a1
-# CHECK-INST: vlsseg2e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 2a <unknown>
+vlseg3e16ff.v v8, (a0)
+# CHECK-INST: vlseg3e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 43 <unknown>
 
-vlsseg2e64.v v8, (a0), a1
-# CHECK-INST: vlsseg2e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 2a <unknown>
+vlseg3e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 41 <unknown>
 
-vlsseg2e128.v v8, (a0), a1
-# CHECK-INST: vlsseg2e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 3a <unknown>
+vlseg3e32ff.v v8, (a0)
+# CHECK-INST: vlseg3e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 43 <unknown>
 
-vlsseg2e256.v v8, (a0), a1
-# CHECK-INST: vlsseg2e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 3a <unknown>
+vlseg3e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 41 <unknown>
 
-vlsseg2e512.v v8, (a0), a1
-# CHECK-INST: vlsseg2e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 3a <unknown>
+vlseg3e64ff.v v8, (a0)
+# CHECK-INST: vlseg3e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 43 <unknown>
 
-vlsseg2e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg2e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 3a <unknown>
+vlseg3e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 51 <unknown>
 
-vlsseg2e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 28 <unknown>
+vlseg3e128ff.v v8, (a0)
+# CHECK-INST: vlseg3e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 53 <unknown>
 
-vlsseg2e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 28 <unknown>
+vlseg3e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 51 <unknown>
 
-vlsseg2e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 28 <unknown>
+vlseg3e256ff.v v8, (a0)
+# CHECK-INST: vlseg3e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 53 <unknown>
 
-vlsseg2e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 28 <unknown>
+vlseg3e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 51 <unknown>
 
-vlsseg2e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 38 <unknown>
+vlseg3e512ff.v v8, (a0)
+# CHECK-INST: vlseg3e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 53 <unknown>
 
-vlsseg2e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 38 <unknown>
+vlseg3e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 51 <unknown>
 
-vlsseg2e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 38 <unknown>
+vlseg3e1024ff.v v8, (a0)
+# CHECK-INST: vlseg3e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 53 <unknown>
 
-vlsseg2e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg2e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 38 <unknown>
+vlsseg3e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 48 <unknown>
 
 vlsseg3e8.v v8, (a0), a1
 # CHECK-INST: vlsseg3e8.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 b5 4a <unknown>
 
+vlsseg3e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 48 <unknown>
+
 vlsseg3e16.v v8, (a0), a1
 # CHECK-INST: vlsseg3e16.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x54,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 b5 4a <unknown>
 
+vlsseg3e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 48 <unknown>
+
 vlsseg3e32.v v8, (a0), a1
 # CHECK-INST: vlsseg3e32.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x64,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 b5 4a <unknown>
 
+vlsseg3e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 48 <unknown>
+
 vlsseg3e64.v v8, (a0), a1
 # CHECK-INST: vlsseg3e64.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x74,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 b5 4a <unknown>
 
+vlsseg3e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 58 <unknown>
+
 vlsseg3e128.v v8, (a0), a1
 # CHECK-INST: vlsseg3e128.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 b5 5a <unknown>
 
+vlsseg3e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 58 <unknown>
+
 vlsseg3e256.v v8, (a0), a1
 # CHECK-INST: vlsseg3e256.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x54,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 b5 5a <unknown>
 
+vlsseg3e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 58 <unknown>
+
 vlsseg3e512.v v8, (a0), a1
 # CHECK-INST: vlsseg3e512.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x64,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 b5 5a <unknown>
 
+vlsseg3e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 58 <unknown>
+
 vlsseg3e1024.v v8, (a0), a1
 # CHECK-INST: vlsseg3e1024.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x74,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 b5 5a <unknown>
 
-vlsseg3e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 48 <unknown>
-
-vlsseg3e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 48 <unknown>
-
-vlsseg3e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 48 <unknown>
+vluxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 44 <unknown>
+
+vluxseg3ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 46 <unknown>
+
+vluxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 44 <unknown>
+
+vluxseg3ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 46 <unknown>
+
+vluxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 44 <unknown>
+
+vluxseg3ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 46 <unknown>
+
+vluxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 44 <unknown>
+
+vluxseg3ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg3ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 46 <unknown>
 
-vlsseg3e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 48 <unknown>
+vloxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 4c <unknown>
 
-vlsseg3e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 58 <unknown>
+vloxseg3ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 4e <unknown>
 
-vlsseg3e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 58 <unknown>
+vloxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 4c <unknown>
 
-vlsseg3e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 58 <unknown>
+vloxseg3ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 4e <unknown>
 
-vlsseg3e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg3e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 58 <unknown>
+vloxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 4c <unknown>
 
-vlsseg4e8.v v8, (a0), a1
-# CHECK-INST: vlsseg4e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 6a <unknown>
+vloxseg3ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 4e <unknown>
 
-vlsseg4e16.v v8, (a0), a1
-# CHECK-INST: vlsseg4e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 6a <unknown>
+vloxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 4c <unknown>
 
-vlsseg4e32.v v8, (a0), a1
-# CHECK-INST: vlsseg4e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 6a <unknown>
+vloxseg3ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg3ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 4e <unknown>
 
-vlsseg4e64.v v8, (a0), a1
-# CHECK-INST: vlsseg4e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 6a <unknown>
+vlseg4e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 60 <unknown>
 
-vlsseg4e128.v v8, (a0), a1
-# CHECK-INST: vlsseg4e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 7a <unknown>
+vlseg4e8.v v8, (a0)
+# CHECK-INST: vlseg4e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 62 <unknown>
 
-vlsseg4e256.v v8, (a0), a1
-# CHECK-INST: vlsseg4e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 7a <unknown>
+vlseg4e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 60 <unknown>
 
-vlsseg4e512.v v8, (a0), a1
-# CHECK-INST: vlsseg4e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 7a <unknown>
+vlseg4e16.v v8, (a0)
+# CHECK-INST: vlseg4e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 62 <unknown>
 
-vlsseg4e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg4e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 7a <unknown>
+vlseg4e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 60 <unknown>
 
-vlsseg4e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 68 <unknown>
+vlseg4e32.v v8, (a0)
+# CHECK-INST: vlseg4e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 62 <unknown>
 
-vlsseg4e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 68 <unknown>
+vlseg4e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 60 <unknown>
 
-vlsseg4e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 68 <unknown>
+vlseg4e64.v v8, (a0)
+# CHECK-INST: vlseg4e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 62 <unknown>
 
-vlsseg4e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 68 <unknown>
+vlseg4e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 70 <unknown>
 
-vlsseg4e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 78 <unknown>
+vlseg4e128.v v8, (a0)
+# CHECK-INST: vlseg4e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 72 <unknown>
 
-vlsseg4e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 78 <unknown>
+vlseg4e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 70 <unknown>
 
-vlsseg4e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 78 <unknown>
+vlseg4e256.v v8, (a0)
+# CHECK-INST: vlseg4e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 72 <unknown>
 
-vlsseg4e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg4e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 78 <unknown>
+vlseg4e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 70 <unknown>
 
-vlsseg5e8.v v8, (a0), a1
-# CHECK-INST: vlsseg5e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 8a <unknown>
+vlseg4e512.v v8, (a0)
+# CHECK-INST: vlseg4e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 72 <unknown>
 
-vlsseg5e16.v v8, (a0), a1
-# CHECK-INST: vlsseg5e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 8a <unknown>
+vlseg4e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 70 <unknown>
 
-vlsseg5e32.v v8, (a0), a1
-# CHECK-INST: vlsseg5e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 8a <unknown>
+vlseg4e1024.v v8, (a0)
+# CHECK-INST: vlseg4e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 72 <unknown>
 
-vlsseg5e64.v v8, (a0), a1
-# CHECK-INST: vlsseg5e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 8a <unknown>
+vlseg4e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 61 <unknown>
 
-vlsseg5e128.v v8, (a0), a1
-# CHECK-INST: vlsseg5e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 9a <unknown>
+vlseg4e8ff.v v8, (a0)
+# CHECK-INST: vlseg4e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 63 <unknown>
 
-vlsseg5e256.v v8, (a0), a1
-# CHECK-INST: vlsseg5e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 9a <unknown>
+vlseg4e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 61 <unknown>
 
-vlsseg5e512.v v8, (a0), a1
-# CHECK-INST: vlsseg5e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 9a <unknown>
+vlseg4e16ff.v v8, (a0)
+# CHECK-INST: vlseg4e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 63 <unknown>
 
-vlsseg5e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg5e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 9a <unknown>
+vlseg4e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 61 <unknown>
 
-vlsseg5e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 88 <unknown>
+vlseg4e32ff.v v8, (a0)
+# CHECK-INST: vlseg4e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 63 <unknown>
 
-vlsseg5e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 88 <unknown>
+vlseg4e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 61 <unknown>
 
-vlsseg5e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 88 <unknown>
+vlseg4e64ff.v v8, (a0)
+# CHECK-INST: vlseg4e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 63 <unknown>
 
-vlsseg5e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 88 <unknown>
+vlseg4e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 71 <unknown>
 
-vlsseg5e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 98 <unknown>
+vlseg4e128ff.v v8, (a0)
+# CHECK-INST: vlseg4e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 73 <unknown>
 
-vlsseg5e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 98 <unknown>
+vlseg4e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 71 <unknown>
 
-vlsseg5e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 98 <unknown>
+vlseg4e256ff.v v8, (a0)
+# CHECK-INST: vlseg4e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 73 <unknown>
 
-vlsseg5e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg5e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 98 <unknown>
+vlseg4e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 71 <unknown>
 
-vlsseg6e8.v v8, (a0), a1
-# CHECK-INST: vlsseg6e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 aa <unknown>
+vlseg4e512ff.v v8, (a0)
+# CHECK-INST: vlseg4e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 73 <unknown>
 
-vlsseg6e16.v v8, (a0), a1
-# CHECK-INST: vlsseg6e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 aa <unknown>
+vlseg4e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 71 <unknown>
 
-vlsseg6e32.v v8, (a0), a1
-# CHECK-INST: vlsseg6e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 aa <unknown>
+vlseg4e1024ff.v v8, (a0)
+# CHECK-INST: vlseg4e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 73 <unknown>
 
-vlsseg6e64.v v8, (a0), a1
-# CHECK-INST: vlsseg6e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 aa <unknown>
+vlsseg4e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 68 <unknown>
 
-vlsseg6e128.v v8, (a0), a1
-# CHECK-INST: vlsseg6e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 ba <unknown>
+vlsseg4e8.v v8, (a0), a1
+# CHECK-INST: vlsseg4e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 6a <unknown>
 
-vlsseg6e256.v v8, (a0), a1
-# CHECK-INST: vlsseg6e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 ba <unknown>
+vlsseg4e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 68 <unknown>
 
-vlsseg6e512.v v8, (a0), a1
-# CHECK-INST: vlsseg6e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 ba <unknown>
+vlsseg4e16.v v8, (a0), a1
+# CHECK-INST: vlsseg4e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 6a <unknown>
 
-vlsseg6e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg6e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 ba <unknown>
+vlsseg4e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 68 <unknown>
 
-vlsseg6e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 a8 <unknown>
+vlsseg4e32.v v8, (a0), a1
+# CHECK-INST: vlsseg4e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 6a <unknown>
 
-vlsseg6e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 a8 <unknown>
+vlsseg4e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 68 <unknown>
 
-vlsseg6e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 a8 <unknown>
+vlsseg4e64.v v8, (a0), a1
+# CHECK-INST: vlsseg4e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 6a <unknown>
 
-vlsseg6e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 a8 <unknown>
+vlsseg4e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 78 <unknown>
 
-vlsseg6e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 b8 <unknown>
+vlsseg4e128.v v8, (a0), a1
+# CHECK-INST: vlsseg4e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 7a <unknown>
 
-vlsseg6e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 b8 <unknown>
+vlsseg4e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 78 <unknown>
 
-vlsseg6e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 b8 <unknown>
+vlsseg4e256.v v8, (a0), a1
+# CHECK-INST: vlsseg4e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 7a <unknown>
 
-vlsseg6e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg6e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 b8 <unknown>
+vlsseg4e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 78 <unknown>
 
-vlsseg7e8.v v8, (a0), a1
-# CHECK-INST: vlsseg7e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 ca <unknown>
+vlsseg4e512.v v8, (a0), a1
+# CHECK-INST: vlsseg4e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 7a <unknown>
 
-vlsseg7e16.v v8, (a0), a1
-# CHECK-INST: vlsseg7e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 ca <unknown>
+vlsseg4e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 78 <unknown>
 
-vlsseg7e32.v v8, (a0), a1
-# CHECK-INST: vlsseg7e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 ca <unknown>
+vlsseg4e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg4e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 7a <unknown>
 
-vlsseg7e64.v v8, (a0), a1
-# CHECK-INST: vlsseg7e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 ca <unknown>
+vluxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 64 <unknown>
+
+vluxseg4ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 66 <unknown>
+
+vluxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 64 <unknown>
+
+vluxseg4ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 66 <unknown>
+
+vluxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 64 <unknown>
+
+vluxseg4ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 66 <unknown>
+
+vluxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 64 <unknown>
+
+vluxseg4ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg4ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 66 <unknown>
 
-vlsseg7e128.v v8, (a0), a1
-# CHECK-INST: vlsseg7e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 da <unknown>
+vloxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 6c <unknown>
 
-vlsseg7e256.v v8, (a0), a1
-# CHECK-INST: vlsseg7e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 da <unknown>
+vloxseg4ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 6e <unknown>
 
-vlsseg7e512.v v8, (a0), a1
-# CHECK-INST: vlsseg7e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 da <unknown>
+vloxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 6c <unknown>
 
-vlsseg7e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg7e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 da <unknown>
+vloxseg4ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 6e <unknown>
 
-vlsseg7e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 c8 <unknown>
+vloxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 6c <unknown>
 
-vlsseg7e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 c8 <unknown>
+vloxseg4ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 6e <unknown>
 
-vlsseg7e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 c8 <unknown>
+vloxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 6c <unknown>
 
-vlsseg7e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 c8 <unknown>
+vloxseg4ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg4ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 6e <unknown>
 
-vlsseg7e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 d8 <unknown>
+vlseg5e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 80 <unknown>
 
-vlsseg7e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 d8 <unknown>
+vlseg5e8.v v8, (a0)
+# CHECK-INST: vlseg5e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 82 <unknown>
 
-vlsseg7e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 d8 <unknown>
+vlseg5e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 80 <unknown>
 
-vlsseg7e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg7e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 d8 <unknown>
+vlseg5e16.v v8, (a0)
+# CHECK-INST: vlseg5e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 82 <unknown>
 
-vlsseg8e8.v v8, (a0), a1
-# CHECK-INST: vlsseg8e8.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 ea <unknown>
+vlseg5e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 80 <unknown>
 
-vlsseg8e16.v v8, (a0), a1
-# CHECK-INST: vlsseg8e16.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 ea <unknown>
+vlseg5e32.v v8, (a0)
+# CHECK-INST: vlseg5e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 82 <unknown>
 
-vlsseg8e32.v v8, (a0), a1
-# CHECK-INST: vlsseg8e32.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 ea <unknown>
+vlseg5e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 80 <unknown>
 
-vlsseg8e64.v v8, (a0), a1
-# CHECK-INST: vlsseg8e64.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 ea <unknown>
+vlseg5e64.v v8, (a0)
+# CHECK-INST: vlseg5e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 82 <unknown>
 
-vlsseg8e128.v v8, (a0), a1
-# CHECK-INST: vlsseg8e128.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 fa <unknown>
+vlseg5e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 90 <unknown>
 
-vlsseg8e256.v v8, (a0), a1
-# CHECK-INST: vlsseg8e256.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 fa <unknown>
+vlseg5e128.v v8, (a0)
+# CHECK-INST: vlseg5e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 92 <unknown>
 
-vlsseg8e512.v v8, (a0), a1
-# CHECK-INST: vlsseg8e512.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 fa <unknown>
+vlseg5e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 90 <unknown>
 
-vlsseg8e1024.v v8, (a0), a1
-# CHECK-INST: vlsseg8e1024.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 fa <unknown>
+vlseg5e256.v v8, (a0)
+# CHECK-INST: vlseg5e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 92 <unknown>
 
-vlsseg8e8.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 e8 <unknown>
+vlseg5e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 90 <unknown>
 
-vlsseg8e16.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 e8 <unknown>
+vlseg5e512.v v8, (a0)
+# CHECK-INST: vlseg5e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 92 <unknown>
 
-vlsseg8e32.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 e8 <unknown>
+vlseg5e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 90 <unknown>
 
-vlsseg8e64.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 e8 <unknown>
+vlseg5e1024.v v8, (a0)
+# CHECK-INST: vlseg5e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 92 <unknown>
 
-vlsseg8e128.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e128.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 b5 f8 <unknown>
+vlseg5e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 81 <unknown>
 
-vlsseg8e256.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e256.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 b5 f8 <unknown>
+vlseg5e8ff.v v8, (a0)
+# CHECK-INST: vlseg5e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 83 <unknown>
 
-vlsseg8e512.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e512.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 b5 f8 <unknown>
+vlseg5e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 81 <unknown>
 
-vlsseg8e1024.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsseg8e1024.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x74,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 b5 f8 <unknown>
+vlseg5e16ff.v v8, (a0)
+# CHECK-INST: vlseg5e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 83 <unknown>
 
-vlxseg2ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 2e <unknown>
+vlseg5e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 81 <unknown>
 
-vlxseg2ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 2e <unknown>
+vlseg5e32ff.v v8, (a0)
+# CHECK-INST: vlseg5e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 83 <unknown>
 
-vlxseg2ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 2e <unknown>
+vlseg5e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 81 <unknown>
 
-vlxseg2ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 2e <unknown>
+vlseg5e64ff.v v8, (a0)
+# CHECK-INST: vlseg5e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 83 <unknown>
 
-vlxseg2ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 3e <unknown>
-
-vlxseg2ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 3e <unknown>
-
-vlxseg2ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 3e <unknown>
-
-vlxseg2ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 3e <unknown>
+vlseg5e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 91 <unknown>
 
-vlxseg2ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 2c <unknown>
+vlseg5e128ff.v v8, (a0)
+# CHECK-INST: vlseg5e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 93 <unknown>
 
-vlxseg2ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 2c <unknown>
+vlseg5e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 91 <unknown>
 
-vlxseg2ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 2c <unknown>
+vlseg5e256ff.v v8, (a0)
+# CHECK-INST: vlseg5e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 93 <unknown>
 
-vlxseg2ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 2c <unknown>
+vlseg5e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 91 <unknown>
 
-vlxseg2ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 3c <unknown>
-
-vlxseg2ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 3c <unknown>
-
-vlxseg2ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 3c <unknown>
-
-vlxseg2ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 3c <unknown>
+vlseg5e512ff.v v8, (a0)
+# CHECK-INST: vlseg5e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 93 <unknown>
 
-vlxseg3ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 4e <unknown>
+vlseg5e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 91 <unknown>
 
-vlxseg3ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 4e <unknown>
+vlseg5e1024ff.v v8, (a0)
+# CHECK-INST: vlseg5e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 93 <unknown>
 
-vlxseg3ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 4e <unknown>
+vlsseg5e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 88 <unknown>
 
-vlxseg3ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 4e <unknown>
+vlsseg5e8.v v8, (a0), a1
+# CHECK-INST: vlsseg5e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 8a <unknown>
 
-vlxseg3ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 5e <unknown>
-
-vlxseg3ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 5e <unknown>
-
-vlxseg3ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 5e <unknown>
-
-vlxseg3ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 5e <unknown>
+vlsseg5e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 88 <unknown>
 
-vlxseg3ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 4c <unknown>
+vlsseg5e16.v v8, (a0), a1
+# CHECK-INST: vlsseg5e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 8a <unknown>
 
-vlxseg3ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 4c <unknown>
+vlsseg5e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 88 <unknown>
 
-vlxseg3ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 4c <unknown>
+vlsseg5e32.v v8, (a0), a1
+# CHECK-INST: vlsseg5e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 8a <unknown>
 
-vlxseg3ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 4c <unknown>
+vlsseg5e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 88 <unknown>
 
-vlxseg3ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 5c <unknown>
-
-vlxseg3ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 5c <unknown>
-
-vlxseg3ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 5c <unknown>
-
-vlxseg3ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 5c <unknown>
+vlsseg5e64.v v8, (a0), a1
+# CHECK-INST: vlsseg5e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 8a <unknown>
 
-vlxseg4ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 6e <unknown>
+vlsseg5e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 98 <unknown>
 
-vlxseg4ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 6e <unknown>
+vlsseg5e128.v v8, (a0), a1
+# CHECK-INST: vlsseg5e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 9a <unknown>
 
-vlxseg4ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 6e <unknown>
+vlsseg5e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 98 <unknown>
 
-vlxseg4ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 6e <unknown>
+vlsseg5e256.v v8, (a0), a1
+# CHECK-INST: vlsseg5e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 9a <unknown>
 
-vlxseg4ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 7e <unknown>
-
-vlxseg4ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 7e <unknown>
-
-vlxseg4ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 7e <unknown>
-
-vlxseg4ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 7e <unknown>
+vlsseg5e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 98 <unknown>
 
-vlxseg4ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 6c <unknown>
+vlsseg5e512.v v8, (a0), a1
+# CHECK-INST: vlsseg5e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 9a <unknown>
 
-vlxseg4ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 6c <unknown>
+vlsseg5e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 98 <unknown>
 
-vlxseg4ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 6c <unknown>
+vlsseg5e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg5e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 9a <unknown>
 
-vlxseg4ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 6c <unknown>
+vluxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 84 <unknown>
+
+vluxseg5ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 86 <unknown>
+
+vluxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 84 <unknown>
+
+vluxseg5ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 86 <unknown>
+
+vluxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 84 <unknown>
+
+vluxseg5ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 86 <unknown>
+
+vluxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 84 <unknown>
+
+vluxseg5ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg5ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 86 <unknown>
 
-vlxseg4ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 7c <unknown>
-
-vlxseg4ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 7c <unknown>
-
-vlxseg4ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 7c <unknown>
-
-vlxseg4ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 7c <unknown>
+vloxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 8c <unknown>
 
-vlxseg5ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei8.v v8, (a0), v4
+vloxseg5ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei8.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x04,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 45 8e <unknown>
 
-vlxseg5ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei16.v v8, (a0), v4
+vloxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 8c <unknown>
+
+vloxseg5ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei16.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x54,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 45 8e <unknown>
 
-vlxseg5ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei32.v v8, (a0), v4
+vloxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 8c <unknown>
+
+vloxseg5ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei32.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x64,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 45 8e <unknown>
 
-vlxseg5ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei64.v v8, (a0), v4
+vloxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 8c <unknown>
+
+vloxseg5ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg5ei64.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x74,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 45 8e <unknown>
 
-vlxseg5ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 9e <unknown>
-
-vlxseg5ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 9e <unknown>
-
-vlxseg5ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 9e <unknown>
-
-vlxseg5ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 9e <unknown>
-
-vlxseg5ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 8c <unknown>
+vlseg6e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 a0 <unknown>
 
-vlxseg5ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 8c <unknown>
+vlseg6e8.v v8, (a0)
+# CHECK-INST: vlseg6e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 a2 <unknown>
 
-vlxseg5ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 8c <unknown>
+vlseg6e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 a0 <unknown>
 
-vlxseg5ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 8c <unknown>
+vlseg6e16.v v8, (a0)
+# CHECK-INST: vlseg6e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 a2 <unknown>
 
-vlxseg5ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 9c <unknown>
-
-vlxseg5ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 9c <unknown>
-
-vlxseg5ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 9c <unknown>
-
-vlxseg5ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 9c <unknown>
+vlseg6e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 a0 <unknown>
 
-vlxseg6ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ae <unknown>
+vlseg6e32.v v8, (a0)
+# CHECK-INST: vlseg6e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 a2 <unknown>
 
-vlxseg6ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ae <unknown>
+vlseg6e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 a0 <unknown>
 
-vlxseg6ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ae <unknown>
+vlseg6e64.v v8, (a0)
+# CHECK-INST: vlseg6e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 a2 <unknown>
 
-vlxseg6ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ae <unknown>
+vlseg6e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 b0 <unknown>
 
-vlxseg6ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 be <unknown>
-
-vlxseg6ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 be <unknown>
-
-vlxseg6ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 be <unknown>
-
-vlxseg6ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 be <unknown>
+vlseg6e128.v v8, (a0)
+# CHECK-INST: vlseg6e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 b2 <unknown>
 
-vlxseg6ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ac <unknown>
+vlseg6e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 b0 <unknown>
 
-vlxseg6ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ac <unknown>
+vlseg6e256.v v8, (a0)
+# CHECK-INST: vlseg6e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 b2 <unknown>
 
-vlxseg6ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ac <unknown>
+vlseg6e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 b0 <unknown>
 
-vlxseg6ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ac <unknown>
+vlseg6e512.v v8, (a0)
+# CHECK-INST: vlseg6e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 b2 <unknown>
 
-vlxseg6ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 bc <unknown>
-
-vlxseg6ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 bc <unknown>
-
-vlxseg6ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 bc <unknown>
-
-vlxseg6ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 bc <unknown>
+vlseg6e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 b0 <unknown>
 
-vlxseg7ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ce <unknown>
+vlseg6e1024.v v8, (a0)
+# CHECK-INST: vlseg6e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 b2 <unknown>
 
-vlxseg7ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ce <unknown>
+vlseg6e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 a1 <unknown>
 
-vlxseg7ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ce <unknown>
+vlseg6e8ff.v v8, (a0)
+# CHECK-INST: vlseg6e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 a3 <unknown>
 
-vlxseg7ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ce <unknown>
+vlseg6e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 a1 <unknown>
 
-vlxseg7ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 de <unknown>
-
-vlxseg7ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 de <unknown>
-
-vlxseg7ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 de <unknown>
-
-vlxseg7ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 de <unknown>
+vlseg6e16ff.v v8, (a0)
+# CHECK-INST: vlseg6e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 a3 <unknown>
 
-vlxseg7ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 cc <unknown>
+vlseg6e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 a1 <unknown>
 
-vlxseg7ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 cc <unknown>
+vlseg6e32ff.v v8, (a0)
+# CHECK-INST: vlseg6e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 a3 <unknown>
 
-vlxseg7ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 cc <unknown>
+vlseg6e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 a1 <unknown>
 
-vlxseg7ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 cc <unknown>
+vlseg6e64ff.v v8, (a0)
+# CHECK-INST: vlseg6e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 a3 <unknown>
 
-vlxseg7ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 dc <unknown>
-
-vlxseg7ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 dc <unknown>
-
-vlxseg7ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 dc <unknown>
-
-vlxseg7ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 dc <unknown>
+vlseg6e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 b1 <unknown>
 
-vlxseg8ei8.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei8.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ee <unknown>
+vlseg6e128ff.v v8, (a0)
+# CHECK-INST: vlseg6e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 b3 <unknown>
 
-vlxseg8ei16.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei16.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ee <unknown>
+vlseg6e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 b1 <unknown>
 
-vlxseg8ei32.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei32.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ee <unknown>
+vlseg6e256ff.v v8, (a0)
+# CHECK-INST: vlseg6e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 b3 <unknown>
 
-vlxseg8ei64.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei64.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ee <unknown>
+vlseg6e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 b1 <unknown>
 
-vlxseg8ei128.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei128.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 fe <unknown>
-
-vlxseg8ei256.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei256.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 fe <unknown>
-
-vlxseg8ei512.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei512.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 fe <unknown>
-
-vlxseg8ei1024.v v8, (a0), v4
-# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x74,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 fe <unknown>
+vlseg6e512ff.v v8, (a0)
+# CHECK-INST: vlseg6e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 b3 <unknown>
 
-vlxseg8ei8.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei8.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 ec <unknown>
+vlseg6e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 b1 <unknown>
 
-vlxseg8ei16.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei16.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 ec <unknown>
+vlseg6e1024ff.v v8, (a0)
+# CHECK-INST: vlseg6e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 b3 <unknown>
 
-vlxseg8ei32.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei32.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 ec <unknown>
+vlsseg6e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 a8 <unknown>
 
-vlxseg8ei64.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei64.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 ec <unknown>
+vlsseg6e8.v v8, (a0), a1
+# CHECK-INST: vlsseg6e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 aa <unknown>
 
-vlxseg8ei128.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei128.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 45 fc <unknown>
-
-vlxseg8ei256.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei256.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 45 fc <unknown>
-
-vlxseg8ei512.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei512.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 45 fc <unknown>
-
-vlxseg8ei1024.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x74,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 45 fc <unknown>
+vlsseg6e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 a8 <unknown>
 
-vlseg2e8ff.v v8, (a0)
-# CHECK-INST: vlseg2e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 23 <unknown>
+vlsseg6e16.v v8, (a0), a1
+# CHECK-INST: vlsseg6e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 aa <unknown>
 
-vlseg2e16ff.v v8, (a0)
-# CHECK-INST: vlseg2e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 23 <unknown>
+vlsseg6e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 a8 <unknown>
 
-vlseg2e32ff.v v8, (a0)
-# CHECK-INST: vlseg2e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 23 <unknown>
+vlsseg6e32.v v8, (a0), a1
+# CHECK-INST: vlsseg6e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 aa <unknown>
 
-vlseg2e64ff.v v8, (a0)
-# CHECK-INST: vlseg2e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 23 <unknown>
+vlsseg6e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 a8 <unknown>
 
-vlseg2e128ff.v v8, (a0)
-# CHECK-INST: vlseg2e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 33 <unknown>
+vlsseg6e64.v v8, (a0), a1
+# CHECK-INST: vlsseg6e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 aa <unknown>
 
-vlseg2e256ff.v v8, (a0)
-# CHECK-INST: vlseg2e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 33 <unknown>
+vlsseg6e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 b8 <unknown>
 
-vlseg2e512ff.v v8, (a0)
-# CHECK-INST: vlseg2e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 33 <unknown>
+vlsseg6e128.v v8, (a0), a1
+# CHECK-INST: vlsseg6e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 ba <unknown>
 
-vlseg2e1024ff.v v8, (a0)
-# CHECK-INST: vlseg2e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x33]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 33 <unknown>
+vlsseg6e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 b8 <unknown>
 
-vlseg2e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 21 <unknown>
+vlsseg6e256.v v8, (a0), a1
+# CHECK-INST: vlsseg6e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 ba <unknown>
 
-vlseg2e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 21 <unknown>
+vlsseg6e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 b8 <unknown>
 
-vlseg2e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 21 <unknown>
+vlsseg6e512.v v8, (a0), a1
+# CHECK-INST: vlsseg6e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 ba <unknown>
 
-vlseg2e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 21 <unknown>
+vlsseg6e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 b8 <unknown>
 
-vlseg2e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 31 <unknown>
+vlsseg6e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg6e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 ba <unknown>
 
-vlseg2e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 31 <unknown>
+vluxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 a4 <unknown>
+
+vluxseg6ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 a6 <unknown>
+
+vluxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 a4 <unknown>
+
+vluxseg6ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 a6 <unknown>
+
+vluxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 a4 <unknown>
+
+vluxseg6ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 a6 <unknown>
+
+vluxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 a4 <unknown>
+
+vluxseg6ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg6ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 a6 <unknown>
 
-vlseg2e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 31 <unknown>
+vloxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ac <unknown>
 
-vlseg2e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg2e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x31]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 31 <unknown>
+vloxseg6ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ae <unknown>
 
-vlseg3e8ff.v v8, (a0)
-# CHECK-INST: vlseg3e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 43 <unknown>
+vloxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ac <unknown>
 
-vlseg3e16ff.v v8, (a0)
-# CHECK-INST: vlseg3e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 43 <unknown>
+vloxseg6ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ae <unknown>
 
-vlseg3e32ff.v v8, (a0)
-# CHECK-INST: vlseg3e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 43 <unknown>
+vloxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ac <unknown>
 
-vlseg3e64ff.v v8, (a0)
-# CHECK-INST: vlseg3e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 43 <unknown>
+vloxseg6ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ae <unknown>
 
-vlseg3e128ff.v v8, (a0)
-# CHECK-INST: vlseg3e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 53 <unknown>
+vloxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ac <unknown>
 
-vlseg3e256ff.v v8, (a0)
-# CHECK-INST: vlseg3e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 53 <unknown>
+vloxseg6ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg6ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ae <unknown>
 
-vlseg3e512ff.v v8, (a0)
-# CHECK-INST: vlseg3e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 53 <unknown>
+vlseg7e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 c0 <unknown>
 
-vlseg3e1024ff.v v8, (a0)
-# CHECK-INST: vlseg3e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x53]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 53 <unknown>
+vlseg7e8.v v8, (a0)
+# CHECK-INST: vlseg7e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 c2 <unknown>
 
-vlseg3e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 41 <unknown>
+vlseg7e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 c0 <unknown>
 
-vlseg3e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 41 <unknown>
+vlseg7e16.v v8, (a0)
+# CHECK-INST: vlseg7e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 c2 <unknown>
 
-vlseg3e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 41 <unknown>
+vlseg7e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 c0 <unknown>
 
-vlseg3e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 41 <unknown>
+vlseg7e32.v v8, (a0)
+# CHECK-INST: vlseg7e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 c2 <unknown>
 
-vlseg3e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 51 <unknown>
+vlseg7e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 c0 <unknown>
 
-vlseg3e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 51 <unknown>
+vlseg7e64.v v8, (a0)
+# CHECK-INST: vlseg7e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 c2 <unknown>
 
-vlseg3e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 51 <unknown>
+vlseg7e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 d0 <unknown>
 
-vlseg3e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg3e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x51]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 51 <unknown>
+vlseg7e128.v v8, (a0)
+# CHECK-INST: vlseg7e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 d2 <unknown>
 
-vlseg4e8ff.v v8, (a0)
-# CHECK-INST: vlseg4e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 63 <unknown>
+vlseg7e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 d0 <unknown>
 
-vlseg4e16ff.v v8, (a0)
-# CHECK-INST: vlseg4e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 63 <unknown>
+vlseg7e256.v v8, (a0)
+# CHECK-INST: vlseg7e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 d2 <unknown>
 
-vlseg4e32ff.v v8, (a0)
-# CHECK-INST: vlseg4e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 63 <unknown>
+vlseg7e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d0 <unknown>
 
-vlseg4e64ff.v v8, (a0)
-# CHECK-INST: vlseg4e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 63 <unknown>
+vlseg7e512.v v8, (a0)
+# CHECK-INST: vlseg7e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d2 <unknown>
 
-vlseg4e128ff.v v8, (a0)
-# CHECK-INST: vlseg4e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 73 <unknown>
+vlseg7e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d0 <unknown>
 
-vlseg4e256ff.v v8, (a0)
-# CHECK-INST: vlseg4e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 73 <unknown>
+vlseg7e1024.v v8, (a0)
+# CHECK-INST: vlseg7e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d2 <unknown>
 
-vlseg4e512ff.v v8, (a0)
-# CHECK-INST: vlseg4e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 73 <unknown>
+vlseg7e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 c1 <unknown>
 
-vlseg4e1024ff.v v8, (a0)
-# CHECK-INST: vlseg4e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x73]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 73 <unknown>
+vlseg7e8ff.v v8, (a0)
+# CHECK-INST: vlseg7e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 c3 <unknown>
 
-vlseg4e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 61 <unknown>
+vlseg7e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 c1 <unknown>
 
-vlseg4e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 61 <unknown>
+vlseg7e16ff.v v8, (a0)
+# CHECK-INST: vlseg7e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 c3 <unknown>
 
-vlseg4e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 61 <unknown>
+vlseg7e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 c1 <unknown>
 
-vlseg4e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 61 <unknown>
+vlseg7e32ff.v v8, (a0)
+# CHECK-INST: vlseg7e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 c3 <unknown>
 
-vlseg4e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 71 <unknown>
+vlseg7e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 c1 <unknown>
 
-vlseg4e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 71 <unknown>
+vlseg7e64ff.v v8, (a0)
+# CHECK-INST: vlseg7e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 c3 <unknown>
 
-vlseg4e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 71 <unknown>
+vlseg7e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 d1 <unknown>
 
-vlseg4e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg4e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x71]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 71 <unknown>
+vlseg7e128ff.v v8, (a0)
+# CHECK-INST: vlseg7e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 d3 <unknown>
 
-vlseg5e8ff.v v8, (a0)
-# CHECK-INST: vlseg5e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 83 <unknown>
+vlseg7e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 d1 <unknown>
 
-vlseg5e16ff.v v8, (a0)
-# CHECK-INST: vlseg5e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 83 <unknown>
+vlseg7e256ff.v v8, (a0)
+# CHECK-INST: vlseg7e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 d3 <unknown>
 
-vlseg5e32ff.v v8, (a0)
-# CHECK-INST: vlseg5e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 83 <unknown>
+vlseg7e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d1 <unknown>
 
-vlseg5e64ff.v v8, (a0)
-# CHECK-INST: vlseg5e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 83 <unknown>
+vlseg7e512ff.v v8, (a0)
+# CHECK-INST: vlseg7e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 d3 <unknown>
 
-vlseg5e128ff.v v8, (a0)
-# CHECK-INST: vlseg5e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 93 <unknown>
+vlseg7e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d1 <unknown>
 
-vlseg5e256ff.v v8, (a0)
-# CHECK-INST: vlseg5e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 93 <unknown>
+vlseg7e1024ff.v v8, (a0)
+# CHECK-INST: vlseg7e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 d3 <unknown>
 
-vlseg5e512ff.v v8, (a0)
-# CHECK-INST: vlseg5e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 93 <unknown>
+vlsseg7e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 c8 <unknown>
 
-vlseg5e1024ff.v v8, (a0)
-# CHECK-INST: vlseg5e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0x93]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 93 <unknown>
+vlsseg7e8.v v8, (a0), a1
+# CHECK-INST: vlsseg7e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 ca <unknown>
 
-vlseg5e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 81 <unknown>
+vlsseg7e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 c8 <unknown>
 
-vlseg5e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 81 <unknown>
+vlsseg7e16.v v8, (a0), a1
+# CHECK-INST: vlsseg7e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 ca <unknown>
 
-vlseg5e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 81 <unknown>
+vlsseg7e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 c8 <unknown>
 
-vlseg5e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 81 <unknown>
+vlsseg7e32.v v8, (a0), a1
+# CHECK-INST: vlsseg7e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 ca <unknown>
 
-vlseg5e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 91 <unknown>
+vlsseg7e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 c8 <unknown>
 
-vlseg5e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 91 <unknown>
+vlsseg7e64.v v8, (a0), a1
+# CHECK-INST: vlsseg7e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 ca <unknown>
 
-vlseg5e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 91 <unknown>
+vlsseg7e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 d8 <unknown>
 
-vlseg5e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg5e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0x91]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 91 <unknown>
+vlsseg7e128.v v8, (a0), a1
+# CHECK-INST: vlsseg7e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 da <unknown>
 
-vlseg6e8ff.v v8, (a0)
-# CHECK-INST: vlseg6e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 a3 <unknown>
+vlsseg7e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 d8 <unknown>
 
-vlseg6e16ff.v v8, (a0)
-# CHECK-INST: vlseg6e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 a3 <unknown>
+vlsseg7e256.v v8, (a0), a1
+# CHECK-INST: vlsseg7e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 da <unknown>
 
-vlseg6e32ff.v v8, (a0)
-# CHECK-INST: vlseg6e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 a3 <unknown>
+vlsseg7e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 d8 <unknown>
 
-vlseg6e64ff.v v8, (a0)
-# CHECK-INST: vlseg6e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 a3 <unknown>
+vlsseg7e512.v v8, (a0), a1
+# CHECK-INST: vlsseg7e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 da <unknown>
 
-vlseg6e128ff.v v8, (a0)
-# CHECK-INST: vlseg6e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 b3 <unknown>
+vlsseg7e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 d8 <unknown>
 
-vlseg6e256ff.v v8, (a0)
-# CHECK-INST: vlseg6e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 b3 <unknown>
+vlsseg7e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg7e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 da <unknown>
 
-vlseg6e512ff.v v8, (a0)
-# CHECK-INST: vlseg6e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 b3 <unknown>
+vluxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 c4 <unknown>
+
+vluxseg7ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 c6 <unknown>
+
+vluxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 c4 <unknown>
+
+vluxseg7ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 c6 <unknown>
+
+vluxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 c4 <unknown>
+
+vluxseg7ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 c6 <unknown>
+
+vluxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 c4 <unknown>
+
+vluxseg7ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg7ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 c6 <unknown>
 
-vlseg6e1024ff.v v8, (a0)
-# CHECK-INST: vlseg6e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xb3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 b3 <unknown>
+vloxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 cc <unknown>
 
-vlseg6e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 a1 <unknown>
+vloxseg7ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ce <unknown>
 
-vlseg6e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 a1 <unknown>
+vloxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 cc <unknown>
 
-vlseg6e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 a1 <unknown>
+vloxseg7ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ce <unknown>
 
-vlseg6e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 a1 <unknown>
+vloxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 cc <unknown>
 
-vlseg6e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 b1 <unknown>
+vloxseg7ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ce <unknown>
 
-vlseg6e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 b1 <unknown>
+vloxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 cc <unknown>
 
-vlseg6e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 b1 <unknown>
+vloxseg7ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg7ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ce <unknown>
 
-vlseg6e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg6e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xb1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 b1 <unknown>
+vlseg8e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 e0 <unknown>
 
-vlseg7e8ff.v v8, (a0)
-# CHECK-INST: vlseg7e8ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 c3 <unknown>
+vlseg8e8.v v8, (a0)
+# CHECK-INST: vlseg8e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 e2 <unknown>
 
-vlseg7e16ff.v v8, (a0)
-# CHECK-INST: vlseg7e16ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 c3 <unknown>
+vlseg8e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 e0 <unknown>
 
-vlseg7e32ff.v v8, (a0)
-# CHECK-INST: vlseg7e32ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 c3 <unknown>
+vlseg8e16.v v8, (a0)
+# CHECK-INST: vlseg8e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 e2 <unknown>
 
-vlseg7e64ff.v v8, (a0)
-# CHECK-INST: vlseg7e64ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 c3 <unknown>
+vlseg8e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 e0 <unknown>
 
-vlseg7e128ff.v v8, (a0)
-# CHECK-INST: vlseg7e128ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 d3 <unknown>
+vlseg8e32.v v8, (a0)
+# CHECK-INST: vlseg8e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 e2 <unknown>
 
-vlseg7e256ff.v v8, (a0)
-# CHECK-INST: vlseg7e256ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 d3 <unknown>
+vlseg8e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 e0 <unknown>
 
-vlseg7e512ff.v v8, (a0)
-# CHECK-INST: vlseg7e512ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d3 <unknown>
+vlseg8e64.v v8, (a0)
+# CHECK-INST: vlseg8e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 e2 <unknown>
 
-vlseg7e1024ff.v v8, (a0)
-# CHECK-INST: vlseg7e1024ff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d3 <unknown>
+vlseg8e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 f0 <unknown>
 
-vlseg7e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 c1 <unknown>
+vlseg8e128.v v8, (a0)
+# CHECK-INST: vlseg8e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 f2 <unknown>
 
-vlseg7e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 c1 <unknown>
+vlseg8e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 f0 <unknown>
 
-vlseg7e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 c1 <unknown>
+vlseg8e256.v v8, (a0)
+# CHECK-INST: vlseg8e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 f2 <unknown>
 
-vlseg7e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 c1 <unknown>
+vlseg8e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 f0 <unknown>
 
-vlseg7e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 d1 <unknown>
+vlseg8e512.v v8, (a0)
+# CHECK-INST: vlseg8e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 f2 <unknown>
 
-vlseg7e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 d1 <unknown>
+vlseg8e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 f0 <unknown>
 
-vlseg7e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 d1 <unknown>
+vlseg8e1024.v v8, (a0)
+# CHECK-INST: vlseg8e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 f2 <unknown>
 
-vlseg7e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg7e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xd1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 d1 <unknown>
+vlseg8e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 e1 <unknown>
 
 vlseg8e8ff.v v8, (a0)
 # CHECK-INST: vlseg8e8ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 e3 <unknown>
 
+vlseg8e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 e1 <unknown>
+
 vlseg8e16ff.v v8, (a0)
 # CHECK-INST: vlseg8e16ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 e3 <unknown>
 
+vlseg8e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 e1 <unknown>
+
 vlseg8e32ff.v v8, (a0)
 # CHECK-INST: vlseg8e32ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 e3 <unknown>
 
+vlseg8e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 e1 <unknown>
+
 vlseg8e64ff.v v8, (a0)
 # CHECK-INST: vlseg8e64ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 e3 <unknown>
 
+vlseg8e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 05 f1 <unknown>
+
 vlseg8e128ff.v v8, (a0)
 # CHECK-INST: vlseg8e128ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 04 05 f3 <unknown>
 
+vlseg8e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 05 f1 <unknown>
+
 vlseg8e256ff.v v8, (a0)
 # CHECK-INST: vlseg8e256ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 54 05 f3 <unknown>
 
+vlseg8e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 05 f1 <unknown>
+
 vlseg8e512ff.v v8, (a0)
 # CHECK-INST: vlseg8e512ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 64 05 f3 <unknown>
 
+vlseg8e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 05 f1 <unknown>
+
 vlseg8e1024ff.v v8, (a0)
 # CHECK-INST: vlseg8e1024ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0xf3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 07 74 05 f3 <unknown>
 
-vlseg8e8ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 e1 <unknown>
+vlsseg8e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 e8 <unknown>
 
-vlseg8e16ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 e1 <unknown>
+vlsseg8e8.v v8, (a0), a1
+# CHECK-INST: vlsseg8e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 ea <unknown>
 
-vlseg8e32ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 e1 <unknown>
+vlsseg8e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 e8 <unknown>
 
-vlseg8e64ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 e1 <unknown>
+vlsseg8e16.v v8, (a0), a1
+# CHECK-INST: vlsseg8e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 ea <unknown>
 
-vlseg8e128ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e128ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 04 05 f1 <unknown>
+vlsseg8e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 e8 <unknown>
 
-vlseg8e256ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e256ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 54 05 f1 <unknown>
+vlsseg8e32.v v8, (a0), a1
+# CHECK-INST: vlsseg8e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 ea <unknown>
 
-vlseg8e512ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e512ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 64 05 f1 <unknown>
+vlsseg8e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 e8 <unknown>
 
-vlseg8e1024ff.v v8, (a0), v0.t
-# CHECK-INST: vlseg8e1024ff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x74,0x05,0xf1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 07 74 05 f1 <unknown>
+vlsseg8e64.v v8, (a0), a1
+# CHECK-INST: vlsseg8e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 ea <unknown>
 
-vsseg2e8.v v24, (a0)
-# CHECK-INST: vsseg2e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 22 <unknown>
+vlsseg8e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 f8 <unknown>
 
-vsseg2e16.v v24, (a0)
-# CHECK-INST: vsseg2e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 22 <unknown>
+vlsseg8e128.v v8, (a0), a1
+# CHECK-INST: vlsseg8e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 b5 fa <unknown>
 
-vsseg2e32.v v24, (a0)
-# CHECK-INST: vsseg2e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 22 <unknown>
+vlsseg8e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 f8 <unknown>
 
-vsseg2e64.v v24, (a0)
-# CHECK-INST: vsseg2e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 22 <unknown>
+vlsseg8e256.v v8, (a0), a1
+# CHECK-INST: vlsseg8e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 b5 fa <unknown>
 
-vsseg2e128.v v24, (a0)
-# CHECK-INST: vsseg2e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 32 <unknown>
+vlsseg8e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 f8 <unknown>
 
-vsseg2e256.v v24, (a0)
-# CHECK-INST: vsseg2e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 32 <unknown>
+vlsseg8e512.v v8, (a0), a1
+# CHECK-INST: vlsseg8e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 b5 fa <unknown>
 
-vsseg2e512.v v24, (a0)
-# CHECK-INST: vsseg2e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 32 <unknown>
+vlsseg8e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 f8 <unknown>
 
-vsseg2e1024.v v24, (a0)
-# CHECK-INST: vsseg2e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 32 <unknown>
+vlsseg8e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg8e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 b5 fa <unknown>
+
+vluxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 e4 <unknown>
+
+vluxseg8ei8.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 e6 <unknown>
+
+vluxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 e4 <unknown>
+
+vluxseg8ei16.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 e6 <unknown>
+
+vluxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 e4 <unknown>
+
+vluxseg8ei32.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 e6 <unknown>
+
+vluxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vluxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 e4 <unknown>
+
+vluxseg8ei64.v v8, (a0), v4
+# CHECK-INST: vluxseg8ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 e6 <unknown>
+
+vloxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ec <unknown>
+
+vloxseg8ei8.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 04 45 ee <unknown>
+
+vloxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ec <unknown>
+
+vloxseg8ei16.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 54 45 ee <unknown>
+
+vloxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ec <unknown>
+
+vloxseg8ei32.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 64 45 ee <unknown>
+
+vloxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vloxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ec <unknown>
+
+vloxseg8ei64.v v8, (a0), v4
+# CHECK-INST: vloxseg8ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 07 74 45 ee <unknown>
 
 vsseg2e8.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c 05 20 <unknown>
 
+vsseg2e8.v v24, (a0)
+# CHECK-INST: vsseg2e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 22 <unknown>
+
 vsseg2e16.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e16.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c 05 20 <unknown>
 
+vsseg2e16.v v24, (a0)
+# CHECK-INST: vsseg2e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 22 <unknown>
+
 vsseg2e32.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e32.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c 05 20 <unknown>
 
+vsseg2e32.v v24, (a0)
+# CHECK-INST: vsseg2e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 22 <unknown>
+
 vsseg2e64.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e64.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c 05 20 <unknown>
 
+vsseg2e64.v v24, (a0)
+# CHECK-INST: vsseg2e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 22 <unknown>
+
 vsseg2e128.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e128.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c 05 30 <unknown>
 
+vsseg2e128.v v24, (a0)
+# CHECK-INST: vsseg2e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 32 <unknown>
+
 vsseg2e256.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e256.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c 05 30 <unknown>
 
+vsseg2e256.v v24, (a0)
+# CHECK-INST: vsseg2e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 32 <unknown>
+
 vsseg2e512.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e512.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c 05 30 <unknown>
 
+vsseg2e512.v v24, (a0)
+# CHECK-INST: vsseg2e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 32 <unknown>
+
 vsseg2e1024.v v24, (a0), v0.t
 # CHECK-INST: vsseg2e1024.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x05,0x30]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c 05 30 <unknown>
 
-vsseg3e8.v v24, (a0)
-# CHECK-INST: vsseg3e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 42 <unknown>
-
-vsseg3e16.v v24, (a0)
-# CHECK-INST: vsseg3e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 42 <unknown>
-
-vsseg3e32.v v24, (a0)
-# CHECK-INST: vsseg3e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 42 <unknown>
-
-vsseg3e64.v v24, (a0)
-# CHECK-INST: vsseg3e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 42 <unknown>
-
-vsseg3e128.v v24, (a0)
-# CHECK-INST: vsseg3e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 52 <unknown>
-
-vsseg3e256.v v24, (a0)
-# CHECK-INST: vsseg3e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 52 <unknown>
-
-vsseg3e512.v v24, (a0)
-# CHECK-INST: vsseg3e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 52 <unknown>
-
-vsseg3e1024.v v24, (a0)
-# CHECK-INST: vsseg3e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x52]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 52 <unknown>
-
-vsseg3e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 40 <unknown>
-
-vsseg3e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 40 <unknown>
-
-vsseg3e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 40 <unknown>
-
-vsseg3e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 40 <unknown>
-
-vsseg3e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 50 <unknown>
-
-vsseg3e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 50 <unknown>
-
-vsseg3e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 50 <unknown>
-
-vsseg3e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg3e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 50 <unknown>
-
-vsseg4e8.v v24, (a0)
-# CHECK-INST: vsseg4e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 62 <unknown>
-
-vsseg4e16.v v24, (a0)
-# CHECK-INST: vsseg4e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 62 <unknown>
-
-vsseg4e32.v v24, (a0)
-# CHECK-INST: vsseg4e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 62 <unknown>
-
-vsseg4e64.v v24, (a0)
-# CHECK-INST: vsseg4e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 62 <unknown>
-
-vsseg4e128.v v24, (a0)
-# CHECK-INST: vsseg4e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 72 <unknown>
-
-vsseg4e256.v v24, (a0)
-# CHECK-INST: vsseg4e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 72 <unknown>
-
-vsseg4e512.v v24, (a0)
-# CHECK-INST: vsseg4e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 72 <unknown>
-
-vsseg4e1024.v v24, (a0)
-# CHECK-INST: vsseg4e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x72]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 72 <unknown>
-
-vsseg4e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 60 <unknown>
-
-vsseg4e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 60 <unknown>
-
-vsseg4e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 60 <unknown>
-
-vsseg4e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 60 <unknown>
-
-vsseg4e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 70 <unknown>
-
-vsseg4e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 70 <unknown>
-
-vsseg4e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 70 <unknown>
-
-vsseg4e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg4e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x70]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 70 <unknown>
-
-vsseg5e8.v v24, (a0)
-# CHECK-INST: vsseg5e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 82 <unknown>
-
-vsseg5e16.v v24, (a0)
-# CHECK-INST: vsseg5e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 82 <unknown>
-
-vsseg5e32.v v24, (a0)
-# CHECK-INST: vsseg5e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 82 <unknown>
-
-vsseg5e64.v v24, (a0)
-# CHECK-INST: vsseg5e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 82 <unknown>
-
-vsseg5e128.v v24, (a0)
-# CHECK-INST: vsseg5e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 92 <unknown>
-
-vsseg5e256.v v24, (a0)
-# CHECK-INST: vsseg5e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 92 <unknown>
-
-vsseg5e512.v v24, (a0)
-# CHECK-INST: vsseg5e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 92 <unknown>
-
-vsseg5e1024.v v24, (a0)
-# CHECK-INST: vsseg5e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x92]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 92 <unknown>
-
-vsseg5e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 80 <unknown>
-
-vsseg5e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 80 <unknown>
-
-vsseg5e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 80 <unknown>
-
-vsseg5e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 80 <unknown>
-
-vsseg5e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 90 <unknown>
-
-vsseg5e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 90 <unknown>
-
-vsseg5e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 90 <unknown>
-
-vsseg5e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg5e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0x90]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 90 <unknown>
-
-vsseg6e8.v v24, (a0)
-# CHECK-INST: vsseg6e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 a2 <unknown>
-
-vsseg6e16.v v24, (a0)
-# CHECK-INST: vsseg6e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 a2 <unknown>
-
-vsseg6e32.v v24, (a0)
-# CHECK-INST: vsseg6e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 a2 <unknown>
-
-vsseg6e64.v v24, (a0)
-# CHECK-INST: vsseg6e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 a2 <unknown>
-
-vsseg6e128.v v24, (a0)
-# CHECK-INST: vsseg6e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 b2 <unknown>
-
-vsseg6e256.v v24, (a0)
-# CHECK-INST: vsseg6e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 b2 <unknown>
-
-vsseg6e512.v v24, (a0)
-# CHECK-INST: vsseg6e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 b2 <unknown>
-
-vsseg6e1024.v v24, (a0)
-# CHECK-INST: vsseg6e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xb2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 b2 <unknown>
-
-vsseg6e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 a0 <unknown>
-
-vsseg6e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 a0 <unknown>
-
-vsseg6e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 a0 <unknown>
-
-vsseg6e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 a0 <unknown>
-
-vsseg6e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 b0 <unknown>
-
-vsseg6e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 b0 <unknown>
-
-vsseg6e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 b0 <unknown>
-
-vsseg6e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg6e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xb0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 b0 <unknown>
-
-vsseg7e8.v v24, (a0)
-# CHECK-INST: vsseg7e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 c2 <unknown>
-
-vsseg7e16.v v24, (a0)
-# CHECK-INST: vsseg7e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 c2 <unknown>
-
-vsseg7e32.v v24, (a0)
-# CHECK-INST: vsseg7e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 c2 <unknown>
-
-vsseg7e64.v v24, (a0)
-# CHECK-INST: vsseg7e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 c2 <unknown>
-
-vsseg7e128.v v24, (a0)
-# CHECK-INST: vsseg7e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 d2 <unknown>
-
-vsseg7e256.v v24, (a0)
-# CHECK-INST: vsseg7e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 d2 <unknown>
-
-vsseg7e512.v v24, (a0)
-# CHECK-INST: vsseg7e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 d2 <unknown>
-
-vsseg7e1024.v v24, (a0)
-# CHECK-INST: vsseg7e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xd2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 d2 <unknown>
-
-vsseg7e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 c0 <unknown>
-
-vsseg7e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 c0 <unknown>
-
-vsseg7e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 c0 <unknown>
-
-vsseg7e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 c0 <unknown>
-
-vsseg7e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 d0 <unknown>
-
-vsseg7e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 d0 <unknown>
-
-vsseg7e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 d0 <unknown>
-
-vsseg7e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg7e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xd0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 d0 <unknown>
-
-vsseg8e8.v v24, (a0)
-# CHECK-INST: vsseg8e8.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 e2 <unknown>
-
-vsseg8e16.v v24, (a0)
-# CHECK-INST: vsseg8e16.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 e2 <unknown>
-
-vsseg8e32.v v24, (a0)
-# CHECK-INST: vsseg8e32.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 e2 <unknown>
-
-vsseg8e64.v v24, (a0)
-# CHECK-INST: vsseg8e64.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 e2 <unknown>
-
-vsseg8e128.v v24, (a0)
-# CHECK-INST: vsseg8e128.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 f2 <unknown>
-
-vsseg8e256.v v24, (a0)
-# CHECK-INST: vsseg8e256.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 f2 <unknown>
-
-vsseg8e512.v v24, (a0)
-# CHECK-INST: vsseg8e512.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 f2 <unknown>
-
-vsseg8e1024.v v24, (a0)
-# CHECK-INST: vsseg8e1024.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xf2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 f2 <unknown>
-
-vsseg8e8.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e8.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 e0 <unknown>
-
-vsseg8e16.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e16.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 e0 <unknown>
-
-vsseg8e32.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e32.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 e0 <unknown>
-
-vsseg8e64.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e64.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 e0 <unknown>
-
-vsseg8e128.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e128.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 05 f0 <unknown>
-
-vsseg8e256.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e256.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 05 f0 <unknown>
-
-vsseg8e512.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e512.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 05 f0 <unknown>
+vsseg2e1024.v v24, (a0)
+# CHECK-INST: vsseg2e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 32 <unknown>
 
-vsseg8e1024.v v24, (a0), v0.t
-# CHECK-INST: vsseg8e1024.v v24, (a0), v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x05,0xf0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 05 f0 <unknown>
+vssseg2e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 28 <unknown>
 
 vssseg2e8.v v24, (a0), a1
 # CHECK-INST: vssseg2e8.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 2a <unknown>
 
+vssseg2e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 28 <unknown>
+
 vssseg2e16.v v24, (a0), a1
 # CHECK-INST: vssseg2e16.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 2a <unknown>
 
+vssseg2e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 28 <unknown>
+
 vssseg2e32.v v24, (a0), a1
 # CHECK-INST: vssseg2e32.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 2a <unknown>
 
+vssseg2e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 28 <unknown>
+
 vssseg2e64.v v24, (a0), a1
 # CHECK-INST: vssseg2e64.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 2a <unknown>
 
+vssseg2e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 38 <unknown>
+
 vssseg2e128.v v24, (a0), a1
 # CHECK-INST: vssseg2e128.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 3a <unknown>
 
+vssseg2e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 38 <unknown>
+
 vssseg2e256.v v24, (a0), a1
 # CHECK-INST: vssseg2e256.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 3a <unknown>
 
+vssseg2e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 38 <unknown>
+
 vssseg2e512.v v24, (a0), a1
 # CHECK-INST: vssseg2e512.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 3a <unknown>
 
+vssseg2e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 38 <unknown>
+
 vssseg2e1024.v v24, (a0), a1
 # CHECK-INST: vssseg2e1024.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x3a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 3a <unknown>
 
-vssseg2e8.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 28 <unknown>
+vsuxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 24 <unknown>
+
+vsuxseg2ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 26 <unknown>
+
+vsuxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 24 <unknown>
+
+vsuxseg2ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 26 <unknown>
+
+vsuxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 24 <unknown>
+
+vsuxseg2ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 26 <unknown>
+
+vsuxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 24 <unknown>
+
+vsuxseg2ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 26 <unknown>
 
-vssseg2e16.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 28 <unknown>
+vsoxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 2c <unknown>
 
-vssseg2e32.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 28 <unknown>
+vsoxseg2ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 2e <unknown>
 
-vssseg2e64.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 28 <unknown>
+vsoxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 2c <unknown>
 
-vssseg2e128.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e128.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 38 <unknown>
+vsoxseg2ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 2e <unknown>
 
-vssseg2e256.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e256.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 38 <unknown>
+vsoxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 2c <unknown>
 
-vssseg2e512.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e512.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 38 <unknown>
+vsoxseg2ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 2e <unknown>
 
-vssseg2e1024.v v24, (a0), a1, v0.t
-# CHECK-INST: vssseg2e1024.v v24, (a0), a1, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x38]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 38 <unknown>
+vsoxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 2c <unknown>
 
-vssseg3e8.v v24, (a0), a1
-# CHECK-INST: vssseg3e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 4a <unknown>
+vsoxseg2ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 2e <unknown>
 
-vssseg3e16.v v24, (a0), a1
-# CHECK-INST: vssseg3e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 4a <unknown>
+vsseg3e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 40 <unknown>
 
-vssseg3e32.v v24, (a0), a1
-# CHECK-INST: vssseg3e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 4a <unknown>
+vsseg3e8.v v24, (a0)
+# CHECK-INST: vsseg3e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 42 <unknown>
 
-vssseg3e64.v v24, (a0), a1
-# CHECK-INST: vssseg3e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 4a <unknown>
+vsseg3e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 40 <unknown>
 
-vssseg3e128.v v24, (a0), a1
-# CHECK-INST: vssseg3e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 5a <unknown>
+vsseg3e16.v v24, (a0)
+# CHECK-INST: vsseg3e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 42 <unknown>
 
-vssseg3e256.v v24, (a0), a1
-# CHECK-INST: vssseg3e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 5a <unknown>
+vsseg3e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 40 <unknown>
 
-vssseg3e512.v v24, (a0), a1
-# CHECK-INST: vssseg3e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 5a <unknown>
+vsseg3e32.v v24, (a0)
+# CHECK-INST: vsseg3e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 42 <unknown>
 
-vssseg3e1024.v v24, (a0), a1
-# CHECK-INST: vssseg3e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x5a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 5a <unknown>
+vsseg3e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 40 <unknown>
+
+vsseg3e64.v v24, (a0)
+# CHECK-INST: vsseg3e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 42 <unknown>
+
+vsseg3e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 50 <unknown>
+
+vsseg3e128.v v24, (a0)
+# CHECK-INST: vsseg3e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 52 <unknown>
+
+vsseg3e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 50 <unknown>
+
+vsseg3e256.v v24, (a0)
+# CHECK-INST: vsseg3e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 52 <unknown>
+
+vsseg3e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 50 <unknown>
+
+vsseg3e512.v v24, (a0)
+# CHECK-INST: vsseg3e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 52 <unknown>
+
+vsseg3e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 50 <unknown>
+
+vsseg3e1024.v v24, (a0)
+# CHECK-INST: vsseg3e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 52 <unknown>
 
 vssseg3e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 48 <unknown>
 
+vssseg3e8.v v24, (a0), a1
+# CHECK-INST: vssseg3e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 4a <unknown>
+
 vssseg3e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 48 <unknown>
 
+vssseg3e16.v v24, (a0), a1
+# CHECK-INST: vssseg3e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 4a <unknown>
+
 vssseg3e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 48 <unknown>
 
+vssseg3e32.v v24, (a0), a1
+# CHECK-INST: vssseg3e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 4a <unknown>
+
 vssseg3e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 48 <unknown>
 
+vssseg3e64.v v24, (a0), a1
+# CHECK-INST: vssseg3e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 4a <unknown>
+
 vssseg3e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 58 <unknown>
 
+vssseg3e128.v v24, (a0), a1
+# CHECK-INST: vssseg3e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 5a <unknown>
+
 vssseg3e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 58 <unknown>
 
+vssseg3e256.v v24, (a0), a1
+# CHECK-INST: vssseg3e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 5a <unknown>
+
 vssseg3e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 58 <unknown>
 
+vssseg3e512.v v24, (a0), a1
+# CHECK-INST: vssseg3e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 5a <unknown>
+
 vssseg3e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg3e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x58]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 58 <unknown>
 
-vssseg4e8.v v24, (a0), a1
-# CHECK-INST: vssseg4e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 6a <unknown>
+vssseg3e1024.v v24, (a0), a1
+# CHECK-INST: vssseg3e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 5a <unknown>
 
-vssseg4e16.v v24, (a0), a1
-# CHECK-INST: vssseg4e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 6a <unknown>
+vsuxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 44 <unknown>
+
+vsuxseg3ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 46 <unknown>
+
+vsuxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 44 <unknown>
+
+vsuxseg3ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 46 <unknown>
+
+vsuxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 44 <unknown>
+
+vsuxseg3ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 46 <unknown>
+
+vsuxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 44 <unknown>
+
+vsuxseg3ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 46 <unknown>
 
-vssseg4e32.v v24, (a0), a1
-# CHECK-INST: vssseg4e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 6a <unknown>
+vsoxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 4c <unknown>
 
-vssseg4e64.v v24, (a0), a1
-# CHECK-INST: vssseg4e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 6a <unknown>
+vsoxseg3ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 4e <unknown>
 
-vssseg4e128.v v24, (a0), a1
-# CHECK-INST: vssseg4e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 7a <unknown>
+vsoxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 4c <unknown>
 
-vssseg4e256.v v24, (a0), a1
-# CHECK-INST: vssseg4e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 7a <unknown>
+vsoxseg3ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 4e <unknown>
 
-vssseg4e512.v v24, (a0), a1
-# CHECK-INST: vssseg4e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 7a <unknown>
+vsoxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 4c <unknown>
 
-vssseg4e1024.v v24, (a0), a1
-# CHECK-INST: vssseg4e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x7a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 7a <unknown>
+vsoxseg3ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 4e <unknown>
+
+vsoxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 4c <unknown>
+
+vsoxseg3ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 4e <unknown>
+
+vsseg4e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 60 <unknown>
+
+vsseg4e8.v v24, (a0)
+# CHECK-INST: vsseg4e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 62 <unknown>
+
+vsseg4e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 60 <unknown>
+
+vsseg4e16.v v24, (a0)
+# CHECK-INST: vsseg4e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 62 <unknown>
+
+vsseg4e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 60 <unknown>
+
+vsseg4e32.v v24, (a0)
+# CHECK-INST: vsseg4e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 62 <unknown>
+
+vsseg4e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 60 <unknown>
+
+vsseg4e64.v v24, (a0)
+# CHECK-INST: vsseg4e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 62 <unknown>
+
+vsseg4e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 70 <unknown>
+
+vsseg4e128.v v24, (a0)
+# CHECK-INST: vsseg4e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 72 <unknown>
+
+vsseg4e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 70 <unknown>
+
+vsseg4e256.v v24, (a0)
+# CHECK-INST: vsseg4e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 72 <unknown>
+
+vsseg4e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 70 <unknown>
+
+vsseg4e512.v v24, (a0)
+# CHECK-INST: vsseg4e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 72 <unknown>
+
+vsseg4e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 70 <unknown>
+
+vsseg4e1024.v v24, (a0)
+# CHECK-INST: vsseg4e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 72 <unknown>
 
 vssseg4e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 68 <unknown>
 
+vssseg4e8.v v24, (a0), a1
+# CHECK-INST: vssseg4e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 6a <unknown>
+
 vssseg4e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 68 <unknown>
 
+vssseg4e16.v v24, (a0), a1
+# CHECK-INST: vssseg4e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 6a <unknown>
+
 vssseg4e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 68 <unknown>
 
+vssseg4e32.v v24, (a0), a1
+# CHECK-INST: vssseg4e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 6a <unknown>
+
 vssseg4e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 68 <unknown>
 
+vssseg4e64.v v24, (a0), a1
+# CHECK-INST: vssseg4e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 6a <unknown>
+
 vssseg4e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 78 <unknown>
 
+vssseg4e128.v v24, (a0), a1
+# CHECK-INST: vssseg4e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 7a <unknown>
+
 vssseg4e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 78 <unknown>
 
+vssseg4e256.v v24, (a0), a1
+# CHECK-INST: vssseg4e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 7a <unknown>
+
 vssseg4e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 78 <unknown>
 
+vssseg4e512.v v24, (a0), a1
+# CHECK-INST: vssseg4e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 7a <unknown>
+
 vssseg4e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg4e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x78]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 78 <unknown>
 
-vssseg5e8.v v24, (a0), a1
-# CHECK-INST: vssseg5e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 8a <unknown>
+vssseg4e1024.v v24, (a0), a1
+# CHECK-INST: vssseg4e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 7a <unknown>
 
-vssseg5e16.v v24, (a0), a1
-# CHECK-INST: vssseg5e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 8a <unknown>
+vsuxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 64 <unknown>
+
+vsuxseg4ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 66 <unknown>
+
+vsuxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 64 <unknown>
+
+vsuxseg4ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 66 <unknown>
+
+vsuxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 64 <unknown>
+
+vsuxseg4ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 66 <unknown>
+
+vsuxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 64 <unknown>
+
+vsuxseg4ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 66 <unknown>
 
-vssseg5e32.v v24, (a0), a1
-# CHECK-INST: vssseg5e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 8a <unknown>
+vsoxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 6c <unknown>
 
-vssseg5e64.v v24, (a0), a1
-# CHECK-INST: vssseg5e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 8a <unknown>
+vsoxseg4ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 6e <unknown>
 
-vssseg5e128.v v24, (a0), a1
-# CHECK-INST: vssseg5e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 9a <unknown>
+vsoxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 6c <unknown>
 
-vssseg5e256.v v24, (a0), a1
-# CHECK-INST: vssseg5e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 9a <unknown>
+vsoxseg4ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 6e <unknown>
 
-vssseg5e512.v v24, (a0), a1
-# CHECK-INST: vssseg5e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 9a <unknown>
+vsoxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 6c <unknown>
 
-vssseg5e1024.v v24, (a0), a1
-# CHECK-INST: vssseg5e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0x9a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 9a <unknown>
+vsoxseg4ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 6e <unknown>
+
+vsoxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 6c <unknown>
+
+vsoxseg4ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 6e <unknown>
+
+vsseg5e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 80 <unknown>
+
+vsseg5e8.v v24, (a0)
+# CHECK-INST: vsseg5e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 82 <unknown>
+
+vsseg5e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 80 <unknown>
+
+vsseg5e16.v v24, (a0)
+# CHECK-INST: vsseg5e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 82 <unknown>
+
+vsseg5e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 80 <unknown>
+
+vsseg5e32.v v24, (a0)
+# CHECK-INST: vsseg5e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 82 <unknown>
+
+vsseg5e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 80 <unknown>
+
+vsseg5e64.v v24, (a0)
+# CHECK-INST: vsseg5e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 82 <unknown>
+
+vsseg5e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 90 <unknown>
+
+vsseg5e128.v v24, (a0)
+# CHECK-INST: vsseg5e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 92 <unknown>
+
+vsseg5e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 90 <unknown>
+
+vsseg5e256.v v24, (a0)
+# CHECK-INST: vsseg5e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 92 <unknown>
+
+vsseg5e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 90 <unknown>
+
+vsseg5e512.v v24, (a0)
+# CHECK-INST: vsseg5e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 92 <unknown>
+
+vsseg5e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 90 <unknown>
+
+vsseg5e1024.v v24, (a0)
+# CHECK-INST: vsseg5e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 92 <unknown>
 
 vssseg5e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 88 <unknown>
 
+vssseg5e8.v v24, (a0), a1
+# CHECK-INST: vssseg5e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 8a <unknown>
+
 vssseg5e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 88 <unknown>
 
+vssseg5e16.v v24, (a0), a1
+# CHECK-INST: vssseg5e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 8a <unknown>
+
 vssseg5e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 88 <unknown>
 
+vssseg5e32.v v24, (a0), a1
+# CHECK-INST: vssseg5e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 8a <unknown>
+
 vssseg5e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 88 <unknown>
 
+vssseg5e64.v v24, (a0), a1
+# CHECK-INST: vssseg5e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 8a <unknown>
+
 vssseg5e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 98 <unknown>
 
+vssseg5e128.v v24, (a0), a1
+# CHECK-INST: vssseg5e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 9a <unknown>
+
 vssseg5e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 98 <unknown>
 
+vssseg5e256.v v24, (a0), a1
+# CHECK-INST: vssseg5e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 9a <unknown>
+
 vssseg5e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 98 <unknown>
 
+vssseg5e512.v v24, (a0), a1
+# CHECK-INST: vssseg5e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 9a <unknown>
+
 vssseg5e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg5e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x98]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 98 <unknown>
 
-vssseg6e8.v v24, (a0), a1
-# CHECK-INST: vssseg6e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 aa <unknown>
+vssseg5e1024.v v24, (a0), a1
+# CHECK-INST: vssseg5e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 9a <unknown>
 
-vssseg6e16.v v24, (a0), a1
-# CHECK-INST: vssseg6e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 aa <unknown>
+vsuxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 84 <unknown>
+
+vsuxseg5ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 86 <unknown>
+
+vsuxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 84 <unknown>
+
+vsuxseg5ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 86 <unknown>
+
+vsuxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 84 <unknown>
+
+vsuxseg5ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 86 <unknown>
+
+vsuxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 84 <unknown>
+
+vsuxseg5ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 86 <unknown>
 
-vssseg6e32.v v24, (a0), a1
-# CHECK-INST: vssseg6e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 aa <unknown>
+vsoxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 8c <unknown>
 
-vssseg6e64.v v24, (a0), a1
-# CHECK-INST: vssseg6e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 aa <unknown>
+vsoxseg5ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 8e <unknown>
 
-vssseg6e128.v v24, (a0), a1
-# CHECK-INST: vssseg6e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 ba <unknown>
+vsoxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 8c <unknown>
 
-vssseg6e256.v v24, (a0), a1
-# CHECK-INST: vssseg6e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 ba <unknown>
+vsoxseg5ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 8e <unknown>
 
-vssseg6e512.v v24, (a0), a1
-# CHECK-INST: vssseg6e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 ba <unknown>
+vsoxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 8c <unknown>
 
-vssseg6e1024.v v24, (a0), a1
-# CHECK-INST: vssseg6e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xba]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 ba <unknown>
+vsoxseg5ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 8e <unknown>
+
+vsoxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 8c <unknown>
+
+vsoxseg5ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 8e <unknown>
+
+vsseg6e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 a0 <unknown>
+
+vsseg6e8.v v24, (a0)
+# CHECK-INST: vsseg6e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 a2 <unknown>
+
+vsseg6e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 a0 <unknown>
+
+vsseg6e16.v v24, (a0)
+# CHECK-INST: vsseg6e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 a2 <unknown>
+
+vsseg6e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 a0 <unknown>
+
+vsseg6e32.v v24, (a0)
+# CHECK-INST: vsseg6e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 a2 <unknown>
+
+vsseg6e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 a0 <unknown>
+
+vsseg6e64.v v24, (a0)
+# CHECK-INST: vsseg6e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 a2 <unknown>
+
+vsseg6e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 b0 <unknown>
+
+vsseg6e128.v v24, (a0)
+# CHECK-INST: vsseg6e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 b2 <unknown>
+
+vsseg6e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 b0 <unknown>
+
+vsseg6e256.v v24, (a0)
+# CHECK-INST: vsseg6e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 b2 <unknown>
+
+vsseg6e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 b0 <unknown>
+
+vsseg6e512.v v24, (a0)
+# CHECK-INST: vsseg6e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 b2 <unknown>
+
+vsseg6e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 b0 <unknown>
+
+vsseg6e1024.v v24, (a0)
+# CHECK-INST: vsseg6e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 b2 <unknown>
 
 vssseg6e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 a8 <unknown>
 
+vssseg6e8.v v24, (a0), a1
+# CHECK-INST: vssseg6e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 aa <unknown>
+
 vssseg6e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 a8 <unknown>
 
+vssseg6e16.v v24, (a0), a1
+# CHECK-INST: vssseg6e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 aa <unknown>
+
 vssseg6e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 a8 <unknown>
 
+vssseg6e32.v v24, (a0), a1
+# CHECK-INST: vssseg6e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 aa <unknown>
+
 vssseg6e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 a8 <unknown>
 
+vssseg6e64.v v24, (a0), a1
+# CHECK-INST: vssseg6e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 aa <unknown>
+
 vssseg6e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 b8 <unknown>
 
+vssseg6e128.v v24, (a0), a1
+# CHECK-INST: vssseg6e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 ba <unknown>
+
 vssseg6e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 b8 <unknown>
 
+vssseg6e256.v v24, (a0), a1
+# CHECK-INST: vssseg6e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 ba <unknown>
+
 vssseg6e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 b8 <unknown>
 
+vssseg6e512.v v24, (a0), a1
+# CHECK-INST: vssseg6e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 ba <unknown>
+
 vssseg6e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg6e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xb8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 b8 <unknown>
 
-vssseg7e8.v v24, (a0), a1
-# CHECK-INST: vssseg7e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 ca <unknown>
+vssseg6e1024.v v24, (a0), a1
+# CHECK-INST: vssseg6e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 ba <unknown>
 
-vssseg7e16.v v24, (a0), a1
-# CHECK-INST: vssseg7e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 ca <unknown>
+vsuxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 a4 <unknown>
+
+vsuxseg6ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 a6 <unknown>
+
+vsuxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 a4 <unknown>
+
+vsuxseg6ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 a6 <unknown>
+
+vsuxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 a4 <unknown>
+
+vsuxseg6ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 a6 <unknown>
+
+vsuxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 a4 <unknown>
+
+vsuxseg6ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 a6 <unknown>
 
-vssseg7e32.v v24, (a0), a1
-# CHECK-INST: vssseg7e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 ca <unknown>
+vsoxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ac <unknown>
 
-vssseg7e64.v v24, (a0), a1
-# CHECK-INST: vssseg7e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 ca <unknown>
+vsoxseg6ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ae <unknown>
 
-vssseg7e128.v v24, (a0), a1
-# CHECK-INST: vssseg7e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 da <unknown>
+vsoxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ac <unknown>
 
-vssseg7e256.v v24, (a0), a1
-# CHECK-INST: vssseg7e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 da <unknown>
+vsoxseg6ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ae <unknown>
 
-vssseg7e512.v v24, (a0), a1
-# CHECK-INST: vssseg7e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 da <unknown>
+vsoxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ac <unknown>
 
-vssseg7e1024.v v24, (a0), a1
-# CHECK-INST: vssseg7e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xda]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 da <unknown>
+vsoxseg6ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ae <unknown>
+
+vsoxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ac <unknown>
+
+vsoxseg6ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ae <unknown>
+
+vsseg7e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 c0 <unknown>
+
+vsseg7e8.v v24, (a0)
+# CHECK-INST: vsseg7e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 c2 <unknown>
+
+vsseg7e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 c0 <unknown>
+
+vsseg7e16.v v24, (a0)
+# CHECK-INST: vsseg7e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 c2 <unknown>
+
+vsseg7e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 c0 <unknown>
+
+vsseg7e32.v v24, (a0)
+# CHECK-INST: vsseg7e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 c2 <unknown>
+
+vsseg7e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 c0 <unknown>
+
+vsseg7e64.v v24, (a0)
+# CHECK-INST: vsseg7e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 c2 <unknown>
+
+vsseg7e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 d0 <unknown>
+
+vsseg7e128.v v24, (a0)
+# CHECK-INST: vsseg7e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 d2 <unknown>
+
+vsseg7e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 d0 <unknown>
+
+vsseg7e256.v v24, (a0)
+# CHECK-INST: vsseg7e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 d2 <unknown>
+
+vsseg7e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 d0 <unknown>
+
+vsseg7e512.v v24, (a0)
+# CHECK-INST: vsseg7e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 d2 <unknown>
+
+vsseg7e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 d0 <unknown>
+
+vsseg7e1024.v v24, (a0)
+# CHECK-INST: vsseg7e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 d2 <unknown>
 
 vssseg7e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 c8 <unknown>
 
+vssseg7e8.v v24, (a0), a1
+# CHECK-INST: vssseg7e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 ca <unknown>
+
 vssseg7e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 c8 <unknown>
 
+vssseg7e16.v v24, (a0), a1
+# CHECK-INST: vssseg7e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 ca <unknown>
+
 vssseg7e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 c8 <unknown>
 
+vssseg7e32.v v24, (a0), a1
+# CHECK-INST: vssseg7e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 ca <unknown>
+
 vssseg7e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 c8 <unknown>
 
+vssseg7e64.v v24, (a0), a1
+# CHECK-INST: vssseg7e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 ca <unknown>
+
 vssseg7e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 d8 <unknown>
 
+vssseg7e128.v v24, (a0), a1
+# CHECK-INST: vssseg7e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 da <unknown>
+
 vssseg7e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 d8 <unknown>
 
+vssseg7e256.v v24, (a0), a1
+# CHECK-INST: vssseg7e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 da <unknown>
+
 vssseg7e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 d8 <unknown>
 
+vssseg7e512.v v24, (a0), a1
+# CHECK-INST: vssseg7e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 da <unknown>
+
 vssseg7e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg7e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xd8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 d8 <unknown>
 
-vssseg8e8.v v24, (a0), a1
-# CHECK-INST: vssseg8e8.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 ea <unknown>
+vssseg7e1024.v v24, (a0), a1
+# CHECK-INST: vssseg7e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 da <unknown>
 
-vssseg8e16.v v24, (a0), a1
-# CHECK-INST: vssseg8e16.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 ea <unknown>
+vsuxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 c4 <unknown>
+
+vsuxseg7ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 c6 <unknown>
+
+vsuxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 c4 <unknown>
+
+vsuxseg7ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 c6 <unknown>
+
+vsuxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 c4 <unknown>
+
+vsuxseg7ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 c6 <unknown>
+
+vsuxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 c4 <unknown>
+
+vsuxseg7ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 c6 <unknown>
 
-vssseg8e32.v v24, (a0), a1
-# CHECK-INST: vssseg8e32.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 ea <unknown>
+vsoxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 cc <unknown>
 
-vssseg8e64.v v24, (a0), a1
-# CHECK-INST: vssseg8e64.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 ea <unknown>
+vsoxseg7ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ce <unknown>
 
-vssseg8e128.v v24, (a0), a1
-# CHECK-INST: vssseg8e128.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c b5 fa <unknown>
+vsoxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 cc <unknown>
 
-vssseg8e256.v v24, (a0), a1
-# CHECK-INST: vssseg8e256.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x5c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c b5 fa <unknown>
+vsoxseg7ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ce <unknown>
 
-vssseg8e512.v v24, (a0), a1
-# CHECK-INST: vssseg8e512.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x6c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c b5 fa <unknown>
+vsoxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 cc <unknown>
 
-vssseg8e1024.v v24, (a0), a1
-# CHECK-INST: vssseg8e1024.v v24, (a0), a1
-# CHECK-ENCODING: [0x27,0x7c,0xb5,0xfa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c b5 fa <unknown>
+vsoxseg7ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ce <unknown>
+
+vsoxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 cc <unknown>
+
+vsoxseg7ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ce <unknown>
+
+vsseg8e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 e0 <unknown>
+
+vsseg8e8.v v24, (a0)
+# CHECK-INST: vsseg8e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 e2 <unknown>
+
+vsseg8e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 e0 <unknown>
+
+vsseg8e16.v v24, (a0)
+# CHECK-INST: vsseg8e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 e2 <unknown>
+
+vsseg8e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 e0 <unknown>
+
+vsseg8e32.v v24, (a0)
+# CHECK-INST: vsseg8e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 e2 <unknown>
+
+vsseg8e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 e0 <unknown>
+
+vsseg8e64.v v24, (a0)
+# CHECK-INST: vsseg8e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 e2 <unknown>
+
+vsseg8e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 f0 <unknown>
+
+vsseg8e128.v v24, (a0)
+# CHECK-INST: vsseg8e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 05 f2 <unknown>
+
+vsseg8e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 f0 <unknown>
+
+vsseg8e256.v v24, (a0)
+# CHECK-INST: vsseg8e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 05 f2 <unknown>
+
+vsseg8e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 f0 <unknown>
+
+vsseg8e512.v v24, (a0)
+# CHECK-INST: vsseg8e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 05 f2 <unknown>
+
+vsseg8e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 f0 <unknown>
+
+vsseg8e1024.v v24, (a0)
+# CHECK-INST: vsseg8e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 05 f2 <unknown>
 
 vssseg8e8.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 e8 <unknown>
 
+vssseg8e8.v v24, (a0), a1
+# CHECK-INST: vssseg8e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 ea <unknown>
+
 vssseg8e16.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 e8 <unknown>
 
+vssseg8e16.v v24, (a0), a1
+# CHECK-INST: vssseg8e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 ea <unknown>
+
 vssseg8e32.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 e8 <unknown>
 
+vssseg8e32.v v24, (a0), a1
+# CHECK-INST: vssseg8e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 ea <unknown>
+
 vssseg8e64.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 e8 <unknown>
 
+vssseg8e64.v v24, (a0), a1
+# CHECK-INST: vssseg8e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 ea <unknown>
+
 vssseg8e128.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e128.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c b5 f8 <unknown>
 
+vssseg8e128.v v24, (a0), a1
+# CHECK-INST: vssseg8e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c b5 fa <unknown>
+
 vssseg8e256.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e256.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c b5 f8 <unknown>
 
+vssseg8e256.v v24, (a0), a1
+# CHECK-INST: vssseg8e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c b5 fa <unknown>
+
 vssseg8e512.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e512.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c b5 f8 <unknown>
 
+vssseg8e512.v v24, (a0), a1
+# CHECK-INST: vssseg8e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c b5 fa <unknown>
+
 vssseg8e1024.v v24, (a0), a1, v0.t
 # CHECK-INST: vssseg8e1024.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xf8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c b5 f8 <unknown>
 
-vsxseg2ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 2e <unknown>
-
-vsxseg2ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 2e <unknown>
-
-vsxseg2ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 2e <unknown>
-
-vsxseg2ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 2e <unknown>
-
-vsxseg2ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 3e <unknown>
-
-vsxseg2ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 3e <unknown>
-
-vsxseg2ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 3e <unknown>
-
-vsxseg2ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x3e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 3e <unknown>
-
-vsxseg2ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 2c <unknown>
-
-vsxseg2ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 2c <unknown>
-
-vsxseg2ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 2c <unknown>
-
-vsxseg2ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 2c <unknown>
-
-vsxseg2ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 3c <unknown>
-
-vsxseg2ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 3c <unknown>
-
-vsxseg2ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 3c <unknown>
-
-vsxseg2ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x3c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 3c <unknown>
-
-vsxseg3ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 4e <unknown>
-
-vsxseg3ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 4e <unknown>
-
-vsxseg3ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 4e <unknown>
-
-vsxseg3ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 4e <unknown>
-
-vsxseg3ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 5e <unknown>
-
-vsxseg3ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 5e <unknown>
-
-vsxseg3ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 5e <unknown>
-
-vsxseg3ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x5e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 5e <unknown>
-
-vsxseg3ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 4c <unknown>
-
-vsxseg3ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 4c <unknown>
-
-vsxseg3ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 4c <unknown>
-
-vsxseg3ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 4c <unknown>
-
-vsxseg3ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 5c <unknown>
-
-vsxseg3ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 5c <unknown>
-
-vsxseg3ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 5c <unknown>
-
-vsxseg3ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x5c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 5c <unknown>
-
-vsxseg4ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 6e <unknown>
-
-vsxseg4ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 6e <unknown>
-
-vsxseg4ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 6e <unknown>
-
-vsxseg4ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 6e <unknown>
-
-vsxseg4ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 7e <unknown>
-
-vsxseg4ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 7e <unknown>
-
-vsxseg4ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 7e <unknown>
-
-vsxseg4ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x7e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 7e <unknown>
-
-vsxseg4ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 6c <unknown>
-
-vsxseg4ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 6c <unknown>
-
-vsxseg4ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 6c <unknown>
-
-vsxseg4ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 6c <unknown>
-
-vsxseg4ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 7c <unknown>
-
-vsxseg4ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 7c <unknown>
-
-vsxseg4ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 7c <unknown>
-
-vsxseg4ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x7c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 7c <unknown>
-
-vsxseg5ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 8e <unknown>
-
-vsxseg5ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 8e <unknown>
-
-vsxseg5ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 8e <unknown>
-
-vsxseg5ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 8e <unknown>
-
-vsxseg5ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 9e <unknown>
-
-vsxseg5ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 9e <unknown>
-
-vsxseg5ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 9e <unknown>
-
-vsxseg5ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 9e <unknown>
-
-vsxseg5ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 8c <unknown>
-
-vsxseg5ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 8c <unknown>
-
-vsxseg5ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 8c <unknown>
-
-vsxseg5ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 8c <unknown>
-
-vsxseg5ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 9c <unknown>
-
-vsxseg5ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 9c <unknown>
-
-vsxseg5ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 9c <unknown>
-
-vsxseg5ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 9c <unknown>
-
-vsxseg6ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ae <unknown>
-
-vsxseg6ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ae <unknown>
-
-vsxseg6ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ae <unknown>
-
-vsxseg6ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ae <unknown>
-
-vsxseg6ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 be <unknown>
-
-vsxseg6ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 be <unknown>
-
-vsxseg6ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 be <unknown>
-
-vsxseg6ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xbe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 be <unknown>
-
-vsxseg6ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ac <unknown>
-
-vsxseg6ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ac <unknown>
-
-vsxseg6ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ac <unknown>
-
-vsxseg6ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ac <unknown>
-
-vsxseg6ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 bc <unknown>
-
-vsxseg6ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 bc <unknown>
-
-vsxseg6ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 bc <unknown>
-
-vsxseg6ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xbc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 bc <unknown>
-
-vsxseg7ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei8.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ce <unknown>
-
-vsxseg7ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ce <unknown>
-
-vsxseg7ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ce <unknown>
-
-vsxseg7ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ce <unknown>
-
-vsxseg7ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 de <unknown>
-
-vsxseg7ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 de <unknown>
-
-vsxseg7ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 de <unknown>
-
-vsxseg7ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xde]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 de <unknown>
-
-vsxseg7ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 cc <unknown>
-
-vsxseg7ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei16.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 cc <unknown>
-
-vsxseg7ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei32.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 cc <unknown>
+vssseg8e1024.v v24, (a0), a1
+# CHECK-INST: vssseg8e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c b5 fa <unknown>
 
-vsxseg7ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei64.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 cc <unknown>
+vsuxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 e4 <unknown>
+
+vsuxseg8ei8.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 e6 <unknown>
+
+vsuxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 e4 <unknown>
+
+vsuxseg8ei16.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 e6 <unknown>
+
+vsuxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 e4 <unknown>
+
+vsuxseg8ei32.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 e6 <unknown>
+
+vsuxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 e4 <unknown>
+
+vsuxseg8ei64.v v24, (a0), v4
+# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 e6 <unknown>
 
-vsxseg7ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 dc <unknown>
-
-vsxseg7ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 dc <unknown>
-
-vsxseg7ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 dc <unknown>
-
-vsxseg7ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xdc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 dc <unknown>
+vsoxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 0c 45 ec <unknown>
 
-vsxseg8ei8.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei8.v v24, (a0), v4
+vsoxseg8ei8.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x0c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 0c 45 ee <unknown>
 
-vsxseg8ei16.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei16.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 ee <unknown>
-
-vsxseg8ei32.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei32.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 ee <unknown>
-
-vsxseg8ei64.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei64.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 ee <unknown>
-
-vsxseg8ei128.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei128.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 fe <unknown>
-
-vsxseg8ei256.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei256.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 fe <unknown>
-
-vsxseg8ei512.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei512.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 fe <unknown>
-
-vsxseg8ei1024.v v24, (a0), v4
-# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xfe]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 fe <unknown>
-
-vsxseg8ei8.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei8.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 ec <unknown>
-
-vsxseg8ei16.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei16.v v24, (a0), v4, v0.t
+vsoxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 5c 45 ec <unknown>
 
-vsxseg8ei32.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei32.v v24, (a0), v4, v0.t
+vsoxseg8ei16.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 5c 45 ee <unknown>
+
+vsoxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 6c 45 ec <unknown>
 
-vsxseg8ei64.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei64.v v24, (a0), v4, v0.t
+vsoxseg8ei32.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 6c 45 ee <unknown>
+
+vsoxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
 # CHECK-UNKNOWN: 27 7c 45 ec <unknown>
 
-vsxseg8ei128.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei128.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x0c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 0c 45 fc <unknown>
-
-vsxseg8ei256.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei256.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x5c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 5c 45 fc <unknown>
-
-vsxseg8ei512.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei512.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x6c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 6c 45 fc <unknown>
-
-vsxseg8ei1024.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4, v0.t
-# CHECK-ENCODING: [0x27,0x7c,0x45,0xfc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)
-# CHECK-UNKNOWN: 27 7c 45 fc <unknown>
+vsoxseg8ei64.v v24, (a0), v4
+# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-UNKNOWN: 27 7c 45 ee <unknown>