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[RISCV] Update V instructions constraints to conform to v1.0
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Authored by HsiangKai on Dec 20 2020, 11:21 PM.

Details

Summary

Upgrade RISC-V V extension to v1.0-08a0b46.
Update instruction constraints to conform to v1.0.

Diff Detail

Event Timeline

HsiangKai created this revision.Dec 20 2020, 11:21 PM
HsiangKai requested review of this revision.Dec 20 2020, 11:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 20 2020, 11:21 PM
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craig.topper added inline comments.Dec 21 2020, 4:25 PM
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
96 ↗(On Diff #313025)

Were we missing test coverage for the constraint removed here?

99 ↗(On Diff #313025)

Same here?

99 ↗(On Diff #313025)

Why wouldn't VMConstraint apply to SlideUp and Vrgather? I thought that was a general rule.

craig.topper added inline comments.Dec 23 2020, 2:36 PM
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
93 ↗(On Diff #313025)

These enum values aren't used. Just the ones in X86InstrFormats.td are used and now they aren't in sync.

HsiangKai updated this revision to Diff 313726.Dec 25 2020, 5:49 AM

Address @craig.topper's comments.

HsiangKai marked 4 inline comments as done.Dec 25 2020, 5:49 AM
This revision is now accepted and ready to land.Dec 27 2020, 8:58 PM
This revision was landed with ongoing or failed builds.Jan 21 2021, 9:16 AM
This revision was automatically updated to reflect the committed changes.