[X86] Fix variadic argument handling for x32

[hvdijk]

Summary

The X86-64 ABI defines va_list as

typedef struct {
  unsigned int gp_offset;
  unsigned int fp_offset;
  void *overflow_arg_area;
  void *reg_save_area;
} va_list[1];

This means the size, alignment, and reg_save_area offset will depend on
whether we are in LP64 or in ILP32 mode, so this commit adds the checks.
Additionally, the VAARG_64 pseudo-instruction assumed 64-bit pointers, so
this commit adds a VAARG_X32 pseudo-instruction that behaves just like
VAARG_64, except for assuming 32-bit pointers.

Some of these changes were originally done by
Michael Liao <[e-mail]>.

Fixes https://bugs.llvm.org/show_bug.cgi?id=48428.

[RKSimon]

Its OK to commit the asm.py / update_llc_test_checks.py changes right away to split them from the rest of this patch

llvm/lib/Target/X86/X86ISelLowering.cpp

31558

update comment

[hvdijk]

In D93160#2450356, @RKSimon wrote:

Its OK to commit the asm.py / update_llc_test_checks.py changes right away to split them from the rest of this patch

Thanks, done.

llvm/lib/Target/X86/X86ISelLowering.cpp

31558

This comment looks correct to me in its current form. I'm not sure if you mean to change va_arg or X86-64, but va_arg is the spelling that the LLVM IR instruction uses, and X86-64 includes both the LP64 and ILP32 ABIs. If I am missing something here, please let me know what.

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

31558

OK - I was thinking that maybe we should explicitly mention that we're trying to handle x32 here as well - but I agree it was rather pedantic!

[RKSimon]

rebase?

[hvdijk]

In D93160#2450846, @RKSimon wrote:

rebase?

Sure, rebased to take out the already applied update to UpdateTestChecks.

[RKSimon]

llvm/test/CodeGen/X86/x86-64-varargs.ll

1–3

Please can you regenerate + commit this test file with the no_x86_scrub_sp arg just to confirm theres no diff in the X64 codegen - then rebase adding the X32 run

[hvdijk]

Rebase again, taking the X64 changes out of the diff.

[hvdijk]

llvm/test/CodeGen/X86/x86-64-varargs.ll

1–3

Sure, done.

[RKSimon]

LGTM - cheers

llvm/lib/Target/X86/X86ISelLowering.h

enum NodeType : unsigned {
     FLD,
 
     /// This instruction implements a truncating store from FP stack
     /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
     /// chain operand, value to store, address, and glue. The memory VT
     /// specifies the type to store as.
     FST,
 
-    /// This instruction grabs the address of the next argument
+    /// These instructions grab the address of the next argument
     /// from a va_list. (reads and modifies the va_list in memory)
     VAARG_64,
+    VAARG_X32,
 
     // Vector truncating store with unsigned/signed saturation
     VTRUNCSTOREUS,
     VTRUNCSTORES,
     // Vector truncating masked store with unsigned/signed saturation
     VMTRUNCSTOREUS,
     VMTRUNCSTORES,
 
private:
 
     bool needsCmpXchgNb(Type *MemType) const;
 
     void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
                                 MachineBasicBlock *DispatchBB, int FI) const;
 
     // Utility function to emit the low-level va_arg code for X86-64.
     MachineBasicBlock *
-    EmitVAARG64WithCustomInserter(MachineInstr &MI,
-                                  MachineBasicBlock *MBB) const;
+    EmitVAARGWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
 
     /// Utility function to emit the xmm reg save portion of va_start.
     MachineBasicBlock *
     EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr,
                                              MachineBasicBlock *BB) const;
 
     MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
                                                  MachineInstr &MI2,

llvm/lib/Target/X86/X86ISelLowering.cpp

SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
 
   if (ArgMode == 2) {
     // Sanity Check: Make sure using fp_offset makes sense.
     assert(!Subtarget.useSoftFloat() &&
            !(MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat)) &&
            Subtarget.hasSSE1());
   }
 
-  // Insert VAARG_64 node into the DAG
-  // VAARG_64 returns two values: Variable Argument Address, Chain
+  // Insert VAARG node into the DAG
+  // VAARG returns two values: Variable Argument Address, Chain
   SDValue InstOps[] = {Chain, SrcPtr,
                        DAG.getTargetConstant(ArgSize, dl, MVT::i32),
                        DAG.getTargetConstant(ArgMode, dl, MVT::i8),
                        DAG.getTargetConstant(Align, dl, MVT::i32)};
   SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
   SDValue VAARG = DAG.getMemIntrinsicNode(
-      X86ISD::VAARG_64, dl, VTs, InstOps, MVT::i64, MachinePointerInfo(SV),
+      Subtarget.isTarget64BitLP64() ? X86ISD::VAARG_64 : X86ISD::VAARG_X32, dl,
+      VTs, InstOps, MVT::i64, MachinePointerInfo(SV),
       /*Alignment=*/None,
       MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
   Chain = VAARG.getValue(1);
 
   // Load the next argument and return it
   return DAG.getLoad(ArgVT, dl, Chain, VAARG, MachinePointerInfo());
 }
 
static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget,
 
   SDValue Chain = Op.getOperand(0);
   SDValue DstPtr = Op.getOperand(1);
   SDValue SrcPtr = Op.getOperand(2);
   const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
   const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
   SDLoc DL(Op);
 
-  return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(24, DL),
-                       Align(8), /*isVolatile*/ false, false, false,
-                       MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
+  return DAG.getMemcpy(
+      Chain, DL, DstPtr, SrcPtr,
+      DAG.getIntPtrConstant(Subtarget.isTarget64BitLP64() ? 24 : 16, DL),
+      Align(Subtarget.isTarget64BitLP64() ? 8 : 4), /*isVolatile*/ false, false,
+      false, MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
 }
 
 // Helper to get immediate/variable SSE shift opcode from other shift opcodes.
 static unsigned getTargetVShiftUniformOpcode(unsigned Opc, bool IsVariable) {
   switch (Opc) {
   case ISD::SHL:
   case X86ISD::VSHL:
   case X86ISD::VSHLI:
#define NODE_NAME_CASE(NODE) case X86ISD::NODE: return "X86ISD::" #NODE;
   NODE_NAME_CASE(VRANGES)
   NODE_NAME_CASE(VRANGES_SAE)
   NODE_NAME_CASE(PMULUDQ)
   NODE_NAME_CASE(PMULDQ)
   NODE_NAME_CASE(PSADBW)
   NODE_NAME_CASE(DBPSADBW)
   NODE_NAME_CASE(VASTART_SAVE_XMM_REGS)
   NODE_NAME_CASE(VAARG_64)
+  NODE_NAME_CASE(VAARG_X32)
   NODE_NAME_CASE(WIN_ALLOCA)
   NODE_NAME_CASE(MEMBARRIER)
   NODE_NAME_CASE(MFENCE)
   NODE_NAME_CASE(SEG_ALLOCA)
   NODE_NAME_CASE(PROBED_ALLOCA)
   NODE_NAME_CASE(RDRAND)
   NODE_NAME_CASE(RDSEED)
   NODE_NAME_CASE(RDPKRU)
static MachineBasicBlock *emitXBegin(MachineInstr &MI, MachineBasicBlock *MBB,
   BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI), DstReg)
       .addReg(mainDstReg).addMBB(mainMBB)
       .addReg(fallDstReg).addMBB(fallMBB);
 
   MI.eraseFromParent();
   return sinkMBB;
 }
 
-
-
 MachineBasicBlock *
-X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr &MI,
-                                                 MachineBasicBlock *MBB) const {
+X86TargetLowering::EmitVAARGWithCustomInserter(MachineInstr &MI,
   // Emit va_arg instruction on X86-64.
 
   // Operands to this pseudo-instruction:
   // 0  ) Output        : destination address (reg)
   // 1-5) Input         : va_list address (addr, i64mem)
   // 6  ) ArgSize       : Size (in bytes) of vararg type
   // 7  ) ArgMode       : 0=overflow only, 1=use gp_offset, 2=use fp_offset
   // 8  ) Align         : Alignment of type
   // 9  ) EFLAGS (implicit-def)
 
-  assert(MI.getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
-  static_assert(X86::AddrNumOperands == 5,
-                "VAARG_64 assumes 5 address operands");
+  assert(MI.getNumOperands() == 10 && "VAARG should have 10 operands!");
+  static_assert(X86::AddrNumOperands == 5, "VAARG assumes 5 address operands");
 
   Register DestReg = MI.getOperand(0).getReg();
   MachineOperand &Base = MI.getOperand(1);
   MachineOperand &Scale = MI.getOperand(2);
   MachineOperand &Index = MI.getOperand(3);
   MachineOperand &Disp = MI.getOperand(4);
   MachineOperand &Segment = MI.getOperand(5);
   unsigned ArgSize = MI.getOperand(6).getImm();
   unsigned ArgMode = MI.getOperand(7).getImm();
   Align Alignment = Align(MI.getOperand(8).getImm());
 
   MachineFunction *MF = MBB->getParent();
 
   // Memory Reference
-  assert(MI.hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
+  assert(MI.hasOneMemOperand() && "Expected VAARG to have one memoperand");
 
   MachineMemOperand *OldMMO = MI.memoperands().front();
 
   // Clone the MMO into two separate MMOs for loading and storing
   MachineMemOperand *LoadOnlyMMO = MF->getMachineMemOperand(
       OldMMO, OldMMO->getFlags() & ~MachineMemOperand::MOStore);
   MachineMemOperand *StoreOnlyMMO = MF->getMachineMemOperand(
       OldMMO, OldMMO->getFlags() & ~MachineMemOperand::MOLoad);
 
   // Machine Information
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
-  const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
+  const TargetRegisterClass *AddrRegClass =
+      getRegClassFor(getPointerTy(MBB->getParent()->getDataLayout()));
   const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
   const DebugLoc &DL = MI.getDebugLoc();
 
   // struct va_list {
   //   i32   gp_offset
   //   i32   fp_offset
   //   i64   overflow_area (address)
   //   i64   reg_save_area (address)
X86TargetLowering::EmitVAARGWithCustomInserter(MachineInstr &MI,
   }
 
   // In offsetMBB, emit code to use the reg_save_area.
   if (offsetMBB) {
     assert(OffsetReg != 0);
 
     // Read the reg_save_area address.
     Register RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
-    BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
+    BuildMI(
+        offsetMBB, DL,
+        TII->get(Subtarget.isTarget64BitLP64() ? X86::MOV64rm : X86::MOV32rm),
+        RegSaveReg)
         .add(Base)
         .add(Scale)
         .add(Index)
-        .addDisp(Disp, 16)
+        .addDisp(Disp, Subtarget.isTarget64BitLP64() ? 16 : 12)
         .add(Segment)
         .setMemRefs(LoadOnlyMMO);
 
+    if (Subtarget.isTarget64BitLP64()) {
       // Zero-extend the offset
       Register OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
       BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
           .addImm(0)
           .addReg(OffsetReg)
           .addImm(X86::sub_32bit);
 
       // Add the offset to the reg_save_area to get the final address.
       BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
           .addReg(OffsetReg64)
           .addReg(RegSaveReg);
+    } else {
+      // Add the offset to the reg_save_area to get the final address.
+      BuildMI(offsetMBB, DL, TII->get(X86::ADD32rr), OffsetDestReg)
+          .addReg(OffsetReg)
+          .addReg(RegSaveReg);
+    }
 
     // Compute the offset for the next argument
     Register NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
     BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
       .addReg(OffsetReg)
       .addImm(UseFPOffset ? 16 : 8);
 
     // Store it back into the va_list.
X86TargetLowering::EmitVAARGWithCustomInserter(MachineInstr &MI,
   }
 
   //
   // Emit code to use overflow area
   //
 
   // Load the overflow_area address into a register.
   Register OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
-  BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
+  BuildMI(overflowMBB, DL,
+          TII->get(Subtarget.isTarget64BitLP64() ? X86::MOV64rm : X86::MOV32rm),
+          OverflowAddrReg)
       .add(Base)
       .add(Scale)
       .add(Index)
       .addDisp(Disp, 8)
       .add(Segment)
       .setMemRefs(LoadOnlyMMO);
 
   // If we need to align it, do so. Otherwise, just copy the address
   // to OverflowDestReg.
   if (NeedsAlign) {
     // Align the overflow address
     Register TmpReg = MRI.createVirtualRegister(AddrRegClass);
 
     // aligned_addr = (addr + (align-1)) & ~(align-1)
-    BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
+    BuildMI(
+        overflowMBB, DL,
+        TII->get(Subtarget.isTarget64BitLP64() ? X86::ADD64ri32 : X86::ADD32ri),
+        TmpReg)
         .addReg(OverflowAddrReg)
         .addImm(Alignment.value() - 1);
 
-    BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
+    BuildMI(
+        overflowMBB, DL,
+        TII->get(Subtarget.isTarget64BitLP64() ? X86::AND64ri32 : X86::AND32ri),
+        OverflowDestReg)
         .addReg(TmpReg)
         .addImm(~(uint64_t)(Alignment.value() - 1));
   } else {
     BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
       .addReg(OverflowAddrReg);
   }
 
   // Compute the next overflow address after this argument.
   // (the overflow address should be kept 8-byte aligned)
   Register NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
-  BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
+  BuildMI(
+      overflowMBB, DL,
+      TII->get(Subtarget.isTarget64BitLP64() ? X86::ADD64ri32 : X86::ADD32ri),
+      NextAddrReg)
       .addReg(OverflowDestReg)
       .addImm(ArgSizeA8);
 
   // Store the new overflow address.
-  BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
+  BuildMI(overflowMBB, DL,
+          TII->get(Subtarget.isTarget64BitLP64() ? X86::MOV64mr : X86::MOV32mr))
       .add(Base)
       .add(Scale)
       .add(Index)
       .addDisp(Disp, 8)
       .add(Segment)
       .addReg(NextAddrReg)
       .setMemRefs(StoreOnlyMMO);
 
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   // xbegin
   case X86::XBEGIN:
     return emitXBegin(MI, BB, Subtarget.getInstrInfo());
 
   case X86::VASTART_SAVE_XMM_REGS:
     return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
 
   case X86::VAARG_64:
-    return EmitVAARG64WithCustomInserter(MI, BB);
+  case X86::VAARG_X32:
+    return EmitVAARGWithCustomInserter(MI, BB);
 
   case X86::EH_SjLj_SetJmp32:
   case X86::EH_SjLj_SetJmp64:
     return emitEHSjLjSetJmp(MI, BB);
 
   case X86::EH_SjLj_LongJmp32:
   case X86::EH_SjLj_LongJmp64:
     return emitEHSjLjLongJmp(MI, BB);

llvm/lib/Target/X86/X86InstrCompiler.td

def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
                                    i32imm:$regsavefi, i32imm:$offset,
                                    variable_ops),
                               "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
                               [(X86vastart_save_xmm_regs GR8:$al,
                                                          timm:$regsavefi,
                                                          timm:$offset),
                                (implicit EFLAGS)]>;
 
-// The VAARG_64 pseudo-instruction takes the address of the va_list,
-// and places the address of the next argument into a register.
-let Defs = [EFLAGS] in
+// The VAARG_64 and VAARG_X32 pseudo-instructions take the address of the
+// va_list, and place the address of the next argument into a register.
+let Defs = [EFLAGS] in {
 def VAARG_64 : I<0, Pseudo,
                  (outs GR64:$dst),
                  (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
                  "#VAARG_64 $dst, $ap, $size, $mode, $align",
                  [(set GR64:$dst,
                     (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align)),
-                  (implicit EFLAGS)]>;
-
+                  (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
+def VAARG_X32 : I<0, Pseudo,
+                 (outs GR32:$dst),
+                 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
+                 "#VAARG_X32 $dst, $ap, $size, $mode, $align",
+                 [(set GR32:$dst,
+                    (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align)),
+                  (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
+}
 
 // When using segmented stacks these are lowered into instructions which first
 // check if the current stacklet has enough free memory. If it does, memory is
 // allocated by bumping the stack pointer. Otherwise memory is allocated from
 // the heap.
 
 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),

llvm/lib/Target/X86/X86InstrInfo.td

 def SDT_X86Call   : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
 
 def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
 
 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
                                                          SDTCisVT<1, iPTR>,
                                                          SDTCisVT<2, iPTR>]>;
 
-def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
-                                            SDTCisPtrTy<1>,
-                                            SDTCisVT<2, i32>,
-                                            SDTCisVT<3, i8>,
-                                            SDTCisVT<4, i32>]>;
+def SDT_X86VAARG : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
 
 def SDTX86RepStr  : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
 
 def SDTX86Void    : SDTypeProfile<0, 0, []>;
 
 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
 
 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;

 def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret,
                         [SDNPHasChain, SDNPOptInGlue]>;
 
 def X86vastart_save_xmm_regs :
                  SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
                         SDT_X86VASTART_SAVE_XMM_REGS,
                         [SDNPHasChain, SDNPVariadic]>;
 def X86vaarg64 :
-                 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
+                 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG,
+                        [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
+                         SDNPMemOperand]>;
+def X86vaargx32 :
+                 SDNode<"X86ISD::VAARG_X32", SDT_X86VAARG,
                         [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
                          SDNPMemOperand]>;
 def X86callseq_start :
                  SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
                         [SDNPHasChain, SDNPOutGlue]>;
 def X86callseq_end :
                  SDNode<"ISD::CALLSEQ_END",   SDT_X86CallSeqEnd,
                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;

llvm/test/CodeGen/X86/x86-64-varargs.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -code-model=large -relocation-model=static | FileCheck --check-prefix=CHECK-X64 %s
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck --check-prefix=CHECK-X32 %s
 
 @.str = internal constant [38 x i8] c"%d, %f, %d, %lld, %d, %f, %d, %d, %d\0A\00"    ; <[38 x i8]*> [#uses=1]
 
 declare i32 @printf(i8*, ...) nounwind
 
 declare void @llvm.va_start(i8*)
 declare void @llvm.va_copy(i8*, i8*)
 declare void @llvm.va_end(i8*)

 ; CHECK-X64-NEXT:    movabsq $_printf, %rbx
 ; CHECK-X64-NEXT:    movb $2, %al
 ; CHECK-X64-NEXT:    pushq %r10
 ; CHECK-X64-NEXT:    pushq %r11
 ; CHECK-X64-NEXT:    callq *%rbx
 ; CHECK-X64-NEXT:    addq $240, %rsp
 ; CHECK-X64-NEXT:    popq %rbx
 ; CHECK-X64-NEXT:    retq
+;
+; CHECK-X32-LABEL: func:
+; CHECK-X32:       # %bb.0: # %entry
+; CHECK-X32-NEXT:    subl $216, %esp
+; CHECK-X32-NEXT:    testb %al, %al
+; CHECK-X32-NEXT:    je .LBB0_2
+; CHECK-X32-NEXT:  # %bb.1: # %entry
+; CHECK-X32-NEXT:    movaps %xmm0, 80(%esp)
+; CHECK-X32-NEXT:    movaps %xmm1, 96(%esp)
+; CHECK-X32-NEXT:    movaps %xmm2, 112(%esp)
+; CHECK-X32-NEXT:    movaps %xmm3, 128(%esp)
+; CHECK-X32-NEXT:    movaps %xmm4, 144(%esp)
+; CHECK-X32-NEXT:    movaps %xmm5, 160(%esp)
+; CHECK-X32-NEXT:    movaps %xmm6, 176(%esp)
+; CHECK-X32-NEXT:    movaps %xmm7, 192(%esp)
+; CHECK-X32-NEXT:  .LBB0_2: # %entry
+; CHECK-X32-NEXT:    movq %rdi, 32(%esp)
+; CHECK-X32-NEXT:    movq %rsi, 40(%esp)
+; CHECK-X32-NEXT:    movq %rdx, 48(%esp)
+; CHECK-X32-NEXT:    movq %rcx, 56(%esp)
+; CHECK-X32-NEXT:    movq %r8, 64(%esp)
+; CHECK-X32-NEXT:    movq %r9, 72(%esp)
+; CHECK-X32-NEXT:    movabsq $206158430208, %rax # imm = 0x3000000000
+; CHECK-X32-NEXT:    movq %rax, (%esp)
+; CHECK-X32-NEXT:    leal 224(%rsp), %eax
+; CHECK-X32-NEXT:    movl %eax, 8(%esp)
+; CHECK-X32-NEXT:    leal 32(%rsp), %eax
+; CHECK-X32-NEXT:    movl %eax, 12(%esp)
+; CHECK-X32-NEXT:    movl (%esp), %ecx
+; CHECK-X32-NEXT:    cmpl $48, %ecx
+; CHECK-X32-NEXT:    jae .LBB0_4
+; CHECK-X32-NEXT:  # %bb.3: # %entry
+; CHECK-X32-NEXT:    movl 12(%esp), %eax
+; CHECK-X32-NEXT:    addl %ecx, %eax
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, (%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_5
+; CHECK-X32-NEXT:  .LBB0_4: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %ecx
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_5: # %entry
+; CHECK-X32-NEXT:    movl (%eax), %r10d
+; CHECK-X32-NEXT:    movl (%esp), %ecx
+; CHECK-X32-NEXT:    cmpl $48, %ecx
+; CHECK-X32-NEXT:    jae .LBB0_7
+; CHECK-X32-NEXT:  # %bb.6: # %entry
+; CHECK-X32-NEXT:    movl 12(%esp), %eax
+; CHECK-X32-NEXT:    addl %ecx, %eax
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, (%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_8
+; CHECK-X32-NEXT:  .LBB0_7: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %ecx
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_8: # %entry
+; CHECK-X32-NEXT:    movl (%eax), %r11d
+; CHECK-X32-NEXT:    movl (%esp), %ecx
+; CHECK-X32-NEXT:    cmpl $48, %ecx
+; CHECK-X32-NEXT:    jae .LBB0_10
+; CHECK-X32-NEXT:  # %bb.9: # %entry
+; CHECK-X32-NEXT:    movl 12(%esp), %eax
+; CHECK-X32-NEXT:    addl %ecx, %eax
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, (%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_11
+; CHECK-X32-NEXT:  .LBB0_10: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %ecx
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_11: # %entry
+; CHECK-X32-NEXT:    movl (%eax), %r9d
+; CHECK-X32-NEXT:    movq (%esp), %rax
+; CHECK-X32-NEXT:    movq 8(%esp), %rcx
+; CHECK-X32-NEXT:    movq %rcx, 24(%esp)
+; CHECK-X32-NEXT:    movq %rax, 16(%esp)
+; CHECK-X32-NEXT:    movl 4(%esp), %eax
+; CHECK-X32-NEXT:    cmpl $176, %eax
+; CHECK-X32-NEXT:    jae .LBB0_13
+; CHECK-X32-NEXT:  # %bb.12: # %entry
+; CHECK-X32-NEXT:    addl $16, %eax
+; CHECK-X32-NEXT:    movl %eax, 4(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_14
+; CHECK-X32-NEXT:  .LBB0_13: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_14: # %entry
+; CHECK-X32-NEXT:    movl 20(%esp), %ecx
+; CHECK-X32-NEXT:    cmpl $176, %ecx
+; CHECK-X32-NEXT:    jae .LBB0_16
+; CHECK-X32-NEXT:  # %bb.15: # %entry
+; CHECK-X32-NEXT:    movl 28(%esp), %eax
+; CHECK-X32-NEXT:    addl %ecx, %eax
+; CHECK-X32-NEXT:    addl $16, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 20(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_17
+; CHECK-X32-NEXT:  .LBB0_16: # %entry
+; CHECK-X32-NEXT:    movl 24(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %ecx
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 24(%esp)
+; CHECK-X32-NEXT:  .LBB0_17: # %entry
+; CHECK-X32-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
+; CHECK-X32-NEXT:    movl (%esp), %ecx
+; CHECK-X32-NEXT:    cmpl $48, %ecx
+; CHECK-X32-NEXT:    jae .LBB0_19
+; CHECK-X32-NEXT:  # %bb.18: # %entry
+; CHECK-X32-NEXT:    movl 12(%esp), %eax
+; CHECK-X32-NEXT:    addl %ecx, %eax
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, (%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_20
+; CHECK-X32-NEXT:  .LBB0_19: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %ecx
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_20: # %entry
+; CHECK-X32-NEXT:    movl (%eax), %r8d
+; CHECK-X32-NEXT:    movl 16(%esp), %eax
+; CHECK-X32-NEXT:    cmpl $48, %eax
+; CHECK-X32-NEXT:    jae .LBB0_22
+; CHECK-X32-NEXT:  # %bb.21: # %entry
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 16(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_23
+; CHECK-X32-NEXT:  .LBB0_22: # %entry
+; CHECK-X32-NEXT:    movl 24(%esp), %eax
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 24(%esp)
+; CHECK-X32-NEXT:  .LBB0_23: # %entry
+; CHECK-X32-NEXT:    movl (%esp), %eax
+; CHECK-X32-NEXT:    cmpl $48, %eax
+; CHECK-X32-NEXT:    jae .LBB0_25
+; CHECK-X32-NEXT:  # %bb.24: # %entry
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, (%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_26
+; CHECK-X32-NEXT:  .LBB0_25: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_26: # %entry
+; CHECK-X32-NEXT:    movl 16(%esp), %ecx
+; CHECK-X32-NEXT:    cmpl $48, %ecx
+; CHECK-X32-NEXT:    jae .LBB0_28
+; CHECK-X32-NEXT:  # %bb.27: # %entry
+; CHECK-X32-NEXT:    movl 28(%esp), %eax
+; CHECK-X32-NEXT:    addl %ecx, %eax
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 16(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_29
+; CHECK-X32-NEXT:  .LBB0_28: # %entry
+; CHECK-X32-NEXT:    movl 24(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %ecx
+; CHECK-X32-NEXT:    addl $8, %ecx
+; CHECK-X32-NEXT:    movl %ecx, 24(%esp)
+; CHECK-X32-NEXT:  .LBB0_29: # %entry
+; CHECK-X32-NEXT:    movq (%eax), %rcx
+; CHECK-X32-NEXT:    movl (%esp), %edx
+; CHECK-X32-NEXT:    cmpl $48, %edx
+; CHECK-X32-NEXT:    jae .LBB0_31
+; CHECK-X32-NEXT:  # %bb.30: # %entry
+; CHECK-X32-NEXT:    movl 12(%esp), %eax
+; CHECK-X32-NEXT:    addl %edx, %eax
+; CHECK-X32-NEXT:    addl $8, %edx
+; CHECK-X32-NEXT:    movl %edx, (%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_32
+; CHECK-X32-NEXT:  .LBB0_31: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %edx
+; CHECK-X32-NEXT:    addl $8, %edx
+; CHECK-X32-NEXT:    movl %edx, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_32: # %entry
+; CHECK-X32-NEXT:    movl (%eax), %edx
+; CHECK-X32-NEXT:    movl 16(%esp), %eax
+; CHECK-X32-NEXT:    cmpl $48, %eax
+; CHECK-X32-NEXT:    jae .LBB0_34
+; CHECK-X32-NEXT:  # %bb.33: # %entry
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 16(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_35
+; CHECK-X32-NEXT:  .LBB0_34: # %entry
+; CHECK-X32-NEXT:    movl 24(%esp), %eax
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 24(%esp)
+; CHECK-X32-NEXT:  .LBB0_35: # %entry
+; CHECK-X32-NEXT:    movl 4(%esp), %eax
+; CHECK-X32-NEXT:    cmpl $176, %eax
+; CHECK-X32-NEXT:    jae .LBB0_37
+; CHECK-X32-NEXT:  # %bb.36: # %entry
+; CHECK-X32-NEXT:    addl $16, %eax
+; CHECK-X32-NEXT:    movl %eax, 4(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_38
+; CHECK-X32-NEXT:  .LBB0_37: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_38: # %entry
+; CHECK-X32-NEXT:    movl 20(%esp), %esi
+; CHECK-X32-NEXT:    cmpl $176, %esi
+; CHECK-X32-NEXT:    jae .LBB0_40
+; CHECK-X32-NEXT:  # %bb.39: # %entry
+; CHECK-X32-NEXT:    movl 28(%esp), %eax
+; CHECK-X32-NEXT:    addl %esi, %eax
+; CHECK-X32-NEXT:    addl $16, %esi
+; CHECK-X32-NEXT:    movl %esi, 20(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_41
+; CHECK-X32-NEXT:  .LBB0_40: # %entry
+; CHECK-X32-NEXT:    movl 24(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %esi
+; CHECK-X32-NEXT:    addl $8, %esi
+; CHECK-X32-NEXT:    movl %esi, 24(%esp)
+; CHECK-X32-NEXT:  .LBB0_41: # %entry
+; CHECK-X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-X32-NEXT:    movl (%esp), %esi
+; CHECK-X32-NEXT:    cmpl $48, %esi
+; CHECK-X32-NEXT:    jae .LBB0_43
+; CHECK-X32-NEXT:  # %bb.42: # %entry
+; CHECK-X32-NEXT:    movl 12(%esp), %eax
+; CHECK-X32-NEXT:    addl %esi, %eax
+; CHECK-X32-NEXT:    addl $8, %esi
+; CHECK-X32-NEXT:    movl %esi, (%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_44
+; CHECK-X32-NEXT:  .LBB0_43: # %entry
+; CHECK-X32-NEXT:    movl 8(%esp), %eax
+; CHECK-X32-NEXT:    movl %eax, %esi
+; CHECK-X32-NEXT:    addl $8, %esi
+; CHECK-X32-NEXT:    movl %esi, 8(%esp)
+; CHECK-X32-NEXT:  .LBB0_44: # %entry
+; CHECK-X32-NEXT:    movl (%eax), %esi
+; CHECK-X32-NEXT:    movl 16(%esp), %eax
+; CHECK-X32-NEXT:    cmpl $48, %eax
+; CHECK-X32-NEXT:    jae .LBB0_46
+; CHECK-X32-NEXT:  # %bb.45: # %entry
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 16(%esp)
+; CHECK-X32-NEXT:    jmp .LBB0_47
+; CHECK-X32-NEXT:  .LBB0_46: # %entry
+; CHECK-X32-NEXT:    movl 24(%esp), %eax
+; CHECK-X32-NEXT:    addl $8, %eax
+; CHECK-X32-NEXT:    movl %eax, 24(%esp)
+; CHECK-X32-NEXT:  .LBB0_47: # %entry
+; CHECK-X32-NEXT:    movl $.str, %edi
+; CHECK-X32-NEXT:    movb $2, %al
+; CHECK-X32-NEXT:    pushq %r10
+; CHECK-X32-NEXT:    pushq %r11
+; CHECK-X32-NEXT:    callq printf@PLT
+; CHECK-X32-NEXT:    addl $232, %esp
+; CHECK-X32-NEXT:    retq
 entry:
   %ap1 = alloca %struct.va_list
   %ap2 = alloca %struct.va_list
   %ap1p = bitcast %struct.va_list* %ap1 to i8*
   %ap2p = bitcast %struct.va_list* %ap2 to i8*
   tail call void @llvm.va_start(i8* %ap1p)
   %arg1 = va_arg i8* %ap1p, i32
   %arg2 = va_arg i8* %ap1p, i32

 ; CHECK-X64-NEXT:    movl $3, %edx
 ; CHECK-X64-NEXT:    movl $-10, %ecx
 ; CHECK-X64-NEXT:    movl $120, %r9d
 ; CHECK-X64-NEXT:    movb $2, %al
 ; CHECK-X64-NEXT:    callq *%r10
 ; CHECK-X64-NEXT:    xorl %eax, %eax
 ; CHECK-X64-NEXT:    popq %rcx
 ; CHECK-X64-NEXT:    retq
+;
+; CHECK-X32-LABEL: main:
+; CHECK-X32:       # %bb.0: # %entry
+; CHECK-X32-NEXT:    pushq %rax
+; CHECK-X32-NEXT:    movl $12, (%esp)
+; CHECK-X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-X32-NEXT:    movabsq $123456677890, %r8 # imm = 0x1CBE976802
+; CHECK-X32-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
+; CHECK-X32-NEXT:    movl $1, %edi
+; CHECK-X32-NEXT:    movl $2, %esi
+; CHECK-X32-NEXT:    movl $3, %edx
+; CHECK-X32-NEXT:    movl $-10, %ecx
+; CHECK-X32-NEXT:    movl $120, %r9d
+; CHECK-X32-NEXT:    movb $2, %al
+; CHECK-X32-NEXT:    callq func
+; CHECK-X32-NEXT:    xorl %eax, %eax
+; CHECK-X32-NEXT:    popq %rcx
+; CHECK-X32-NEXT:    retq
 entry:
   tail call void (...) @func(i32 1, i32 2, i32 3, double 4.500000e+15, i32 -10, i64 123456677890, i32 120, double 0x3FF3EB8520000000, i32 12) nounwind
   ret i32 0
 }