[AArch64] Add support for the Call Stack Recorder extension

[pratlucas]

Summary

This introduces support for the Call Stack Recorder extension, through the
new 'csre' subtarget feature. The extension consists of a new set of system
registers and the new 'CSR PDEC' instruction.

Based on patches written by Simon Tatham and Victor Campos.

llvm/include/llvm/Support/AArch64TargetParser.h

 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements a target parser to recognise AArch64 hardware features
enum ArchExtKind : uint64_t {
   AEK_SVE2BITPERM = 1 << 27,
   AEK_TME =         1 << 28,
   AEK_BF16 =        1 << 29,
   AEK_I8MM =        1 << 30,
   AEK_F32MM =       1ULL << 31,
   AEK_F64MM =       1ULL << 32,
   AEK_LS64 =        1ULL << 33,
   AEK_BRBE =        1ULL << 34,
+  AEK_CSRE =        1ULL << 35,
 };
 
 enum class ArchKind {
 #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
 #include "AArch64TargetParser.def"
 };
 
 const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = {

llvm/include/llvm/Support/AArch64TargetParser.def

 AARCH64_ARCH_EXT_NAME("predres",      AArch64::AEK_PREDRES,     "+predres", "-predres")
 AARCH64_ARCH_EXT_NAME("bf16",         AArch64::AEK_BF16,        "+bf16",  "-bf16")
 AARCH64_ARCH_EXT_NAME("i8mm",         AArch64::AEK_I8MM,        "+i8mm",  "-i8mm")
 AARCH64_ARCH_EXT_NAME("f32mm",        AArch64::AEK_F32MM,       "+f32mm", "-f32mm")
 AARCH64_ARCH_EXT_NAME("f64mm",        AArch64::AEK_F64MM,       "+f64mm", "-f64mm")
 AARCH64_ARCH_EXT_NAME("tme",          AArch64::AEK_TME,         "+tme",   "-tme")
 AARCH64_ARCH_EXT_NAME("ls64",         AArch64::AEK_LS64,        "+ls64",  "-ls64")
 AARCH64_ARCH_EXT_NAME("brbe",         AArch64::AEK_BRBE,        "+brbe",  "-brbe")
+AARCH64_ARCH_EXT_NAME("csre",         AArch64::AEK_CSRE,        "+csre",  "-csre")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
 #endif
 AARCH64_CPU_NAME("cortex-a34", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,

llvm/lib/Support/AArch64TargetParser.cpp

bool AArch64::getExtensionFeatures(uint64_t Extensions,
   if (Extensions & AEK_SVE2SHA3)
     Features.push_back("+sve2-sha3");
   if (Extensions & AEK_SVE2BITPERM)
     Features.push_back("+sve2-bitperm");
   if (Extensions & AEK_RCPC)
     Features.push_back("+rcpc");
   if (Extensions & AEK_BRBE)
     Features.push_back("+brbe");
+  if (Extensions & AEK_CSRE)
+    Features.push_back("+csre");
 
   return true;
 }
 
 bool AArch64::getArchFeatures(AArch64::ArchKind AK,
                               std::vector<StringRef> &Features) {
   if (AK == ArchKind::ARMV8_1A)
     Features.push_back("+v8.1a");

llvm/lib/Target/AArch64/AArch64.td

def FeatureHCX : SubtargetFeature<
     "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
 
 def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
     "true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
 
 def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
     "true", "Enable Branch Record Buffer Extension">;
 
+def FeatureCSRE : SubtargetFeature<"csre", "HasCSRE",
+    "true", "Enable Call Stack Recorder Extension">;
+
 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
     "true", "Enable fine grained virtualization traps extension">;
 
 def FeatureEnhancedCounterVirtualization :
       SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
       "true", "Enable enhanced counter virtualization extension">;
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def HasXS            : Predicate<"Subtarget->hasXS()">,
                        AssemblerPredicate<(all_of FeatureXS), "xs">;
 def HasWFxT          : Predicate<"Subtarget->hasWFxT()">,
                        AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
 def HasLS64          : Predicate<"Subtarget->hasLS64()">,
                        AssemblerPredicate<(all_of FeatureLS64), "ls64">;
 def HasBRBE          : Predicate<"Subtarget->hasBRBE()">,
                        AssemblerPredicate<(all_of FeatureBRBE), "brbe">;
+def HasCSRE          : Predicate<"Subtarget->hasCSRE()">,
+                       AssemblerPredicate<(all_of FeatureCSRE), "csre">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
 def UseExperimentalZeroingPseudos
     : Predicate<"Subtarget->useExperimentalZeroingPseudos()">;
 def UseAlternateSExtLoadCVTF32
     : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
 
def DSBnXS  : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {
   let Predicates = [HasXS];
 }
 
 let Predicates = [HasWFxT] in {
 def WFET : RegInputSystemI<0b0000, 0b000, "wfet">;
 def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;
 }
 
+def CSR_PDEC: SimpleSystemI<0, (ins), "csr", "\tpdec">, Sched<[WriteSys]> {
+  let Inst{20-5} = 0b0101101110010000;
+  let Predicates = [HasCSRE];
+}
+
 }
 
 // ARMv8.2-A Dot Product
 let Predicates = [HasDotProd] in {
 defm SDOT : SIMDThreeSameVectorDot<0, 0, "sdot", int_aarch64_neon_sdot>;
 defm UDOT : SIMDThreeSameVectorDot<1, 0, "udot", int_aarch64_neon_udot>;
 defm SDOTlane : SIMDThreeSameVectorDotIndex<0, 0, 0b10, "sdot", int_aarch64_neon_sdot>;
 defm UDOTlane : SIMDThreeSameVectorDotIndex<1, 0, 0b10, "udot", int_aarch64_neon_udot>;

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasSVE2SM4 = false;
   bool HasSVE2SHA3 = false;
   bool HasSVE2BitPerm = false;
 
   // Future architecture extensions.
   bool HasETE = false;
   bool HasTRBE = false;
   bool HasBRBE = false;
+  bool HasCSRE = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
 
   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
   bool HasZeroCycleZeroing = false;
   bool HasZeroCycleZeroingGP = false;
   bool HasZeroCycleZeroingFP = false;

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 foreach n = 0-31 in {
   defvar nb = !cast<bits<5>>(n);
   def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>;
   def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>;
   def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>;
 }
 }
 
+// Call Stack Recorder system registers
+let Requires = [{ {AArch64::FeatureCSRE} }] in {
+def : RWSysReg<"CSRCR_EL0",         0b10, 0b011, 0b1000, 0b0000, 0b000>;
+def : RWSysReg<"CSRCR_EL1",         0b10, 0b000, 0b1000, 0b0000, 0b000>;
+def : RWSysReg<"CSRCR_EL12",        0b10, 0b101, 0b1000, 0b0000, 0b000>;
+def : RWSysReg<"CSRCR_EL2",         0b10, 0b100, 0b1000, 0b0000, 0b000>;
+def : ROSysReg<"CSRIDR_EL0",        0b10, 0b011, 0b1000, 0b0000, 0b010>;
+def : ROSysReg<"CSRPTRIDX_EL0",     0b10, 0b011, 0b1000, 0b0000, 0b011>;
+def : ROSysReg<"CSRPTRIDX_EL1",     0b10, 0b000, 0b1000, 0b0000, 0b011>;
+def : ROSysReg<"CSRPTRIDX_EL2",     0b10, 0b100, 0b1000, 0b0000, 0b011>;
+def : RWSysReg<"CSRPTR_EL0",        0b10, 0b011, 0b1000, 0b0000, 0b001>;
+def : RWSysReg<"CSRPTR_EL1",        0b10, 0b000, 0b1000, 0b0000, 0b001>;
+def : RWSysReg<"CSRPTR_EL12",       0b10, 0b101, 0b1000, 0b0000, 0b001>;
+def : RWSysReg<"CSRPTR_EL2",        0b10, 0b100, 0b1000, 0b0000, 0b001>;
+}
+
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcAppleA7} }] in
 def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

private:
   void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S);
   AArch64CC::CondCode parseCondCodeString(StringRef Cond);
   bool parseCondCode(OperandVector &Operands, bool invertCondCode);
   unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
   bool parseRegister(OperandVector &Operands);
   bool parseSymbolicImmVal(const MCExpr *&ImmVal);
   bool parseNeonVectorList(OperandVector &Operands);
   bool parseOptionalMulOperand(OperandVector &Operands);
+  bool parseKeywordOperand(OperandVector &Operands);
   bool parseOperand(OperandVector &Operands, bool isCondCode,
                     bool invertCondCode);
   bool parseImmExpr(int64_t &Out);
   bool parseComma();
   bool parseRegisterInRange(unsigned &Out, unsigned Base, unsigned First,
                             unsigned Last);
 
   bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo,
if (!Parser.parseExpression(ImmVal))
             getContext()));
         return MatchOperand_Success;
       }
   }
 
   return Error(getLoc(), "expected 'vl' or '#<imm>'");
 }
 
+bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
+  MCAsmParser &Parser = getParser();
+  auto Tok = Parser.getTok();
+  if (Tok.isNot(AsmToken::Identifier))
+    return true;
+  Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false,
+                                                 Tok.getLoc(), getContext()));
+  Parser.Lex();
+  return false;
+}
+
 /// parseOperand - Parse a arm instruction operand.  For now this parses the
 /// operand regardless of the mnemonic.
 bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
                                   bool invertCondCode) {
   MCAsmParser &Parser = getParser();
 
   OperandMatchResultTy ResTy =
       MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/ true);
if (!parseOptionalMulOperand(Operands))
       return false;
 
     // This could be an optional "shift" or "extend" operand.
     OperandMatchResultTy GotShift = tryParseOptionalShiftExtend(Operands);
     // We can only continue if no tokens were eaten.
     if (GotShift != MatchOperand_NoMatch)
       return GotShift;
 
+    // If this is a "csr" instruction, parse its special keyword
+    // operand as an identifier.
+    if (Mnemonic == "csr")
+      return parseKeywordOperand(Operands);
+
     // This was not a register so parse other operands that start with an
     // identifier (like labels) as expressions and create them as immediates.
     const MCExpr *IdVal;
     S = getLoc();
     if (getParser().parseExpression(IdVal))
       return true;
     E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
     Operands.push_back(AArch64Operand::CreateImm(IdVal, S, E, getContext()));

llvm/test/MC/AArch64/csre.s

+// RUN: not llvm-mc -triple aarch64 -mattr +csre -show-encoding %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t
+// RUN: FileCheck --check-prefix=ERROR-NO-CSRE %s < %t
+
+msr CSRCR_EL0, x0
+mrs x1, CSRCR_EL0
+// CHECK: msr     CSRCR_EL0, x0           // encoding: [0x00,0x80,0x13,0xd5]
+// CHECK: mrs     x1, CSRCR_EL0           // encoding: [0x01,0x80,0x33,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:9: error: expected readable system register
+
+msr CSRCR_EL1, x2
+mrs x3, CSRCR_EL1
+// CHECK: msr     CSRCR_EL1, x2           // encoding: [0x02,0x80,0x10,0xd5]
+// CHECK: mrs     x3, CSRCR_EL1           // encoding: [0x03,0x80,0x30,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:9: error: expected readable system register
+
+msr CSRCR_EL12, x4
+mrs x5, CSRCR_EL12
+// CHECK: msr     CSRCR_EL12, x4          // encoding: [0x04,0x80,0x15,0xd5]
+// CHECK: mrs     x5, CSRCR_EL12          // encoding: [0x05,0x80,0x35,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:9: error: expected readable system register
+
+msr CSRCR_EL2, x6
+mrs x7, CSRCR_EL2
+// CHECK: msr     CSRCR_EL2, x6           // encoding: [0x06,0x80,0x14,0xd5]
+// CHECK: mrs     x7, CSRCR_EL2           // encoding: [0x07,0x80,0x34,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:9: error: expected readable system register
+
+msr CSRIDR_EL0, x8
+mrs x9, CSRIDR_EL0
+// ERROR: [[@LINE-2]]:5: error: expected writable system register
+// CHECK: mrs     x9, CSRIDR_EL0          // encoding: [0x49,0x80,0x33,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:9: error: expected readable system register
+
+msr CSRPTRIDX_EL0, x10
+mrs x11, CSRPTRIDX_EL0
+// ERROR: [[@LINE-2]]:5: error: expected writable system register
+// CHECK: mrs     x11, CSRPTRIDX_EL0      // encoding: [0x6b,0x80,0x33,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:10: error: expected readable system register
+
+msr CSRPTR_EL0, x12
+mrs x13, CSRPTR_EL0
+// CHECK: msr     CSRPTR_EL0, x12         // encoding: [0x2c,0x80,0x13,0xd5]
+// CHECK: mrs     x13, CSRPTR_EL0         // encoding: [0x2d,0x80,0x33,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:10: error: expected readable system register
+
+msr CSRPTR_EL1, x14
+mrs x15, CSRPTR_EL1
+// CHECK: msr     CSRPTR_EL1, x14         // encoding: [0x2e,0x80,0x10,0xd5]
+// CHECK: mrs     x15, CSRPTR_EL1         // encoding: [0x2f,0x80,0x30,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:10: error: expected readable system register
+
+msr CSRPTR_EL12, x16
+mrs x17, CSRPTR_EL12
+// CHECK: msr     CSRPTR_EL12, x16        // encoding: [0x30,0x80,0x15,0xd5]
+// CHECK: mrs     x17, CSRPTR_EL12        // encoding: [0x31,0x80,0x35,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:10: error: expected readable system register
+
+msr CSRPTR_EL2, x18
+mrs x19, CSRPTR_EL2
+// CHECK: msr     CSRPTR_EL2, x18         // encoding: [0x32,0x80,0x14,0xd5]
+// CHECK: mrs     x19, CSRPTR_EL2         // encoding: [0x33,0x80,0x34,0xd5]
+// ERROR-NO-CSRE: [[@LINE-4]]:5: error: expected writable system register
+// ERROR-NO-CSRE: [[@LINE-4]]:10: error: expected readable system register
+
+csr pdec
+// CHECK: csr     pdec                    // encoding: [0x1f,0x72,0x0b,0xd5]
+// ERROR-NO-CSRE: [[@LINE-2]]:1: error: instruction requires: csre
+
+csr pduc
+// ERROR: [[@LINE-1]]:5: error: invalid operand for instruction
+csr pdec,1
+// ERROR: [[@LINE-1]]:10: error: invalid operand for instruction
+csr
+// ERROR: [[@LINE-1]]:1: error: too few operands for instruction

llvm/test/MC/Disassembler/AArch64/csre.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+csre -disassemble %s 2> %t | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -disassemble %s 2> %t | FileCheck --check-prefix=NO-CSRE %s
+
+[0x00,0x80,0x13,0xd5]
+[0x01,0x80,0x33,0xd5]
+# CHECK:   msr     CSRCR_EL0, x0
+# CHECK:   mrs     x1, CSRCR_EL0
+# NO-CSRE: msr     S2_3_C8_C0_0, x0
+# NO-CSRE: mrs     x1, S2_3_C8_C0_0
+
+[0x02,0x80,0x10,0xd5]
+[0x03,0x80,0x30,0xd5]
+# CHECK:   msr     CSRCR_EL1, x2
+# CHECK:   mrs     x3, CSRCR_EL1
+# NO-CSRE: msr     S2_0_C8_C0_0, x2
+# NO-CSRE: mrs     x3, S2_0_C8_C0_0
+
+[0x04,0x80,0x15,0xd5]
+[0x05,0x80,0x35,0xd5]
+# CHECK:   msr     CSRCR_EL12, x4
+# CHECK:   mrs     x5, CSRCR_EL12
+# NO-CSRE: msr     S2_5_C8_C0_0, x4
+# NO-CSRE: mrs     x5, S2_5_C8_C0_0
+
+[0x06,0x80,0x14,0xd5]
+[0x07,0x80,0x34,0xd5]
+# CHECK:   msr     CSRCR_EL2, x6
+# CHECK:   mrs     x7, CSRCR_EL2
+# NO-CSRE: msr     S2_4_C8_C0_0, x6
+# NO-CSRE: mrs     x7, S2_4_C8_C0_0
+
+[0x48,0x80,0x13,0xd5] # expect failure: CSRIDR_EL0 is RO
+[0x49,0x80,0x33,0xd5]
+# CHECK:   msr     S2_3_C8_C0_2, x8
+# CHECK:   mrs     x9, CSRIDR_EL0
+# NO-CSRE: msr     S2_3_C8_C0_2, x8
+# NO-CSRE: mrs     x9, S2_3_C8_C0_2
+
+[0x6a,0x80,0x13,0xd5] # expect failure: CSRPTRIDX_EL0 is RO
+[0x6b,0x80,0x33,0xd5]
+# CHECK:   msr     S2_3_C8_C0_3, x10
+# CHECK:   mrs     x11, CSRPTRIDX_EL0
+# NO-CSRE: msr     S2_3_C8_C0_3, x10
+# NO-CSRE: mrs     x11, S2_3_C8_C0_3
+
+[0x6a,0x80,0x10,0xd5] # expect failure: CSRPTRIDX_EL1 is RO
+[0x6b,0x80,0x30,0xd5]
+# CHECK:   msr     S2_0_C8_C0_3, x10
+# CHECK:   mrs     x11, CSRPTRIDX_EL1
+# NO-CSRE: msr     S2_0_C8_C0_3, x10
+# NO-CSRE: mrs     x11, S2_0_C8_C0_3
+
+[0x6a,0x80,0x14,0xd5] # expect failure: CSRPTRIDX_EL2 is RO
+[0x6b,0x80,0x34,0xd5]
+# CHECK:   msr     S2_4_C8_C0_3, x10
+# CHECK:   mrs     x11, CSRPTRIDX_EL2
+# NO-CSRE: msr     S2_4_C8_C0_3, x10
+# NO-CSRE: mrs     x11, S2_4_C8_C0_3
+
+[0x2c,0x80,0x13,0xd5]
+[0x2d,0x80,0x33,0xd5]
+# CHECK:   msr     CSRPTR_EL0, x12
+# CHECK:   mrs     x13, CSRPTR_EL0
+# NO-CSRE: msr     S2_3_C8_C0_1, x12
+# NO-CSRE: mrs     x13, S2_3_C8_C0_1
+
+[0x2e,0x80,0x10,0xd5]
+[0x2f,0x80,0x30,0xd5]
+# CHECK:   msr     CSRPTR_EL1, x14
+# CHECK:   mrs     x15, CSRPTR_EL1
+# NO-CSRE: msr     S2_0_C8_C0_1, x14
+# NO-CSRE: mrs     x15, S2_0_C8_C0_1
+
+[0x30,0x80,0x15,0xd5]
+[0x31,0x80,0x35,0xd5]
+# CHECK:   msr     CSRPTR_EL12, x16
+# CHECK:   mrs     x17, CSRPTR_EL12
+# NO-CSRE: msr     S2_5_C8_C0_1, x16
+# NO-CSRE: mrs     x17, S2_5_C8_C0_1
+
+[0x32,0x80,0x14,0xd5]
+[0x33,0x80,0x34,0xd5]
+# CHECK:   msr     CSRPTR_EL2, x18
+# CHECK:   mrs     x19, CSRPTR_EL2
+# NO-CSRE: msr     S2_4_C8_C0_1, x18
+# NO-CSRE: mrs     x19, S2_4_C8_C0_1
+
+[0x1f,0x72,0x0b,0xd5]
+# CHECK:   csr     pdec
+# NO-CSRE: sys     #3, c7, c2, #0