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Differential D91842

[SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma node in tablegen. Remove explicit commuted patterns from targets.
ClosedPublic

Authored by craig.topper on Nov 19 2020, 10:14 PM.

Details

Reviewers
efriedma
RKSimon
spatel
arsenm
foad
Commits
rG4252f7773a5b: [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma…
Summary

X86 was already specially marking fma as commutable which allowed
tablegen to autogenerate commuted patterns. This moves it to the target
independent definition and fix up the targets to remove now
unneeded patterns.

Unfortunately, the tests change because the commuted version of
the patterns are generating operands in a different than the
explicit patterns.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 19 2020, 10:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 19 2020, 10:14 PM
Herald added subscribers: frasercrmck, NickHung, ecnelises and 32 others. · View Herald Transcript
craig.topper requested review of this revision.Nov 19 2020, 10:14 PM
Herald added a subscriber: MaskRay. · View Herald TranscriptNov 19 2020, 10:14 PM
Harbormaster completed remote builds in B79566: Diff 306599.Nov 19 2020, 10:48 PM
RKSimon added inline comments.Nov 20 2020, 3:29 AM
llvm/include/llvm/Target/TargetSelectionDAG.td
443–444

Can fmad be updated as well?

craig.topper updated this revision to Diff 306828.Nov 21 2020, 12:38 AM

Make fmad commutable as well. Looks like only AMDGPU uses it and I don't think they have patterns that care.

Harbormaster completed remote builds in B79677: Diff 306828.Nov 21 2020, 1:20 AM
RKSimon added reviewers: arsenm, foad.Nov 21 2020, 6:06 AM
RKSimon added subscribers: foad, arsenm.

LGTM - @arsenm @foad is the FMAD change OK for AMDGPU?

Herald added a subscriber: wdng. · View Herald TranscriptNov 21 2020, 6:06 AM
foad added a comment.Nov 23 2020, 1:20 AM
In D91842#2409550, @RKSimon wrote:

LGTM - @arsenm @foad is the FMAD change OK for AMDGPU?

It looks correct and I can't imagine how it would break anything.

RKSimon accepted this revision.Nov 23 2020, 2:14 AM
This revision is now accepted and ready to land.Nov 23 2020, 2:14 AM
This revision was landed with ongoing or failed builds.Nov 23 2020, 10:30 AM
Closed by commit rG4252f7773a5b: [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG4252f7773a5b: [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma….
thakis added a subscriber: thakis.Nov 23 2020, 10:38 AM

Looks like this needs updates over in clang land: http://45.33.8.238/linux/33569/step_7.txt

Revision Contents

PathSize
llvm/
include/
llvm/
Target/
6 lines
lib/
Target/
AArch64/
23 lines
ARM/
6 lines
20 lines
Hexagon/
2 lines
RISCV/
4 lines
4 lines
X86/
12 lines
22 lines
3 lines
test/
CodeGen/
AArch64/
GlobalISel/
14 lines
6 lines
ARM/
GlobalISel/
2 lines
2 lines
16 lines
RISCV/
8 lines
8 lines
Thumb2/
2 lines
4 lines
mve-intrinsics/
4 lines

Diff 307117

llvm/include/llvm/Target/TargetSelectionDAG.td

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def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>; def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>; def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>;
def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp, [SDNPCommutative]>;
def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>; def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>;
RKSimonUnsubmitted
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Can fmad be updated as well?

RKSimon: Can fmad be updated as well?
def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp,
[SDNPCommutative, SDNPAssociative]>; [SDNPCommutative, SDNPAssociative]>;
def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
[SDNPCommutative, SDNPAssociative]>; [SDNPCommutative, SDNPAssociative]>;
def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp, def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp,
[SDNPCommutative]>; [SDNPCommutative]>;
def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp, def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
Show All 40 Linesdef strict_fsub : SDNode<"ISD::STRICT_FSUB",
SDTFPBinOp, [SDNPHasChain]>; SDTFPBinOp, [SDNPHasChain]>;
def strict_fmul : SDNode<"ISD::STRICT_FMUL", def strict_fmul : SDNode<"ISD::STRICT_FMUL",
SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>;
def strict_fdiv : SDNode<"ISD::STRICT_FDIV", def strict_fdiv : SDNode<"ISD::STRICT_FDIV",
SDTFPBinOp, [SDNPHasChain]>; SDTFPBinOp, [SDNPHasChain]>;
def strict_frem : SDNode<"ISD::STRICT_FREM", def strict_frem : SDNode<"ISD::STRICT_FREM",
SDTFPBinOp, [SDNPHasChain]>; SDTFPBinOp, [SDNPHasChain]>;
def strict_fma : SDNode<"ISD::STRICT_FMA", def strict_fma : SDNode<"ISD::STRICT_FMA",
SDTFPTernaryOp, [SDNPHasChain]>; SDTFPTernaryOp, [SDNPHasChain, SDNPCommutative]>;
def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT", def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT",
SDTFPUnaryOp, [SDNPHasChain]>; SDTFPUnaryOp, [SDNPHasChain]>;
def strict_fsin : SDNode<"ISD::STRICT_FSIN", def strict_fsin : SDNode<"ISD::STRICT_FSIN",
SDTFPUnaryOp, [SDNPHasChain]>; SDTFPUnaryOp, [SDNPHasChain]>;
def strict_fcos : SDNode<"ISD::STRICT_FCOS", def strict_fcos : SDNode<"ISD::STRICT_FCOS",
SDTFPUnaryOp, [SDNPHasChain]>; SDTFPUnaryOp, [SDNPHasChain]>;
def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2", def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2",
SDTFPUnaryOp, [SDNPHasChain]>; SDTFPUnaryOp, [SDNPHasChain]>;
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llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,732 Lines • ▼ Show 20 Linesdef : Pat<(f16 (fma (fneg FPR16:$Rn), FPR16:$Rm, (fneg FPR16:$Ra))),
(FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;
def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))), def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
(FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))), def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
(FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
// And here "(-a) + b*(-c)"
let Predicates = [HasNEON, HasFullFP16] in
def : Pat<(f16 (fma FPR16:$Rn, (fneg FPR16:$Rm), (fneg FPR16:$Ra))),
(FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>;
def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
(FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
(FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating point comparison instructions. // Floating point comparison instructions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm FCMPE : FPComparison<1, "fcmpe", AArch64strict_fcmpe>; defm FCMPE : FPComparison<1, "fcmpe", AArch64strict_fcmpe>;
defm FCMP : FPComparison<0, "fcmp", AArch64any_fcmp>; defm FCMP : FPComparison<0, "fcmp", AArch64any_fcmp>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
// instruction expects the addend first, while the fma intrinsic puts it last. // instruction expects the addend first, while the fma intrinsic puts it last.
defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla", defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla",
TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >; TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls", defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls",
TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
// The following def pats catch the case where the LHS of an FMA is negated.
// The TriOpFrag above catches the case where the middle operand is negated.
def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
(FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
(FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
(FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>; defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>;
defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>; defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>;
defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>; defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>;
defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>; defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>;
defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>; defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>;
// MLA and MLS are generated in MachineCombine // MLA and MLS are generated in MachineCombine
defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", null_frag>; defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla", null_frag>;
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llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,678 Lines • ▼ Show 20 Linesmulticlass MVE_VFMA_fp_multi<string iname, bit fms, MVEVectorVTInfo VTI> {
defvar m2 = (VTI.Vec MQPR:$m2); defvar m2 = (VTI.Vec MQPR:$m2);
defvar add = (VTI.Vec MQPR:$add); defvar add = (VTI.Vec MQPR:$add);
defvar pred = (VTI.Pred VCCR:$pred); defvar pred = (VTI.Pred VCCR:$pred);
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
if fms then { if fms then {
def : Pat<(VTI.Vec (fma (fneg m1), m2, add)), def : Pat<(VTI.Vec (fma (fneg m1), m2, add)),
(Inst $add, $m1, $m2)>; (Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (fma m1, (fneg m2), add)),
(Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma (fneg m1), m2, add)), (VTI.Vec (fma (fneg m1), m2, add)),
add)), add)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma m1, (fneg m2), add)),
add)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)), def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)), def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
} else { } else {
def : Pat<(VTI.Vec (fma m1, m2, add)), def : Pat<(VTI.Vec (fma m1, m2, add)),
(Inst $add, $m1, $m2)>; (Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
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llvm/lib/Target/ARM/ARMInstrVFP.td

Show First 20 Lines • Show All 2,258 Lines • ▼ Show 20 Linesdef : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
Requires<[HasVFP4,HasDPVFP]>; Requires<[HasVFP4,HasDPVFP]>;
def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
Requires<[HasVFP4]>; Requires<[HasVFP4]>;
def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))), def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))),
(VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,
Requires<[HasFullFP16]>; Requires<[HasFullFP16]>;
// (fma x, (fneg y), z) -> (vfms z, x, y)
def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
(VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
Requires<[HasVFP4,HasDPVFP]>;
def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
(VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
Requires<[HasVFP4]>;
def : Pat<(f16 (fma (f16 HPR:$Sn), (fneg (f16 HPR:$Sm)), (f16 HPR:$Sdin))),
(VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,
Requires<[HasFullFP16]>;
def VFNMAD : ADbI<0b11101, 0b01, 1, 0, def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
(outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
(f64 DPR:$Ddin)))]>, (f64 DPR:$Ddin)))]>,
RegConstraint<"$Ddin = $Dd">, RegConstraint<"$Ddin = $Dd">,
Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>,
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Linesdef : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
Requires<[HasVFP4,HasDPVFP]>; Requires<[HasVFP4,HasDPVFP]>;
def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
Requires<[HasVFP4]>; Requires<[HasVFP4]>;
def : Pat<(fneg (f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))), def : Pat<(fneg (f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))),
(VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,
Requires<[HasFullFP16]>; Requires<[HasFullFP16]>;
// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
(VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
Requires<[HasVFP4,HasDPVFP]>;
def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
(VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
Requires<[HasVFP4]>;
def : Pat<(fneg (f16 (fma (f16 HPR:$Sn), (fneg (f16 HPR:$Sm)), (f16 HPR:$Sdin)))),
(VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>,
Requires<[HasFullFP16]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// FP Conditional moves. // FP Conditional moves.
// //
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
IIC_fpUNA64, IIC_fpUNA64,
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llvm/lib/Target/Hexagon/HexagonPatterns.td

Show First 20 Lines • Show All 1,702 Lines • ▼ Show 20 Lineslet Predicates = [UseCompound] in {
def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)),
(M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
} }
def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx),
(F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>;
def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx),
(F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx),
(F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>;
def: Pat<(mul V2I32:$Rs, V2I32:$Rt), def: Pat<(mul V2I32:$Rs, V2I32:$Rt),
(PS_vmulw V2I32:$Rs, V2I32:$Rt)>; (PS_vmulw V2I32:$Rs, V2I32:$Rt)>;
def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)), def: Pat<(add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)),
(PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>; (PS_vmulw_acc V2I32:$Rx, V2I32:$Rs, V2I32:$Rt)>;
// Add/subtract two v4i8: Hexagon does not have an insn for this one, so // Add/subtract two v4i8: Hexagon does not have an insn for this one, so
// we use the double add v8i8, and use only the low part of the result. // we use the double add v8i8, and use only the low part of the result.
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llvm/lib/Target/RISCV/RISCVInstrInfoD.td

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// fmsub: rs1 * rs2 - rs3 // fmsub: rs1 * rs2 - rs3
def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)), def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
(FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
// fnmsub: -rs1 * rs2 + rs3 // fnmsub: -rs1 * rs2 + rs3
def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
(FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
def : Pat<(fma FPR64:$rs1, (fneg FPR64:$rs2), FPR64:$rs3),
(FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
// fnmadd: -rs1 * rs2 - rs3 // fnmadd: -rs1 * rs2 - rs3
def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
def : Pat<(fma FPR64:$rs1, (fneg FPR64:$rs2), (fneg FPR64:$rs3)),
(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
// canonical NaN when giving a signaling NaN. This doesn't match the LLVM // canonical NaN when giving a signaling NaN. This doesn't match the LLVM
// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the // behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that // draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
// matches LLVM's fminnum and fmaxnum // matches LLVM's fminnum and fmaxnum
// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
def : PatFpr64Fpr64<fminnum, FMIN_D>; def : PatFpr64Fpr64<fminnum, FMIN_D>;
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llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
// fmsub: rs1 * rs2 - rs3 // fmsub: rs1 * rs2 - rs3
def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
(FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
// fnmsub: -rs1 * rs2 + rs3 // fnmsub: -rs1 * rs2 + rs3
def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
(FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
def : Pat<(fma FPR32:$rs1, (fneg FPR32:$rs2), FPR32:$rs3),
(FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
// fnmadd: -rs1 * rs2 - rs3 // fnmadd: -rs1 * rs2 - rs3
def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
def : Pat<(fma FPR32:$rs1, (fneg FPR32:$rs2), (fneg FPR32:$rs3)),
(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
// canonical NaN when given a signaling NaN. This doesn't match the LLVM // canonical NaN when given a signaling NaN. This doesn't match the LLVM
// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the // behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that // draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
// matches LLVM's fminnum and fmaxnum // matches LLVM's fminnum and fmaxnum
// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
def : PatFpr32Fpr32<fminnum, FMIN_S>; def : PatFpr32Fpr32<fminnum, FMIN_S>;
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llvm/lib/Target/X86/X86InstrAVX512.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 6,527 Lines • ▼ Show 20 Linesmulticlass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode, defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode,
OpNodeRnd, SchedWriteFMA, OpNodeRnd, SchedWriteFMA,
avx512vl_f32_info, "PS">; avx512vl_f32_info, "PS">;
defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, MaskOpNode, defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, MaskOpNode,
OpNodeRnd, SchedWriteFMA, OpNodeRnd, SchedWriteFMA,
avx512vl_f64_info, "PD">, VEX_W; avx512vl_f64_info, "PD">, VEX_W;
} }
defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86any_Fmadd, defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", any_fma,
X86Fmadd, X86FmaddRnd>; X86Fmadd, X86FmaddRnd>;
defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86any_Fmsub, defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86any_Fmsub,
X86Fmsub, X86FmsubRnd>; X86Fmsub, X86FmsubRnd>;
defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub,
X86Fmaddsub, X86FmaddsubRnd>; X86Fmaddsub, X86FmaddsubRnd>;
defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd,
X86Fmsubadd, X86FmsubaddRnd>; X86Fmsubadd, X86FmsubaddRnd>;
defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86any_Fnmadd, defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86any_Fnmadd,
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesmulticlass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode, defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode,
OpNodeRnd, SchedWriteFMA, OpNodeRnd, SchedWriteFMA,
avx512vl_f32_info, "PS">; avx512vl_f32_info, "PS">;
defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, MaskOpNode, defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, MaskOpNode,
OpNodeRnd, SchedWriteFMA, OpNodeRnd, SchedWriteFMA,
avx512vl_f64_info, "PD">, VEX_W; avx512vl_f64_info, "PD">, VEX_W;
} }
defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86any_Fmadd, defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", any_fma,
X86Fmadd, X86FmaddRnd>; X86Fmadd, X86FmaddRnd>;
defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86any_Fmsub, defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86any_Fmsub,
X86Fmsub, X86FmsubRnd>; X86Fmsub, X86FmsubRnd>;
defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub,
X86Fmaddsub, X86FmaddsubRnd>; X86Fmaddsub, X86FmaddsubRnd>;
defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd,
X86Fmsubadd, X86FmsubaddRnd>; X86Fmsubadd, X86FmsubaddRnd>;
defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86any_Fnmadd, defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86any_Fnmadd,
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesmulticlass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode, defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, MaskOpNode,
OpNodeRnd, SchedWriteFMA, OpNodeRnd, SchedWriteFMA,
avx512vl_f32_info, "PS">; avx512vl_f32_info, "PS">;
defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, MaskOpNode, defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, MaskOpNode,
OpNodeRnd, SchedWriteFMA, OpNodeRnd, SchedWriteFMA,
avx512vl_f64_info, "PD">, VEX_W; avx512vl_f64_info, "PD">, VEX_W;
} }
defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86any_Fmadd, defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", any_fma,
X86Fmadd, X86FmaddRnd>; X86Fmadd, X86FmaddRnd>;
defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86any_Fmsub, defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86any_Fmsub,
X86Fmsub, X86FmsubRnd>; X86Fmsub, X86FmsubRnd>;
defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub,
X86Fmaddsub, X86FmaddsubRnd>; X86Fmaddsub, X86FmaddsubRnd>;
defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd,
X86Fmsubadd, X86FmsubaddRnd>; X86Fmsubadd, X86FmsubaddRnd>;
defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86any_Fnmadd, defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86any_Fnmadd,
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
OpNodeRnd, f32x_info, "SS">, OpNodeRnd, f32x_info, "SS">,
EVEX_CD8<32, CD8VT1>, VEX_LIG; EVEX_CD8<32, CD8VT1>, VEX_LIG;
defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode, defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
OpNodeRnd, f64x_info, "SD">, OpNodeRnd, f64x_info, "SD">,
EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W; EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
} }
} }
defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86any_Fmadd, X86FmaddRnd>; defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", any_fma, X86FmaddRnd>;
defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86any_Fmsub, X86FmsubRnd>; defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86any_Fmsub, X86FmsubRnd>;
defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86any_Fnmadd, X86FnmaddRnd>; defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86any_Fnmadd, X86FnmaddRnd>;
defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86any_Fnmsub, X86FnmsubRnd>; defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86any_Fnmsub, X86FnmsubRnd>;
multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode MaskedOp, multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode MaskedOp,
SDNode RndOp, string Prefix, SDNode RndOp, string Prefix,
string Suffix, SDNode Move, string Suffix, SDNode Move,
X86VectorVTInfo _, PatLeaf ZeroFP> { X86VectorVTInfo _, PatLeaf ZeroFP> {
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
(_.EltVT ZeroFP)))))), (_.EltVT ZeroFP)))))),
(!cast<I>(Prefix#"231"#Suffix#"Zrb_Intkz") (!cast<I>(Prefix#"231"#Suffix#"Zrb_Intkz")
VR128X:$src1, VK1WM:$mask, VR128X:$src1, VK1WM:$mask,
(_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)), (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
(_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), AVX512RC:$rc)>; (_.VT (COPY_TO_REGCLASS _.FRC:$src3, VR128X)), AVX512RC:$rc)>;
} }
} }
defm : avx512_scalar_fma_patterns<X86any_Fmadd, X86Fmadd, X86FmaddRnd, "VFMADD", defm : avx512_scalar_fma_patterns<any_fma, X86Fmadd, X86FmaddRnd, "VFMADD",
"SS", X86Movss, v4f32x_info, fp32imm0>; "SS", X86Movss, v4f32x_info, fp32imm0>;
defm : avx512_scalar_fma_patterns<X86any_Fmsub, X86Fmsub, X86FmsubRnd, "VFMSUB", defm : avx512_scalar_fma_patterns<X86any_Fmsub, X86Fmsub, X86FmsubRnd, "VFMSUB",
"SS", X86Movss, v4f32x_info, fp32imm0>; "SS", X86Movss, v4f32x_info, fp32imm0>;
defm : avx512_scalar_fma_patterns<X86any_Fnmadd, X86Fnmadd, X86FnmaddRnd, "VFNMADD", defm : avx512_scalar_fma_patterns<X86any_Fnmadd, X86Fnmadd, X86FnmaddRnd, "VFNMADD",
"SS", X86Movss, v4f32x_info, fp32imm0>; "SS", X86Movss, v4f32x_info, fp32imm0>;
defm : avx512_scalar_fma_patterns<X86any_Fnmsub, X86Fnmsub, X86FnmsubRnd, "VFNMSUB", defm : avx512_scalar_fma_patterns<X86any_Fnmsub, X86Fnmsub, X86FnmsubRnd, "VFNMSUB",
"SS", X86Movss, v4f32x_info, fp32imm0>; "SS", X86Movss, v4f32x_info, fp32imm0>;
defm : avx512_scalar_fma_patterns<X86any_Fmadd, X86Fmadd, X86FmaddRnd, "VFMADD", defm : avx512_scalar_fma_patterns<any_fma, X86Fmadd, X86FmaddRnd, "VFMADD",
"SD", X86Movsd, v2f64x_info, fp64imm0>; "SD", X86Movsd, v2f64x_info, fp64imm0>;
defm : avx512_scalar_fma_patterns<X86any_Fmsub, X86Fmsub, X86FmsubRnd, "VFMSUB", defm : avx512_scalar_fma_patterns<X86any_Fmsub, X86Fmsub, X86FmsubRnd, "VFMSUB",
"SD", X86Movsd, v2f64x_info, fp64imm0>; "SD", X86Movsd, v2f64x_info, fp64imm0>;
defm : avx512_scalar_fma_patterns<X86any_Fnmadd, X86Fnmadd, X86FnmaddRnd, "VFNMADD", defm : avx512_scalar_fma_patterns<X86any_Fnmadd, X86Fnmadd, X86FnmaddRnd, "VFNMADD",
"SD", X86Movsd, v2f64x_info, fp64imm0>; "SD", X86Movsd, v2f64x_info, fp64imm0>;
defm : avx512_scalar_fma_patterns<X86any_Fnmsub, X86Fnmsub, X86FnmsubRnd, "VFNMSUB", defm : avx512_scalar_fma_patterns<X86any_Fnmsub, X86Fnmsub, X86FnmsubRnd, "VFNMSUB",
"SD", X86Movsd, v2f64x_info, fp64imm0>; "SD", X86Movsd, v2f64x_info, fp64imm0>;
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llvm/lib/Target/X86/X86InstrFMA.td

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Linesmulticlass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
defm NAME#132#Suff#Y : fma3p_rm_132<opc132, !strconcat(OpcodeStr, "132", PackTy), defm NAME#132#Suff#Y : fma3p_rm_132<opc132, !strconcat(OpcodeStr, "132", PackTy),
VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>, VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>,
VEX_L; VEX_L;
} }
// Fused Multiply-Add // Fused Multiply-Add
let ExeDomain = SSEPackedSingle in { let ExeDomain = SSEPackedSingle in {
defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS", defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS",
loadv4f32, loadv8f32, X86any_Fmadd, v4f32, v8f32, loadv4f32, loadv8f32, any_fma, v4f32, v8f32,
SchedWriteFMA>; SchedWriteFMA>;
defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS", defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS",
loadv4f32, loadv8f32, X86any_Fmsub, v4f32, v8f32, loadv4f32, loadv8f32, X86any_Fmsub, v4f32, v8f32,
SchedWriteFMA>; SchedWriteFMA>;
defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS", defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS",
loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32, loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32,
SchedWriteFMA>; SchedWriteFMA>;
defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS", defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS",
loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32, loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32,
SchedWriteFMA>; SchedWriteFMA>;
} }
let ExeDomain = SSEPackedDouble in { let ExeDomain = SSEPackedDouble in {
defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD", defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD",
loadv2f64, loadv4f64, X86any_Fmadd, v2f64, loadv2f64, loadv4f64, any_fma, v2f64,
v4f64, SchedWriteFMA>, VEX_W; v4f64, SchedWriteFMA>, VEX_W;
defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD", defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD",
loadv2f64, loadv4f64, X86any_Fmsub, v2f64, loadv2f64, loadv4f64, X86any_Fmsub, v2f64,
v4f64, SchedWriteFMA>, VEX_W; v4f64, SchedWriteFMA>, VEX_W;
defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD", defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD",
loadv2f64, loadv4f64, X86Fmaddsub, loadv2f64, loadv4f64, X86Fmaddsub,
v2f64, v4f64, SchedWriteFMA>, VEX_W; v2f64, v4f64, SchedWriteFMA>, VEX_W;
defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD", defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD",
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesmulticlass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
let ExeDomain = SSEPackedDouble in let ExeDomain = SSEPackedDouble in
defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "SD", OpNode, defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "SD", OpNode,
FR64, f64mem, sched>, FR64, f64mem, sched>,
fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", "SD", fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", "SD",
VR128, sdmem, sched>, VEX_W; VR128, sdmem, sched>, VEX_W;
} }
defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86any_Fmadd, defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", any_fma,
SchedWriteFMA.Scl>, VEX_LIG; SchedWriteFMA.Scl>, VEX_LIG;
defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86any_Fmsub, defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86any_Fmsub,
SchedWriteFMA.Scl>, VEX_LIG; SchedWriteFMA.Scl>, VEX_LIG;
defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86any_Fnmadd, defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86any_Fnmadd,
SchedWriteFMA.Scl>, VEX_LIG; SchedWriteFMA.Scl>, VEX_LIG;
defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86any_Fnmsub, defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86any_Fnmsub,
SchedWriteFMA.Scl>, VEX_LIG; SchedWriteFMA.Scl>, VEX_LIG;
Show All 36 Lines def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector
(Op RC:$src2, (mem_frag addr:$src3), (Op RC:$src2, (mem_frag addr:$src3),
(EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))),
(!cast<Instruction>(Prefix#"231"#Suffix#"m_Int") (!cast<Instruction>(Prefix#"231"#Suffix#"m_Int")
VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
addr:$src3)>; addr:$src3)>;
} }
} }
defm : scalar_fma_patterns<X86any_Fmadd, "VFMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; defm : scalar_fma_patterns<any_fma, "VFMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
defm : scalar_fma_patterns<X86any_Fmadd, "VFMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; defm : scalar_fma_patterns<any_fma, "VFMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// FMA4 - AMD 4 operand Fused Multiply-Add instructions // FMA4 - AMD 4 operand Fused Multiply-Add instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines def Yrr_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
VEX_L, Sched<[sched.YMM]>, FoldGenData<NAME#Yrr>; VEX_L, Sched<[sched.YMM]>, FoldGenData<NAME#Yrr>;
} // isCodeGenOnly = 1 } // isCodeGenOnly = 1
} }
let ExeDomain = SSEPackedSingle in { let ExeDomain = SSEPackedSingle in {
// Scalar Instructions // Scalar Instructions
defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86any_Fmadd, loadf32, defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, any_fma, loadf32,
SchedWriteFMA.Scl>, SchedWriteFMA.Scl>,
fma4s_int<0x6A, "vfmaddss", ssmem, v4f32, fma4s_int<0x6A, "vfmaddss", ssmem, v4f32,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86any_Fmsub, loadf32, defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86any_Fmsub, loadf32,
SchedWriteFMA.Scl>, SchedWriteFMA.Scl>,
fma4s_int<0x6E, "vfmsubss", ssmem, v4f32, fma4s_int<0x6E, "vfmsubss", ssmem, v4f32,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
X86any_Fnmadd, loadf32, SchedWriteFMA.Scl>, X86any_Fnmadd, loadf32, SchedWriteFMA.Scl>,
fma4s_int<0x7A, "vfnmaddss", ssmem, v4f32, fma4s_int<0x7A, "vfnmaddss", ssmem, v4f32,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
X86any_Fnmsub, loadf32, SchedWriteFMA.Scl>, X86any_Fnmsub, loadf32, SchedWriteFMA.Scl>,
fma4s_int<0x7E, "vfnmsubss", ssmem, v4f32, fma4s_int<0x7E, "vfnmsubss", ssmem, v4f32,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
// Packed Instructions // Packed Instructions
defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86any_Fmadd, v4f32, v8f32, defm VFMADDPS4 : fma4p<0x68, "vfmaddps", any_fma, v4f32, v8f32,
loadv4f32, loadv8f32, SchedWriteFMA>; loadv4f32, loadv8f32, SchedWriteFMA>;
defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86any_Fmsub, v4f32, v8f32, defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86any_Fmsub, v4f32, v8f32,
loadv4f32, loadv8f32, SchedWriteFMA>; loadv4f32, loadv8f32, SchedWriteFMA>;
defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86any_Fnmadd, v4f32, v8f32, defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86any_Fnmadd, v4f32, v8f32,
loadv4f32, loadv8f32, SchedWriteFMA>; loadv4f32, loadv8f32, SchedWriteFMA>;
defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86any_Fnmsub, v4f32, v8f32, defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86any_Fnmsub, v4f32, v8f32,
loadv4f32, loadv8f32, SchedWriteFMA>; loadv4f32, loadv8f32, SchedWriteFMA>;
defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32, defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
loadv4f32, loadv8f32, SchedWriteFMA>; loadv4f32, loadv8f32, SchedWriteFMA>;
defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32, defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
loadv4f32, loadv8f32, SchedWriteFMA>; loadv4f32, loadv8f32, SchedWriteFMA>;
} }
let ExeDomain = SSEPackedDouble in { let ExeDomain = SSEPackedDouble in {
// Scalar Instructions // Scalar Instructions
defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86any_Fmadd, loadf64, defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, any_fma, loadf64,
SchedWriteFMA.Scl>, SchedWriteFMA.Scl>,
fma4s_int<0x6B, "vfmaddsd", sdmem, v2f64, fma4s_int<0x6B, "vfmaddsd", sdmem, v2f64,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86any_Fmsub, loadf64, defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86any_Fmsub, loadf64,
SchedWriteFMA.Scl>, SchedWriteFMA.Scl>,
fma4s_int<0x6F, "vfmsubsd", sdmem, v2f64, fma4s_int<0x6F, "vfmsubsd", sdmem, v2f64,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
X86any_Fnmadd, loadf64, SchedWriteFMA.Scl>, X86any_Fnmadd, loadf64, SchedWriteFMA.Scl>,
fma4s_int<0x7B, "vfnmaddsd", sdmem, v2f64, fma4s_int<0x7B, "vfnmaddsd", sdmem, v2f64,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64, defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
X86any_Fnmsub, loadf64, SchedWriteFMA.Scl>, X86any_Fnmsub, loadf64, SchedWriteFMA.Scl>,
fma4s_int<0x7F, "vfnmsubsd", sdmem, v2f64, fma4s_int<0x7F, "vfnmsubsd", sdmem, v2f64,
SchedWriteFMA.Scl>; SchedWriteFMA.Scl>;
// Packed Instructions // Packed Instructions
defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86any_Fmadd, v2f64, v4f64, defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", any_fma, v2f64, v4f64,
loadv2f64, loadv4f64, SchedWriteFMA>; loadv2f64, loadv4f64, SchedWriteFMA>;
defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86any_Fmsub, v2f64, v4f64, defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86any_Fmsub, v2f64, v4f64,
loadv2f64, loadv4f64, SchedWriteFMA>; loadv2f64, loadv4f64, SchedWriteFMA>;
defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86any_Fnmadd, v2f64, v4f64, defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86any_Fnmadd, v2f64, v4f64,
loadv2f64, loadv4f64, SchedWriteFMA>; loadv2f64, loadv4f64, SchedWriteFMA>;
defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86any_Fnmsub, v2f64, v4f64, defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86any_Fnmsub, v2f64, v4f64,
loadv2f64, loadv4f64, SchedWriteFMA>; loadv2f64, loadv4f64, SchedWriteFMA>;
defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64, defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
Show All 24 Lines def : Pat<(VT (X86vzmovl (VT (scalar_to_vector
(Op RC:$src1, (mem_frag addr:$src2), (Op RC:$src1, (mem_frag addr:$src2),
RC:$src3))))), RC:$src3))))),
(!cast<Instruction>(Name#"mr_Int") (!cast<Instruction>(Name#"mr_Int")
(VT (COPY_TO_REGCLASS RC:$src1, VR128)), addr:$src2, (VT (COPY_TO_REGCLASS RC:$src1, VR128)), addr:$src2,
(VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
} }
} }
defm : scalar_fma4_patterns<X86any_Fmadd, "VFMADDSS4", v4f32, f32, FR32, loadf32>; defm : scalar_fma4_patterns<any_fma, "VFMADDSS4", v4f32, f32, FR32, loadf32>;
defm : scalar_fma4_patterns<X86any_Fmsub, "VFMSUBSS4", v4f32, f32, FR32, loadf32>; defm : scalar_fma4_patterns<X86any_Fmsub, "VFMSUBSS4", v4f32, f32, FR32, loadf32>;
defm : scalar_fma4_patterns<X86any_Fnmadd, "VFNMADDSS4", v4f32, f32, FR32, loadf32>; defm : scalar_fma4_patterns<X86any_Fnmadd, "VFNMADDSS4", v4f32, f32, FR32, loadf32>;
defm : scalar_fma4_patterns<X86any_Fnmsub, "VFNMSUBSS4", v4f32, f32, FR32, loadf32>; defm : scalar_fma4_patterns<X86any_Fnmsub, "VFNMSUBSS4", v4f32, f32, FR32, loadf32>;
defm : scalar_fma4_patterns<X86any_Fmadd, "VFMADDSD4", v2f64, f64, FR64, loadf64>; defm : scalar_fma4_patterns<any_fma, "VFMADDSD4", v2f64, f64, FR64, loadf64>;
defm : scalar_fma4_patterns<X86any_Fmsub, "VFMSUBSD4", v2f64, f64, FR64, loadf64>; defm : scalar_fma4_patterns<X86any_Fmsub, "VFMSUBSD4", v2f64, f64, FR64, loadf64>;
defm : scalar_fma4_patterns<X86any_Fnmadd, "VFNMADDSD4", v2f64, f64, FR64, loadf64>; defm : scalar_fma4_patterns<X86any_Fnmadd, "VFNMADDSD4", v2f64, f64, FR64, loadf64>;
defm : scalar_fma4_patterns<X86any_Fnmsub, "VFNMSUBSD4", v2f64, f64, FR64, loadf64>; defm : scalar_fma4_patterns<X86any_Fnmsub, "VFNMSUBSD4", v2f64, f64, FR64, loadf64>;

llvm/lib/Target/X86/X86InstrFragmentsSIMD.td

Show First 20 Lines • Show All 534 Lines • ▼ Show 20 Lines
def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>; def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
def X86fgetexp : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>; def X86fgetexp : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>;
def X86fgetexpSAE : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>; def X86fgetexpSAE : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>;
def X86fgetexps : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>; def X86fgetexps : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>;
def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>; def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>;
def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>; def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>;
def X86strict_Fmadd : SDNode<"ISD::STRICT_FMA", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; def X86strict_Fmadd : SDNode<"ISD::STRICT_FMA", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
def X86any_Fmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[(X86strict_Fmadd node:$src1, node:$src2, node:$src3),
(X86Fmadd node:$src1, node:$src2, node:$src3)]>;
def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>;
def X86strict_Fnmadd : SDNode<"X86ISD::STRICT_FNMADD", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; def X86strict_Fnmadd : SDNode<"X86ISD::STRICT_FNMADD", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3), def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[(X86strict_Fnmadd node:$src1, node:$src2, node:$src3), [(X86strict_Fnmadd node:$src1, node:$src2, node:$src3),
(X86Fnmadd node:$src1, node:$src2, node:$src3)]>; (X86Fnmadd node:$src1, node:$src2, node:$src3)]>;
def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>; def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
def X86strict_Fmsub : SDNode<"X86ISD::STRICT_FMSUB", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; def X86strict_Fmsub : SDNode<"X86ISD::STRICT_FMSUB", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3), def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir

Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Lines
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: test_rule96_id2146_at_idx8070 ; CHECK-LABEL: name: test_rule96_id2146_at_idx8070
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1) ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1)
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[LDRBui]] ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[LDRBui]]
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY2]], 0, 0 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 0
; CHECK: $noreg = PATCHABLE_RET [[UBFMWri]] ; CHECK: $noreg = PATCHABLE_RET [[UBFMWri]]
%2:gpr(p0) = COPY $x0 %2:gpr(p0) = COPY $x0
%0:fpr(s1) = G_LOAD %2(p0) :: (load 1) %0:fpr(s1) = G_LOAD %2(p0) :: (load 1)
%1:gpr(s32) = G_ZEXT %0(s1) %1:gpr(s32) = G_ZEXT %0(s1)
$noreg = PATCHABLE_RET %1(s32) $noreg = PATCHABLE_RET %1(s32)
... ...
--- ---
▲ Show 20 Lines • Show All 247 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $s0, $s1, $s2 liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_rule341_id2371_at_idx26820 ; CHECK-LABEL: name: test_rule341_id2371_at_idx26820
; CHECK: liveins: $s0, $s1, $s2 ; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]] ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
%5:fpr(s32) = COPY $s2 %5:fpr(s32) = COPY $s2
%4:fpr(s32) = COPY $s1 %4:fpr(s32) = COPY $s1
%3:fpr(s32) = COPY $s0 %3:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FNEG %5 %1:fpr(s32) = G_FNEG %5
%0:fpr(s32) = G_FNEG %4 %0:fpr(s32) = G_FNEG %4
%2:fpr(s32) = G_FMA %3, %0, %1 %2:fpr(s32) = G_FMA %3, %0, %1
$noreg = PATCHABLE_RET %2(s32) $noreg = PATCHABLE_RET %2(s32)
Show All 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule342_id2372_at_idx26926 ; CHECK-LABEL: name: test_rule342_id2372_at_idx26926
; CHECK: liveins: $d0, $d1, $d2 ; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]] ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
%5:fpr(s64) = COPY $d2 %5:fpr(s64) = COPY $d2
%4:fpr(s64) = COPY $d1 %4:fpr(s64) = COPY $d1
%3:fpr(s64) = COPY $d0 %3:fpr(s64) = COPY $d0
%1:fpr(s64) = G_FNEG %5 %1:fpr(s64) = G_FNEG %5
%0:fpr(s64) = G_FNEG %4 %0:fpr(s64) = G_FNEG %4
%2:fpr(s64) = G_FMA %3, %0, %1 %2:fpr(s64) = G_FMA %3, %0, %1
$noreg = PATCHABLE_RET %2(s64) $noreg = PATCHABLE_RET %2(s64)
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bb.0.entry: bb.0.entry:
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule930_id2446_at_idx60191 ; CHECK-LABEL: name: test_rule930_id2446_at_idx60191
; CHECK: liveins: $d0, $d1, $d2 ; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY]], [[COPY2]] ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]] ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
%4:fpr(<2 x s32>) = COPY $d2 %4:fpr(<2 x s32>) = COPY $d2
%3:fpr(<2 x s32>) = COPY $d1 %3:fpr(<2 x s32>) = COPY $d1
%2:fpr(<2 x s32>) = COPY $d0 %2:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FNEG %4 %0:fpr(<2 x s32>) = G_FNEG %4
%1:fpr(<2 x s32>) = G_FMA %0, %2, %3 %1:fpr(<2 x s32>) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(<2 x s32>) $noreg = PATCHABLE_RET %1(<2 x s32>)
Show All 18 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule931_id2447_at_idx60277 ; CHECK-LABEL: name: test_rule931_id2447_at_idx60277
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY]], [[COPY2]] ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]] ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
%4:fpr(<4 x s32>) = COPY $q2 %4:fpr(<4 x s32>) = COPY $q2
%3:fpr(<4 x s32>) = COPY $q1 %3:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = COPY $q0 %2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FNEG %4 %0:fpr(<4 x s32>) = G_FNEG %4
%1:fpr(<4 x s32>) = G_FMA %0, %2, %3 %1:fpr(<4 x s32>) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(<4 x s32>) $noreg = PATCHABLE_RET %1(<4 x s32>)
Show All 18 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule932_id2448_at_idx60363 ; CHECK-LABEL: name: test_rule932_id2448_at_idx60363
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY]], [[COPY2]] ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]] ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
%4:fpr(<2 x s64>) = COPY $q2 %4:fpr(<2 x s64>) = COPY $q2
%3:fpr(<2 x s64>) = COPY $q1 %3:fpr(<2 x s64>) = COPY $q1
%2:fpr(<2 x s64>) = COPY $q0 %2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FNEG %4 %0:fpr(<2 x s64>) = G_FNEG %4
%1:fpr(<2 x s64>) = G_FMA %0, %2, %3 %1:fpr(<2 x s64>) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(<2 x s64>) $noreg = PATCHABLE_RET %1(<2 x s64>)
▲ Show 20 Lines • Show All 3,394 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-vmul.ll

Show First 20 Lines • Show All 719 Lines • ▼ Show 20 Lines
} }
define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
; CHECK-LABEL: fmls_commuted_neg_2s: ; CHECK-LABEL: fmls_commuted_neg_2s:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: ldr d2, [x1] ; CHECK-NEXT: ldr d2, [x1]
; CHECK-NEXT: ldr d0, [x2] ; CHECK-NEXT: ldr d0, [x2]
; CHECK-NEXT: fmls.2s v0, v2, v1 ; CHECK-NEXT: fmls.2s v0, v1, v2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x float>, <2 x float>* %A %tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = load <2 x float>, <2 x float>* %B %tmp2 = load <2 x float>, <2 x float>* %B
%tmp3 = load <2 x float>, <2 x float>* %C %tmp3 = load <2 x float>, <2 x float>* %C
%tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2 %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2
%tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp4, <2 x float> %tmp1, <2 x float> %tmp3) %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp4, <2 x float> %tmp1, <2 x float> %tmp3)
ret <2 x float> %tmp5 ret <2 x float> %tmp5
} }
define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
; CHECK-LABEL: fmls_commuted_neg_4s: ; CHECK-LABEL: fmls_commuted_neg_4s:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr q2, [x1] ; CHECK-NEXT: ldr q2, [x1]
; CHECK-NEXT: ldr q0, [x2] ; CHECK-NEXT: ldr q0, [x2]
; CHECK-NEXT: fmls.4s v0, v2, v1 ; CHECK-NEXT: fmls.4s v0, v1, v2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x float>, <4 x float>* %A %tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B %tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = load <4 x float>, <4 x float>* %C %tmp3 = load <4 x float>, <4 x float>* %C
%tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2 %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2
%tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp4, <4 x float> %tmp1, <4 x float> %tmp3) %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp4, <4 x float> %tmp1, <4 x float> %tmp3)
ret <4 x float> %tmp5 ret <4 x float> %tmp5
} }
define <2 x double> @fmls_commuted_neg_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind { define <2 x double> @fmls_commuted_neg_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
; CHECK-LABEL: fmls_commuted_neg_2d: ; CHECK-LABEL: fmls_commuted_neg_2d:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: ldr q1, [x0]
; CHECK-NEXT: ldr q2, [x1] ; CHECK-NEXT: ldr q2, [x1]
; CHECK-NEXT: ldr q0, [x2] ; CHECK-NEXT: ldr q0, [x2]
; CHECK-NEXT: fmls.2d v0, v2, v1 ; CHECK-NEXT: fmls.2d v0, v1, v2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x double>, <2 x double>* %A %tmp1 = load <2 x double>, <2 x double>* %A
%tmp2 = load <2 x double>, <2 x double>* %B %tmp2 = load <2 x double>, <2 x double>* %B
%tmp3 = load <2 x double>, <2 x double>* %C %tmp3 = load <2 x double>, <2 x double>* %C
%tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2 %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2
%tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp4, <2 x double> %tmp1, <2 x double> %tmp3) %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp4, <2 x double> %tmp1, <2 x double> %tmp3)
ret <2 x double> %tmp5 ret <2 x double> %tmp5
} }
▲ Show 20 Lines • Show All 1,957 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

Show First 20 Lines • Show All 634 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_vfmsd ; CHECK-LABEL: name: test_vfmsd
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg ; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VFMSD]] ; CHECK: $d0 = COPY [[VFMSD]]
; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0 %0(s64) = COPY $d0
%1(s64) = COPY $d1 %1(s64) = COPY $d1
%2(s64) = COPY $d2 %2(s64) = COPY $d2
%3(s64) = G_FNEG %1 %3(s64) = G_FNEG %1
%4(s64) = G_FMA %0, %3, %2 %4(s64) = G_FMA %0, %3, %2
▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir

Show All 25 Lines
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: vfnmsd ; CHECK-LABEL: name: vfnmsd
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
; CHECK: $d0 = COPY [[VFNMSD]] ; CHECK: $d0 = COPY [[VFNMSD]]
; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0 ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0
%0:fprb(s64) = COPY $d0 %0:fprb(s64) = COPY $d0
%1:fprb(s64) = COPY $d1 %1:fprb(s64) = COPY $d1
%2:fprb(s64) = COPY $d2 %2:fprb(s64) = COPY $d2
%3:fprb(s64) = G_FNEG %1 %3:fprb(s64) = G_FNEG %1
%4:fprb(s64) = G_FMA %0, %3, %2 %4:fprb(s64) = G_FMA %0, %3, %2
%5:fprb(s64) = G_FNEG %4 %5:fprb(s64) = G_FNEG %4
$d0 = COPY %5(s64) $d0 = COPY %5(s64)
MOVPCLR 14, $noreg, implicit $d0 MOVPCLR 14, $noreg, implicit $d0
... ...

llvm/test/CodeGen/ARM/fp16-fusedMAC.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Lines; DONT-FUSE-NEXT: bx lr
%ret = call half @llvm.fma.f16(half %s, half %f2, half %f3) %ret = call half @llvm.fma.f16(half %s, half %f2, half %f3)
store half %ret, half *%a1, align 2 store half %ret, half *%a1, align 2
ret void ret void
} }
define arm_aapcs_vfpcc void @fms2(half *%a1, half *%a2, half *%a3) { define arm_aapcs_vfpcc void @fms2(half *%a1, half *%a2, half *%a3) {
; CHECK-LABEL: fms2: ; CHECK-LABEL: fms2:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r0] ; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vldr.16 s2, [r1] ; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vldr.16 s4, [r2] ; CHECK-NEXT: vldr.16 s4, [r2]
; CHECK-NEXT: vfms.f16 s4, s2, s0 ; CHECK-NEXT: vfms.f16 s4, s2, s0
; CHECK-NEXT: vstr.16 s4, [r0] ; CHECK-NEXT: vstr.16 s4, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; DONT-FUSE-LABEL: fms2: ; DONT-FUSE-LABEL: fms2:
; DONT-FUSE: @ %bb.0: ; DONT-FUSE: @ %bb.0:
; DONT-FUSE-NEXT: vldr.16 s0, [r0] ; DONT-FUSE-NEXT: vldr.16 s0, [r1]
; DONT-FUSE-NEXT: vldr.16 s2, [r1] ; DONT-FUSE-NEXT: vldr.16 s2, [r0]
; DONT-FUSE-NEXT: vldr.16 s4, [r2] ; DONT-FUSE-NEXT: vldr.16 s4, [r2]
; DONT-FUSE-NEXT: vfms.f16 s4, s2, s0 ; DONT-FUSE-NEXT: vfms.f16 s4, s2, s0
; DONT-FUSE-NEXT: vstr.16 s4, [r0] ; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr ; DONT-FUSE-NEXT: bx lr
%f1 = load half, half *%a1, align 2 %f1 = load half, half *%a1, align 2
%f2 = load half, half *%a2, align 2 %f2 = load half, half *%a2, align 2
%f3 = load half, half *%a3, align 2 %f3 = load half, half *%a3, align 2
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; DONT-FUSE-NEXT: bx lr
%n = fsub half -0.0, %fma %n = fsub half -0.0, %fma
store half %n, half *%a1, align 2 store half %n, half *%a1, align 2
ret void ret void
} }
define arm_aapcs_vfpcc void @fnms3(half *%a1, half *%a2, half *%a3) { define arm_aapcs_vfpcc void @fnms3(half *%a1, half *%a2, half *%a3) {
; CHECK-LABEL: fnms3: ; CHECK-LABEL: fnms3:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vldr.16 s0, [r1] ; CHECK-NEXT: vldr.16 s0, [r0]
; CHECK-NEXT: vldr.16 s2, [r0] ; CHECK-NEXT: vldr.16 s2, [r1]
; CHECK-NEXT: vldr.16 s4, [r2] ; CHECK-NEXT: vldr.16 s4, [r2]
; CHECK-NEXT: vfnms.f16 s4, s2, s0 ; CHECK-NEXT: vfnms.f16 s4, s2, s0
; CHECK-NEXT: vstr.16 s4, [r0] ; CHECK-NEXT: vstr.16 s4, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; DONT-FUSE-LABEL: fnms3: ; DONT-FUSE-LABEL: fnms3:
; DONT-FUSE: @ %bb.0: ; DONT-FUSE: @ %bb.0:
; DONT-FUSE-NEXT: vldr.16 s0, [r1] ; DONT-FUSE-NEXT: vldr.16 s0, [r0]
; DONT-FUSE-NEXT: vldr.16 s2, [r0] ; DONT-FUSE-NEXT: vldr.16 s2, [r1]
; DONT-FUSE-NEXT: vldr.16 s4, [r2] ; DONT-FUSE-NEXT: vldr.16 s4, [r2]
; DONT-FUSE-NEXT: vfnms.f16 s4, s2, s0 ; DONT-FUSE-NEXT: vfnms.f16 s4, s2, s0
; DONT-FUSE-NEXT: vstr.16 s4, [r0] ; DONT-FUSE-NEXT: vstr.16 s4, [r0]
; DONT-FUSE-NEXT: bx lr ; DONT-FUSE-NEXT: bx lr
%f1 = load half, half *%a1, align 2 %f1 = load half, half *%a1, align 2
%f2 = load half, half *%a2, align 2 %f2 = load half, half *%a2, align 2
%f3 = load half, half *%a3, align 2 %f3 = load half, half *%a3, align 2
Show All 9 Lines

llvm/test/CodeGen/RISCV/double-arith.ll

Show First 20 Lines • Show All 537 Lines • ▼ Show 20 Lines
; RV32IFD-NEXT: sw a5, 12(sp) ; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp) ; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fcvt.d.w ft3, zero ; RV32IFD-NEXT: fcvt.d.w ft3, zero
; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 ; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
; RV32IFD-NEXT: fadd.d ft1, ft1, ft3 ; RV32IFD-NEXT: fadd.d ft1, ft1, ft3
; RV32IFD-NEXT: fnmadd.d ft0, ft0, ft2, ft1 ; RV32IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmadd_d_2: ; RV64IFD-LABEL: fnmadd_d_2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a2 ; RV64IFD-NEXT: fmv.d.x ft1, a2
; RV64IFD-NEXT: fmv.d.x ft2, a1 ; RV64IFD-NEXT: fmv.d.x ft2, a1
; RV64IFD-NEXT: fmv.d.x ft3, zero ; RV64IFD-NEXT: fmv.d.x ft3, zero
; RV64IFD-NEXT: fadd.d ft2, ft2, ft3 ; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
; RV64IFD-NEXT: fadd.d ft1, ft1, ft3 ; RV64IFD-NEXT: fadd.d ft1, ft1, ft3
; RV64IFD-NEXT: fnmadd.d ft0, ft0, ft2, ft1 ; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%b_ = fadd double 0.0, %b %b_ = fadd double 0.0, %b
%c_ = fadd double 0.0, %c %c_ = fadd double 0.0, %c
%negb = fsub double -0.0, %b_ %negb = fsub double -0.0, %b_
%negc = fsub double -0.0, %c_ %negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %a, double %negb, double %negc) %1 = call double @llvm.fma.f64(double %a, double %negb, double %negc)
ret double %1 ret double %1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp) ; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fcvt.d.w ft3, zero ; RV32IFD-NEXT: fcvt.d.w ft3, zero
; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 ; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
; RV32IFD-NEXT: fnmsub.d ft0, ft1, ft2, ft0 ; RV32IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fnmsub_d_2: ; RV64IFD-LABEL: fnmsub_d_2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2 ; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fmv.d.x ft2, a1 ; RV64IFD-NEXT: fmv.d.x ft2, a1
; RV64IFD-NEXT: fmv.d.x ft3, zero ; RV64IFD-NEXT: fmv.d.x ft3, zero
; RV64IFD-NEXT: fadd.d ft2, ft2, ft3 ; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
; RV64IFD-NEXT: fnmsub.d ft0, ft1, ft2, ft0 ; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%b_ = fadd double 0.0, %b %b_ = fadd double 0.0, %b
%negb = fsub double -0.0, %b_ %negb = fsub double -0.0, %b_
%1 = call double @llvm.fma.f64(double %a, double %negb, double %c) %1 = call double @llvm.fma.f64(double %a, double %negb, double %c)
ret double %1 ret double %1
} }

llvm/test/CodeGen/RISCV/float-arith.ll

Show First 20 Lines • Show All 399 Lines • ▼ Show 20 Lines
; RV32IF-LABEL: fnmadd_s_2: ; RV32IF-LABEL: fnmadd_s_2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a2 ; RV32IF-NEXT: fmv.w.x ft1, a2
; RV32IF-NEXT: fmv.w.x ft2, a1 ; RV32IF-NEXT: fmv.w.x ft2, a1
; RV32IF-NEXT: fmv.w.x ft3, zero ; RV32IF-NEXT: fmv.w.x ft3, zero
; RV32IF-NEXT: fadd.s ft2, ft2, ft3 ; RV32IF-NEXT: fadd.s ft2, ft2, ft3
; RV32IF-NEXT: fadd.s ft1, ft1, ft3 ; RV32IF-NEXT: fadd.s ft1, ft1, ft3
; RV32IF-NEXT: fnmadd.s ft0, ft0, ft2, ft1 ; RV32IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmadd_s_2: ; RV64IF-LABEL: fnmadd_s_2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a2 ; RV64IF-NEXT: fmv.w.x ft1, a2
; RV64IF-NEXT: fmv.w.x ft2, a1 ; RV64IF-NEXT: fmv.w.x ft2, a1
; RV64IF-NEXT: fmv.w.x ft3, zero ; RV64IF-NEXT: fmv.w.x ft3, zero
; RV64IF-NEXT: fadd.s ft2, ft2, ft3 ; RV64IF-NEXT: fadd.s ft2, ft2, ft3
; RV64IF-NEXT: fadd.s ft1, ft1, ft3 ; RV64IF-NEXT: fadd.s ft1, ft1, ft3
; RV64IF-NEXT: fnmadd.s ft0, ft0, ft2, ft1 ; RV64IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%b_ = fadd float 0.0, %b %b_ = fadd float 0.0, %b
%c_ = fadd float 0.0, %c %c_ = fadd float 0.0, %c
%negb = fsub float -0.0, %b_ %negb = fsub float -0.0, %b_
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %negb, float %negc) %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
ret float %1 ret float %1
Show All 30 Lines
define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s_2: ; RV32IF-LABEL: fnmsub_s_2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2 ; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fmv.w.x ft2, a1 ; RV32IF-NEXT: fmv.w.x ft2, a1
; RV32IF-NEXT: fmv.w.x ft3, zero ; RV32IF-NEXT: fmv.w.x ft3, zero
; RV32IF-NEXT: fadd.s ft2, ft2, ft3 ; RV32IF-NEXT: fadd.s ft2, ft2, ft3
; RV32IF-NEXT: fnmsub.s ft0, ft1, ft2, ft0 ; RV32IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fnmsub_s_2: ; RV64IF-LABEL: fnmsub_s_2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2 ; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fmv.w.x ft2, a1 ; RV64IF-NEXT: fmv.w.x ft2, a1
; RV64IF-NEXT: fmv.w.x ft3, zero ; RV64IF-NEXT: fmv.w.x ft3, zero
; RV64IF-NEXT: fadd.s ft2, ft2, ft3 ; RV64IF-NEXT: fadd.s ft2, ft2, ft3
; RV64IF-NEXT: fnmsub.s ft0, ft1, ft2, ft0 ; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%b_ = fadd float 0.0, %b %b_ = fadd float 0.0, %b
%negb = fsub float -0.0, %b_ %negb = fsub float -0.0, %b_
%1 = call float @llvm.fma.f32(float %a, float %negb, float %c) %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
ret float %1 ret float %1
} }

llvm/test/CodeGen/Thumb2/mve-float32regloops.ll

Show First 20 Lines • Show All 1,586 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ldr r4, [r2] ; CHECK-NEXT: ldr r4, [r2]
; CHECK-NEXT: dls lr, r5 ; CHECK-NEXT: dls lr, r5
; CHECK-NEXT: vdup.32 q0, r4 ; CHECK-NEXT: vdup.32 q0, r4
; CHECK-NEXT: .LBB18_3: @ %while.body ; CHECK-NEXT: .LBB18_3: @ %while.body
; CHECK-NEXT: @ Parent Loop BB18_2 Depth=1 ; CHECK-NEXT: @ Parent Loop BB18_2 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: vldrw.u32 q2, [r0], #16 ; CHECK-NEXT: vldrw.u32 q2, [r0], #16
; CHECK-NEXT: vfms.f32 q2, q0, q1 ; CHECK-NEXT: vfms.f32 q2, q1, q0
; CHECK-NEXT: vstrb.8 q2, [r3], #16 ; CHECK-NEXT: vstrb.8 q2, [r3], #16
; CHECK-NEXT: le lr, .LBB18_3 ; CHECK-NEXT: le lr, .LBB18_3
; CHECK-NEXT: @ %bb.4: @ %while.end ; CHECK-NEXT: @ %bb.4: @ %while.end
; CHECK-NEXT: @ in Loop: Header=BB18_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB18_2 Depth=1
; CHECK-NEXT: subs.w r12, r12, #1 ; CHECK-NEXT: subs.w r12, r12, #1
; CHECK-NEXT: add.w r2, r2, #4 ; CHECK-NEXT: add.w r2, r2, #4
; CHECK-NEXT: bne .LBB18_2 ; CHECK-NEXT: bne .LBB18_2
; CHECK-NEXT: .LBB18_5: @ %do.end ; CHECK-NEXT: .LBB18_5: @ %do.end
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llvm/test/CodeGen/Thumb2/mve-fma-loops.ll

Show First 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov r4, s0 ; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vdup.32 q0, r4 ; CHECK-NEXT: vdup.32 q0, r4
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: dlstp.32 lr, r3 ; CHECK-NEXT: dlstp.32 lr, r3
; CHECK-NEXT: .LBB6_2: @ %vector.body ; CHECK-NEXT: .LBB6_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add.w r12, r12, #4 ; CHECK-NEXT: add.w r12, r12, #4
; CHECK-NEXT: vmov q3, q0 ; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r0], #16 ; CHECK-NEXT: vldrw.u32 q2, [r1], #16
; CHECK-NEXT: vfms.f32 q3, q2, q1 ; CHECK-NEXT: vfms.f32 q3, q2, q1
; CHECK-NEXT: vstrw.32 q3, [r2], #16 ; CHECK-NEXT: vstrw.32 q3, [r2], #16
; CHECK-NEXT: letp lr, .LBB6_2 ; CHECK-NEXT: letp lr, .LBB6_2
; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
entry: entry:
%cmp8 = icmp sgt i32 %n, 0 %cmp8 = icmp sgt i32 %n, 0
br i1 %cmp8, label %vector.ph, label %for.cond.cleanup br i1 %cmp8, label %vector.ph, label %for.cond.cleanup
▲ Show 20 Lines • Show All 369 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Linesentry:
%.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
%0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %.splat) %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %.splat)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) { define arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
; CHECK-LABEL: test_vfmsq_f16: ; CHECK-LABEL: test_vfmsq_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vfms.f16 q0, q1, q2 ; CHECK-NEXT: vfms.f16 q0, q2, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = fneg <8 x half> %c %0 = fneg <8 x half> %c
%1 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %0, <8 x half> %a) %1 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %0, <8 x half> %a)
ret <8 x half> %1 ret <8 x half> %1
} }
define arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { define arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: test_vfmsq_f32: ; CHECK-LABEL: test_vfmsq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vfms.f32 q0, q1, q2 ; CHECK-NEXT: vfms.f32 q0, q2, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = fneg <4 x float> %c %0 = fneg <4 x float> %c
%1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %0, <4 x float> %a) %1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %0, <4 x float> %a)
ret <4 x float> %1 ret <4 x float> %1
} }
define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) { define arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> %a, <16 x i8> %b, i8 signext %c) {
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