[RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions.

[craig.topper]

Summary

fsl/fsr take their shift amount in $rs2 or an immediate. The
sources are $rs1 and $rs3.

fshl/fshr ISD opcodes both concatenate operand 0 in the high bits and
operand 1 in the lower bits. fshl returns the high bits after
shifting and fshr returns the low bits. So a shift amount of 0
returns operand 0 for fshl and operand 1 for fshr.

fsl/fsr concatenate their operands in different orders such that
$rs1 will be returned for a shift amount of 0. So $rs1 needs to
come from operand 0 of fshl and operand 1 of fshr.

[frasercrmck]

LGTM

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

828–829

Looks like I still missed swapping $rs1 and $rs3 here for FSRI. I'll fix it in the commit.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def : Pat<(bitreverse GPR:$rs1), (GREVI GPR:$rs1, (i64 63))>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(or (and (xor GPR:$rs2, -1), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
           (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(riscv_selectcc GPR:$rs2, (XLenVT 0), (XLenVT 17), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(fshl GPR:$rs1, GPR:$rs2, GPR:$rs3),
+
+// fshl and fshr concatenate their operands in the same order. fsr and fsl
+// instruction use different orders. fshl will return its first operand for
+// shift of zero, fshr will return its second operand. fsl and fsr both return
+// $rs1 so the patterns need to have different operand orders.
+def : Pat<(fshl GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(fshr GPR:$rs1, GPR:$rs2, GPR:$rs3),
+def : Pat<(fshr GPR:$rs3, GPR:$rs1, GPR:$rs2),
           (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(fshr GPR:$rs1, GPR:$rs2, uimmlog2xlen:$shamt),
-          (FSRI GPR:$rs1, GPR:$rs2, uimmlog2xlen:$shamt)>;
+def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
+          (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbb] in {
 def : Pat<(ctlz GPR:$rs1), (CLZ GPR:$rs1)>;
 def : Pat<(cttz GPR:$rs1), (CTZ GPR:$rs1)>;
 def : Pat<(ctpop GPR:$rs1), (PCNT GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb]
 
def : Pat<(sext_inreg (or (shl GPR:$rs1, (i64 16)),
                           (srl (and GPR:$rs1, 0xFFFF0000), (i64 16))), i32),
           (GREVIW GPR:$rs1, (i64 16))>;
 def : Pat<(sra (bswap GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 24))>;
 def : Pat<(sra (bitreverse GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 31))>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
 def : Pat<(sext_inreg (fshl (assertsexti32 GPR:$rs1),
-                            (shl (assertsexti32 GPR:$rs2), (i64 32)),
-                            (and (assertsexti32 GPR:$rs3), (i64 31))),
+                            (shl (assertsexti32 GPR:$rs3), (i64 32)),
+                            (and (assertsexti32 GPR:$rs2), (i64 31))),
                       i32),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs1),
-                            (shl (assertsexti32 GPR:$rs2), (i64 32)),
-                            (or (assertsexti32 GPR:$rs3), (i64 32))),
+def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3),
+                            (shl (assertsexti32 GPR:$rs1), (i64 32)),
+                            (or (assertsexti32 GPR:$rs2), (i64 32))),
                       i32),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
-def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs1),
-                            (shl (assertsexti32 GPR:$rs2), (i64 32)),
+def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3),
+                            (shl (assertsexti32 GPR:$rs1), (i64 32)),
                             uimm6gt32:$shamt),
                       i32),
-          (FSRIW GPR:$rs1, GPR:$rs2, (ImmSub32 uimm6gt32:$shamt))>;
+          (FSRIW GPR:$rs1, GPR:$rs3, (ImmSub32 uimm6gt32:$shamt))>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
           (CLZW GPR:$rs1)>;
 // We don't pattern-match CTZW here as it has the same pattern and result as
 // RV64 CTZ
 def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (PCNTW GPR:$rs1)>;

llvm/test/CodeGen/RISCV/rv32Zbb.ll

 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    ori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sloi_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a2, zero, 1
-; RV32IB-NEXT:    fsl a1, a1, a2, a0
+; RV32IB-NEXT:    fsl a1, a1, a0, a2
 ; RV32IB-NEXT:    sloi a0, a0, 1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: sloi_i64:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    srli a2, a0, 31
 ; RV32IBB-NEXT:    slli a1, a1, 1
 ; RV32IBB-NEXT:    or a1, a1, a2

 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sroi_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a2, zero, 31
-; RV32IB-NEXT:    fsl a0, a1, a2, a0
+; RV32IB-NEXT:    fsl a0, a1, a0, a2
 ; RV32IB-NEXT:    sroi a1, a1, 1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: sroi_i64:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    slli a2, a1, 31
 ; RV32IBB-NEXT:    srli a0, a0, 1
 ; RV32IBB-NEXT:    or a0, a0, a2

llvm/test/CodeGen/RISCV/rv32Zbbp.ll

 ; RV32I-NEXT:    slli a0, a0, 31
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: rori_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a3, zero, 31
-; RV32IB-NEXT:    fsl a2, a1, a3, a0
-; RV32IB-NEXT:    fsl a1, a0, a3, a1
+; RV32IB-NEXT:    fsl a2, a1, a0, a3
+; RV32IB-NEXT:    fsl a1, a0, a1, a3
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: rori_i64:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    slli a2, a1, 31
 ; RV32IBB-NEXT:    srli a3, a0, 1
 ; RV32IBB-NEXT:    or a2, a3, a2

 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: rori_i64_fshr:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a3, zero, 1
-; RV32IB-NEXT:    fsl a2, a0, a3, a1
-; RV32IB-NEXT:    fsl a1, a1, a3, a0
+; RV32IB-NEXT:    fsl a2, a0, a1, a3
+; RV32IB-NEXT:    fsl a1, a1, a0, a3
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: rori_i64_fshr:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    slli a2, a0, 1
 ; RV32IBB-NEXT:    srli a3, a1, 31
 ; RV32IBB-NEXT:    or a2, a3, a2

llvm/test/CodeGen/RISCV/rv32Zbt.ll

 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    srl a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshl_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    fsl a0, a0, a2, a1
+; RV32IB-NEXT:    fsl a0, a0, a1, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshl_i32:
 ; RV32IBT:       # %bb.0:
-; RV32IBT-NEXT:    fsl a0, a0, a2, a1
+; RV32IBT-NEXT:    fsl a0, a0, a1, a2
 ; RV32IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet an efficient pattern-matching with bit manipulation
 ; instructions on RV32.

 ; RV32IB-NEXT:    andn a5, a1, a4
 ; RV32IB-NEXT:    addi a1, a5, -32
 ; RV32IB-NEXT:    srli t3, a3, 1
 ; RV32IB-NEXT:    bltz a1, .LBB5_7
 ; RV32IB-NEXT:  # %bb.4:
 ; RV32IB-NEXT:    mv t0, zero
 ; RV32IB-NEXT:    bgez a1, .LBB5_8
 ; RV32IB-NEXT:  .LBB5_5:
-; RV32IB-NEXT:    fsl a1, a3, a6, a2
+; RV32IB-NEXT:    fsl a1, a3, a2, a6
 ; RV32IB-NEXT:    srl a1, a1, t1
 ; RV32IB-NEXT:    sub a2, a6, a5
 ; RV32IB-NEXT:    slli a3, t3, 1
 ; RV32IB-NEXT:    sll a2, a3, a2
 ; RV32IB-NEXT:    or a2, a1, a2
 ; RV32IB-NEXT:    or a1, a7, t0
 ; RV32IB-NEXT:    bgez t2, .LBB5_9
 ; RV32IB-NEXT:  .LBB5_6:

 ; RV32IBT-NEXT:    andi t3, a1, 63
 ; RV32IBT-NEXT:    addi a5, t3, -32
 ; RV32IBT-NEXT:    srli t2, a3, 1
 ; RV32IBT-NEXT:    bltz a5, .LBB5_7
 ; RV32IBT-NEXT:  # %bb.4:
 ; RV32IBT-NEXT:    mv t0, zero
 ; RV32IBT-NEXT:    bgez a5, .LBB5_8
 ; RV32IBT-NEXT:  .LBB5_5:
-; RV32IBT-NEXT:    fsl a2, a3, a6, a2
+; RV32IBT-NEXT:    fsl a2, a3, a2, a6
 ; RV32IBT-NEXT:    srl a1, a2, a1
 ; RV32IBT-NEXT:    sub a2, a6, t3
 ; RV32IBT-NEXT:    slli a3, t2, 1
 ; RV32IBT-NEXT:    sll a2, a3, a2
 ; RV32IBT-NEXT:    or a2, a1, a2
 ; RV32IBT-NEXT:    or a1, a7, t0
 ; RV32IBT-NEXT:    bgez t1, .LBB5_9
 ; RV32IBT-NEXT:  .LBB5_6:

 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    sll a0, a0, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshr_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    fsr a0, a0, a2, a1
+; RV32IB-NEXT:    fsr a0, a1, a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshr_i32:
 ; RV32IBT:       # %bb.0:
-; RV32IBT-NEXT:    fsr a0, a0, a2, a1
+; RV32IBT-NEXT:    fsr a0, a1, a0, a2
 ; RV32IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet an efficient pattern-matching with bit manipulation
 ; instructions on RV32.

 ; RV32IB-NEXT:    addi a5, a2, -32
 ; RV32IB-NEXT:    slli t3, a0, 1
 ; RV32IB-NEXT:    bltz a5, .LBB7_7
 ; RV32IB-NEXT:  # %bb.4:
 ; RV32IB-NEXT:    mv t0, zero
 ; RV32IB-NEXT:    bgez a5, .LBB7_8
 ; RV32IB-NEXT:  .LBB7_5:
 ; RV32IB-NEXT:    addi a5, zero, 1
-; RV32IB-NEXT:    fsl a1, a1, a5, a0
+; RV32IB-NEXT:    fsl a1, a1, a0, a5
 ; RV32IB-NEXT:    sll a1, a1, t1
 ; RV32IB-NEXT:    sub a2, a6, a2
 ; RV32IB-NEXT:    lui a5, 524288
 ; RV32IB-NEXT:    addi a5, a5, -1
 ; RV32IB-NEXT:    and a0, a0, a5
 ; RV32IB-NEXT:    srl a0, a0, a2
 ; RV32IB-NEXT:    or a1, a1, a0
 ; RV32IB-NEXT:    or a0, t0, a7

 ; RV32IBT-NEXT:    addi t2, t1, -32
 ; RV32IBT-NEXT:    slli a6, a0, 1
 ; RV32IBT-NEXT:    bltz t2, .LBB7_2
 ; RV32IBT-NEXT:  # %bb.1:
 ; RV32IBT-NEXT:    sll t1, a6, t2
 ; RV32IBT-NEXT:    j .LBB7_3
 ; RV32IBT-NEXT:  .LBB7_2:
 ; RV32IBT-NEXT:    addi a5, zero, 1
-; RV32IBT-NEXT:    fsl a1, a1, a5, a0
+; RV32IBT-NEXT:    fsl a1, a1, a0, a5
 ; RV32IBT-NEXT:    sll a1, a1, a7
 ; RV32IBT-NEXT:    lui a5, 524288
 ; RV32IBT-NEXT:    addi a5, a5, -1
 ; RV32IBT-NEXT:    and a0, a0, a5
 ; RV32IBT-NEXT:    sub a5, t0, t1
 ; RV32IBT-NEXT:    srl a0, a0, a5
 ; RV32IBT-NEXT:    or t1, a1, a0
 ; RV32IBT-NEXT:  .LBB7_3:

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a1, a1, 5
 ; RV32I-NEXT:    slli a0, a0, 27
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshri_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    fsri a0, a0, a1, 5
+; RV32IB-NEXT:    fsri a0, a1, a0, 5
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshri_i32:
 ; RV32IBT:       # %bb.0:
-; RV32IBT-NEXT:    fsri a0, a0, a1, 5
+; RV32IBT-NEXT:    fsri a0, a1, a0, 5
 ; RV32IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
   ret i32 %1
 }
 
 define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: fshri_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a3, 27
 ; RV32I-NEXT:    srli a2, a2, 5
 ; RV32I-NEXT:    or a2, a2, a1
 ; RV32I-NEXT:    srli a1, a3, 5
 ; RV32I-NEXT:    slli a0, a0, 27
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshri_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a1, zero, 27
-; RV32IB-NEXT:    fsl a2, a3, a1, a2
-; RV32IB-NEXT:    fsl a1, a0, a1, a3
+; RV32IB-NEXT:    fsl a2, a3, a2, a1
+; RV32IB-NEXT:    fsl a1, a0, a3, a1
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshri_i64:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    addi a1, zero, 27
-; RV32IBT-NEXT:    fsl a2, a3, a1, a2
-; RV32IBT-NEXT:    fsl a1, a0, a1, a3
+; RV32IBT-NEXT:    fsl a2, a3, a2, a1
+; RV32IBT-NEXT:    fsl a1, a0, a3, a1
 ; RV32IBT-NEXT:    mv a0, a2
 ; RV32IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }
 
 define i32 @fshli_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: fshli_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a1, a1, 27
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshli_i32:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a2, zero, 5
-; RV32IB-NEXT:    fsl a0, a0, a2, a1
+; RV32IB-NEXT:    fsl a0, a0, a1, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshli_i32:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    addi a2, zero, 5
-; RV32IBT-NEXT:    fsl a0, a0, a2, a1
+; RV32IBT-NEXT:    fsl a0, a0, a1, a2
 ; RV32IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
   ret i32 %1
 }
 
 define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: fshli_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a2, a3, 27
 ; RV32I-NEXT:    slli a3, a0, 5
 ; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    srli a0, a0, 27
 ; RV32I-NEXT:    slli a1, a1, 5
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshli_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a4, zero, 5
-; RV32IB-NEXT:    fsl a2, a0, a4, a3
-; RV32IB-NEXT:    fsl a1, a1, a4, a0
+; RV32IB-NEXT:    fsl a2, a0, a3, a4
+; RV32IB-NEXT:    fsl a1, a1, a0, a4
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshli_i64:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    addi a4, zero, 5
-; RV32IBT-NEXT:    fsl a2, a0, a4, a3
-; RV32IBT-NEXT:    fsl a1, a1, a4, a0
+; RV32IBT-NEXT:    fsl a2, a0, a3, a4
+; RV32IBT-NEXT:    fsl a1, a1, a0, a4
 ; RV32IBT-NEXT:    mv a0, a2
 ; RV32IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/rv64Zbt.ll

 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    andi a1, a2, 31
 ; RV64I-NEXT:    sll a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshl_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    fslw a0, a0, a2, a1
+; RV64IB-NEXT:    fslw a0, a0, a1, a2
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshl_i32:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    fslw a0, a0, a2, a1
+; RV64IBT-NEXT:    fslw a0, a0, a1, a2
 ; RV64IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
 declare i64 @llvm.fshl.i64(i64, i64, i64)
 
 define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: fshl_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    not a2, a2
 ; RV64I-NEXT:    srli a1, a1, 1
 ; RV64I-NEXT:    srl a1, a1, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshl_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    fsl a0, a0, a2, a1
+; RV64IB-NEXT:    fsl a0, a0, a1, a2
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshl_i64:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    fsl a0, a0, a2, a1
+; RV64IBT-NEXT:    fsl a0, a0, a1, a2
 ; RV64IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 %c)
   ret i64 %1
 }
 
 declare i32 @llvm.fshr.i32(i32, i32, i32)
 
 define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
 ; RV64I-LABEL: fshr_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    andi a1, a2, 31
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshr_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    fsrw a0, a0, a2, a1
+; RV64IB-NEXT:    fsrw a0, a1, a0, a2
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshr_i32:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    fsrw a0, a0, a2, a1
+; RV64IBT-NEXT:    fsrw a0, a1, a0, a2
 ; RV64IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
   ret i32 %1
 }
 
 declare i64 @llvm.fshr.i64(i64, i64, i64)
 
 define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: fshr_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srl a1, a1, a2
 ; RV64I-NEXT:    not a2, a2
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshr_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    fsr a0, a0, a2, a1
+; RV64IB-NEXT:    fsr a0, a1, a0, a2
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshr_i64:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    fsr a0, a0, a2, a1
+; RV64IBT-NEXT:    fsr a0, a1, a0, a2
 ; RV64IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
   ret i64 %1
 }
 
 define signext i32 @fshri_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: fshri_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srliw a1, a1, 5
 ; RV64I-NEXT:    slli a0, a0, 27
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshri_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    fsriw a0, a0, a1, 5
+; RV64IB-NEXT:    fsriw a0, a1, a0, 5
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshri_i32:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    fsriw a0, a0, a1, 5
+; RV64IBT-NEXT:    fsriw a0, a1, a0, 5
 ; RV64IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5)
   ret i32 %1
 }
 
 define i64 @fshri_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: fshri_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a1, a1, 5
 ; RV64I-NEXT:    slli a0, a0, 59
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshri_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    fsri a0, a0, a1, 5
+; RV64IB-NEXT:    fsri a0, a1, a0, 5
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshri_i64:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    fsri a0, a0, a1, 5
+; RV64IBT-NEXT:    fsri a0, a1, a0, 5
 ; RV64IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }
 
 define signext i32 @fshli_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: fshli_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srliw a1, a1, 27
 ; RV64I-NEXT:    slli a0, a0, 5
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshli_i32:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    slli a1, a1, 32
 ; RV64IB-NEXT:    addi a2, zero, 5
-; RV64IB-NEXT:    fsl a0, a0, a2, a1
+; RV64IB-NEXT:    fsl a0, a0, a1, a2
 ; RV64IB-NEXT:    sext.w a0, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshli_i32:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    slli a1, a1, 32
 ; RV64IBT-NEXT:    addi a2, zero, 5
-; RV64IBT-NEXT:    fsl a0, a0, a2, a1
+; RV64IBT-NEXT:    fsl a0, a0, a1, a2
 ; RV64IBT-NEXT:    sext.w a0, a0
 ; RV64IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
   ret i32 %1
 }
 
 define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: fshli_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a1, a1, 59
 ; RV64I-NEXT:    slli a0, a0, 5
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshli_i64:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    addi a2, zero, 5
-; RV64IB-NEXT:    fsl a0, a0, a2, a1
+; RV64IB-NEXT:    fsl a0, a0, a1, a2
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshli_i64:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    addi a2, zero, 5
-; RV64IBT-NEXT:    fsl a0, a0, a2, a1
+; RV64IBT-NEXT:    fsl a0, a0, a1, a2
 ; RV64IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }