[RISCV] Remove custom isel for (srl (shl val, 32), imm). Use pattern instead. NFCI

[craig.topper]

Summary

We don't need custom matching, we just a need a predicate to check
the immediate is greater than 32. We can use the existing ImmSub32
to adjust the immediate.

I've also used the new predicate in the other location that used
ImmSub32. I tried to create a test case where we would break without
the greater than 32 check on that pattern, but DAG combine defeated me.
Still seemed safer to have it.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

1042

I might be wrong here, but are we getting the operands to fshr the wrong way round? I'm seeing that the intrinsic documentation says that it takes operands %a, %b with %a in the MSB of the wide value, and we're passing them through to FSR as rs1 and rs3 respectively, where rs1 is the LSB of the wide value. I'm reading spec 0.92 so maybe there's a mismatch.

I don't think this applies to FSL because the spec says rs1 is the MSB of the wide value.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

1042

Typical; I just saw D90735. Let's move this discussion over there, then.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

if (isa<ConstantSDNode>(Node->getOperand(1)) && isConstantMask(Op0, Mask)) {
       if ((Mask | maskTrailingOnes<uint64_t>(ShAmt)) == 0xffffffff) {
         SDValue ShAmtVal =
             CurDAG->getTargetConstant(ShAmt, SDLoc(Node), XLenVT);
         CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0->getOperand(0),
                              ShAmtVal);
         return;
       }
     }
-    // Match (srl (shl val, 32), imm).
-    if (Op0->getOpcode() == ISD::SHL &&
-        isa<ConstantSDNode>(Op0->getOperand(1)) &&
-        isa<ConstantSDNode>(Node->getOperand(1))) {
-      uint64_t ShlAmt = Op0->getConstantOperandVal(1);
-      uint64_t SrlAmt = Node->getConstantOperandVal(1);
-      if (ShlAmt == 32 && SrlAmt > 32) {
-        SDValue SrlAmtSub32Val =
-            CurDAG->getTargetConstant(SrlAmt - 32, SDLoc(Node), XLenVT);
-        CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0->getOperand(0),
-                             SrlAmtSub32Val);
-        return;
-      }
-    }
     break;
   }
   case RISCVISD::READ_CYCLE_WIDE:
     assert(!Subtarget->is64Bit() && "READ_CYCLE_WIDE is only used on riscv32");
 
     ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ReadCycleWide, DL, MVT::i32,
                                              MVT::i32, MVT::Other,
                                              Node->getOperand(0)));

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>;
 // A mask value that won't affect significant shift bits.
 def immbottomxlenset : ImmLeaf<XLenVT, [{
   if (Subtarget->is64Bit())
     return countTrailingOnes<uint64_t>(Imm) >= 6;
   return countTrailingOnes<uint64_t>(Imm) >= 5;
 }]>;
 
+// A 6-bit constant greater than 32.
+def uimm6gt32 : ImmLeaf<XLenVT, [{
+  return isUInt<6>(Imm) && Imm > 32;
+}]>;
+
 // Addressing modes.
 // Necessary because a frameindex can't be matched directly in a pattern.
 def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;
 
 // Extract least significant 12 bits from an immediate value and sign extend
 // them.
 def LO12Sext : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()),

 }]>;
 
 // Return the negation of an immediate value.
 def NegImm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
+// Return an immediate value minus 32.
+def ImmSub32 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrFormats.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates

 def : Pat<(sext_inreg (add GPR:$rs1, simm12:$imm12), i32),
           (ADDIW GPR:$rs1, simm12:$imm12)>;
 def : Pat<(sext_inreg (sub GPR:$rs1, GPR:$rs2), i32),
           (SUBW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(sext_inreg (shl GPR:$rs1, uimm5:$shamt), i32),
           (SLLIW GPR:$rs1, uimm5:$shamt)>;
 // (srl (zexti32 ...), uimm5:$shamt) is matched with custom code due to the
 // need to undo manipulation of the mask value performed by DAGCombine.
+def : Pat<(srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt),
+          (SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>;
 def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt),
           (SRAIW GPR:$rs1, uimm5:$shamt)>;
 
 def : PatGprGpr<riscv_sllw, SLLW>;
 def : PatGprGpr<riscv_srlw, SRLW>;
 def : PatGprGpr<riscv_sraw, SRAW>;
 
 /// Loads

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

let MCOperandPredicate = [{
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     if (STI.getTargetTriple().isArch64Bit())
       return  isUInt<5>(Imm);
     return isUInt<4>(Imm);
   }];
 }
 
-// Return an immediate value minus 32.
-def ImmSub32 : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
-                                   N->getValueType(0));
-}]>;
-
 
 // Convert rotl immediate to a rotr immediate.
 def ImmROTL2R : SDNodeXForm<imm, [{
   uint64_t XLen = Subtarget->getXLen();
   return CurDAG->getTargetConstant(XLen - N->getZExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
def : Pat<(sext_inreg (fshl (assertsexti32 GPR:$rs1),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs1),
                             (shl (assertsexti32 GPR:$rs2), (i64 32)),
                             (or (assertsexti32 GPR:$rs3), (i64 32))),
                       i32),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs1),
                             (shl (assertsexti32 GPR:$rs2), (i64 32)),
-                            uimmlog2xlen:$shamt),
+                            uimm6gt32:$shamt),
                       i32),
-          (FSRIW GPR:$rs1, GPR:$rs2, (ImmSub32 uimm5:$shamt))>;
+          (FSRIW GPR:$rs1, GPR:$rs2, (ImmSub32 uimm6gt32:$shamt))>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
           (CLZW GPR:$rs1)>;
 // We don't pattern-match CTZW here as it has the same pattern and result as
 // RV64 CTZ
 def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (PCNTW GPR:$rs1)>;