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[RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions.
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Authored by craig.topper on Nov 3 2020, 9:38 PM.

Details

Summary

fsl/fsr take their shift amount in $rs2 or an immediate. The
sources are $rs1 and $rs3.

fshl/fshr ISD opcodes both concatenate operand 0 in the high bits and
operand 1 in the lower bits. fshl returns the high bits after
shifting and fshr returns the low bits. So a shift amount of 0
returns operand 0 for fshl and operand 1 for fshr.

fsl/fsr concatenate their operands in different orders such that
$rs1 will be returned for a shift amount of 0. So $rs1 needs to
come from operand 0 of fshl and operand 1 of fshr.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 3 2020, 9:38 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 3 2020, 9:38 PM
craig.topper requested review of this revision.Nov 3 2020, 9:38 PM
This revision is now accepted and ready to land.Nov 4 2020, 3:58 AM
craig.topper added inline comments.Nov 4 2020, 11:00 AM
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
828–829

Looks like I still missed swapping $rs1 and $rs3 here for FSRI. I'll fix it in the commit.

This revision was landed with ongoing or failed builds.Nov 4 2020, 11:14 AM
This revision was automatically updated to reflect the committed changes.