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Differential D90739

[RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.
ClosedPublic

Authored by craig.topper on Nov 3 2020, 10:45 PM.

Details

Reviewers
asb
lenary
luismarques
lewis-revill
PaoloS
Commits
rGcc3bf270776b: [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns.
Summary

The operations in these patterns shouldn't be effected by sign
bits. And the pattern is starting from a sign_extend_inreg so
we aren't expecting sign bits to be passed through either.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 3 2020, 10:45 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 3 2020, 10:45 PM
Herald added subscribers: frasercrmck, NickHung, evandro and 24 others. · View Herald Transcript
craig.topper requested review of this revision.Nov 3 2020, 10:45 PM
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Harbormaster completed remote builds in B77508: Diff 302753.Nov 3 2020, 10:45 PM
craig.topper added a parent revision: D90735: [RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions..Nov 3 2020, 10:46 PM
luismarques accepted this revision.Nov 4 2020, 8:08 AM

LGTM.

This revision is now accepted and ready to land.Nov 4 2020, 8:08 AM
This revision was landed with ongoing or failed builds.Nov 4 2020, 11:38 AM
Closed by commit rGcc3bf270776b: [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGcc3bf270776b: [RISCV] Remove assertsexti32 from fslw/fsrw isel patterns..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
13 lines

Diff 302925

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Show First 20 Lines • Show All 1,018 Lines • ▼ Show 20 Lines
def : Pat<(sext_inreg (or (shl GPR:$rs1, (i64 16)), def : Pat<(sext_inreg (or (shl GPR:$rs1, (i64 16)),
(srl (and GPR:$rs1, 0xFFFF0000), (i64 16))), i32), (srl (and GPR:$rs1, 0xFFFF0000), (i64 16))), i32),
(GREVIW GPR:$rs1, (i64 16))>; (GREVIW GPR:$rs1, (i64 16))>;
def : Pat<(sra (bswap GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 24))>; def : Pat<(sra (bswap GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 24))>;
def : Pat<(sra (bitreverse GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 31))>; def : Pat<(sra (bitreverse GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 31))>;
} // Predicates = [HasStdExtZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbt, IsRV64] in { let Predicates = [HasStdExtZbt, IsRV64] in {
def : Pat<(sext_inreg (fshl (assertsexti32 GPR:$rs1), def : Pat<(sext_inreg (fshl GPR:$rs1, (shl GPR:$rs3, (i64 32)),
(shl (assertsexti32 GPR:$rs3), (i64 32)), (and GPR:$rs2, (i64 31))),
(and (assertsexti32 GPR:$rs2), (i64 31))),
i32), i32),
(FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3), def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
(shl (assertsexti32 GPR:$rs1), (i64 32)), (or GPR:$rs2, (i64 32))),
(or (assertsexti32 GPR:$rs2), (i64 32))),
i32), i32),
(FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(sext_inreg (fshr (assertsexti32 GPR:$rs3), def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
(shl (assertsexti32 GPR:$rs1), (i64 32)),
uimm6gt32:$shamt), uimm6gt32:$shamt),
i32), i32),
(FSRIW GPR:$rs1, GPR:$rs3, (ImmSub32 uimm6gt32:$shamt))>; (FSRIW GPR:$rs1, GPR:$rs3, (ImmSub32 uimm6gt32:$shamt))>;
} // Predicates = [HasStdExtZbt, IsRV64] } // Predicates = [HasStdExtZbt, IsRV64]
let Predicates = [HasStdExtZbb, IsRV64] in { let Predicates = [HasStdExtZbb, IsRV64] in {
def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)), def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
(CLZW GPR:$rs1)>; (CLZW GPR:$rs1)>;
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