[PowerPC][LLD] Support for PC Relative TLS for Local Dynamic

[stefanp]

Summary

Add support to LLD for PC Relative Thread Local Storage for Local Dynamic.
This patch adds support for two relocations: R_PPC64_GOT_TLSLD_PCREL34 and
R_PPC64_DTPREL34.

The Local Dynamic code is:

pla r3, x@got@tlsld@pcrel        R_PPC64_GOT_TLSLD_PCREL34
bl __tls_get_addr@notoc(x@tlsld) R_PPC64_TLSLD
                                 R_PPC64_REL24_NOTOC
...
paddi r9, r3, x@dtprel           R_PPC64_DTPREL34

After relaxation to Local Exec:

paddi r3, r13, 0x1000
nop
...
paddi r9, r3, x@dtprel          R_PPC64_DTPREL34

[MaskRay]

lld/ELF/Arch/PPC64.cpp

793

locAsInt % 4 == 0

794

NOP

lld/test/ELF/ppc64-tls-pcrel-ld.s

53

misaligned.

Use 2 space indentation everywhere?

[stefanp]

Fixed formatting in source file.
Fixed spacing in test file.

[stefanp]

Replace error() with errorOrWarn().

[MaskRay]

lld/test/ELF/ppc64-tls-pcrel-ld.s

39

It is important to check .got

See riscv-tls-ld.s

[MaskRay]

lld/ELF/Arch/PPC64.cpp

784

Use the constant NOP

789

This can be errorOrWarn as well

We sometimes use error/fatal when we want to exit prematurely because some constraints makes it difficult not to do so. For recoverable errors, use errorOrWarn

[stefanp]

Updated test case to check for .got.
Used warningOrErr.
Used NOP.

[NeHuang]

lld/ELF/Arch/PPC64.cpp

779

nit: please add the comment to elaborate Relax from ... to ... for PCRel LD to LE relaxation.

779

Do we need to add , 0x1000 in the comment?

784

nit: // nop

787

nit: // nop

lld/test/ELF/ppc64-tls-pcrel-ld.s

38

missing relocation for R_PPC64_TPREL34?

[stefanp]

Rebased this patch on top of master and on top of the updated D87318.
This patch does depend on D87318.

Also added more comments and addressed a number of nits.

[NeHuang]

lld/ELF/Arch/PPC64.cpp

788

nit: remove to

[stefanp]

Rebased to top of trunk.
Fixed a couple of comments.
Removed some lines that are not required form the test.

lld/ELF/Arch/PPC64.cpp

779

I think we should add the constant. The way that the relaxation works is that we will always be using that same constant in this situation so I figured it should be there. However, I will add the , 0 at the end so show that we are not using the PC Rel version of the instruction.

lld/test/ELF/ppc64-tls-pcrel-ld.s

38

I don't believe that this relocation would appear in the final output file. The linker can compute that value and just fill in the instruction.

[stefanp]

All of the dependencies of this patch have now been committed.

[NeHuang]

LGTM but of course please wait to hear from @sfertile/@MaskRay before committing it.

[sfertile]

lld/ELF/Arch/PPC64.cpp

1301

Do we not need to adjust the value being relocated by the dynamic thread pointer bias?

From the ISA:

Each DTV pointer points 0x8000 bytes past the start of each TLS block. (For implementation
reasons, the actual value stored in the DTV may point to the start of a TLS block. However, values
returned by accessor functions will be offset by 0x8000 bytes.)

[stefanp]

lld/ELF/Arch/PPC64.cpp

1301

Yes, you are correct we are off by an offset of 0x8000.
Thank you for finding this!

[stefanp]

Fixed the issue where the 0x8000 offset was not being considered.

[sfertile]

lld/ELF/Arch/PPC64.cpp

780

missing the 'r' on the registers.

781

Real minor nit: No need to duplicate the comment on this line.

785

Real minor nit: move the 'to' to the next line. It matches how you structured the comment on the toc case, and helps to delineate the original code from the optimized code.

1305

Would you consider having the R_PPC64_DTPREL34 case come first and adjust the value, then fall through to the common case?

1306

We have a constant for this already: dynamicThreadPointerOffset.

[stefanp]

Fixed a couple of comments.
Moved the R_PPC64_DTPREL34 case first and adjusted the dynamic thread offset
there before falling through to the common case.

[sfertile]

lld/ELF/Arch/PPC64.cpp

1291

LLVM_FALLTHROUGH;

lld/test/ELF/ppc64-tls-pcrel-ld.s

3

Is using split file the preferred way to do this now?

11

missing --soname

36

Am I reading/interpreting this correctly?

The .got section is at address: 0x01004150, This is the first word of hex.
The first entry is the .TOC. symbol with a value of .got + 0x8000 = 0x000000000100c150. This is the second and third words of hex.
Then there are 2 words of zeros --> This is the ti_module field of the struct tls_index for local tls symbols for this module.

Then output ends. I would expect 2 more words of zeros for the ti_offset field, although maybe readobj is truncating the output, or we are missing a line?

Also shouldn't the relocation 0000000001004150 0000000000000044 R_PPC64_DTPMOD64 0
Be relocating address 0x1004158, since that is the address of the e ti_module field? Right now it seems to me like it would modify the toc-base value instead of filing in the second entry with the module tls id ...

[stefanp]

Fixed the LLVM_FALLTHROUGH
Added split-file and -soname to the test file.

Added a .TOC. symbol to the test file. This addition is a workaround for the
GOT offsets that are incorrect. This is a bug that was noticed in this test case
but has existed previous to this patch and should be fixed in a later patch.

[sfertile]

lld/test/ELF/ppc64-tls-pcrel-ld.s

63

Minor nit: use '##' for comments.

I suggest tweaking the comment a bit:

Adding a reference to .TOC. since LLD doesn't gracefully handle the case where we define a .got section but have no references to
the toc base yet.

[stefanp]

Updated comment in test case.

lld/ELF/Arch/PPC64.cpp

void PPC64::relaxTlsLdToLe(uint8_t *loc, const Relocation &rel,
 
   switch (rel.type) {
   case R_PPC64_GOT_TLSLD16_HA:
     writeFromHalf16(loc, 0x60000000); // nop
     break;
   case R_PPC64_GOT_TLSLD16_LO:
     writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13, 0
     break;
-  case R_PPC64_TLSLD:
-    write32(loc, 0x60000000);     // nop
+  case R_PPC64_GOT_TLSLD_PCREL34:
+    writePrefixedInstruction(loc, 0x06000000386d1000); // paddi 3, 13, 0x1000
+    break;
+  case R_PPC64_TLSLD: {
+    const uintptr_t locAsInt = reinterpret_cast<uintptr_t>(loc);
+    if (locAsInt % 4 == 0) {
+      write32(loc, 0x60000000);     // NOP
       write32(loc + 4, 0x38631000); // addi r3, r3, 4096
+    } else if (locAsInt % 4 == 1)
+      write32(loc - 1, 0x60000000); // NOP
+    else
+      error("R_PPC64_TLSLD has unexpected byte alignment");
     break;
+  }
   case R_PPC64_DTPREL16:
   case R_PPC64_DTPREL16_HA:
   case R_PPC64_DTPREL16_HI:
   case R_PPC64_DTPREL16_DS:
   case R_PPC64_DTPREL16_LO:
   case R_PPC64_DTPREL16_LO_DS:
+  case R_PPC64_DTPREL34:
     relocate(loc, rel, val);
     break;
   default:
     llvm_unreachable("unsupported relocation for TLS LD to LE relaxation");
   }
 }
 
 unsigned elf::getPPCDFormOp(unsigned secondaryOp) {
case R_PPC64_GOT_TLSGD16_LO:
     return R_TLSGD_GOT;
   case R_PPC64_GOT_TLSGD_PCREL34:
     return R_TLSGD_PC;
   case R_PPC64_GOT_TLSLD16:
   case R_PPC64_GOT_TLSLD16_HA:
   case R_PPC64_GOT_TLSLD16_HI:
   case R_PPC64_GOT_TLSLD16_LO:
     return R_TLSLD_GOT;
+  case R_PPC64_GOT_TLSLD_PCREL34:
+    return R_TLSLD_PC;
   case R_PPC64_GOT_TPREL16_HA:
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_TPREL16_DS:
   case R_PPC64_GOT_TPREL16_HI:
     return R_GOT_OFF;
   case R_PPC64_GOT_DTPREL16_HA:
   case R_PPC64_GOT_DTPREL16_LO_DS:
   case R_PPC64_GOT_DTPREL16_DS:
RelExpr PPC64::getRelExpr(RelType type, const Symbol &s,
   case R_PPC64_DTPREL16_HI:
   case R_PPC64_DTPREL16_HIGHER:
   case R_PPC64_DTPREL16_HIGHERA:
   case R_PPC64_DTPREL16_HIGHEST:
   case R_PPC64_DTPREL16_HIGHESTA:
   case R_PPC64_DTPREL16_LO:
   case R_PPC64_DTPREL16_LO_DS:
   case R_PPC64_DTPREL64:
+  case R_PPC64_DTPREL34:
     return R_DTPREL;
   case R_PPC64_TLSGD:
     return R_TLSDESC_CALL;
   case R_PPC64_TLSLD:
     return R_TLSLD_HINT;
   case R_PPC64_TLS:
     return R_TLSIE_HINT;
   default:
case R_PPC64_REL24_NOTOC: {
     checkAlignment(loc, val, 4, rel);
     write32(loc, (read32(loc) & ~mask) | (val & mask));
     break;
   }
   case R_PPC64_DTPREL64:
     write64(loc, val - dynamicThreadPointerOffset);
     break;
   case R_PPC64_PCREL34:
-  case R_PPC64_GOT_TLSGD_PCREL34: {
+  case R_PPC64_GOT_TLSGD_PCREL34:
+  case R_PPC64_GOT_TLSLD_PCREL34: {
     const uint64_t si0Mask = 0x00000003ffff0000;
     const uint64_t si1Mask = 0x000000000000ffff;
     const uint64_t fullMask = 0x0003ffff0000ffff;
     checkInt(loc, val, 34, rel);
 
     uint64_t instr = readPrefixedInstruction(loc) & ~fullMask;
     writePrefixedInstruction(loc, instr | ((val & si0Mask) << 16) |
                              (val & si1Mask));
     break;
   }
   case R_PPC64_GOT_PCREL34:
   case R_PPC64_GOT_TPREL_PCREL34:
-  case R_PPC64_TPREL34: {
+  case R_PPC64_TPREL34:
+  case R_PPC64_DTPREL34: {
     const uint64_t si0Mask = 0x00000003ffff0000;
     const uint64_t si1Mask = 0x000000000000ffff;
     const uint64_t fullMask = 0x0003ffff0000ffff;
     checkInt(loc, val, 34, rel);
 
     uint64_t instr = readPrefixedInstruction(loc) & ~fullMask;
     writePrefixedInstruction(loc, instr | ((val & si0Mask) << 16) |
                              (val & si1Mask));
     break;
   }
   // If we encounter a PCREL_OPT relocation that we won't optimize.
   case R_PPC64_PCREL_OPT:

lld/ELF/Relocations.cpp

if (isPPC64SmallCodeModelTocReloc(type))
       sec.file->ppc64SmallCodeModelTocRelocs = true;
 
     // Record the TOC entry (.toc + addend) as not relaxable. See the comment in
     // InputSectionBase::relocateAlloc().
     if (type == R_PPC64_TOC16_LO && sym.isSection() && isa<Defined>(sym) &&
         cast<Defined>(sym).section->name == ".toc")
       ppc64noTocRelax.insert({&sym, addend});
 
-    if (type == R_PPC64_TLSGD && expr == R_TLSDESC_CALL) {
+    if ((type == R_PPC64_TLSGD && expr == R_TLSDESC_CALL) ||
+        (type == R_PPC64_TLSLD && expr == R_TLSLD_HINT)) {
       if (i == end) {
-        error("R_PPC64_TLSGD may not be the last relocation" +
+        error("R_PPC64_TLSGD/R_PPC64_TLSLD may not be the last relocation" +
               getLocation(sec, sym, offset));
         return;
       }
 
       if ((offset%4) != 0) {
-        error("R_PPC64_TLSGD must be 4 byte aligned" +
+        error("R_PPC64_TLSGD/R_PPC64_TLSLD must be 4 byte aligned" +
               getLocation(sec, sym, offset));
         return;
       }
 
       // Offset R_PPC64_TLSGD by one byte in the NOTOC case.
       // For the TOC case the relocaiton should always be 4 byte aligned
       // by adding 1 we can mark the NOTOC case as it will be one byte offset
       // from the 4 byte alignment.

lld/test/ELF/ppc64-tls-pcrel-ld.s

+# REQUIRES: ppc
+# RUN: echo 'SECTIONS { \
+# RUN:   .text_addr 0x1001000 : { *(.text_addr) } \
+# RUN:   .text_val 0x1002000 : { *(.text_val) } \
+# RUN:   .text_twoval 0x1003000 : { *(.text_twoval) } \
+# RUN:   .text_incrval 0x1004000 : { *(.text_incrval) } \
+# RUN:   }' > %t.script
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o
+# RUN: ld.lld -T %t.script --shared %t.o -o %t-ld.so
+# RUN: ld.lld -T %t.script %t.o -o %t-ldtole
+
+# RUN: llvm-readelf -r %t-ld.so | FileCheck %s --check-prefix=LD-RELOC
+# RUN: llvm-readelf -s %t-ld.so | FileCheck %s --check-prefix=LD-SYM
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t-ld.so | FileCheck %s --check-prefix=LD
+
+# RUN: llvm-readelf -r %t-ldtole | FileCheck %s --check-prefix=LDTOLE-RELOC
+# RUN: llvm-readelf -s %t-ldtole | FileCheck %s --check-prefix=LDTOLE-SYM
+# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t-ldtole | FileCheck %s --check-prefix=LDTOLE
+
+## This test checks the Local Dynamic PC Relative TLS implementation for lld.
+## LD - Local Dynamic with no relaxation possible
+## LDTOLE - Local Dynamic relaxed to Local Exec
+
+# LD-RELOC: Relocation section '.rela.dyn' at offset 0x10078 contains 1 entries:
+# LD-RELOC: 0000000001004158  0000000000000044 R_PPC64_DTPMOD64                  0
+
+# LD-SYM:      Symbol table '.symtab' contains 10 entries:
+# LD-SYM:      5: 0000000000000000     0 TLS     LOCAL  DEFAULT    13 x
+# LD-SYM-NEXT: 6: 0000000000000004     0 TLS     LOCAL  DEFAULT    13 y
+
+# LDTOLE-RELOC: There are no relocations in this file.
+
+# LDTOLE-SYM:      Symbol table '.symtab' contains 8 entries:
+# LDTOLE-SYM:      5: 0000000000000000     0 TLS     LOCAL  DEFAULT     6 x
+# LDTOLE-SYM-NEXT: 6: 0000000000000004     0 TLS     LOCAL  DEFAULT     6 y
+
+# LD-LABEL: <LDAddr>:
+# LD:         paddi 3, 0, 12632, 1
+# LD-NEXT:    bl 0x1001020
+# LD-NEXT:    paddi 3, 3, 0, 0
+# LD-NEXT:    blr
+# LDTOLE-LABEL: <LDAddr>:
+# LDTOLE:         paddi 3, 13, 4096, 0
+# LDTOLE-NEXT:    nop
+# LDTOLE-NEXT:    paddi 3, 3, 0, 0
+# LDTOLE-NEXT:    blr
+.section .text_addr, "ax", %progbits
+LDAddr:
+  paddi 3, 0, x@got@tlsld@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsld)
+  paddi 3, 3, x@dtprel, 0
+  blr
+
+# LD-LABEL: <LDVal>:
+# LD:         paddi 3, 0, 8536, 1
+# LD-NEXT:    bl 0x1001020
+# LD-NEXT:    paddi 3, 3, 0, 0
+# LD-NEXT:    lwz 3, 0(3)
+# LD-NEXT:    blr
+# LDTOLE-LABEL: <LDVal>:
+# LDTOLE:         paddi 3, 13, 4096, 0
+# LDTOLE-NEXT:    nop
+# LDTOLE-NEXT:    paddi 3, 3, 0, 0
+# LDTOLE-NEXT:    lwz 3, 0(3)
+# LDTOLE-NEXT:    blr
+.section .text_val, "ax", %progbits
+LDVal:
+  paddi 3, 0, x@got@tlsld@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsld)
+  paddi 3, 3, x@dtprel, 0
+  lwz 3, 0(3)
+  blr
+
+# LD-LABEL: <LDTwoVal>:
+# LD:         paddi 3, 0, 4440, 1
+# LD-NEXT:    bl 0x1001020
+# LD-NEXT:    paddi 3, 3, 0, 0
+# LD-NEXT:    lwz 2, 0(3)
+# LD-NEXT:    paddi 3, 3, 4, 0
+# LD-NEXT:    lwz 3, 0(3)
+# LD-NEXT:    add 3, 3, 2
+# LD-NEXT:    blr
+# LDTOLE-LABEL: <LDTwoVal>:
+# LDTOLE:         paddi 3, 13, 4096, 0
+# LDTOLE-NEXT:    nop
+# LDTOLE-NEXT:    paddi 3, 3, 0, 0
+# LDTOLE-NEXT:    lwz 2, 0(3)
+# LDTOLE-NEXT:    paddi 3, 3, 4, 0
+# LDTOLE-NEXT:    lwz 3, 0(3)
+# LDTOLE-NEXT:    add 3, 3, 2
+# LDTOLE-NEXT:    blr
+.section .text_twoval, "ax", %progbits
+LDTwoVal:
+  paddi 3, 0, x@got@tlsld@pcrel, 1
+  bl __tls_get_addr@notoc(x@tlsld)
+  paddi 3, 3, x@dtprel, 0
+  lwz 2, 0(3)
+  paddi 3, 3, y@dtprel, 0
+  lwz 3, 0(3)
+  add 3, 3, 2
+  blr
+
+# LD-LABEL: <LDIncrementVal>:
+# LD:         paddi 3, 0, 344, 1
+# LD-NEXT:    bl 0x1001020
+# LD-NEXT:    paddi 9, 3, 4, 0
+# LD-NEXT:    lwz 4, 0(9)
+# LD-NEXT:    addi 5, 4, 1
+# LD-NEXT:    clrldi 3, 5, 32
+# LD-NEXT:    stw 5, 0(9)
+# LD-NEXT:    blr
+# LDTOLE-LABEL: <LDIncrementVal>:
+# LDTOLE:         paddi 3, 13, 4096, 0
+# LDTOLE-NEXT:    nop
+# LDTOLE-NEXT:    paddi 9, 3, 4, 0
+# LDTOLE-NEXT:    lwz 4, 0(9)
+# LDTOLE-NEXT:    addi 5, 4, 1
+# LDTOLE-NEXT:    clrldi 3, 5, 32
+# LDTOLE-NEXT:    stw 5, 0(9)
+# LDTOLE-NEXT:    blr
+.section .text_incrval, "ax", %progbits
+LDIncrementVal:
+  paddi 3, 0, y@got@tlsld@pcrel, 1
+  bl __tls_get_addr@notoc(y@tlsld)
+  paddi 9, 3, y@dtprel, 0
+  lwz 4, 0(9)
+  addi 5, 4, 1
+  clrldi 3, 5, 32
+  stw 5, 0(9)
+  blr
+
+.section .tbss,"awT",@nobits
+x:
+  .long   0
+y:
+  .long   0