[clang][aarch64] Fix ILP32 ABI for arm_sve_vector_bits

[c-rhodes]

Summary

The element types of scalable vectors are defined in terms of stdint
types in the ACLE. This patch fixes the mapping to builtin types for the
ILP32 ABI when creating VLS types with the arm_sve_vector_bits, where
the mapping is as follows:

int32_t -> LongTy
int64_t -> LongLongTy
uint32_t -> UnsignedLongTy
uint64_t -> UnsignedLongLongTy

This is implemented by leveraging getBuiltinVectorTypeInfo which is
target agnostic since it calls ASTContext::getIntTypeForBitwidth for
integer types. The element type for svfloat16_t is changed from
Float16Ty to HalfTy when creating VLS types since this is what is used
elsewhere.

For more information, see:

https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#types-varying-by-data-model
https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-support-for-scalable-vectors

[sdesmalen]

clang/lib/AST/Type.cpp

2339

Rather than comparing with a specific triple, how about getting the information from TargetInfo, i.e.

case BuiltinType::SveInt32:
  Ctx.getTargetInfo().getLongWidth() == 32 ? Ctx.LongTy : Ctx.IntTy

[efriedma]

clang/lib/AST/Type.cpp

2339

The type that actually corresponds to int64_t is TargetInfo::getInt64Type(). Not sure if you need that here.

[c-rhodes]

• Get the element type of scalable vectors from getBuiltinVectorTypeInfo when creating VLS types. This fixes the ABI issue since it calls ASTContext::getIntTypeForBitwidth which gets the correct type for a given target.
• Element type for svfloat16_t is changed from Float16Ty to HalfTy for VLS types since this is what’s used elsewhere.

[c-rhodes]

clang/lib/AST/Type.cpp

2339

I realised ASTContext::getIntTypeForBitwidth handles this and noticed getBuiltinVectorTypeInfo which Sander recently added makes use of it so I've updated it to use that instead for all types except predicates since we still need to represent them as i8.

[efriedma]

LGTM

clang/lib/AST/Type.cpp

2354

For 8-bit types, not sure you're getting anything by using getIntTypeForBitwidth instead of Ctx.UnsignedCharTy; there isn't actually any possible variation. I don't care much either way, though.

[c-rhodes]

clang/lib/AST/Type.cpp

2354

For 8-bit types, not sure you're getting anything by using getIntTypeForBitwidth instead of Ctx.UnsignedCharTy; there isn't actually any possible variation. I don't care much either way, though.

Yeah you're right, may as well keep Ctx.UnsignedCharTy, I changed it before pushing. Thanks for reviewing!

clang/lib/AST/Type.cpp

if (const BuiltinType *BT = getAs<BuiltinType>()) {
     }
   }
   return false;
 }
 
 QualType Type::getSveEltType(const ASTContext &Ctx) const {
   assert(isVLSTBuiltinType() && "unsupported type!");
 
+  llvm::Triple Triple = Ctx.getTargetInfo().getTriple();
+  bool IsILP32 = Triple.getArch() == llvm::Triple::aarch64_32;
+
   const BuiltinType *BTy = getAs<BuiltinType>();
   switch (BTy->getKind()) {
   default:
     llvm_unreachable("Unknown builtin SVE type!");
   case BuiltinType::SveInt8:
     return Ctx.SignedCharTy;
   case BuiltinType::SveUint8:
   case BuiltinType::SveBool:
     // Represent predicates as i8 rather than i1 to avoid any layout issues.
     // The type is bitcasted to a scalable predicate type when casting between
     // scalable and fixed-length vectors.
     return Ctx.UnsignedCharTy;
   case BuiltinType::SveInt16:
     return Ctx.ShortTy;
   case BuiltinType::SveUint16:
     return Ctx.UnsignedShortTy;
   case BuiltinType::SveInt32:
-    return Ctx.IntTy;
+    return IsILP32 ? Ctx.LongTy : Ctx.IntTy;
   case BuiltinType::SveUint32:
-    return Ctx.UnsignedIntTy;
+    return IsILP32 ? Ctx.UnsignedLongTy : Ctx.UnsignedIntTy;
   case BuiltinType::SveInt64:
-    return Ctx.LongTy;
+    return IsILP32 ? Ctx.LongLongTy : Ctx.LongTy;
   case BuiltinType::SveUint64:
-    return Ctx.UnsignedLongTy;
+    return IsILP32 ? Ctx.UnsignedLongLongTy : Ctx.UnsignedLongTy;
   case BuiltinType::SveFloat16:
     return Ctx.Float16Ty;
   case BuiltinType::SveBFloat16:
     return Ctx.BFloat16Ty;
   case BuiltinType::SveFloat32:
     return Ctx.FloatTy;
   case BuiltinType::SveFloat64:
     return Ctx.DoubleTy;
   }
 }
 
 bool QualType::isPODType(const ASTContext &Context) const {
   // C++11 has a more relaxed definition of POD.
   if (Context.getLangOpts().CPlusPlus11)
     return isCXX11PODType(Context);
 
   return isCXX98PODType(Context);

clang/test/CodeGen/attr-arm-sve-vector-bits-types.c

 // REQUIRES: aarch64-registered-target
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=128 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-128
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=256 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-256
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=1024 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-1024
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=2048 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-2048
+// RUN: %clang_cc1 -triple aarch64_32-unknown-darwin -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ILP32
 
 #include <arm_sve.h>
 
 #define N __ARM_FEATURE_SVE_BITS
 
 typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
 typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
 typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));

 // CHECK-2048-NEXT:  %local_arr_u16 = alloca [3 x <128 x i16>], align 16
 // CHECK-2048-NEXT:  %local_arr_u32 = alloca [3 x <64 x i32>], align 16
 // CHECK-2048-NEXT:  %local_arr_u64 = alloca [3 x <32 x i64>], align 16
 // CHECK-2048-NEXT:  %local_arr_f16 = alloca [3 x <128 x half>], align 16
 // CHECK-2048-NEXT:  %local_arr_f32 = alloca [3 x <64 x float>], align 16
 // CHECK-2048-NEXT:  %local_arr_f64 = alloca [3 x <32 x double>], align 16
 // CHECK-2048-NEXT:  %local_arr_bf16 = alloca [3 x <128 x bfloat>], align 16
 // CHECK-2048-NEXT:  %local_arr_bool = alloca [3 x <32 x i8>], align 2
+
+//===----------------------------------------------------------------------===//
+// ILP32 ABI
+//===----------------------------------------------------------------------===//
+// CHECK-ILP32: @global_i32 = global <16 x i32> zeroinitializer, align 16
+// CHECK-ILP32: @global_i64 = global <8 x i64> zeroinitializer, align 16
+// CHECK-ILP32: @global_u32 = global <16 x i32> zeroinitializer, align 16
+// CHECK-ILP32: @global_u64 = global <8 x i64> zeroinitializer, align 16